Wafer etching processing method and device, equipment and storage medium

Abstract

The embodiment of the invention relates to the field of semiconductors, and discloses a wafer etching processing method, which comprises the following steps: providing a liquid medicine tank filled with etching liquid which flows along a first direction in an etching process; a wafer is placed in the etching liquid, an initial circuit layer to be etched is arranged on the surface of the wafer, and the included angle between the layout direction of at least part of circuits on the initial circuit layer and the first direction is not 90 degrees; and controlling the etching liquid to flow along the first direction, and carrying out scouring type etching on the initial circuit layer to obtain the circuit layer. According to the wafer etching processing method disclosed by the invention, the problem that the performance and the reliability of the chip are seriously influenced due to the fact that metal residues are still easy to appear on the wafer even if the etching time is increased in an existing etching mode is solved, and at least the aims of changing the impact force of the etching liquid on the initial circuit layer and the corrosivity of the etching surface, improving the etching efficiency and improving the product quality can be achieved. And the occurrence probability of metal residues in the wafer in wet etching is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a wafer etching processing method, device, equipment and storage medium. Background Art

[0002] In the semiconductor manufacturing process, wet etching is a commonly used metal etching process. The material to be etched is immersed in a specific etching solution. Through the chemical reaction between the etching solution and the material, the part not covered by the photoresist or other masking materials is removed, thereby achieving the purpose of etching.

[0003] In some technologies, during the wet etching process, the etching time is increased to reduce the occurrence of metal residue on the wafer. However, due to the different thickness of the metal film layer on the wafer in different processes and the different actual graphic designs, even if the etching time is increased, the wafer is still prone to metal residue problems, which seriously affects the performance and reliability of the manufactured chip. Summary of the invention

[0004] The purpose of the present invention is to at least provide a wafer etching processing method, device, equipment and storage medium, which can at least solve the problem that due to the different thicknesses of the metal film layer of the wafer in different processes and the different actual graphic designs, the wafer is still prone to metal residue even if the etching time is increased, thus causing serious impact on the performance and reliability of the manufactured chip. At least the impact force of the etching solution on the initial circuit layer and the corrosiveness of the etching surface can be changed, the etching efficiency can be increased, and the metal residue of the etching can be reduced, so that the etching solution can more easily corrode the metal film layer in the wafer, the replacement capacity of the etching solution on the surface of the metal film layer can be increased, the etching efficiency of the metal film layer can be reduced due to the reaction attachment hindering the etching efficiency, and the probability of the presence of metal residue on the wafer during wet etching can be reduced.

[0005] To solve the above technical problems, at least one embodiment of the present application provides a wafer etching processing method, comprising:

[0006] Providing a liquid tank filled with an etching solution, wherein the etching solution flows along a first direction during the etching process;

[0007] Placing a wafer into the etching solution, wherein an initial circuit layer to be etched is disposed on the surface of the wafer, and an angle between a layout direction of at least part of the circuits on the initial circuit layer and the first direction is non-90 degrees;

[0008] The etching solution is controlled to flow along the first direction to perform flushing etching on the initial circuit layer to obtain a circuit layer.

[0009] At least one embodiment of the present application further provides a wafer etching processing device, comprising:

[0010] A supply module, used for providing a liquid tank containing an etching solution, wherein the etching solution flows along a first direction during the etching process;

[0011] An angle adjustment module, used for placing a wafer into the etching solution, wherein an initial circuit layer to be etched is arranged on the surface of the wafer, and the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction is non-90 degrees;

[0012] The etching module is used for performing flushing etching on the initial circuit layer by controlling the etching solution to flow along the first direction to obtain the circuit layer.

[0013] At least one embodiment of the present application also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the above-mentioned wafer etching processing method.

[0014] At least one embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program implements the above-mentioned wafer etching processing method when executed by a processor.

[0015] The wafer etching processing method provided in the embodiment of the present application places the wafer into the etching solution in the chemical solution tank, and the angle between the layout direction of at least part of the circuit on the initial circuit layer on the surface of the wafer and the first direction is not 90 degrees. By controlling the etching solution to flow along the first direction, the initial circuit layer is eroded and etched to obtain the circuit layer. In this way, the impact force of the etching solution on the initial circuit layer and the corrosiveness of the etching surface are changed, the etching efficiency is increased, and the metal residue of the etching is reduced, so that the etching solution is more likely to corrode the metal film layer in the wafer, the replacement capacity of the etching solution on the surface of the metal film layer is increased, the etching efficiency of the metal film layer is reduced due to the reaction attachment hindering the etching efficiency, and the probability of the occurrence of metal residue on the wafer during wet etching is reduced.

[0016] In some optional embodiments, the initial circuit layer is located on the etching surface of the wafer, and the circuit layout direction on the initial circuit layer is parallel to the etching surface;

[0017] Placing the wafer into the etching solution comprises:

[0018] Adjusting the wafer to be placed in the etching solution to a first state, wherein the first state is that the angle between the etching surface of the wafer and the first direction is non-90 degrees;

[0019] placing the wafer into the etching solution while maintaining the first state;

[0020] or,

[0021] Placing the wafer into the etching solution comprises:

[0022] placing the wafer in the etching solution in any state;

[0023] The wafer placed in the etching solution is adjusted to a second state, wherein the second state is that the angle between the etching surface of the wafer and the first direction is not 90 degrees.

[0024] By adjusting the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction before or after the wafer is placed in the etching solution, the impact force of the etching solution on the initial circuit layer and the corrosiveness of the etching surface are changed, the etching efficiency is increased, and the etched metal residue is reduced, making it easier for the etching solution to corrode the metal film layer in the wafer.

[0025] In some optional embodiments, the initial circuit layer includes a metal film layer;

[0026] Before placing the wafer into the etching solution, the process further includes:

[0027] Acquiring design parameters of the wafer, wherein the design parameters of the wafer include material, thickness of the metal film layer and circuit design parameters;

[0028] According to the material of the wafer, the thickness of the metal film layer and the circuit design parameters, the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction is determined.

[0029] By determining the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction according to the design parameters of the wafer, the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction is more accurate, which can effectively enhance the etching rate of the wafer.

[0030] In some optional embodiments, after determining the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction according to the material of the wafer, the thickness of the metal film layer and the circuit design parameters, the method further includes:

[0031] Calculating an etching rate of flush etching of the initial circuit layer according to an angle between a layout direction of at least part of the circuits on the initial circuit layer and the first direction;

[0032] According to the etching rate, calculating the etching time for flush etching the initial circuit layer;

[0033] The step of controlling the etching solution to flow along the first direction to perform flushing etching on the initial circuit layer to obtain the circuit layer comprises:

[0034] Based on the etching time, the etching solution is controlled to flow along the first direction, and the initial circuit layer is eroded and etched to obtain the circuit layer.

[0035] By calculating the etching time of the etching solution on the initial circuit layer of the wafer, the wafer can be taken out of the etching solution after the etching time is over, so as to facilitate subsequent operations.

[0036] In some optional embodiments, the method further includes:

[0037] Detecting whether the thickness of the metal film layer is greater than a preset film layer thickness;

[0038] When the thickness of the metal film layer is greater than the preset film layer thickness, the wafer placed in the etching solution is pulled up to pull the wafer out of the liquid surface of the etching solution and then placed back into the etching solution.

[0039] By detecting whether the thickness of the metal film layer is greater than the preset film layer thickness, when the thickness of the metal film layer is greater than the preset film layer thickness, the wafer placed in the etching solution is pulled up to pull the wafer out of the liquid surface of the etching solution and then placed in the etching solution. In this way, under the action of gravity, the reaction attachments quickly detach from the wafer surface, so that the chemical reaction rate (that is, the etching rate) of the metal at the bottom of the metal film layer is increased.

[0040] In some optional embodiments, after the etching solution is controlled to flow along the first direction to perform flush etching on the initial circuit layer to obtain the circuit layer, the method further includes:

[0041] Detecting whether the thickness of the metal film layer is greater than a preset film layer thickness;

[0042] When the thickness of the metal film layer is greater than the preset film layer thickness, detecting whether there is metal residue on the circuit layer of the wafer etched for the etching time;

[0043] When metal residues exist on the circuit layer of the wafer after etching for the etching time, the wafer placed in the etching solution is pulled out of the liquid surface of the etching solution and then placed in the etching solution.

[0044] By detecting whether the thickness of the metal film layer is greater than the preset film layer thickness and detecting whether there is metal residue on the circuit layer of the etched wafer after the etching time. When the thickness of the metal film layer is greater than the preset film layer thickness and there is metal residue on the circuit layer of the etched wafer after the etching time, the wafer placed in the etching liquid is pulled up. In this way, under the action of gravity, the reaction attachments generated by the reaction of the etching liquid and the metal film layer quickly detach from the wafer surface, so that the chemical reaction rate (that is, the etching rate) of the metal at the bottom of the metal film layer increases.

[0045] In some optional embodiments, the step of performing a lifting process on the wafer placed in the etching solution includes:

[0046] Calculating the number of times the wafer is pulled according to the thickness of the metal film layer and the etching rate;

[0047] The wafer placed in the etching solution is pulled the number of times.

[0048] By calculating the number of pull-ups, the wafer is taken out of the etching solution after the number of pull-ups is reached, so as to facilitate subsequent operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] One or more embodiments are exemplarily described by the pictures in the corresponding drawings, and these exemplary descriptions do not constitute limitations on the embodiments.

[0050] Figure 1 It is a schematic flow chart of a wafer etching processing method provided by an embodiment of the present application;

[0051] Figure 2 It is a schematic diagram of a process of a wafer etching processing device provided by an embodiment of the present application;

[0052] Figure 3 is a structural schematic diagram of an electronic device provided by another embodiment of the present application;

[0053] Figure 4 is a schematic flow chart of a wafer etching processing method provided by another embodiment of the present application;

[0054] Figure 5 is a schematic diagram of an etching method of the prior art provided by an embodiment of the present application;

[0055] Figure 6a and Figure 6b is a schematic diagram of a structure for characterizing the presence and absence of metal residues on a wafer provided by another embodiment of the present application;

[0056] Figure 7This is one of the schematic diagrams of adjusting the angle at which a wafer enters a chemical solution provided by another embodiment of the present application;

[0057] Figure 8 This is a second schematic diagram for adjusting the angle at which a wafer enters a chemical solution, provided by another embodiment of the present application;

[0058] Fig. 9 It is a schematic diagram of an etching mode provided by another embodiment of the present application. DETAILED DESCRIPTION

[0059] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined and referenced with each other under the premise of no contradiction.

[0060] In order to facilitate understanding of the embodiments of the present application, relevant contents about the wafer etching processing method are first introduced here.

[0061] In the semiconductor manufacturing process, wet etching is a commonly used metal etching process. The material to be etched is immersed in a specific etching solution. Through the chemical reaction between the etching solution and the material, the part not covered by the photoresist or other masking materials is removed, thereby achieving the purpose of etching.

[0062] In some technologies, after the wafer is placed in the wafer cassette (i.e., wafer carrier), it enters the feeding unit of the equipment, and after a certain transmission distance, the robotic arm places the entire wafer cassette into the etching solution (i.e., etching liquid), allowing the entire wafer to be immersed in the etching liquid for chemical reaction, and finally completes the metal wet etching to obtain the required pattern. During the wet etching process, the etching time is increased to reduce the occurrence of metal residue on the wafer. Figure 5 As shown, all wafers are immersed in the etching solution to carry out chemical reaction until the specified time is up, and then they are lifted up by arms and transported to the water washing unit to clean the etching solution and reaction attachments on the surface, and then dried to complete the entire etching process. In the existing wet etching method, the thickness of the metal film layer will continue to change and increase with different process requirements, which is very likely to cause the problem of metal residue; the main reasons are two points:

[0063] 1. As the thickness of the metal film increases, the etching time needs to be increased. After the metal on the surface undergoes a chemical reaction, the amount of attachment on its surface will also increase, thus blocking the etching of the film layer below.

[0064] 2. As the reaction proceeds, a large number of bubbles will be generated on the surface of the film layer, which will further block the chemical reaction etching of the film layer below. In this etching mode, even if the etching time is increased, the metal at the bottom layer will still remain, such as Figure 6a As shown; the normal etching without residual pattern is as follows Figure 6b As shown, there is no residue at the bottom.

[0065] However, the existing problem of metal residue occurs during the wet etching of metal wafers. The residue locations are mainly concentrated on the vertical lines within the wafer. Due to the different thicknesses of the metal film layer on the wafer in different processes and the different actual graphic designs, even if the etching time is increased, the wafer is still prone to metal residue problems, which has a serious impact on the performance and reliability of the manufactured chips.

[0066] In order to solve the above-mentioned problem that due to the different thicknesses of the metal film layer of the wafer in different processes and the different actual graphic designs, even if the etching time is increased, the wafer is still prone to metal residue, thus causing serious impact on the performance and reliability of the manufactured chip. The present invention proposes a wafer etching processing method. The implementation details of the wafer etching processing method of this embodiment are specifically described below. The following content is only the implementation details provided for ease of understanding and is not necessary for the implementation of this solution.

[0067] Embodiment 1:

[0068] The wafer etching method of this embodiment can be applied to electronic devices with communication, computing and data storage capabilities. The specific process can be as follows: Figure 1 As shown, including:

[0069] Step 101, providing a solution tank filled with etching solution, wherein the etching solution flows along a first direction during etching.

[0070] Specifically, the liquid medicine tank is connected to an external pump to enable the etching solution to flow in the first direction in the liquid medicine tank, wherein the etching solution is selected according to the material of the metal film layer of the wafer. In some examples, the first direction can be vertical, horizontal or any direction, but the first direction must be 90 degrees perpendicular to the bottom of the liquid medicine tank.

[0071] Step 102, placing a wafer into an etching solution, an initial circuit layer to be etched is arranged on the surface of the wafer, and the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction is non-90 degrees.

[0072] Specifically, if Figure 6a and Figure 6b As shown, the wafer includes a photoresist film layer, a metal film layer and an underlying structure, the metal film layer is located on the underlying structure of the wafer, the photoresist film layer is located on a side of the metal film layer away from the underlying structure, the photoresist film layer and the metal film layer form an initial circuit layer, wherein the photoresist film layer is engraved with an integrated circuit layout by photolithography technology, and during etching, the metal film layer not covered with photoresist is etched by an etching liquid to obtain an etched wafer. In this embodiment, the wafer is placed in the etching liquid, and the angle between the layout direction of at least part of the circuits on the initial circuit layer of the wafer placed in the etching liquid and the first direction is non-90 degrees.

[0073] In some examples, the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction is in the range of (0 degrees, 180 degrees). Preferably, the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction is in the range of (0 degrees, 90 degrees) and (90 degrees, 180 degrees).

[0074] Step 103 , by controlling the etching solution to flow along a first direction, flush etching is performed on the initial circuit layer to obtain a circuit layer.

[0075] Specifically, during the etching process, after adjusting the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction, the etching solution is controlled to flow in the first direction. At this time, the flow direction of the etching solution is vertically downward and perpendicular to the bottom of the liquid tank. Since the angle between at least part of the circuit layout direction of the initial circuit layer and the first direction is not 90 degrees, at this time, the etching solution performs flushing etching on the initial circuit layer in the first direction. Compared with the existing initial circuit layer, at least part of the circuit layout direction is parallel to the first direction. In this way, the impact force of the etching solution on the initial circuit layer and the corrosiveness of the etching surface are changed, the etching efficiency is increased, and the metal residue of the etching is reduced, so that the etching solution is easier to corrode the metal film layer in the wafer, the replacement capacity of the etching solution on the surface of the metal film layer is increased, the etching efficiency of the metal film layer is reduced due to the reaction attachment hindering the etching efficiency of the metal film layer, and the probability of the occurrence of metal residue on the wafer during wet etching is reduced.

[0076] In this embodiment, the wafer is placed in the etching solution in the chemical solution tank, and the angle between the layout direction of at least part of the circuits on the surface of the initial circuit layer of the wafer and the first direction is not 90 degrees. By controlling the etching solution to flow along the first direction, the initial circuit layer is eroded to obtain the circuit layer. In this way, the impact force of the etching solution on the initial circuit layer and the corrosiveness of the etching surface are changed, the etching efficiency is increased, and the metal residues of the etching are reduced, making it easier for the etching solution to corrode the metal film layer in the wafer, increasing the replacement capacity of the etching solution on the surface of the metal film layer, reducing the etching efficiency of the metal film layer hindered by the reaction attachments, and reducing the probability of the occurrence of metal residues on the wafer during wet etching.

[0077] In some embodiments, the initial circuit layer is located on the etching surface of the wafer, and the circuit layout direction on the initial circuit layer is parallel to the etching surface;

[0078] Place the wafer into the etching solution, including:

[0079] Adjusting the wafer to be placed in the etching solution to be in a first state, wherein the first state is that the angle between the etching surface of the wafer and the first direction is not 90 degrees;

[0080] The wafer is placed in the etching solution while maintaining the first state.

[0081] Specifically, the etching surface of the wafer is the surface of the metal film layer close to the photoresist film layer. When etching the wafer, etching is performed from the etching surface of the wafer gradually in the direction close to the underlying structure. In this embodiment, before the wafer is placed in the etching solution, the state of the wafer is adjusted to the first state, that is, the wafer is adjusted so that the angle between the etching surface of the wafer and the first direction is not 90 degrees, and then the wafer is placed in the etching solution while maintaining the first state. At this time, the etching solution performs flushing etching on the initial circuit layer of the wafer maintained in the first state in the first direction. In this way, the impact force of the etching solution on the initial circuit layer and the corrosiveness of the etching surface are changed, the etching efficiency is increased, and the etched metal residue is reduced, so that the etching solution can more easily corrode the metal film layer in the wafer.

[0082] In some embodiments, placing the wafer into an etching solution includes:

[0083] Place the wafer into the etching solution, including:

[0084] Place the wafer in an etching solution in any state;

[0085] The wafer placed in the etching solution is adjusted to a second state, wherein the second state is that the angle between the etching surface of the wafer and the first direction is not 90 degrees.

[0086] Specifically, the etching surface of the wafer is the surface of the metal film layer close to the photoresist film layer. When etching the wafer, etching is performed gradually from the etching surface of the wafer in the direction close to the underlying structure. In this embodiment, before the wafer is placed in the etching solution, the state of the wafer is not limited, that is, the wafer is placed in the etching solution in any state. After the wafer has been placed in the etching solution, the state of the wafer is adjusted to the second state, that is, the wafer is adjusted so that the angle between the etching surface of the wafer and the first direction is not 90 degrees, and then the wafer is placed in the etching solution while maintaining the second state. At this time, the etching solution performs flushing etching on the initial circuit layer of the wafer maintained in the second state in the first direction. In this way, the impact force of the etching solution on the initial circuit layer and the corrosiveness of the etching surface are changed, the etching efficiency is increased, and the etched metal residue is reduced, so that the etching solution is more likely to corrode the metal film layer in the wafer.

[0087] In some embodiments, the initial circuit layer includes a metal film layer;

[0088] Before placing the wafer into the etching solution, it also includes:

[0089] Obtaining wafer design parameters, wherein the wafer design parameters include material, thickness of metal film layer and circuit design parameters;

[0090] According to the material of the wafer, the thickness of the metal film layer and the circuit design parameters, the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction is determined.

[0091] Specifically, the initial circuit layer includes a photoresist film layer and a metal film layer, the metal film layer is located on the bottom structure of the wafer, and the photoresist film layer is located on the side of the metal film layer away from the bottom structure. Before placing the wafer in the etching solution, it is necessary to obtain the design parameters of the wafer for use in the subsequent etching process, wherein the design parameters include the material, the thickness of the metal film layer and the circuit design parameters, the material refers to the material of the metal film layer, and the etching solution is selected according to the material of the metal film layer, and the circuit design parameters refer to the specific integrated circuit layout on the wafer. In this embodiment, the angle between the layout direction of at least part of the circuit on the initial circuit layer and the first direction is determined according to the material of the wafer, the thickness of the metal film layer and the circuit design parameters, and here, the angle between the layout direction of at least part of the circuit on the initial circuit layer and the first direction refers to the optimized angle used to increase the etching rate to reduce the presence of metal residues on the wafer.

[0092] In some examples, when the thickness of the metal film layer is 10000A, the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction is 0° / 30° / 45°; when the thickness of the metal film layer is 15000A, the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction is 30°-60°; when the thickness of the metal film layer is more than 20000A, the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction is 30°-60°.

[0093] In some examples, historical experimental parameters are obtained; based on the historical experimental parameters, a parameter association relationship between the material of the wafer, the thickness of the metal film layer, the circuit design parameters, and the angle between the layout direction of at least part of the circuit on the initial circuit layer and the first direction is determined; based on the parameter association relationship, according to the material of the wafer, the thickness of the metal film layer, and the circuit design parameters, the angle between the layout direction of at least part of the circuit on the initial circuit layer and the first direction is determined. The historical experimental parameters refer to experimental parameters collected in the process of etching different types of wafers in the past.

[0094] In some embodiments, after determining the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction according to the material of the wafer, the thickness of the metal film layer and the circuit design parameters, the method further includes:

[0095] Calculating an etching rate of flush etching of the initial circuit layer according to an angle between a layout direction of at least part of the circuits on the initial circuit layer and the first direction;

[0096] Specifically, the increase in etching rate is calculated by the following relationship: Etching rate increase = angle increase * 45A / min, wherein the angle increase refers to the increase in the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction compared to the first direction.

[0097] According to the etching rate, the etching time of the etching solution on the initial circuit layer of the wafer is calculated;

[0098] Specifically, after obtaining the etching rate, the etching time of the initial circuit layer of the wafer can be calculated based on the etching rate and the thickness of the metal film layer. That is to say, after the wafer is placed in the etching solution and etched for the etching time, the metal film layer corresponding to the integrated circuit layout on the photoresist film layer is etched cleanly.

[0099] By controlling the etching liquid to flow along the first direction, the initial circuit layer is subjected to flushing etching to obtain the circuit layer, including:

[0100] Based on the etching time, the etching solution is controlled to flow along a first direction, and the initial circuit layer is etched by flushing to obtain the circuit layer.

[0101] Specifically, after the etching time is obtained, the etching liquid is controlled to flow in the first direction by an external pump, and the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction is not 90 degrees. The metal film layer of the initial circuit layer in the wafer maintaining the first state or the second state is flush-etched to obtain the circuit layer.

[0102] In some embodiments, the method further comprises:

[0103] Detect whether the thickness of the metal film layer is greater than the preset film layer thickness;

[0104] When the thickness of the metal film layer is greater than the preset film layer thickness, the wafer placed in the etching solution is pulled up to pull the wafer out of the liquid surface of the etching solution and then placed back into the etching solution.

[0105] Specifically, due to the different circuit design parameters of different wafers or different device design requirements, the thickness of the metal film layer will be different. As the thickness increases, the metal at the bottom of the metal film layer will have residual problems. As the thickness of the metal film layer increases, the chemical reaction between the etching solution and the metal film layer proceeds, and a large amount of reaction products adhere to it, resulting in a significant reduction in the etching rate of the metal at the bottom, thereby reducing the etching rate. In this embodiment, it is detected whether the thickness of the metal film layer is greater than the preset film thickness. When the thickness of the metal film layer is greater than the preset film thickness, the wafer that has been placed in the etching solution is pulled up to pull the wafer out of the liquid surface of the etching solution and then placed in the etching solution. In this way, under the action of gravity, the reaction attachments quickly detach from the wafer surface, so that the chemical reaction rate (that is, the etching rate) of the metal at the bottom of the metal film layer increases.

[0106] In some embodiments, after the initial circuit layer is eroded by controlling the etching solution to flow along the first direction to obtain the circuit layer, the method further includes:

[0107] Detect whether the thickness of the metal film layer is greater than the preset film layer thickness;

[0108] Specifically, during the etching process in the etching liquid, after adjusting the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction, since the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction is not 90 degrees, the etching liquid performs flushing etching on the initial circuit layer in the first direction. However, as the thickness of the metal film layer increases, the chemical reaction between the etching liquid and the metal film layer proceeds, and a large amount of reaction products adhere to it, resulting in a significant reduction in the metal etching rate of the bottom layer, thereby reducing the etching rate. At this time, even by increasing the etching time or adjusting the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction to be non-90 degrees, it is impossible to avoid the presence of metal residue on the wafer. In this embodiment, by detecting whether the thickness of the metal film layer is greater than the preset film thickness, it is mainly to detect an overly thick metal film layer. If the thickness of the metal film layer is less than or equal to the preset film thickness, there is no need to perform other operations on the wafer placed in the etching liquid. By adjusting the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction, the problem of metal residue during wafer etching can be solved.

[0109] In some examples, as shown in Table 1 below, when the thickness of the metal film layer is 10000A, by adjusting the angle between at least part of the layout direction of the initial circuit layer and the first direction to 0° / 30° / 45°, no metal residue will appear on the wafer during the etching process. When the thickness of the metal film layer is 15000A, by adjusting the angle between at least part of the layout direction of the initial circuit layer and the first direction to 30°-60°, no metal residue will appear on the wafer during the etching process.

[0110] When the thickness of the metal film layer is greater than the preset film layer thickness, detecting whether there is metal residue on the circuit layer of the wafer etched for the etching time;

[0111] Specifically, by detecting whether the thickness of the metal film layer is greater than the preset film layer thickness, if the thickness of the metal film layer is greater than the preset film layer thickness, it means that the problem of metal residues appearing on the wafer during the etching process cannot be completely solved by adjusting the angle between at least part of the circuit layout direction of the initial circuit layer and the first direction. In this embodiment, when the thickness of the metal film layer is greater than the preset film layer thickness, it is detected whether there is metal residue on the circuit layer of the etched wafer after the etching time.

[0112] When metal residues exist on the circuit layer of the wafer after etching for a certain period of time, the wafer placed in the etching solution is pulled out of the liquid surface of the etching solution and then placed in the etching solution again.

[0113] Specifically, during the etching process in the etching solution, after adjusting the angle between at least part of the circuit layout direction on the initial circuit layer and the first direction, since the angle between at least part of the circuit layout direction of the initial circuit layer and the first direction is not 90 degrees, the etching solution performs flushing etching on the initial circuit layer in the first direction. However, as the thickness of the metal film layer increases, the chemical reaction between the etching solution and the metal film layer proceeds, and a large amount of reaction products adhere to it, resulting in a significant reduction in the metal etching rate of the bottom layer, thereby reducing the etching rate, and even increasing the etching time cannot solve the problem of metal residue. In this embodiment, when the thickness of the metal film layer is greater than the preset film layer thickness, and there is metal residue on the circuit layer of the etched wafer after the etching time, the wafer that has been placed in the etching solution needs to be pulled up to pull the wafer out of the liquid surface of the etching solution and then placed in the etching solution. In this way, under the action of gravity, the reaction attachment quickly detaches from the wafer surface, so that the chemical reaction rate (that is, the etching rate) of the metal at the bottom of the metal film layer increases.

[0114] Table 1 Correspondence between the thickness of the metal film layer and the number of pull-ups

[0115]

[0116] In this embodiment, it is detected whether the thickness of the metal film layer is greater than the preset film layer thickness. When the thickness of the metal film layer is greater than the preset film layer thickness, it is detected whether there is metal residue on the circuit layer of the etched wafer after the etching time. When there is metal residue on the circuit layer of the etched wafer after the etching time, the wafer placed in the etching liquid is pulled out of the liquid surface of the etching liquid and then placed in the etching liquid. In this way, under the action of gravity, the reaction attachments generated by the reaction of the etching liquid and the metal film layer quickly detach from the wafer surface, so that the chemical reaction rate (that is, the etching rate) of the metal at the bottom of the metal film layer increases.

[0117] In some embodiments, the wafer placed in the etching solution is subjected to a pull-up process, including:

[0118] The number of times the wafer is pulled is calculated according to the thickness of the metal film layer and the etching rate;

[0119] The wafer placed in the etching solution is pulled a number of times.

[0120] Specifically, since the thickness of the metal film layer of different wafers is different, the specific number of pull-ups needs to be calculated when the wafer is pulled. After the etching rate is obtained, the number of pull-ups is calculated by the following relationship: number of pull-ups = thickness of the metal film layer / etching rate*60 / 15, thereby obtaining the specific number of pull-ups. In this embodiment, after obtaining the number of pull-ups, the wafer placed in the etching solution is pulled the number of times, that is, the wafer is pulled out of the liquid surface of the etching solution and then placed in the etching solution, and the step is repeated according to the number of pull-ups.

[0121] In some examples, the etching time is related to the thickness of the metal film layer, the angle between the layout direction of at least a portion of the circuits in the initial circuit layer and the first direction, and the number of pull times.

[0122] Embodiment 2:

[0123] like Figure 4 As shown, this embodiment provides exemplary content of the first embodiment, that is, provides an exemplary process of a wafer etching processing method, and the specific content includes:

[0124] Step 1: If Figure 7As shown, by changing the angle at which the wafer enters the solution (i.e., the etching solution) (i.e., the angle between the layout direction of at least part of the initial circuit layer and the first direction), the angle at which the wafer enters the solution is changed from the previous level, and by adjusting the wafer to a certain angle, the angle between the wafer circuit design layout direction and the circulation of the solution is changed, so that the impact of the solution on the circuit is increased, and finally the etching rate is increased; there are certain differences between metal film layers of different thicknesses and types, taking metal AL (aluminum) as an example, between 0-45°, as shown in Table 2 below, the relationship between the increase in angle and the etching rate is: the increase in etching rate = the increase in angle * 45A / min; so, Figure 8 As shown, the impact force of the chemical solution on the etching circuit and the corrosiveness of the side are changed, the etching efficiency is increased, and the etching residue is reduced;

[0125] Table 2 Relationship between angle and etching rate

[0126]

[0127] Step 2: If Fig. 9 As shown in the figure, after the wafer is immersed in the chemical solution for a period of time, it is separated from the chemical solution through a new etching mode with a change in the flow field direction (immersion in chemical solution, separation from chemical solution, immersion in chemical solution, immersion in chemical solution... and so on and so forth, until the prescribed process time is completed), so that the reaction attachments and bubbles are easily removed from the wafer surface under the action of the gravity of the liquid, and this is repeated, so that the chemical reaction rate of the film layer underneath is accelerated, the etching uniformity is improved, and finally the metal etching residue-free effect is achieved;

[0128] Description of parameters related to the entire etching mode:

[0129] Taking metal AL as an example, the thickness is about 30000A, and the solution used is conventional AL (H3PO4HON3CH3COOH) in a certain ratio (about 1:7:50-70). Under the condition of 45° temperature, the etching process of the whole test process is shown in Table 3 below:

[0130] Table 3 Etching mode description

[0131]

[0132] Due to different wafer circuit designs and device design requirements, the thickness of the metal film layer will have different requirements. As the thickness increases, the metal residue on the bottom layer will appear.

[0133] The above problems are solved in the following ways:

[0134] Method 1: By adjusting the angle at which the wafer enters the chemical solution, the vertical line of the wafer is at a certain angle to the circulation direction of the chemical solution, so as to increase the aggressiveness of the chemical solution to the line, thereby speeding up the etching speed and reducing the etching residue in the same time;

[0135] Method 2, as shown in Table 1, as the thickness of the metal film layer increases, the chemical reaction proceeds, and a large amount of reaction products adhere to it, which greatly reduces the metal etching rate of the bottom layer, thereby reducing the etching rate. Ultimately, even if the etching time is increased, the residue cannot be solved. Therefore, in this case, there is a second method, which is to pull the wafer out of the liquid surface. In this way, under the action of gravity, the reaction attachments quickly detach from the wafer surface, and the chemical reaction rate (that is, the etching rate) of the bottom metal film layer increases. Finally, under the joint action of method 1 & method 2, no residue is completely achieved.

[0136] The implementation logic of the final solution: The final etching time is determined by the thickness of the metal film layer, the angle at which the wafer enters the solution, and the pulling process.

[0137] Table 1 Correspondence between the thickness of the metal film layer and the number of pull-ups

[0138]

[0139]

[0140] In the present embodiment, the problem of wet metal etching residues on the wafers of the production line is solved. By adjusting the angle between the wafer layout direction and the circulating liquid flow field and combining a new etching method to improve the liquid flow field direction, under the same process conditions, the etching rate of the film layer is greatly increased, the uniformity is improved, the process time is reduced, and ultimately the problem of wet metal etching residues on the wafers is eradicated.

[0141] Embodiment three:

[0142] Another embodiment of the present application relates to a wafer etching processing device. The implementation details of the wafer etching processing device of this embodiment are specifically described below. The following content is only for the convenience of understanding the implementation details provided, and is not necessary for the implementation of this solution. The schematic diagram of the wafer etching processing device of this embodiment can be as follows Figure 2 As shown, including:

[0143] A supply module 201 is used to provide a liquid tank containing an etching solution, wherein the etching solution flows along a first direction during the etching process;

[0144] An angle adjustment module 202 is used to place a wafer into an etching solution, the surface of the wafer is provided with an initial circuit layer to be etched, and the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction is non-90 degrees;

[0145] The etching module 203 is used to perform flushing etching on the initial circuit layer by controlling the etching solution to flow along a first direction to obtain the circuit layer.

[0146] It is worth mentioning that all modules involved in this embodiment are logic modules. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0147] Embodiment 4:

[0148] Another embodiment of the present application relates to an electronic device, such as Figure 3 As shown, it includes: at least one processor 901; and a memory 902 that is communicatively connected to the at least one processor 901; wherein the memory 902 stores instructions that can be executed by the at least one processor 901, and the instructions are executed by the at least one processor 901 so that the at least one processor 901 can execute the wafer etching processing method in the above-mentioned embodiments.

[0149] Among them, the memory and the processor are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. The data processed by the processor is transmitted on a wireless medium via an antenna, and further, the antenna also receives data and transmits the data to the processor.

[0150] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0151] Embodiment five:

[0152] Another embodiment of the present application relates to a computer-readable storage medium storing a computer program, which implements the above method embodiment when executed by a processor.

[0153] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as: ROM), random access memory (Random Access Memory, referred to as: RAM), disk or optical disk and other media that can store program codes.

[0154] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A wafer etching method, characterized in that: include: Providing a liquid tank filled with an etching solution, wherein the etching solution flows along a first direction during the etching process; Placing a wafer into the etching solution, wherein an initial circuit layer to be etched is disposed on the surface of the wafer, and an angle between a layout direction of at least part of the circuits on the initial circuit layer and the first direction is non-90 degrees; The etching solution is controlled to flow along the first direction to perform flushing etching on the initial circuit layer to obtain a circuit layer.

2. The wafer etching method according to claim 1, characterized in that: The initial circuit layer is located on the etching surface of the wafer, and the circuit layout direction on the initial circuit layer is parallel to the etching surface; Placing the wafer into the etching solution comprises: Adjusting the wafer to be placed in the etching solution to a first state, wherein the first state is that the angle between the etching surface of the wafer and the first direction is non-90 degrees; placing the wafer into the etching solution while maintaining the first state; or, Placing the wafer into the etching solution comprises: placing the wafer in the etching solution in any state; The wafer placed in the etching solution is adjusted to a second state, wherein the second state is that the angle between the etching surface of the wafer and the first direction is not 90 degrees.

3. The wafer etching method according to claim 1, characterized in that: The initial circuit layer includes a metal film layer; Before placing the wafer into the etching solution, the process further includes: Acquiring design parameters of the wafer, wherein the design parameters of the wafer include material, thickness of the metal film layer and circuit design parameters; According to the material of the wafer, the thickness of the metal film layer and the circuit design parameters, the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction is determined.

4. The wafer etching method according to claim 3, characterized in that: After determining the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction according to the material of the wafer, the thickness of the metal film layer and the circuit design parameters, the method further includes: Calculating an etching rate of flush etching of the initial circuit layer according to an angle between a layout direction of at least part of the circuits on the initial circuit layer and the first direction; According to the etching rate, calculating the etching time for flush etching the initial circuit layer; The step of controlling the etching solution to flow along the first direction to perform flushing etching on the initial circuit layer to obtain the circuit layer comprises: Based on the etching time, the etching solution is controlled to flow along the first direction, and the initial circuit layer is eroded and etched to obtain the circuit layer.

5. The wafer etching method according to claim 4, characterized in that: The method further comprises: Detecting whether the thickness of the metal film layer is greater than a preset film layer thickness; When the thickness of the metal film layer is greater than the preset film layer thickness, the wafer placed in the etching solution is pulled up to pull the wafer out of the liquid surface of the etching solution and then placed back into the etching solution.

6. The wafer etching method according to claim 4, characterized in that: After the etching solution is controlled to flow in the first direction to perform flush etching on the initial circuit layer to obtain the circuit layer, the method further includes: Detecting whether the thickness of the metal film layer is greater than a preset film layer thickness; When the thickness of the metal film layer is greater than the preset film layer thickness, detecting whether there is metal residue on the circuit layer of the wafer etched for the etching time; When metal residues exist on the circuit layer of the wafer after etching for the etching time, the wafer placed in the etching solution is pulled out of the liquid surface of the etching solution and then placed in the etching solution.

7. The wafer etching method according to claim 5 or 6, characterized in that: The step of performing a lifting process on the wafer placed in the etching solution comprises: Calculating the number of times the wafer is pulled according to the thickness of the metal film layer and the etching rate; The wafer placed in the etching solution is pulled the number of times.

8. A wafer etching processing device, characterized in that: include: A supply module, used for providing a liquid tank containing an etching solution, wherein the etching solution flows along a first direction during the etching process; An angle adjustment module, used for placing a wafer into the etching solution, wherein an initial circuit layer to be etched is arranged on the surface of the wafer, and the angle between the layout direction of at least part of the circuits on the initial circuit layer and the first direction is non-90 degrees; The etching module is used for performing flushing etching on the initial circuit layer by controlling the etching solution to flow along the first direction to obtain the circuit layer.

9. An electronic device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the wafer etching processing method as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the wafer etching processing method according to any one of claims 1 to 7 is implemented.

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