Semiconductor device and method for manufacturing the same

Abstract

The present application discloses a semiconductor device and a method for preparing the same, and relates to the field of semiconductor processing technology. The method for preparing the semiconductor device of the present application comprises providing a wafer, wherein the wafer comprises an effective area and an edge area; sequentially forming a first dielectric layer and a first metal wiring layer on the wafer, wherein the first metal wiring layer is connected to the wafer; sequentially forming a second dielectric layer and a peeling layer on the first metal wiring layer to form a structure to be wired, heating the peeling layer to release the stress between the first metal wiring layer and the first dielectric layer to form particles by cracking, and the peeling layer in the edge area wraps the particles to form peeling impurities; cleaning the structure to be wired to remove the peeling impurities; sequentially forming a third dielectric layer and a second metal wiring layer on the upper surface of the structure to be wired, wherein the second metal wiring is connected to the first metal wiring layer. The method for preparing the semiconductor device provided by the present application can reduce the shedding of the edge area of ​​the semiconductor device and improve the reliability of the product.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technology, and in particular, to a semiconductor device and a method for preparing the same. Background Art

[0002] With the continuous development of semiconductor technology, the film structure of the edge area of ​​the wafer is becoming more and more complex. Since the edge area of ​​the wafer cannot be etched, the edge area has become the source of more and more defects. Specifically, etching is a necessary step in the semiconductor manufacturing process, and etching includes wet etching, plasma etching, etc. However, during the etching process, or other semiconductor device processing processes, byproducts or shedding defects often form impurity particles near the edge of the semiconductor device (including the top, side and bottom). Among them, the presence of impurity particles will seriously affect the subsequent process.

[0003] In the prior art, adding a chamfer polishing process to the unexposed area can effectively reduce the number of shedding defects in the edge area of ​​the wafer. However, the chamfer polishing process is a very risky process and can easily cause wafer breakage. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device and a method for preparing the same, which can reduce the shedding of the edge area of ​​the semiconductor device and improve the reliability of the product.

[0005] On the one hand, an embodiment of the present application provides a method for preparing a semiconductor device, including providing a wafer, the wafer including an effective area and an edge area located at the periphery of the effective area, and a plurality of chips are arranged in the effective area; forming a first dielectric layer and a first metal wiring layer on the wafer in sequence, the first metal wiring layer penetrates the first dielectric layer and is connected to the chips; forming a second dielectric layer and a peeling layer in sequence on the first metal wiring layer to form a structure to be wired, heating the peeling layer when forming it to release the stress between the first metal wiring layer and the first dielectric layer to fracture and form particles, the peeling layer in the edge area wraps the particles to form peeling impurities; cleaning the structure to be wired to remove the peeling impurities; forming a third dielectric layer and a second metal wiring layer in sequence on the upper surface of the structure to be wired, the second metal wiring penetrates the third dielectric layer and the second dielectric layer and is connected to the first metal wiring layer.

[0006] As an practicable method, a second dielectric layer and a peeling layer are sequentially formed on a first metal wiring layer to form a structure to be wired, including: forming a first dielectric sublayer on the first metal wiring layer; forming a second dielectric sublayer on the first dielectric sublayer, wherein the first dielectric sublayer and the second dielectric sublayer are made of the same material; mechanically and chemically grinding the second dielectric sublayer to a preset thickness; forming a peeling layer on the ground second dielectric sublayer, and heating the peeling layer during formation to release stress between the first metal wiring layer and the first dielectric layer to form particles by fracture.

[0007] As an practicable method, forming an exfoliation layer on the second dielectric sublayer includes: placing a wafer formed with the second dielectric layer in a vapor deposition device and heating it to a preset temperature, so that the first metal wiring layer and the first dielectric layer release stress at the preset temperature to form particles; introducing a reaction gas into the vapor deposition device; turning on the radio frequency signal of the vapor deposition device, so that the reaction gas forms plasma and is deposited on the upper surface of the second dielectric layer to form an exfoliation layer, and the exfoliation layer wraps the particles to form exfoliation impurities.

[0008] As an practicable manner, a high-density plasma process is used to form the first dielectric sub-layer; and a thin film deposition process of ultra-pure silicon dioxide material is used to form the second dielectric sub-layer.

[0009] As an implementable manner, the first dielectric sub-layer and the second dielectric sub-layer are both silicon oxide layers, and the third dielectric layer is a silicon nitride layer.

[0010] As an practicable manner, the thickness ratio of the third dielectric layer to the exfoliation layer is between 5.5:1 and 6.5:1.

[0011] As a practical approach, the thickness of the exfoliated layer is between 950Å and 1050Å.

[0012] As an implementable method, a first dielectric layer and a first metal wiring layer are sequentially formed on a wafer, including: forming a first dielectric layer on the wafer; etching the first dielectric layer to form a through hole and forming a first metal layer on the first dielectric layer, the first metal layer filling the through hole to form a conductive column; chemically mechanically polishing the first metal layer to expose the upper surface of the first dielectric layer; forming a second metal layer on the first dielectric layer and patterning to form a first metal wiring layer, the first metal wiring layer being connected to the conductive column.

[0013] As an implementable manner, after a third dielectric layer and a second metal wiring layer are sequentially formed on the upper surface of the structure to be wired, the method for preparing a semiconductor device further includes: photolithographically forming grooves on the structure to be wired having the third dielectric layer formed thereon, the grooves isolating an effective area and an edge area; and alloying the structure to be wired having the grooves formed thereon.

[0014] On the other hand, an embodiment of the present application provides a semiconductor device, which is prepared by the above-mentioned semiconductor device preparation method, including a wafer and a first dielectric layer, a first metal wiring layer, a second dielectric layer, a third dielectric layer and a second metal wiring layer formed in sequence on the wafer, the wafer including multiple chips, and the chips, the first metal wiring layer and the second metal wiring layer are connected in sequence.

[0015] The beneficial effects of the embodiments of the present application include:

[0016] The preparation method of the semiconductor device provided by the present application includes providing a wafer, the wafer including an effective area and an edge area located at the periphery of the effective area, and the effective area has multiple wafers; forming a first dielectric layer and a first metal wiring layer on the wafer in sequence, the first metal wiring layer penetrates the first dielectric layer and is connected to the wafer; forming a second dielectric layer and a peeling layer in sequence on the first metal wiring layer to form a structure to be wired, heating is performed to release the stress between the first metal wiring layer and the first dielectric layer when forming the peeling layer, and the particles are formed by breaking, and the peeling layer in the edge area wraps the particles to form peeling impurities, and the peeling layer is formed in an environment with a certain temperature, and the higher temperature increases the thermal stress between the first metal wiring layer and the first dielectric layer, and the hierarchical structure is broken to form particles, at this time, the peeling layer is formed on the particles to wrap the particles, and has a certain fixing effect on the particles. It is prevented that the particles fall onto the wafer surface or the processing equipment, affecting the normal operation of the wafer or the processing equipment. Cleaning the structure to be wired to remove the peeling impurities; forming a third dielectric layer and a second metal wiring layer in sequence on the upper surface of the structure to be wired, and the second metal wiring penetrates the third dielectric layer and the second dielectric layer and is connected to the first metal wiring layer. After the stripping impurities are removed from the edge area of ​​the wafer, a third dielectric layer is formed on the upper surface of the structure to be wired. Since the stripping layer has released stress, there is no stress when the third dielectric layer is formed, thereby avoiding the generation of stripping defects in subsequent processes. That is, the present application implements the method of releasing stress in advance and removing stripping impurities, thereby releasing stress in advance, thereby avoiding the stripping defects of the finished wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 A flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application;

[0019] Figure 2 One of the state diagrams of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0020] Figure 3 A second state diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0021] Figure 4 A third state diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0022] Figure 5A fourth state diagram of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0023] Figure 6 This is a fifth state diagram of a method for preparing a semiconductor device provided in an embodiment of the present application.

[0024] Icons: 110 - wafer; 111 - effective area; 112 - edge area; 120 - first dielectric layer; 130 - first metal wiring layer; 140 - second dielectric layer; 150 - peeling layer; 160 - third dielectric layer; 170 - second metal wiring layer. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0026] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0027] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0028] In the description of this application, it should be noted that the terms "center", "vertical", "horizontal", "inside", "outside", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, or the positions or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0029] The wafer preparation process includes cleaning and oxidation at the front end, photolithography, etching and doping in the middle, and film formation and metal interconnection at the back end. During the film formation and metal interconnection process at the back end, the edge area of ​​the wafer is prone to layer shedding due to the stacking of film layers, forming shedding defects. The shedding particles fall into the effective area of ​​the wafer, affecting the operation of the wafer, or fall into the production equipment, causing pollution to the production equipment.

[0030] The applicant's research shows that the reason for the detachment defect is that in the back-end process, the metal wiring layer and the dielectric layer are alternately arranged to lead out the connection points of the chip. In the edge area, there is no wiring structure, so the metal material and the dielectric material are alternately arranged. Since the materials of the metal wiring layer and the dielectric layer are different, the thermal expansion coefficients are different. When the second dielectric layer is formed, heating is required. The thermal stress between the first metal wiring layer and the first dielectric layer is different. When the thermal stress is large, the edge area is prone to curling, causing detachment.

[0031] The present application provides a method for preparing a semiconductor device, which can prevent the edge region 112 from curling and falling off. Specifically, Figure 1 As shown, including:

[0032] S10: Figure 2 As shown, a wafer 110 is provided, the wafer 110 includes an active area 111 and an edge area 112 located at the periphery of the active area 111, and the active area 111 has a plurality of chips;

[0033] After the wafer 110 passes through the front section and the middle section, the wafer 110 has an effective area 111 and an edge area 112, wherein the effective area 111 has a plurality of wafers, and the wafer, as a predecessor of a chip, has an independent working mode and input and output.

[0034] S20: Figure 3 As shown, a first dielectric layer 120 and a first metal wiring layer 130 are sequentially formed on a wafer 110, and the first metal wiring layer 130 penetrates the first dielectric layer 120 and is connected to the wafer;

[0035] The first metal wiring layer 130 penetrates the first dielectric layer 120 and is connected to the wafer so as to lead the connection points of the wafer to the first metal wiring layer 130. Figure 3 As shown, the first metal wiring layer 130 forms a plurality of connection points in the effective area 111. When the first metal wiring layer 130 is formed, the metal in the edge area 112 is not etched, that is, in the edge area 112, the first metal wiring layer 130 and the first dielectric layer 120 cover the entire edge area 112. Since the materials of the two-layer structure are different, the thermal expansion coefficients are correspondingly different, so that there is a certain stress between the two.

[0036] In practical applications, the positions of the first dielectric layer 120 and the first metal wiring layer 130 may also be swapped, and the first metal wiring layer 130 may be formed on the wafer 110 to lead the connection points of the wafer to the surface of the wafer.

[0037] S30: Figure 4 and Figure 5 As shown, a second dielectric layer 140 and a peeling layer 150 are sequentially formed on the first metal wiring layer 130 to form a structure to be wired. When the peeling layer 150 is formed, heat is applied to release the stress between the first metal wiring layer 130 and the first dielectric layer 120 to form particles. The peeling layer 150 in the edge region 112 wraps the particles to form peeling impurities.

[0038] In the embodiment of the present application, the peeling layer 150 is used to release the stress between the first metal wiring layer 130 and the first dielectric layer 120. Specifically, the peeling layer 150 is formed in an environment with a certain temperature. The higher temperature increases the thermal stress between the first metal wiring layer 130 and the first dielectric layer 120. When the thermal stress is greater than the surface tension, the hierarchical structure breaks to form particles. At this time, the peeling layer 150 is formed on the particles to wrap the particles and has a certain fixing effect on the particles. This prevents the particles from falling onto the wafer surface or into the processing equipment, affecting the normal operation of the wafer or the processing equipment.

[0039] It should be noted that during the formation of the exfoliation layer 150 , the stress between all layers under the exfoliation layer 150 will be released. In the embodiment of the present application, the exfoliation layer 150 releases the stress between the first lithium metal wiring layer, the first dielectric layer 120 and the second dielectric layer 140 .

[0040] S40: cleaning the structure to be wired to remove stripping impurities;

[0041] The specific cleaning method is not limited in the embodiment of the present application, as long as the stripping impurities can be removed. For example, a washing tower can be used for cleaning.

[0042] S50: Figure 6 As shown, a third dielectric layer 160 and a second metal wiring layer 170 are sequentially formed on the upper surface of the structure to be wired, and the second metal wiring penetrates the third dielectric layer 160 and the second dielectric layer 140 to connect with the first metal wiring layer 130 .

[0043] After the stripping impurities are removed from the edge region 112 of the wafer 110, a third dielectric layer 160 is formed on the upper surface of the structure to be wired. Since the stress of the peeling layer 150 has been released, there is no stress when the third dielectric layer 160 is formed, thereby avoiding the generation of peeling defects in subsequent processes.

[0044] The third dielectric layer 160 , the peeling layer 150 and the second dielectric layer 140 serve as a second dielectric layer between the first metal wiring layer 130 and the second metal wiring layer 170 .

[0045] It is understandable that, since the stripping impurities are removed, there will inevitably be some unevenness in the edge area 112 . When the third dielectric layer 160 is formed, the third dielectric layer 160 fills the unevenness, that is, the removal of the stripping impurities does not affect the flatness of the wafer 110 .

[0046] It should be noted that in actual applications, including multiple metal wiring layers and dielectric layers alternately arranged at intervals, technical personnel in this field can set the number of second dielectric layers and second metal wiring layers according to actual conditions, as long as the stress between the previous dielectric layer and the metal wiring layer is released when the next dielectric layer is formed.

[0047] The method for preparing a semiconductor device provided by the present application is to heat the peeling layer 150 when forming it to release the stress between the first metal wiring layer 130 and the first dielectric layer 120 to break and form particles. The peeling layer 150 in the edge region 112 wraps the particles to form peeling impurities. The peeling layer 150 is formed in an environment with a certain temperature. The higher temperature increases the thermal stress between the first metal wiring layer 130 and the first dielectric layer 120, and the hierarchical structure breaks to form particles. At this time, the peeling layer 150 is formed on the particles to wrap the particles, which has a certain fixing effect on the particles. It prevents the particles from falling onto the wafer surface or into the processing equipment, affecting the normal operation of the wafer or the processing equipment. After the peeling impurities are removed from the edge region 112 of the wafer 110, a third dielectric layer 160 is formed on the upper surface of the structure to be wired. Since the peeling layer 150 has released the stress, there is no stress when the third dielectric layer 160 is formed, thereby avoiding the generation of peeling defects in subsequent processes. That is, the present application implements a method of releasing stress in advance and removing stripping impurities, thereby releasing stress in advance, thereby avoiding the falling-off defect of the finished wafer 110.

[0048] Optionally, forming a second dielectric layer 140 and a peeling layer 150 in sequence on the first metal wiring layer 130 to form a structure to be wired includes:

[0049] S31: forming a first dielectric sublayer on the first metal wiring layer 130;

[0050] S32: forming a second dielectric sublayer on the first dielectric sublayer, wherein the first dielectric sublayer and the second dielectric sublayer are made of the same material;

[0051] The first dielectric sublayer and the second dielectric sublayer are formed twice and can be formed by different process methods. For example, the first dielectric sublayer is formed by a high-density plasma process; the second dielectric sublayer is formed by a thin film deposition process of ultra-pure silicon dioxide material. In this way, in the subsequent flattening process, it is easier to make the surface of the wafer 110 flat.

[0052] S33: grinding the second dielectric sublayer to a preset thickness by mechanical chemical grinding;

[0053] S34: forming a peeling layer 150 on the ground second dielectric sub-layer, and applying heat during the formation of the peeling layer 150 to release stress fracture between the first metal wiring layer 130 and the first dielectric layer 120 to form particles.

[0054] In one achievable manner of the embodiment of the present application, forming the exfoliation layer 150 on the second dielectric sublayer includes:

[0055] S341: placing the wafer 110 formed with the second dielectric layer 140 in a vapor deposition device and heating it to a preset temperature, so that the first metal wiring layer 130 and the first dielectric layer 120 release stress at the preset temperature to form particles;

[0056] The specific heating temperature is not limited in the embodiment of the present application, and those skilled in the art may make specific settings according to the materials of the first dielectric layer 120 and the first metal wiring layer 130 , as long as the stress is released as much as possible without affecting the structure of the wafer 110 .

[0057] S342: introducing a reaction gas into the vapor deposition device;

[0058] S343: Turn on the radio frequency signal of the vapor deposition equipment, so that the reaction gas forms plasma and is deposited on the upper surface of the second dielectric layer 140 to form a peeling layer 150, and the peeling layer 150 wraps the particles to form peeling impurities.

[0059] The exfoliation layer 150 wraps and exfoliates impurities, preventing particles from falling onto the wafer surface or into processing equipment, thereby affecting the normal operation of the wafer or processing equipment.

[0060] Optionally, the first dielectric sub-layer is formed by a high-density plasma process; and the second dielectric sub-layer is formed by a thin film deposition process of ultra-pure silicon dioxide material.

[0061] The high-density plasma process can form a thin film with low defect density, so that the first dielectric layer 120 has good uniformity and consistency. The thin film deposition process of ultra-pure silicon dioxide material can reduce impurities and defects in the second dielectric sub-layer and improve purity.

[0062] In one implementable manner of the embodiment of the present application, the first dielectric sub-layer and the second dielectric sub-layer are both silicon oxide layers, and the third dielectric layer 160 is a silicon nitride layer.

[0063] Optionally, the thickness ratio of the third dielectric layer 160 to the exfoliation layer 150 is between 5.5:1 and 6.5:1.

[0064] As can be seen from the foregoing, the exfoliation layer 150 is used to wrap the broken particles, that is, the exfoliation layer 150 only needs to be able to wrap the particles, so the exfoliation layer 150 is set to be thinner. Specifically, the third dielectric layer 160 is a layer deposited on the exfoliation layer 150, and the thickness ratio of the third dielectric layer 160 to the exfoliation layer 150 is set between 5.5:1-6.5:1, and for example, it can be 6:1.

[0065] In one achievable manner of the embodiment of the present application, the thickness of the exfoliation layer 150 is between 950Å and 1050Å.

[0066] As can be seen from the foregoing, the exfoliation layer 150 is used to wrap the broken particles. Therefore, in order to avoid the influence of the exfoliation layer 150 on the entire second dielectric layer, the embodiment of the present application sets the thickness of the exfoliation layer 150 between 950Å-1050Å, and for example, it can be 1000Å. In this way, on the basis of achieving the wrapping of the particles, the thickness of the exfoliation layer 150 is made as thin as possible to avoid the thickness of the exfoliation layer 150 affecting the second dielectric layer.

[0067] Optionally, forming a first dielectric layer 120 and a first metal wiring layer 130 in sequence on the wafer 110 includes:

[0068] S21: forming a first dielectric layer 120 on the wafer 110;

[0069] S22: etching the first dielectric layer 120 to form a through hole and forming a first metal layer on the first dielectric layer 120, wherein the first metal layer fills the through hole to form a conductive column;

[0070] S23: performing chemical mechanical polishing on the first metal layer to expose the upper surface of the first dielectric layer 120;

[0071] S24: forming a second metal layer on the first dielectric layer 120 and patterning the second metal layer 130 to form a first metal wiring layer 130 , wherein the first metal wiring layer 130 is connected to the conductive pillars.

[0072] The first metal wiring layer 130 is connected to the wafer through conductive pillars.

[0073] In one achievable manner of the embodiment of the present application, after the third dielectric layer 160 and the second metal wiring layer 170 are sequentially formed on the upper surface of the structure to be wired, the method for preparing a semiconductor device further includes:

[0074] S51: forming a trench by photolithography on the structure to be wired with the third dielectric layer 160, wherein the trench isolates the effective area 111 and the edge area 112;

[0075] S52: Alloying the structure to be wired with the grooves formed therein.

[0076] The embodiment of the present application also discloses a semiconductor device, which is prepared by the above-mentioned method for preparing a semiconductor device, and includes a wafer 110 and a first dielectric layer 120, a first metal wiring layer 130, a second dielectric layer 140, a third dielectric layer 160 and a second metal wiring layer 170 formed sequentially on the wafer 110, wherein the wafer 110 includes a plurality of wafers, and the wafers, the first metal wiring layer 130 and the second metal wiring layer 170 are connected sequentially. In the embodiment of the present application, when the third dielectric layer 160 is formed, the stress between the first dielectric layer 120 and the first metal wiring layer 130 is released, so when the third dielectric layer 160 is formed, the stress between the third dielectric layer 160 and the second dielectric layer 140 is reduced, thereby reducing the shedding defect of the edge region 112 of the semiconductor device caused by the stress, and improving the defect of the product.

[0077] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a wafer, the wafer comprising an effective area and an edge area located outside the effective area, wherein the effective area has a plurality of chips; forming a first dielectric layer and a first metal wiring layer on the wafer in sequence, wherein the first metal wiring layer penetrates the first dielectric layer and is connected to the wafer; A second dielectric layer and a peeling layer are sequentially formed on the first metal wiring layer to form a to-be-wired structure, and when forming the peeling layer, heating is performed to release stress between the first metal wiring layer and the first dielectric layer, and the first metal wiring layer and the first dielectric layer are broken to form particles, and the peeling layer in the edge area wraps the particles to form peeling impurities; Cleaning the structure to be wired to remove the stripping impurities; A third dielectric layer and a second metal wiring layer are sequentially formed on the upper surface of the structure to be wired, and the second metal wiring layer penetrates the third dielectric layer and the second dielectric layer to be connected to the first metal wiring layer.

2. The preparation method according to claim 1, characterized in that: The step of sequentially forming a second dielectric layer and a peeling layer on the first metal wiring layer to form a structure to be wired comprises: forming a first dielectric sublayer on the first metal wiring layer; forming a second dielectric sublayer on the first dielectric sublayer, wherein the first dielectric sublayer and the second dielectric sublayer are made of the same material; grinding the second dielectric sublayer to a preset thickness by mechanical chemical grinding; A peeling layer is formed on the ground second dielectric sub-layer, and heating is performed during the formation of the peeling layer to release stress between the first metal wiring layer and the first dielectric layer, and the first metal wiring layer and the first dielectric layer are broken into particles.

3. The preparation method according to claim 2, characterized in that: The forming of the peeling layer on the second dielectric sub-layer after grinding comprises: Placing the wafer formed with the second dielectric layer in a vapor deposition device and heating it to a preset temperature, so that the first metal wiring layer and the first dielectric layer release stress at the preset temperature, and the first metal wiring layer and the first dielectric layer are broken to form particles; introducing a reaction gas into the vapor deposition device; The radio frequency signal of the vapor deposition device is turned on, so that the reaction gas forms plasma and is deposited on the upper surface of the second dielectric layer to form a peeling layer, and the peeling layer wraps the particles to form peeling impurities.

4. The preparation method according to claim 2, characterized in that: The first dielectric sub-layer is formed by adopting a high-density plasma process; and the second dielectric sub-layer is formed by adopting a thin film deposition process of ultra-pure silicon dioxide material.

5. The preparation method according to claim 4, characterized in that: The first dielectric sublayer and the second dielectric sublayer are both silicon oxide layers, and the third dielectric layer is a silicon nitride layer.

6. The preparation method according to claim 1, characterized in that: The thickness ratio of the third dielectric layer to the exfoliation layer is between 5.5:1 and 6.5:

1.

7. The preparation method according to claim 6, characterized in that: The thickness of the exfoliated layer is between 950Å and 1050Å.

8. The preparation method according to claim 1, characterized in that: The step of sequentially forming a first dielectric layer and a first metal wiring layer on the wafer comprises: forming a first dielectric layer on the wafer; Etching the first dielectric layer to form a through hole and forming a first metal layer on the first dielectric layer, wherein the first metal layer fills the through hole to form a conductive column; Performing chemical mechanical polishing on the first metal layer to expose the upper surface of the first dielectric layer; A second metal layer is formed on the first dielectric layer and patterned to form a first metal wiring layer, wherein the first metal wiring layer is connected to the conductive pillar.

9. The preparation method according to claim 8, characterized in that: After sequentially forming a third dielectric layer and a second metal wiring layer on the upper surface of the structure to be wired, the method further comprises: Photolithography forms a groove on the structure to be wired with the third dielectric layer, wherein the groove isolates the effective area and the edge area; The structure to be wired in which the trench is formed is alloyed.

10. A semiconductor device, characterized in that: A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising a wafer and a first dielectric layer, a first metal wiring layer, a second dielectric layer, a third dielectric layer and a second metal wiring layer formed sequentially on the wafer, wherein the wafer comprises a plurality of chips, and the chips, the first metal wiring layer and the second metal wiring layer are connected sequentially.

Images