Chip packaging structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a chip packaging structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of chip packaging, and aims to solve the problems that when a plurality of bare chips are stacked in the chip packaging structure, the mechanical property of the chip packaging structure is reduced, the overall strength is reduced, and the bending deformation resistance becomes poor. The chip packaging structure comprises a substrate, a plurality of bare chips, a spacing layer and a packaging layer, the plurality of bare chips are stacked in a staggered manner in a direction perpendicular to the substrate; the spacing layer is arranged on one side, far away from the substrate, of the plurality of bare chips; the packaging layer is positioned on the substrate and surrounds the spacing layer and the plurality of bare chips; wherein the elastic modulus of the spacing layer is greater than that of the packaging layer; and / or the plasticity of the spacing layer is greater than that of the encapsulation layer. The chip packaging structure can be applied to a storage system so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of chip packaging technology, and in particular to a chip packaging structure and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] Some semiconductor chips (e.g., flash memory) have been widely used for data storage. Users of these semiconductor chips expect that data storage capacity will continue to grow, and manufacturers strive to provide larger storage capacity in a low-cost manner while maintaining a standard package size to ensure compatibility with existing electronic devices. Summary of the invention

[0003] Embodiments of the present disclosure provide a chip packaging structure and a method for preparing the same, a storage system, and an electronic device, aiming to improve the overall strength of the chip packaging structure and its ability to resist bending and deformation.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] In one aspect, a chip packaging structure is provided. The chip packaging structure includes a substrate, a plurality of bare chips, a spacer layer, and a packaging layer. The plurality of bare chips are stacked in a staggered manner in a direction perpendicular to the substrate; the spacer layer is disposed on a side of the plurality of bare chips away from the substrate; and the packaging layer is disposed on the substrate and surrounds the spacer layer and the plurality of bare chips. The elastic modulus of the spacer layer is greater than the elastic modulus of the packaging layer; and / or the plasticity of the spacer layer is greater than the plasticity of the packaging layer.

[0006] The chip packaging structure provided by the above-mentioned embodiments of the present disclosure, by arranging a spacer layer on the side of the multiple bare chips away from the substrate, and the elastic modulus of the spacer layer is greater than the elastic modulus of the packaging layer; and / or the plasticity of the spacer layer is greater than the plasticity of the packaging layer, the tensile stress on the bare chips adjacent to the spacer layer under the action of positive bending can be reduced, so that the chip packaging structure can resist greater deformation, and the ability of the chip packaging structure to resist external loads can be improved, that is, such a design improves the mechanical properties of the chip packaging structure, and improves the overall strength of the chip packaging structure and the ability to resist bending deformation.

[0007] In some embodiments, the elastic modulus of the spacer layer is 100 GPa-500 GPa. Since the spacer layer has a higher elastic modulus, it is beneficial to improve the overall ability of the chip packaging structure to resist external loads and bending deformation.

[0008] In some embodiments, the plastic strain of the spacer layer is greater than or equal to 0.5%. Since the spacer layer has a higher plastic strain, it is beneficial to improve the ability of the chip packaging structure to resist fracture in a high stress area.

[0009] In some embodiments, the bonding strength between the spacer layer and the packaging layer is greater than or equal to the bonding strength between the plurality of bare chips and the packaging layer, which can prevent the bonding interface between the spacer layer and the packaging layer from separating when the chip packaging structure is bent under force.

[0010] In some embodiments, the thermal expansion coefficient of the spacer layer is greater than or equal to the thermal expansion coefficient of the bare chip, and less than or equal to the thermal expansion coefficient of the packaging layer. This can reduce the stress generated during the manufacturing process of the chip packaging structure, thereby reducing the risk of cracking at the connection interface between the packaging layer and the spacer layer, and the connection interface between the spacer layer and the bare chip in the chip packaging structure, which is beneficial to improving the stability of the chip packaging structure.

[0011] In some embodiments, the material of the spacer layer includes metal.

[0012] In some embodiments, the surface of the spacer layer away from the substrate is at least partially flush with the surface of the packaging layer away from the substrate; or, the surface of the spacer layer away from the substrate is lower than the surface of the packaging layer away from the substrate, and the packaging layer covers the surface of the spacer layer away from the substrate. As the thickness of the spacer layer increases, the maximum tensile stress on the die adjacent to the spacer layer decreases, the chip packaging structure has a stronger ability to resist external loads, and has a higher ability to resist bending deformation.

[0013] In some embodiments, the spacer layer and the die farthest from the substrate among the plurality of dies have the same shape and are equal in size.

[0014] In some embodiments, the stacking mode between the spacer layer and the die farthest from the substrate among the multiple dies is staggered stacking, which is beneficial to expose the die bonding pads set on the top surface of the die, and facilitate the use of the die bonding pads for further wire bonding.

[0015] In some embodiments, the chip packaging structure further includes: a first adhesive film and a second adhesive film, wherein the first adhesive film is used to connect the substrate and the plurality of bare chips, and any two adjacent bare chips; the second adhesive film is used to connect the bare chips and the spacer layer; wherein the first adhesive film and the second adhesive film are made of the same material. The first adhesive film and the second adhesive film are provided to connect and fix the substrate, the bare chips and the spacer layer, which is conducive to improving the stability of the chip packaging structure.

[0016] On the other hand, a method for preparing a chip packaging structure is provided, comprising: staggeredly stacking a plurality of bare chips in a vertical direction of a substrate; stacking a spacer layer on a side of the plurality of bare chips away from the substrate; and forming a packaging layer on the substrate to surround the plurality of bare chips and the spacer layer.

[0017] In some embodiments, the method for preparing the chip packaging structure further includes: disposing a first adhesive film between the substrate and the plurality of bare chips, and between any two adjacent bare chips; and disposing a second adhesive film between the bare chip and the spacer layer.

[0018] On the other hand, a storage system is provided, comprising: the chip packaging structure as described above and a controller; the controller is electrically connected to the chip packaging structure.

[0019] On the other hand, an electronic device is provided, comprising: a processor and the storage system as described above, wherein the processor is coupled to the storage system; or comprising: a printed circuit board, and the chip packaging structure as described above, wherein the chip packaging structure is arranged on the printed circuit board and electrically connected to the printed circuit board.

[0020] It can be understood that the beneficial effects that can be achieved by the chip packaging structure preparation method, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the chip packaging structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0022] Figure 1 A structural diagram of a chip packaging structure provided according to some embodiments;

[0023] Figure 2 A structural diagram of a chip packaging structure provided in the related art;

[0024] Figure 3 A schematic diagram of the stress of a chip packaging structure provided according to some embodiments;

[0025] Figure 4 A comparison diagram of spacer layers with different elastic moduli and applied pressure at the same deflection according to some embodiments;

[0026] Figure 5 A comparison diagram of the maximum tensile stresses exerted on the spacer layer and the top die with different elastic moduli under the same deflection according to some embodiments;

[0027] Figure 6 A comparison diagram of spacer layers of different thicknesses and applied pressures at the same deflection provided according to some embodiments;

[0028] Figure 7A comparison diagram of the maximum tensile stresses on the spacer layers and the top die with different thicknesses at the same deflection according to some embodiments;

[0029] Figure 8 Another structural diagram of a chip packaging structure provided according to some embodiments;

[0030] Fig. 9 is another structural diagram of a chip packaging structure provided according to some embodiments;

[0031] Fig.10 A structural diagram of a storage system provided according to some embodiments;

[0032] Fig.11 A structural diagram of an electronic device provided according to some embodiments;

[0033] Fig.12 is another structural diagram of an electronic device provided according to some embodiments;

[0034] Fig.13 The present invention is a flow chart of a method for preparing a chip packaging structure according to some embodiments. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0036] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0037] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0038] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0039] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0040] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0041] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of ​​the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0042] The bare die involved in the embodiments of the present disclosure is a device that has not been packaged after the wafer has been cut and tested. This bare die has a pad for packaging and may not be directly applied to an actual circuit. When the bare die is packaged into a semiconductor chip, it can be applied to an actual circuit.

[0043] The above-mentioned bare chips may include NAND type flash memory bare chips, DRAM (dynamic random access memory) bare chips and SRAM (static random access memory) bare chips, etc.

[0044] By stacking multiple semiconductor dies (which can be expressed as Die in English) in a single chip package structure, the storage density of a single chip package structure can be increased. Compared with a single die, the increase in the number of dies will correspondingly increase the storage capacity. Figure 2 As shown, multiple dies 3 can be stacked on the substrate 2 in a vertically offset manner, that is, each die 3 is offset in a certain direction by a certain distance in turn, so that the orthographic projections of the multiple dies 3 on the substrate 2 do not completely overlap, so as to ensure that the die bonding points set on the top surface of each die 3 are exposed, so as to be used for further wire bonding. However, when the number of dies 3 is large, offsetting in one direction may cause the multiple stacked dies 3 to become unstable, which will further reduce the overall strength of the chip packaging structure 10' and deteriorate the ability to resist bending deformation.

[0045] Based on this, in order to improve the overall strength of the chip packaging structure and the ability to resist bending deformation, the embodiment of the present disclosure provides a chip packaging structure 10.

[0046] Figure 1A structural diagram of a chip packaging structure 10 provided in some embodiments of the present disclosure. The chip packaging structure 10 includes a substrate 2, a plurality of bare chips 3, a spacer layer 5 and a packaging layer 1. The plurality of bare chips 3 are stacked in a direction perpendicular to the substrate 2, and the substrate 2 is used to carry the plurality of bare chips 3. It should be noted that, as Figure 1 As shown, two dies 3 are stacked vertically on a substrate 2, and the die 3 away from the substrate 2 (hereinafter collectively referred to as the top die 3 for ease of description) is offset in a certain direction by a certain distance relative to the die 3 located below it. However, based on actual needs, the number of dies 3 attached to the substrate 2 may not be limited to two, and the dies 3 may be stacked vertically on each other and / or spaced apart laterally, and each die 3 may be offset in a certain direction by a certain distance in turn.

[0047] Please continue to refer to Figure 1 , the spacer layer 5 is arranged on the side of the plurality of bare chips 3 away from the substrate 2; the encapsulation layer 1 is located on the substrate 2 and surrounds the spacer layer 5 and the plurality of bare chips 3; the encapsulation layer 1 is arranged outside the bare chips 3 by covering them. On the one hand, the encapsulation layer 1 can increase the strength of the chip encapsulation structure 10; on the other hand, the encapsulation layer 1 can also protect the bare chips 3 in the chip encapsulation structure 10, so that the bare chips 3 are not affected by the external environment (water vapor, temperature, pollution, etc.).

[0048] Exemplarily, the encapsulation layer 1 may include epoxy resin, expansion monomer and curing agent.

[0049] Exemplarily, the shape of the encapsulation layer 1 can be a cuboid, a cylinder, etc. When the encapsulation layer 1 is in a cuboid or a cylinder, the shape of the substrate 2 also matches the shape of the encapsulation layer 1. Specifically, the substrate 2 and the encapsulation layer 1 can be cut into a cylinder or a cuboid in the cutting process, and the final product shape is formed. The shape of the product after cutting is not specifically limited in this application.

[0050] The elastic modulus of the spacer layer 5 is greater than the elastic modulus of the encapsulation layer 1 ; and / or the plasticity of the spacer layer 5 is greater than the plasticity of the encapsulation layer 1 .

[0051] It can be understood that the elastic modulus represents the stiffness of the material and is an indicator of the material's ability to resist elastic deformation. The smaller the elastic modulus, the easier it is to deform after being subjected to external force. Plasticity refers to the ability of an object to deform. The greater the plasticity of an object, the smaller the minimum force required for permanent deformation.

[0052] By arranging a spacer layer 5 on a side of the plurality of bare chips 3 away from the substrate 2, and the elastic modulus of the spacer layer 5 is greater than the elastic modulus of the packaging layer 1; and / or the plasticity of the spacer layer 5 is greater than the plasticity of the packaging layer 1, the tensile stress on the bare chip 3 adjacent to the spacer layer 5 (i.e., the top bare chip 3) under the action of positive bending can be reduced, so that the chip packaging structure 10 can resist greater deformation, and the ability of the chip packaging structure 10 to resist external loads can be improved, that is, such a design improves the mechanical properties of the chip packaging structure 10, and improves the overall strength and the ability of the chip packaging structure 10 to resist bending deformation.

[0053] Figure 2 A structural diagram of a chip packaging structure 10' provided in the related art, Figure 3 FIG. 1 is a schematic diagram of the force acting on a chip package structure 10 provided according to some embodiments. Figure 2 and Figure 3 In the figure, the arrows point to the stress positions of the chip package structure 10 or 10' in the three-point bending test, and the AA layer represents the neutral layer of the die 3 (ie, the top die 3) in the chip package structure 10 or 10' which is farthest from the substrate 2 when subjected to stress bending.

[0054] It should be noted that the three-point bending test refers to placing the object to be tested on two supporting points at a certain distance, applying a downward load to the object to be tested above the midpoint between the two supporting points, and three-point bending occurs when the three contact points of the object to be tested form two equal moments. The three-point bending test can be used to test the mechanical properties of the object to be tested.

[0055] During the stress bending process of the chip packaging structure 10 or 10', the side of the top-layer bare die 3 in the chip packaging structure 10 or 10' away from the substrate 2 is stretched (for the sake of simplicity, it is collectively referred to as the tensile surface 3a below), and the side close to the substrate 2 is squeezed (for the sake of simplicity, it is collectively referred to as the compressive surface 3b below). There is a transition layer between the tensile surface 3a and the compressive surface 3b that is neither tensile nor compressive, and the stress is almost zero. The transition layer here is the aforementioned neutral layer AA.

[0056] like Figure 2 and Figure 3 As shown, in the three-point bending test, Figure 2 The distance between the neutral layer AA of the middle and top die 3 and the tension surface 3a is large. Figure 3The distance between the neutral layer AA of the top bare chip 3 and the tension surface 3a is relatively small. Therefore, when a spacer layer 5 is provided on the side of the plurality of bare chips 3 away from the substrate 2, and the elastic modulus of the spacer layer 5 is greater than the elastic modulus of the encapsulation layer 1; and / or the plasticity of the spacer layer 5 is greater than the plasticity of the encapsulation layer 1, the position of the neutral layer AA of the top bare chip 3 can be changed, so that the distance between the neutral layer AA and the tension surface 3a is reduced. Since the closer the tension surface 3a is to the neutral layer AA, the smaller the tensile stress on the tension surface 3a, the bare chip 3 adjacent to the spacer layer 5 (i.e., the top bare chip 3) is subjected to a decrease in tensile stress under the positive bending action, so that the chip packaging structure 10 can resist greater deformation when performing a three-point bending test, and the ability of the chip packaging structure 10 to resist external loads can be improved. It can be understood that the adoption of such a design improves the overall strength and the ability to resist bending deformation of the chip packaging structure 10.

[0057] In some embodiments, the elastic modulus of the spacer layer 5 is 100 GPa-500 GPa.

[0058] Exemplarily, the elastic modulus of the spacer layer 5 may be 100 Gpa, 200 Gpa, 250 Gpa, 300 Gpa, 400 Gpa or 500 Gpa.

[0059] Exemplarily, two bare chips 3 are stacked in the chip packaging structure 10 as an example for illustration. Figure 4 A comparison diagram of the spacer layers 5 with different elastic moduli and the applied pressure when the deflection of the chip packaging structure 10 provided in some embodiments is the same; Figure 5 The figure is a comparison diagram of the maximum tensile stresses exerted on the spacer layer 5 and the top die 3 with different elastic moduli when the deflection of the chip package structure 10 provided according to some embodiments is the same.

[0060] It should be noted that the deflection of the chip packaging structure 10 refers to the linear displacement of the centroid of the cross section along the direction perpendicular to the axis when the chip packaging structure 10 is bent and deformed. The centroid of the cross section refers to the geometric center of the cross section figure.

[0061] like Figure 4 As shown, when the deflection of the chip packaging structure 10 is the same, as the elastic modulus of the spacer layer 5 increases, in order to make the chip packaging structure 10 reach the same deflection, the pressure applied to the chip packaging structure 10 also increases. Figure 5 As shown, when the deflection of the chip packaging structure 10 is the same, as the elastic modulus of the spacer layer 5 increases, the maximum tensile stress on the die 3 adjacent to the spacer layer 5 (i.e., the top die 3) decreases. In other words, when the deflection is the same, the larger the elastic modulus of the spacer layer 5, the smaller the maximum tensile stress on the die 3 adjacent to the spacer layer 5, and the stronger the overall ability of the chip packaging structure 10 to resist external loads and the higher the ability to resist bending deformation.

[0062] In some embodiments, the plastic strain of the spacer layer 5 is greater than or equal to 0.5%.

[0063] Exemplarily, the plastic strain of the spacer layer 5 is 0.5%, 0.6%, 0.8%, 1%, 1.2%, 2%, 3%, 5%, or 6%.

[0064] Plastic strain refers to the irreversible deformation of an object when an external force exceeds a certain value.

[0065] Since the spacer layer 5 has a relatively high plastic strain and elastic modulus, the chip packaging structure 10 can improve its ability to resist fracture in high stress areas, and further improve the overall strength and the ability to resist bending deformation of the chip packaging structure 10 .

[0066] In some embodiments, the bonding strength between the spacer layer 5 and the packaging layer 1 is greater than or equal to the bonding strength between the plurality of bare chips 3 and the packaging layer 1, which can avoid separation of the bonding interface between the spacer layer 5 and the packaging layer 1 when the chip packaging structure 10 is bent under force.

[0067] In some embodiments, the thermal expansion coefficient of the spacer layer 5 is greater than or equal to the thermal expansion coefficient of the die 3, and less than or equal to the thermal expansion coefficient of the encapsulation layer 1. It is understandable that the thermal expansion coefficient of the spacer layer 5 is between the thermal expansion coefficient of the die 3 and the thermal expansion coefficient of the encapsulation layer 1 and includes two end point values. Through the above-mentioned setting, the problem of excessive stress generated by heating and cooling during the manufacturing process of the chip packaging structure 10 can be improved, thereby reducing the risk of cracking of the connection interface between the encapsulation layer 1 and the spacer layer 5, and the connection interface between the spacer layer 5 and the die 3 in the chip packaging structure 10, which is conducive to improving the stability of the chip packaging structure 10.

[0068] In some embodiments, the material of the spacer layer 5 includes metal. For example, the metal may be tungsten, stainless steel, titanium alloy, and of course, other suitable metal materials may also be selected, and the present disclosure does not make any specific limitation on this.

[0069] The following is an example of stacking two bare chips 3 in the chip packaging structure 10 . Figure 6 A comparison diagram of the spacer layers 5 with different thicknesses and the applied pressure when the deflection of the chip packaging structure 10 provided in some embodiments is the same; Figure 7 The figure is a comparison diagram of the maximum tensile stresses exerted on the spacer layer 5 and the top die 3 with different thicknesses when the deflection of the chip package structure 10 provided according to some embodiments is the same.

[0070] It should be noted that the deflection of the chip packaging structure 10 represents the bending degree of the chip packaging structure 10 when it is bent and deformed.

[0071] like Figure 6 As shown, when the deflection of the chip packaging structure 10 is the same, as the thickness of the spacer layer 5 increases, in order to make the chip packaging structure 10 reach the same deflection, the pressure applied to the chip packaging structure 10 also increases. Figure 7 As shown in the figure, when the deflection of the chip packaging structure 10 is the same, as the thickness of the spacer layer 5 increases, the maximum tensile stress on the die 3 adjacent to the spacer layer 5 (i.e., the top die 3) decreases. In other words, under the same deflection, the thicker the spacer layer 5, the smaller the maximum tensile stress on the die 3 adjacent to the spacer layer 5, and the stronger the overall ability of the chip packaging structure 10 to resist external loads and the higher the ability to resist bending deformation.

[0072] Based on this, the thickness of the spacer layer 5 can be set according to actual needs.

[0073] For example, Figure 1 As shown, the side surface of the spacer layer 5 away from the substrate 2 can be set lower than the side surface of the encapsulation layer 1 away from the substrate 2, and the encapsulation layer 1 covers the side surface of the spacer layer 5 away from the substrate 2. It can be understood that the spacer layer 5 can be completely set in the encapsulation layer 1.

[0074] The side surface of the spacer layer 5 away from the substrate 2 can also be set to be at least partially flush with the side surface of the packaging layer 1 away from the substrate 2. In this case, the packaging layer 1 does not cover the side surface of the spacer layer 5 away from the substrate 2, but is arranged around the spacer layer 5 and the plurality of bare chips 3.

[0075] For example, Figure 8 As shown, part of the surface of the side of the spacer layer 5 away from the substrate 2 is flush with the surface of the side of the encapsulation layer 1 away from the substrate 2, and part of the surface is lower or higher than the surface of the side of the encapsulation layer 1 away from the substrate 2. It can be understood that the surface of the side of the spacer layer 5 away from the substrate 2 may be undulating or rough, so that the lower position of the surface of the side of the spacer layer 5 away from the substrate 2 may be lower than the surface of the side of the encapsulation layer 1 away from the substrate 2, and the higher position of the surface of the side of the spacer layer 5 away from the substrate 2 may be higher than the surface of the side of the encapsulation layer 1 away from the substrate 2. Of course, there may be some areas on the surface of the side of the spacer layer away from the substrate 2 that are flush with the surface of the side of the encapsulation layer 1 away from the substrate 2.

[0076] For example, Fig. 9 As shown, the surface of the spacer layer 5 away from the substrate 2 is completely flush with the surface of the packaging layer 1 away from the substrate 2 .

[0077] In some embodiments, the spacer layer 5 and the top die 3 among the multiple die 3 have the same shape and are equal in size, and the stacking method between the two is staggered stacking, which can expose the die bonding points set on the top surface of the top die 3, making it convenient to use the die bonding points for further wire bonding.

[0078] In some embodiments, Figure 1 As shown, the chip packaging structure 10 also includes: a first adhesive film 41 and a second adhesive film 42, the first adhesive film 41 is used to connect the substrate 2 and multiple bare chips 3, and any two adjacent bare chips 3; the second adhesive film 42 is used to connect the bare chips 3 and the spacer layer 5; wherein the first adhesive film 41 and the second adhesive film 42 are made of the same material.

[0079] Exemplarily, the first adhesive film 41 and the second adhesive film 42 may both be DAF (Die Attach Film) adhesive films.

[0080] Some embodiments of the present disclosure also provide a method for preparing a chip packaging structure 10, such as Fig.13 As shown, the preparation method comprises the following steps:

[0081] S1: stacking a plurality of bare chips 3 in a staggered manner in the vertical direction of the substrate 2 .

[0082] In some embodiments, each of the plurality of dies 3 is offset in a certain direction by a certain distance in turn, and the substrate 2 and the dies 3 and two adjacent dies 3 are connected via a first adhesive film 41 .

[0083] S2 : stacking a spacer layer 5 on a side of the plurality of bare chips 3 away from the substrate 2 .

[0084] In some embodiments, the stacking manner between the spacer layer 5 and the top die 3 is staggered stacking, and the second adhesive film 42 is used to connect the spacer layer 5 and the top die 3 .

[0085] S3 : forming a packaging layer 1 surrounding the plurality of bare chips 3 and the spacer layer 5 on the substrate 2 .

[0086] It should be noted that the elastic modulus, plasticity, bonding strength between the spacer layer 5 and the packaging layer 1, thermal expansion coefficient and material of the preparation method of the chip packaging structure 10 are the same as those of the spacer layer 5 in the aforementioned chip packaging structure 10, and will not be repeated here.

[0087] Exemplarily, the encapsulation layer 1 may include epoxy resin, expansion monomer, curing agent and the like.

[0088] Exemplarily, the process of forming the encapsulation layer 1 may be one of a compression molding process, a transfer molding process, a liquid sealant curing molding process, a vacuum lamination process, and a spin coating process.

[0089] Some embodiments of the present disclosure also provide a storage system 100. Fig.10 As shown, the storage system 100 includes: a controller 6 and a chip packaging structure 10 provided in any of the above embodiments. The bare die 3 in the chip packaging structure 10 may be a bare die including a storage array. The controller 6 may be electrically connected to the chip packaging structure 10 to control the chip packaging structure 10 to store data.

[0090] Exemplarily, the controller 6 is integrated with the chip packaging structure 10, the controller 6 is attached to the substrate 2, and the packaging layer 1 of the chip packaging structure 10 covers the controller 6. The controller 6 can also be arranged outside the chip packaging structure 10 and electrically connected to the chip packaging structure 10 through leads or a transfer layer.

[0091] The storage system 100 may be integrated into a memory card. The memory card includes, for example, any one of a PC card (Personal Computer Memory Card International Association, PCMCIA), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), and a UFS.

[0092] The storage system 100 can also be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the storage system 100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0093] In some embodiments, the controller 6 in the storage system 100 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0094] In other embodiments, the controller 6 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0095] In some embodiments, the controller 6 may be configured to manage data stored in the chip package structure 10 and communicate with an external device (eg, a host).

[0096] In some embodiments, the controller 6 may also be configured to control operations of the chip package structure 10 , such as read, erase, and program operations.

[0097] In some embodiments, the controller 6 may also be configured to manage various functions regarding data stored or to be stored in the chip package structure 10 , including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling.

[0098] In some embodiments, the controller 6 is further configured to process an error correction code on data read from or written to the chip package structure 10 .

[0099] Of course, the controller 6 may also perform any other suitable functions, such as formatting the chip package structure 10; for example, the controller 6 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0100] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0101] like Fig.11 and Fig.12As shown, the embodiment of the present disclosure further provides an electronic device 1000. The electronic device 1000 includes but is not limited to any one of a mobile phone, a tablet computer, a laptop, a television, a personal digital assistant (PDA), an ultra-mobile personal computer (UMPC), a netbook, a wearable device (such as a smart watch, a smart bracelet, smart glasses), etc. The embodiment of the present application does not limit the type of the electronic device.

[0102] In some embodiments, Fig.11 As shown, the electronic device 1000 may include the storage system 100 described above, and may also include a processor 7 , where the processor 7 is coupled to the storage system 100 to interact with the storage system 100 .

[0103] Exemplarily, the processor 7 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0104] In other embodiments, Fig.12 As shown, the electronic device 1000 further includes a printed circuit board 8 and a chip packaging structure 10 described in any of the above embodiments, and the chip packaging structure 10 is disposed on the printed circuit board 8 and electrically connected to the printed circuit board 8. Thus, the chip packaging structure 10 can realize signal transmission with other chips on the printed circuit board 8.

[0105] Exemplarily, one or more chip packaging structures 10 may be provided on the printed circuit board 8. In the case where multiple chip packaging structures 10 are provided on the printed circuit board 8, these chip packaging structures 10 may implement the same or different functions, for example, these chip packaging structures 10 may include a chip packaging structure 10 for logic operations, a chip packaging structure 10 with a storage function, etc.

[0106] Exemplarily, the chip package structure 10 can be electrically connected to the printed circuit board 8 via a ball grid array (BGA). In an optional embodiment, if the size of the chip package structure 10 is relatively large. In order to ensure the reliability of the electrical connection between the chip package structure 10 and the printed circuit board 8, a connection terminal (socket) with a slot-type fixing structure can also be used for connection, and the connection terminal can also be called a connector, a plug-in connector, etc.

[0107] For example, components such as capacitors, resistors, and inductors may also be disposed on the printed circuit board 8. Among them, the resistor can control the magnitude of the current through the resistance value, so that the current is properly adjusted in the circuit; the capacitor can store charge and release it when needed, and has the function of smoothing the power supply voltage, stabilizing the current, and in some cases can complete the filtering function of the electrical signal; the inductor has the characteristics of storing and releasing energy, and can complete the energy conversion and distribution of the circuit.

[0108] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A plurality of dies stacked offset in a direction perpendicular to the substrate; A spacer layer is disposed on a side of the plurality of dies away from the substrate; A packaging layer, located on the substrate and surrounding the spacer layer and the plurality of bare chips; The elastic modulus of the spacing layer is greater than the elastic modulus of the encapsulation layer; and / or the plasticity of the spacing layer is greater than the plasticity of the encapsulation layer.

2. The chip packaging structure according to claim 1, characterized in that: The elastic modulus of the spacer layer is 100 Gpa-500 Gpa.

3. The chip packaging structure according to claim 1, characterized in that: The plastic strain of the spacer layer is greater than or equal to 0.5%.

4. The chip packaging structure according to claim 1, characterized in that: The bonding strength between the spacer layer and the packaging layer is greater than or equal to the bonding strength between the plurality of dies and the packaging layer.

5. The chip packaging structure according to claim 1, characterized in that: The thermal expansion coefficient of the spacer layer is greater than or equal to the thermal expansion coefficient of the die, and less than or equal to the thermal expansion coefficient of the packaging layer.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The material of the spacer layer includes metal.

7. The chip packaging structure according to any one of claims 1 to 5, characterized in that: A surface of the spacer layer on one side away from the substrate is at least partially flush with a surface of the encapsulation layer on one side away from the substrate; or, A surface of the spacer layer on one side away from the substrate is lower than a surface of the packaging layer on one side away from the substrate, and the packaging layer covers a surface of the spacer layer on one side away from the substrate.

8. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The spacer layer and a die among the plurality of dies that is farthest from the substrate have the same shape and are equal in size.

9. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The stacking manner between the spacer layer and the die farthest from the substrate among the plurality of die is staggered stacking.

10. The chip packaging structure according to any one of claims 1 to 5, characterized in that: Also includes: A first adhesive film, used for connecting the substrate and the plurality of bare chips, and any two adjacent bare chips; A second adhesive film, used for connecting the bare chip and the spacer layer; Wherein, the first adhesive film and the second adhesive film are made of the same material.

11. A method for preparing a chip packaging structure, characterized in that: include: Stacking a plurality of bare chips in a staggered manner in a vertical direction of a substrate; stacking a spacer layer on a side of the plurality of dies away from the substrate; An encapsulation layer is formed on the substrate to surround the plurality of dies and the spacer layer.

12. The method for preparing a chip packaging structure according to claim 11, characterized in that: Also includes: Disposing a first adhesive film between the substrate and the plurality of bare chips, and between any two adjacent bare chips; A second adhesive film is disposed between the bare chip and the spacer layer.

13. The method for preparing a chip packaging structure according to claim 11 or 12, characterized in that: The elastic modulus of the spacer layer is 100 GPa-500 GPa; and / or the plastic strain of the spacer layer is greater than or equal to 0.5%.

14. The method for preparing a chip packaging structure according to claim 11 or 12, characterized in that: The bonding strength between the spacer layer and the packaging layer is greater than or equal to the bonding strength between the plurality of dies and the packaging layer.

15. The method for preparing a chip packaging structure according to claim 11 or 12, characterized in that: The thermal expansion coefficient of the spacer layer is greater than or equal to the thermal expansion coefficient of the die, and less than or equal to the thermal expansion coefficient of the packaging layer.

16. The method for preparing a chip packaging structure according to claim 11 or 12, characterized in that: The material of the spacer layer includes metal.

17. A storage system, characterized in that: include: The chip packaging structure according to any one of claims 1 to 10; A controller is electrically connected to the chip packaging structure.

18. An electronic device, characterized in that: include: A processor, and a storage system as claimed in claim 17, wherein the processor is coupled to the storage system; or, It comprises: a printed circuit board, and a chip packaging structure as described in any one of claims 1 to 10, wherein the chip packaging structure is arranged on the printed circuit board and is electrically connected to the printed circuit board.

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