Stacked structure, method for manufacturing the same, and semiconductor device

Abstract

The application relates to a laminated structure and a preparation method thereof and a semiconductor device. The structure comprises a substrate, a dielectric layer on the substrate, a first metal layer, an insulating protective layer and a second metal layer which are sequentially laminated on a first surface of the dielectric layer and away from the dielectric layer. The longitudinal section of the first metal layer is a right-angled trapezoid with a target acute angle. The insulating protective layer is on the outer surface of the first metal layer and extends to the first surface. The second metal layer covers the insulating protective layer and part of the top surface of the first metal layer and extends to the first surface. The structure can effectively alleviate and reduce the cracking of the insulating protective layer and can enhance the stability and reliability of the whole device in an extreme environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a laminated structure, a preparation method thereof and a semiconductor device. BACKGROUND

[0002] Semiconductor power devices are widely used in power conversion, automotive electronics, aerospace and other fields due to their excellent electrical performance. These devices often need to work in high temperature, high humidity and high pressure environments, which pose severe challenges to the performance and life of the devices. Among them, the insulating protective layer, as a commonly used insulating and protective material, is widely used in surface coating in semiconductor power devices. However, the insulating protective layer is prone to micro-cracks when exposed to high temperature and humid environment for a long time. The existence of these cracks will become a channel for water vapor intrusion, which will trigger the corrosion problem of the internal metallization layer. The corrosion of the metal layer not only reduces the conductive performance of the device, but also may cause early failure of the device in high pressure applications. In addition, under the working conditions of high temperature and high pressure, the thermal stress and electric field stress inside the semiconductor power device will also accelerate the destruction process of the insulating protective layer, thereby exacerbating the aging problem of the device. Therefore, it is of great significance to develop new technical solutions to enhance the protective layer on the surface of the semiconductor power device, prevent water vapor penetration and inhibit metal corrosion, in order to improve the overall performance and reliability of the device.

[0003] In summary, it is urgent to develop a new semiconductor power device manufacturing technology, especially an improved surface treatment technology, to improve the reliability and life of the device in high temperature, high humidity and high pressure environments. SUMMARY

[0004] Therefore, it is necessary to provide a laminated structure, a preparation method thereof and a semiconductor device, which can at least help to reduce the cracking of the insulating protective layer, in view of the technical problems in the prior art.

[0005] In a first aspect, the present application provides a laminated structure, comprising: a substrate, a dielectric layer located on the substrate, and a first metal layer, an insulating protective layer and a second metal layer which are sequentially stacked in a direction away from the dielectric layer and located on a first surface of the dielectric layer; wherein the longitudinal section of the first metal layer is a right trapezoid with a target acute angle, the insulating protective layer is located on the outer surface of the first metal layer and extends to the first surface; and the second metal layer covers part of the top surface of the first metal layer and the insulating protective layer, and extends to the first surface.

[0006] The stack structure in the above embodiments can adjust the climbing angle of the insulating protective layer and the second metal layer by adjusting the thickness of the first metal layer and the angle of the target acute angle, and more effectively and reasonably distribute and relieve the internal stress between the insulating protective layer and the medium layer caused by the difference in the coefficient of thermal expansion. A proper climbing angle can reduce stress concentration caused by uneven material shrinkage and achieve the purpose of reducing the risk of cracking on the premise of ensuring the uniformity of the coating. A proper intermediate layer material can also be added to optimize the adhesion between the first metal layer or the second metal layer and the insulating protective layer, further preventing interlayer peeling; the first metal layer or the second metal layer can also act as a buffer layer to prevent the insulating protective layer from breaking when subjected to external force impact or vibration.

[0007] In addition, the metal interlayer structure formed by the first metal layer and the second metal layer also has the functions of electromagnetic interference (EMI) shielding and heat dissipation. As an electromagnetic shield, it can prevent external electromagnetic interference and internal electromagnetic leakage, and improve the reliability and stability of the device. The connected metal interlayer has good thermal conductivity and can improve the heat dissipation performance of the device.

[0008] In some embodiments, the stack structure includes a substrate, and the medium layer is located on the substrate.

[0009] In some embodiments, the stack structure includes an epitaxial layer, and the medium layer is located on the epitaxial layer.

[0010] In some embodiments, the stack structure includes an epitaxial layer located on the substrate, and the medium layer is located on the epitaxial layer.

[0011] In some embodiments, the first metal layer and the second metal layer are made of the same material or different materials.

[0012] In some embodiments, the thickness of the second metal layer is greater than the thickness of the insulating protective layer; the first metal layer and the first surface form a first included angle; the second metal layer and the first surface form a second included angle; and the first included angle and the second included angle are both in the range of 30°-70°.

[0013] In some embodiments, the material of the first metal layer includes titanium, tungsten, nickel, cobalt, silver, aluminum, palladium, copper, or a combination thereof.

[0014] In some embodiments, the material of the second metal layer includes titanium, tungsten, nickel, cobalt, silver, aluminum, palladium, copper, or a combination thereof.

[0015] In some embodiments, the material of the insulation protective layer comprises silicon nitride, silicon carbon nitride, silicon oxynitride, or a combination thereof.

[0016] In some embodiments, the stack structure further comprises a passivation layer; the passivation layer covers at least the slope of the second metal layer having the target acute angle.

[0017] In some embodiments, the substrate comprises a substrate, and the dielectric layer is on the substrate; the substrate comprises a first-type drift region therein; the first-type drift region comprises second-type doped regions spaced apart along a first direction parallel to the top surface of the substrate, and channel regions between adjacent second-type doped regions along the first direction; the substrate further comprises a gate on the channel regions; the dielectric layer covers the first-type drift region, the second-type doped regions, and the gate; the first-type drift region and the second-type doped regions have different conductive types.

[0018] In a second aspect, the present application provides a method for manufacturing a stack structure, comprising: providing a substrate, the substrate comprising a dielectric layer thereon; forming a first metal layer and an insulation protective layer on a first surface of the dielectric layer in sequence along a direction away from the dielectric layer; wherein a longitudinal section of the first metal layer has a right-angled trapezoid with a target acute angle, and the insulation protective layer is on an outer surface of the first metal layer and extends to the first surface; and forming a second metal layer covering part of a top surface of the first metal layer and the insulation protective layer, and extending to the first surface.

[0019] The stack structure can be optimized for specific applications. The thicknesses of the first metal layer and the second metal layer, the ramping angle, and the process parameters can be customized according to the electrical, mechanical, and heat dissipation requirements of the power device. For example, a high-power IGBT module uses thicker first metal layer and second metal layer to increase heat dissipation. The customizability of the stack structure provides great flexibility for engineers to develop high-performance packaging solutions that meet the requirements of various power devices.

[0020] In some embodiments, the forming of the first metal layer comprises: forming a first metal material layer on the top surface of the dielectric layer; and removing part of the first metal material layer to obtain the first metal layer; wherein a longitudinal section of the first metal layer has a right-angled trapezoid with a target acute angle.

[0021] In some embodiments, the insulation protective layer and the second metal layer are simultaneously manufactured in the same process step.

[0022] In a third aspect, the present application provides a semiconductor device comprising the above stack structure; or comprising a stack structure manufactured by the above method for manufacturing a stack structure.

[0023] The semiconductor device with the new laminated structure has been significantly improved in reliability, electromagnetic compatibility and heat dissipation performance. The structure reasonably distributes and relieves the internal stress between the insulating protective layer and the first metal layer and the second metal layer, reduces the risk of device cracking and improves the reliability of the device. At the same time, the metal interlayer composed of the first metal layer and the second metal layer as an electromagnetic shield effectively avoids the occurrence of electromagnetic interference and leakage, and enhances the electromagnetic compatibility of the device. In addition, the good thermal conductivity of the metal material helps to dissipate heat, reduces the temperature of the device, improves the power density, and reduces the repair rate of the device, making the semiconductor device more competitive in the market.

[0024] In a fourth aspect, the present application also provides an electronic device comprising the laminated structure described above; or comprising a laminated structure prepared by the preparation method of the laminated structure described above.

[0025] The electronic device is, for example but not limited to, a suitable type of electronic product such as a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, etc., and an electronic product containing the laminated structure according to any embodiment of the present application. Among them, the consumer electronic product is, for example, a mobile phone, a tablet computer, a notebook computer, an all-in-one computer, etc. The household electronic product is, for example, an air conditioner, a television, a refrigerator, a sound equipment, etc. The vehicle-mounted electronic product is, for example, power management, intelligent door control, electric sunroof, etc. The financial terminal product is, for example, an ATM machine, a self-service terminal, etc. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0027] Figure 1 A flow chart of the preparation method of the laminated structure provided in an embodiment;

[0028] Figure 2 A cross-sectional schematic diagram of the structure obtained after forming the dielectric layer in step S204 of the preparation method of the laminated structure provided in an embodiment;

[0029] Figure 3 A cross-sectional schematic diagram of the structure obtained after forming the first metal material layer in step S402 of the preparation method of the laminated structure provided in an embodiment;

[0030] Figure 4 A cross-sectional schematic diagram of the structure obtained after forming the first metal layer in step S402 of the preparation method of the laminated structure provided in an embodiment;

[0031] Figure 5 A cross-sectional view of the structure obtained after forming the insulating protective material layer in step S404 of the method for preparing a laminated structure according to an embodiment;

[0032] Figure 6 A cross-sectional view of the structure obtained when forming the insulating protective layer in step S404 of the method for preparing a laminated structure according to an embodiment;

[0033] Figure 7 A cross-sectional view of the structure obtained after forming the second metal material layer in step S60 of the method for preparing a laminated structure according to an embodiment;

[0034] Figure 8 A cross-sectional view of the structure obtained after forming the second metal layer in step S60 of the method for preparing a laminated structure according to an embodiment;

[0035] Figure 9 A cross-sectional view of the structure obtained after forming the passivation layer of the method for preparing a laminated structure according to an embodiment.

[0036] BRIEF DESCRIPTION OF DRAWINGS

[0037] 10, substrate; 11, dielectric layer; 121, first metal material layer; 12, first metal layer; 131, insulating protective material layer; 13, insulating protective layer; 141, second metal material layer; 14, second metal layer; 15, passivation layer; 20, laminated structure. DETAILED DESCRIPTION

[0038] In order to facilitate the understanding of the present application, a more complete and comprehensive description of the present application will be made with reference to the relevant drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing the specific embodiments of the present application, and are not intended to limit the present application.

[0040] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be p-type and a second doped type can be n-type, or the first doped type can be n-type and the second doped type can be p-type.

[0041] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0042] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Also, as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] Embodiments of the application are described herein with reference to cross-sectional illustrations of idealized embodiments (and intermediate structures) of the application that are illustrated for the purposes of explanation only and are not limiting of the present application in their use, for example, in conjunction with the making of a device. Thus, embodiments of the present application should not be construed as limited to the particular shapes of regions illustrated herein but are to include any shapes that might be achieved by applying the principles described herein, for example, in conjunction with the making of a device. For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from implanted to non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic only and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.

[0044] Power devices have higher requirements for resistance to pressure. In a high-temperature and humid environment, the current mainstream silicon oxide and silicon nitride insulation protective layer is prone to defects such as cracks and cavities due to accelerated oxidation under the action of a high electric field, and becomes a path for water vapor penetration, thereby seriously affecting the performance and service life of the device and greatly reducing the reliability. In addition, in the traditional single-layer structure, the silicon nitride is directly coated on the bottom layer material, and the thermal expansion coefficient difference is large. In a high-temperature working environment, the material will change in volume due to thermal expansion, and the volume change amount is different. A large internal stress is generated between the silicon nitride and the bottom layer material, thereby causing warping or cracking. This is one of the main reasons for the cracking of silicon nitride.

[0045] Referring to Figure 1 The application provides a preparation method of a laminated structure, comprising steps S20-S40.

[0046] Step S20: providing a substrate, the substrate comprising a dielectric layer.

[0047] For example, a specific substrate can be selected according to the type, function, and other characteristics of the power device. Common substrate materials can be, but are not limited to, silicon (Si), germanium (Ge), silicon carbide (SiC), gallium arsenide (GaAs), or gallium nitride (GaN) epitaxially grown on a 4H-SiC, sapphire (Al2O3), or silicon substrate, and other wide-bandgap materials. The substrate can be a single-layer structure or a multi-layer structure, for example, the substrate can also comprise AlGaN / GaN, Si / SiC, GaN / Si, or SiGeC / Si, and the like. In addition, other electrical materials can also be included in the substrate. Therefore, the type of substrate should not limit the protection scope of the present disclosure. In the present embodiment, the material of the substrate is silicon carbide.

[0048] For example, the dielectric layer includes, but is not limited to, silicon oxide (SiO2) and high dielectric constant (High-K) materials such as aluminum oxide (Al2O3), titanium oxide (TiO2), zirconium oxide (ZrO2), etc. Among them, silicon oxide has good electrical insulation, thermal stability and chemical stability, and High-K materials can increase the thickness of the dielectric layer film while keeping the gate capacitance unchanged, thereby reducing the current of the dielectric layer. In the embodiment, the material of the dielectric layer is silicon oxide.

[0049] Step S40: forming a first metal layer and an insulating protective layer on the first surface of the dielectric layer in sequence along a direction away from the dielectric layer; wherein the longitudinal section of the first metal layer is a right trapezoid with a target acute angle, and the insulating protective layer is located on the outer surface of the first metal layer and extends to the first surface.

[0050] The insulating protective layer is an insulating protective material, and the insulating protective material has compactness and chemical stability, including but not limited to silicon nitride, silicon carbon nitride, silicon oxynitride or a combination thereof. In the embodiment, the insulating protective layer is silicon nitride.

[0051] Step S60: forming a second metal layer covering part of the top surface of the first metal layer and the protective layer, and extending to the first surface.

[0052] For example, the first metal layer and the second metal layer can be formed of the same or similar materials, or can each be composed of different metal materials, including but not limited to aluminum (Al), copper (Cu) or zinc (Zn), etc. In the embodiment, the first metal layer and the second metal layer are aluminum layers.

[0053] The stack structure obtained after steps S20-S60 can be referred to as 9. Of course, in order to facilitate the understanding of the present application, Figure 9 An example of the stack structure prepared by the preparation method of the present application, the stack structure prepared by the preparation method of the stack structure prepared by the present application can also have other suitable examples, which are not limited herein.

[0054] Please refer to Figure 2 In some embodiments, step S20 includes steps S202-S204.

[0055] Step S202: preparing a first type drift region, a second type doped region and a gate (not shown) in the substrate / epitaxial layer; the first type drift region and the second type doped region are different in conductivity type, and the second type doped region is distributed in a first direction parallel to the top surface of the substrate / epitaxial layer.

[0056] For example, dopant can be implanted into the substrate / epitaxial layer at intervals along a first direction parallel to the top surface of the substrate / epitaxial layer using doping techniques such as ion implantation, to prepare a type II doped region. The dopant has the opposite polarity to the substrate / epitaxial layer, and the doping concentration in the type II doped region gradually decreases towards the interior of the substrate / epitaxial layer. In this embodiment, the types of N-type and P-type impurity ions are not specifically limited. For example, P-type impurity ions can include, but are not limited to, any one or more of boron (B) ions, gallium (Mg) ions, or indium (In) ions; N-type impurity ions can include, but are not limited to, one or more of phosphorus (P) ions, arsenic (As) ions, or antimony (Sb) ions.

[0057] At this time, the substrate / epitaxial layer outside the second-type doped region is used to form the first-type drift region. When the gate-source voltage changes, it will change the amount of induced charge near the dielectric layer 11 in the substrate / epitaxial layer, forming a continuous channel region between adjacent second-type doped regions along the first direction. The thickness of the substrate / epitaxial layer is not limited; in addition, other special structures such as trench isolation structures can be formed within the substrate / epitaxial layer, but this embodiment is not restricted.

[0058] The substrate / epitaxial layer, together with the internal first-type drift region, second-type doped region, channel region, and other structures located within the substrate / epitaxial layer, constitute the substrate 10.

[0059] Step S204: Form a dielectric layer 11 covering the substrate 10 on the substrate 10.

[0060] Please see Figure 2 For example, the above structure can be obtained using deposition processes, including but not limited to one or more of the following processes: Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP), Plasma Enhanced Deposition (PDE), and Spin-on Dielectric (SOD). The dielectric layer 11 can isolate the gate and the substrate 10, preventing direct current conduction between them.

[0061] Please see Figures 3-9 In some embodiments, step S40 further includes: steps S402-S408.

[0062] Step S402: A first metal material layer 121 is formed on the first surface 11a of the dielectric layer 11.

[0063] Referring to Figure 3 For example, a deposition method can be used to form a first metal material layer 121 on the top surface of the dielectric layer 11.

[0064] Referring to Figure 4 For example, a photolithography combined with etching can be used to remove part of the first metal material layer 121 to obtain a first metal layer 12; wherein the longitudinal section of the first metal layer 12 is a right trapezoid with a target acute angle.

[0065] For example, etching can be mainly divided into dry etching and wet etching. Dry etching is usually divided into three types: plasma etching (PE), sputtering etching, and reaction ion etching (RIE). The etching solution of wet etching process can be a mixed solution of hydrofluoric acid and hydrogen peroxide. The specific selection should be made according to different processing objects, requirements and actual situations.

[0066] For example, in this embodiment, photoresist is coated on the first metal material layer 121, and a series of steps such as exposure and development are performed to form an etching window on the top surface of the substrate 10 by using a self-aligned double patterning (SADP) process or a self-aligned quadruple patterning (SAQP) process. The final longitudinal section of the first metal layer 12 is a right trapezoid with a target acute angle as shown in Figure 4 ; wherein the first metal layer 12 and the first surface 11a form a first included angle, and the first included angle ranges from 30° to 70°.

[0067] For example, the thickness of the first metal layer 12 includes but is not limited to 0.5 microns to 3 microns, such as 0.5 microns, 1 micron, 1.5 microns, 2 microns, 2.5 microns or 3 microns, etc.

[0068] Step S404: forming an insulating protective layer 13 on the top surface of the first metal layer 12.

[0069] Referring to Figure 5 For example, a deposition method can be used to form an insulating protective material layer 131 on the top surface of the dielectric layer 11.

[0070] Referring to Figure 6For example, photolithography combined with etching can be used to remove part of the insulating protective material layer 131, exposing part of the top surface of the first metal layer 12; wherein the remaining insulating protective material layer 131 is located on the outer surface of the first metal layer 12 and extends to the first surface 11a.

[0071] For example, in this embodiment, there are no special requirements for the etching angle of the insulating protective material layer 131.

[0072] Please see Figures 7-8 In some embodiments, step S60 further includes: forming a second metal layer 14 on the top surface of the insulating protective material layer 131, wherein the insulating protective material layer 131 is used to constitute the insulating protective layer 13.

[0073] For example, in this embodiment, step S60 is the same as the previous step S402, that is, step S402 is repeated.

[0074] For example, please refer to Figure 7 Deposit a second metallic material layer 141; see also Figure 8 The second metal material layer 141 is etched at a preset angle using a combination of photolithography and etching. At this time, the remaining second metal material layer 141 is used to form the second metal layer 14, and the insulating protective material layer 131 is used to form the insulating protective layer 13.

[0075] The second metal layer 14 covers part of the bottom surface of the insulating protective layer 13 and the first metal layer 12, and extends to the first surface 11a. The second metal layer 14 and the first surface 11a have a second included angle, the second included angle ranging from 30° to 70°.

[0076] For example, the thickness of the insulating protective layer 13 includes, but is not limited to, 0.1 micrometers to 1 micrometer, such as 0.1 micrometers, 0.5 micrometers or 1 micrometer, etc.; the thickness of the second metal layer 14 includes, but is not limited to, 2 micrometers to 6 micrometers, such as 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers or 6 micrometers, etc.

[0077] The thickness of each of the first metal layer 12, the insulating protective layer 13, and the second metal layer 14 can be adjusted as needed. By adjusting their thickness and the angle between them and the first surface 11a, these stresses can be distributed and alleviated more effectively. A smaller angle can increase the uniformity of the coating.

[0078] Furthermore, the adhesion between the insulating protective layer 13 and the first metal layer 12 and the second metal layer 14 in the laminated structure 30 can be optimized by selecting appropriate intermediate layer materials and process parameters. Good adhesion can further prevent interlayer delamination, which is also an important factor in reducing crack formation.

[0079] Please seeFigure 9 In some embodiments, after step S60, the method further comprises forming a passivation layer 15 covering at least the inclined surface of the second metal layer 14 having a right trapezoid with a target acute angle.

[0080] For example, referring to Figure 9 The passivation layer 15 is deposited and etched. The passivation layer 15 can effectively prevent the surface of the first metal layer 12 and the second metal layer 14 from contacting corrosive media such as oxygen and water vapor, thereby inhibiting the occurrence of oxidation corrosion. Not only can the service life of the metal material be prolonged, but also the physical properties such as surface hardness, wear resistance, and corrosion resistance can be significantly improved.

[0081] It should be understood that, although Figure 1 The steps in the flowchart are shown in sequence according to the direction of the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps in the flowchart can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times. The execution sequence of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0082] For example, referring to Figure 9 The application provides a laminated structure 30, comprising a substrate 10, a dielectric layer 11 on the substrate 10, and a first metal layer 12, an insulating protective layer 13, and a second metal layer 14 sequentially stacked in a direction away from the dielectric layer 11 on a first surface 11a of the dielectric layer 11; wherein the longitudinal section of the first metal layer 12 is a right trapezoid with a target acute angle, the insulating protective layer 13 is on the outer surface of the first metal layer 12 and extends to the first surface 11a; the second metal layer 14 covers the insulating protective layer 13 and part of the top surface of the first metal layer 12, and extends to the first surface 11a.

[0083] The longitudinal section of the first metal layer 12 is a right trapezoid with a target acute angle, so that the first metal layer 12 has a climbing angle. The insulating protective layer 13 covering the outer surface of the first metal layer 12 and extending to the first surface 11a of the medium layer 11, together with the second metal layer 14 directly above, forms a laminated structure 30. Compared with a single insulating protective layer 13, the laminated structure 30 can adjust the climbing angles of the insulating protective layer 13 and the second metal layer 14 by adjusting the thickness of the first metal layer 12 and the angle of the target acute angle, and more effectively allocate and relieve the internal stress between the insulating protective layer 13 and the medium layer 11 caused by the difference in thermal expansion coefficient. In addition, the laminated structure 30 also has electromagnetic shielding and heat dissipation functions, which can improve the reliability and performance of the device.

[0084] Referring to Figure 9 In some embodiments, the laminated structure 30 includes a substrate, and the medium layer 11 is located on the substrate.

[0085] Referring to Figure 9 In some embodiments, the laminated structure 30 includes an epitaxial layer, and the medium layer 11 is located on the epitaxial layer. The epitaxial layer is consistent with the conductive type of the substrate.

[0086] Referring to Figure 9 In some embodiments, the laminated structure 30 includes an epitaxial layer located on a substrate, and the medium layer 11 is located on the epitaxial layer.

[0087] Referring to Figure 9 In some embodiments, the first metal layer 12 and the second metal layer 14 are made of the same material or different materials.

[0088] Referring to Figure 9 In some embodiments, the thickness of the second metal layer 14 is greater than the thickness of the insulating protective layer 13; the first metal layer 12 and the first surface 11a form a first included angle; the second metal layer 14 and the first surface 11a form a second included angle; the range of the first included angle and the second included angle both include 30°-70°. Of course, the specific thickness and the size of the included angle can be adjusted according to the application scenario, and should not be limited to the range in this embodiment.

[0089] Referring to Figure 9 In some embodiments, the material of the first metal layer 12 includes titanium, tungsten, nickel, cobalt, silver, aluminum, palladium, copper, or a combination thereof.

[0090] Referring to Figure 9 In some embodiments, the material of the second metal layer 14 includes titanium, tungsten, nickel, cobalt, silver, aluminum, palladium, copper, or a combination thereof.

[0091] Referring to Figure 9 In some embodiments, the material of the insulating protective layer 13 includes silicon nitride, silicon carbon nitride, silicon oxynitride, or a combination thereof.

[0092] Referring to Figure 9 In some embodiments, the laminated structure 30 further comprises a passivation layer 15; the passivation layer 15 covers at least the slope of the second metal layer 14 having a right trapezoid with a target acute angle in the longitudinal section.

[0093] In some embodiments, the substrate 10 comprises a substrate, and the dielectric layer 11 is located on the substrate; the substrate comprises a first-type drift region; the first-type drift region comprises second-type doped regions spaced apart along a first direction parallel to the top surface of the substrate, and channel regions located between adjacent second-type doped regions along the first direction; the substrate further comprises a gate located on the channel regions; the dielectric layer 11 covers the first-type drift region, the second-type doped regions, and the gate; the first-type drift region and the second-type doped regions have different conductive types.

[0094] For example, if the first-type drift region is P-type, the second-type doped regions are N-type, and vice versa. When regions of different conductive types are in contact, holes in the P-type region diffuse to the N-type region, and electrons in the N-type region also diffuse to the P-type region, thereby forming a depletion region at the contact region. The width of the depletion region in each doped region is inversely proportional to its doping concentration, i.e., the side with lower doping concentration has a wider depletion region. Of course, this embodiment only represents one way, and the substrate / epitaxial layer can also include doped regions of multiple conductive types and different doping concentrations, as long as the semiconductor structure is reasonably formed.

[0095] In the above embodiments, the unexpected technical effects of the present application are:

[0096] The laminated structure realizes multiple advantages by combining the first metal layer and the second metal layer with a ramp angle on the basis of the traditional insulating protective layer. The metal interlayer composed of the first metal layer and the second metal layer has good thermal conductivity, which helps to dissipate heat, reduce device temperature, and increase power density. By adjusting the thickness and ramp angle of the metal interlayer, internal stress caused by the difference in thermal expansion coefficients can be more effectively distributed and relieved, reducing the risk of cracking. Selecting a suitable intermediate layer material can enhance the adhesion between the metal interlayer and the insulating protective layer, prevent interlayer peeling, or act as a buffer layer to prevent the insulating protective layer from breaking. The thickness, ramp angle, and process parameters of the laminated structure can be customized for specific applications to meet the electrical, mechanical, and heat dissipation requirements of different power devices.

[0097] In addition to reducing stress concentration problems, the laminated structure also has electromagnetic interference (EMI) shielding function, which can prevent external electromagnetic interference and internal electromagnetic leakage, and improve the reliability and stability of the device.

[0098] In summary, a new type of laminated structure is proposed, which effectively reduces the cracking of the insulation protective layer, and at the same time, can enhance the stability and reliability of the entire device in extreme environments. The semiconductor device using the laminated structure can also be significantly improved in reliability, electromagnetic compatibility and heat dissipation performance, and the device repair rate is effectively reduced, providing new opportunities for the innovation and development of semiconductor devices.

[0099] The technical features of the above-mentioned embodiments can be combined arbitrarily, and in order to make the description simple, all possible combinations of the technical features of the above-mentioned embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the description.

[0100] The above-mentioned embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A layered structure, characterized in that, include: A substrate, a dielectric layer on the substrate, and a first metal layer, an insulating protective layer, a second metal layer, and a passivation layer, which are sequentially stacked on a first surface of the dielectric layer in a direction away from the dielectric layer. Wherein, the longitudinal section of the first metal layer is a right trapezoid with a target acute angle, the insulating protective layer is located on the outer surface of the first metal layer and extends to the first surface; the insulating protective layer covers the inclined surface of the first metal layer with a longitudinal section of a right trapezoid with a target acute angle, and exposes part of the top surface of the first metal layer; The second metal layer covers a portion of the top surface of the first metal layer and the insulating protective layer, and extends to the first surface; the second metal layer covers the slope of the insulating protective layer; The passivation layer at least covers the slope of the second metal layer, which has a right-angled trapezoidal cross-section with a target acute angle; Wherein, the thickness of the second metal layer is greater than the thickness of the insulating protective layer, the first metal layer and the first surface form a first angle, the second metal layer and the first surface form a second angle, and the range of both the first angle and the second angle includes 30°-70°.

2. The stacked structure according to claim 1, characterized in that, The basis includes any one of the following features: Substrate, wherein the dielectric layer is located on the substrate; Epitaxial layer, wherein the dielectric layer is located on the epitaxial layer; An epitaxial layer located on a substrate, wherein the dielectric layer is located on the epitaxial layer.

3. The stacked structure according to claim 1, characterized in that, The first metal layer and the second metal layer may be made of the same or different materials.

4. The laminated structure according to any one of claims 1-3, characterized in that, Includes at least one of the following features: The material of the first metal layer includes titanium, tungsten, nickel, cobalt, silver, aluminum, palladium, copper, or a combination thereof; The material of the second metal layer includes titanium, tungsten, nickel, cobalt, silver, aluminum, palladium, copper, or a combination thereof; The material of the insulating protective layer includes silicon nitride, silicon carbide nitride, silicon oxynitride, or a combination thereof.

5. The laminated structure according to any one of claims 1-3, characterized in that, The substrate includes a substrate, and the dielectric layer is located on the substrate; The substrate includes a type-1 drift region; The first type of drift region includes second type doped regions spaced apart along a first direction parallel to the top surface of the substrate, and a channel region located between adjacent second type doped regions along the first direction; The substrate also includes a gate located on the channel region; The dielectric layer covers the first type drift region, the second type doped region, and the gate; The first type of drift region and the second type of doped region have different conductivity types.

6. A method for preparing a layered structure, characterized in that, include A substrate is provided, wherein a dielectric layer is included on the substrate; A first metal layer, an insulating protective layer, a second metal layer, and a passivation layer are sequentially stacked on the first surface of the dielectric layer in a direction away from the dielectric layer; wherein, the longitudinal section of the first metal layer is a right trapezoid with a target acute angle, and the insulating protective layer is located on the outer surface of the first metal layer and extends to the first surface; Forming the first metal layer includes: After forming a first metal material layer on the top surface of the dielectric layer, a portion of the first metal material layer is removed to obtain the first metal layer; Forming the insulating protective layer includes: After forming an insulating protective material layer on the top surface of the first metal layer, a portion of the insulating protective material layer is removed, exposing a portion of the top surface of the first metal layer. The remaining insulating protective material layer is located on the outer surface of the first metal layer and extends to the first surface, serving to form an insulating protective layer. The insulating protective layer covers the inclined surface of the first metal layer, which has a longitudinal section that is a right trapezoid with a target acute angle. Forming the second metal layer includes: After forming a second metal material layer on the top surface of the insulating protective layer, a portion of the second metal material layer is etched away, and the remaining second metal material layer is used to form the second metal layer; the second metal layer covers a portion of the top surface of the first metal layer and the insulating protective layer, and extends to the first surface; the second metal layer covers the slope of the insulating protective layer; Forming the passivation layer includes: A passivation layer is formed that at least covers the slope of the second metal layer, which has a right-angled trapezoidal cross-section with a target acute angle. Wherein, the thickness of the second metal layer is greater than the thickness of the insulating protective layer, the first metal layer and the first surface form a first angle, the second metal layer and the first surface form a second angle, and the range of both the first angle and the second angle includes 30°-70°.

7. A semiconductor device, characterized in that, Includes the stacked structure described in any one of claims 1-5; or The laminated structure prepared by the laminated structure preparation method described in claim 6.

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