Welding assembly for packaging power semiconductor module and manufacturing method thereof
By using a connecting copper layer of 35nm to 400nm, the problem of tin-based soldering components generating brittle intermetallic compounds and Kokendal holes at high temperatures is solved, and high conductivity, thermal conductivity and shear strength are achieved, and service life is extended.
Patent Information
- Application Number
- CN202311026248.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-15
- Publication Date
- 2025-02-25
AI Technical Summary
When used at high temperatures, brittle intermetallic compounds and cokendal holes are easily generated, resulting in reduced conductivity, reduced shear strength and shortened service life.
A connecting copper layer with an average grain size of 35nm to 400nm is used to form a dense welded component by pre-plating the copper layer and controlling the grain size, reducing the generation of intermetallic compounds and Kokendal holes.
It improves the conductivity, thermal conductivity and shear strength of welding components, extends the service life, and ensures long-term stability and reliability in high temperature environments.
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Figure CN119517880A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a welding assembly for power semiconductor module packaging and a manufacturing method thereof. The welding assembly is particularly suitable for packaging power semiconductor modules, in particular power semiconductor modules used in inverter modules of new energy vehicles. Background Art
[0002] New energy vehicles use clean energy and can achieve zero emissions. They are expected to gradually replace fuel vehicles in the future and become the largest market share. One of the core components of new energy vehicles is the electronic control system, in which the inverter module is responsible for the high-frequency conversion of high-voltage and high-current DC and AC. It is the power transfer station for the car battery and the drive system. Therefore, the performance of the inverter module directly affects the performance of the power system of new energy vehicles.
[0003] The performance and safety of the inverter module of new energy vehicles are greatly affected by packaging. The core of packaging lies in the welding between key components such as copper conductive film, semiconductor chip (with one or more metal layers on the back), copper-clad substrate and heat sink to achieve electrical conductivity and thermal conductivity between them. There are three main situations: 1) The outermost metal layer (usually a gold layer, a silver layer, etc.) on the back of the semiconductor chip and the copper layer of the copper-clad substrate are welded together by a third low-melting-point metal solder; 2) The copper layer of the copper-clad substrate and the surface aluminum layer of the aluminum heat sink are connected together by a third low-melting-point solder or a thermally conductive silicone sheet; and 3) The outermost metal layer (usually an aluminum layer) on the front of the semiconductor chip and the surface copper layer of the copper conductive film are welded together by a third low-melting-point metal solder. The most widely used solder in industry is low-melting-point tin-based solder, which has a melting point between 200 and 250°C and has good welding performance (good wetting and spreading, low surface tension, etc.) and performance. The soldering method is usually: in a vacuum or inert gas protected environment, at a temperature slightly higher than the melting point of the solder, such as 250°C, heating for 1 to 10 minutes.
[0004] However, there are several defects in the welding assembly obtained based on tin-based solder. On the one hand, tin is very active at low temperatures and reacts with metals such as gold, silver, aluminum, titanium, and nickel, resulting in the generation of intermetallic compounds at the welding interface between the two. These intermetallic compounds grow rapidly at the interface at the operating temperature of the inverter module, thereby forming a layer containing a large number of micron-sized intermetallic compounds (such as Ag3Sn, AuSn4, etc., depending on the metal that reacts with tin), which reduces the conductivity of the welding interface and is prone to brittle cracking. This not only reduces the power of the inverter module, but also has a fatal impact on its service life, increasing the safety hazards of the vehicle during use. On the other hand, for example, for the welding of chips and copper-clad substrates using tin-based solders, the obtained welding assembly includes large holes, which not only significantly reduce the electrical conductivity and thermal conductivity of the welding assembly, reduce the power and heat dissipation efficiency of the module, and make the module unable to achieve the expected performance, but also become a stress concentration zone when subjected to mechanical shock or thermal cycling, which is easy to cause the generation of micro cracks and reduce the shear strength, causing premature fracture and shortening the service life of the module. At least based on these issues with current welded components, existing inverter modules are limited in power scaling and cannot operate reliably at high temperatures.
[0005] Therefore, there is an urgent need for a welding assembly that can stably serve for a long time at high temperatures, which can at least reduce or eliminate the above-mentioned technical problems caused by welding dissimilar metals, namely, the decline in performance (such as shear strength and conductivity) caused by holes and brittle intermetallic compounds, thereby improving the long-term service performance of devices containing such welding assemblies. Summary of the invention
[0006] The present invention is made in view of the above-mentioned existing problems.
[0007] One of the purposes of the present invention is to provide a welding assembly for power semiconductor module packaging, the welding assembly comprising:
[0008] a first component, the outermost layer on the first side of the first component being a non-copper metal layer;
[0009] a second component having a first copper layer disposed on a first side of the second component;
[0010] A connecting copper layer, two sides of which are respectively connected to the non-copper metal layer and the first copper layer to form a first interface and a second interface, thereby fixing the first component and the second component together,
[0011] Wherein, the average grain size of the connecting copper layer is 35nm-400nm.
[0012] The average grain size of the connecting copper layer is preferably 35nm to 380nm, further preferably 45nm to 380nm, more preferably 60nm to 220nm, and even more preferably 45nm to 140nm. Preferably, the average thickness of the connecting copper layer is 70nm to 5μm, further preferably 90nm to 5μm, more preferably 500nm to 5μm, and the average thickness of the connecting copper layer is at least one times its average grain size.
[0013] Preferably, within a range of a width of 1 μm extending outward from the first interface and the second interface respectively away from the connecting copper layer and a length of any 10 μm along the length direction of the first / second interface, the average porosity of the soldered assembly is ≤3%, and the pore size is ≤200 nm. Further preferably, the average porosity of the soldered assembly is ≤1%.
[0014] Preferably, for the welding assembly, 1) the first component is a semiconductor chip, and the second component is a copper clad substrate; or 2) the first component is a semiconductor chip, and the second component is a copper conductive film or copper foil; or 3) the first component is a heat sink, and the second component is a copper clad substrate.
[0015] Preferably, the non-copper metal layer is a gold layer, and the average grain size of the connecting copper layer is 35 nm to 140 nm.
[0016] Preferably, the non-copper metal layer is a silver layer, and the average grain size of the connecting copper layer is 100nm to 400nm. This is because the diffusion coefficient of silver in copper is closer to the diffusion coefficient of copper in silver at the same temperature, so the average grain size required to weaken the Cockendale effect is not as high as that of the gold layer.
[0017] Preferably, the first copper layer is formed by an initial copper layer of the copper-clad substrate or the copper conductive film, and has an average grain size of ≥500 nm.
[0018] In addition, preferably, the welding assembly further comprises:
[0019] a second copper layer disposed on a second side of the second component;
[0020] a third component, the outermost layer on the first side of the third component being a non-copper metal layer;
[0021] The other connecting copper layer has two sides connected to the non-copper metal layer of the third component and the second copper layer respectively, so as to fix the second component and the third component together; wherein the average grain size of the other connecting copper layer is 35nm-400nm.
[0022] It will be understood that the soldered assembly can further similarly include more components and corresponding connecting copper layers with an average grain size of 35 nm to 400 nm soldered together.
[0023] Preferably, the shear strength of the above-mentioned welding assembly is 30-40 MPa, more preferably 35-40 MPa, and the resistivity of the connecting copper layer is ≤5 μΩ·cm.
[0024] Preferably, the chip involved in the present invention includes a functional chip with silicon, silicon carbide, and gallium nitride as the main material, one or more metal layers are arranged on the front surface and the back surface of the chip, and the outermost metal layer is a non-copper metal layer. Preferably, the outermost metal layer can be a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer. Preferably, the chip can be an insulated gate bipolar transistor (IGBT) chip, a metal oxide semiconductor field effect transistor (MOSFET) chip, a bipolar transistor (BJT) chip, and a fast recovery diode (FRD) chip.
[0025] Preferably, the copper-clad substrate involved in the present invention can be any substrate with a copper layer on the surface, including but not limited to a direct bond copper ceramic substrate (DBC), an active metal brazed ceramic substrate (AMB), or a copper-clad metal heat dissipation structure.
[0026] Preferably, the heat sink involved in the present invention is a heat dissipation structure with an aluminum layer on the surface.
[0027] Another object of the present invention is a welding assembly for power semiconductor module packaging, comprising:
[0028] A semiconductor chip, wherein a non-copper metal layer is disposed on the outermost layer on the first side and the second side of the semiconductor chip;
[0029] A copper-clad substrate, wherein a first copper layer and a second copper layer are respectively arranged on a first side and a second side of the copper-clad substrate;
[0030] a heat sink having an aluminum layer disposed on a first side of the heat sink;
[0031] A copper conductive film, wherein a third copper layer is disposed on the first side of the copper-clad substrate;
[0032] a first connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the first side of the semiconductor chip and the third copper layer to fix the semiconductor chip and the copper conductive film together;
[0033] A second connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the second side of the semiconductor chip and the first copper layer to fix the semiconductor chip and the copper-clad substrate together; and
[0034] a third connecting copper layer, two sides of which are respectively connected to the second copper layer and the aluminum layer to fix the copper-clad substrate and the heat sink together;
[0035] Wherein, the average grain size of the first, second and third connection copper layers is 35nm-400nm.
[0036] Preferably, the average grain size of the first and second connection copper layers is 35nm to 380nm, further preferably 45nm to 380nm, more preferably 60nm to 220nm, and even more preferably 45nm to 140nm; the average grain size of the third connection copper layer is preferably 35nm to 380nm and more preferably 62nm to 250nm. Preferably, the non-copper metal layer of the semiconductor chip is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer. Preferably, the average porosity of the soldered assembly is ≤3%, more preferably ≤1%, and the pore size is ≤200nm.
[0037] Another object of the present invention is a method for producing a soldered assembly for power semiconductor module packaging, comprising the following steps:
[0038] a) providing a first component and a second component to be welded together and cleaning and drying them, wherein the second component has an initial copper layer on a first side, and the outermost layer on the first side of the first component is a non-copper metal layer, such as a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer;
[0039] b) introducing a pre-plated copper layer on the surface of the initial copper layer of the cleaned second component or on the outermost layer of the first side of the cleaned first component and cleaning to remove an oxide layer on the surface of the pre-plated copper layer, wherein the average grain size of the pre-plated copper layer is 20 nm to 360 nm;
[0040] c) laminating the second component or the pre-plated copper layer of the first component to the non-copper metal layer of the first component or the initial copper layer of the second component in surface contact to form a stacked structure;
[0041] d) welding the first component and the second component together by diffusion welding, thereby obtaining the welded assembly of the present invention.
[0042] Preferably, the average grain size of the pre-copper plating layer is 25nm to 360nm, more preferably 30nm to 300nm, and the average thickness of the pre-copper plating layer is greater than or equal to 2 times the average grain size. Further preferably, the average thickness of the pre-copper plating layer is 100nm to 5μm, more preferably 500nm to 5μm and at least 3 times the average grain size.
[0043] Preferably, the first component is a semiconductor chip, and its non-copper metal layer is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer. Preferably, the first component is a heat sink, and its surface is an aluminum layer, and the average grain size of the pre-plated copper layer is 30nm to 200nm, and the average thickness of the pre-plated copper layer is 100nm to 3μm and is at least 3 times the average grain size.
[0044] Preferably, in step d, diffusion welding is performed as follows: in a helium protective environment at a temperature of 250-350° C., pressurizing is performed from the top and bottom of the stacked structure, the pressure is 15-40 MPa, and the holding time is 10-30 minutes. More preferably, the holding temperature is 250-300° C., or the pressure is 20-30 MPa, or the holding time is 10-20 minutes.
[0045] Preferably, the pre-plated copper layer is formed by electroplating, evaporation, sputtering, ion plating or the like to provide a pre-plated copper layer having relatively uniform thickness and grain size.
[0046] Preferably, in step b, the pre-plated copper layer is deposited by electrochemical deposition, the electrolyte solution used comprises 200-250 g / L of anhydrous copper sulfate, 10-50 ml / L of sulfuric acid and 0.01-0.05 g / L of thiourea, the solution temperature is 30°C, and more preferably, the current density of the electrochemical deposition is 0.05-0.15 A / cm 2 , the deposition time is 60 to 300 seconds. In addition, preferably, the electrolyte solution comprises 200 to 250 g / L of anhydrous copper sulfate, 10 to 50 ml / L of sulfuric acid and 0.005 to 0.01 g / L of thiourea, the solution temperature is 30°C, and further preferably, the current density of the electrochemical deposition is 0.01 to 0.04 A / cm 2 , the deposition time is 250 to 350 seconds.
[0047] The method of the present invention obtains a welding assembly with improved performance with simple operation. Specifically, the present invention obtains a connecting copper layer with a desired grain size by providing a dense pre-plated copper layer for welding two parts and controlling its grain size, so that the welding assembly finally obtained has low porosity and resistivity. At the same time, due to the low activity and small lattice parameter of copper, copper reacts very slowly with dissimilar metals, resulting in very few intermetallic compounds in the welding assembly. Therefore, the welding assembly obtained by the method of the present invention has low porosity and resistivity and basically no intermetallic compounds, and has excellent electrical conductivity, thermal conductivity and high shear strength.
[0048] Furthermore, during service, the high grain boundary volume fraction of the connecting copper layer in the welded assembly provides a fast diffusion channel for dissimilar metals, so that the diffusion rate of dissimilar metal atoms is between 1 / 6 and 6 times the diffusion rate of copper atoms, and more preferably between 0.5 and 2 times, so that the atomic inflow and outflow fluxes in the connecting copper layer are basically consistent, fundamentally slowing down or avoiding the generation of Cockendale holes. At the same time, there are very few intermetallic compounds in the welded assembly. The combination of the two ensures that even if it operates for a long time in a high-temperature environment, a large number of Cockendale holes will not be generated and grow, and intermetallic compounds will not grow in the welded assembly, so that the mechanical properties will not be significantly affected, and the long-term service stability of the welded assembly is improved.
[0049] Compared with the prior art, the welding assembly of the present invention for connecting dissimilar metals in power semiconductor module packaging has excellent performance and stable service performance, and solves the problems of low mechanical strength, high resistivity and poor heat dissipation caused by the generation of Cockkendall holes and intermetallic compounds when the welding assembly of dissimilar metals is in service.
[0050] In addition, those skilled in the art will understand that any range or any value within the above-mentioned intervals is applicable to the present invention. For example, the average grain size of the connecting copper layer is 35nm to 400nm, which means that it can be taken from any range or any specific value within the range, for example: the average grain size is any range of 35nm to 320nm, 40nm to 300nm, 50nm to 300nm, 50nm to 280nm, 50nm to 250nm, 50nm to 200nm, 42nm to 200nm, 45nm to 150nm, 40nm to 150nm, 35nm to 100nm, 50nm to 150nm, or 50nm to 100nm, or any value such as the average grain size is 55nm, 55nm, 68nm, 75nm, 85nm, 90nm, 110nm, 140nm, 170nm, 220nm, 260nm, 275nm, 300nm, 320nm, 340nm, 368nm, etc. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] Figure 1 An example scenario including a welded assembly according to the present invention is shown;
[0052] Figure 2 shows a light illumination microscopy (SIM) image of a cross-section of a copper-clad ceramic substrate after a pre-plating copper layer is deposited according to a first embodiment of the present invention;
[0053] Figure 3 An atomic force microscope (AFM) image showing the surface morphology of a pre-plated copper layer on a copper-clad ceramic substrate after depositing the pre-plated copper layer according to the first embodiment of the present invention;
[0054] Figure 4 A scanning electron microscope (SEM) image showing a cross-section of a welded assembly according to a first embodiment of the present invention;
[0055] Figure 5 Shows Figure 4 Locally enlarged SEM image;
[0056] Figure 6 A transmission electron microscope (TEM) image showing a cross-section of a welded assembly according to a first embodiment of the present invention;
[0057] Figure 7 A SEM image of a shear section of a welded assembly according to a first embodiment of the present invention is shown;
[0058] Figure 8 The SEM image of the cross section of the welded assembly according to the first embodiment of the present invention after being kept at 250° C. for 165 hours is shown;
[0059] Fig. 9 A partially enlarged TEM image of a cross section of a welded assembly according to the first embodiment of the present invention after being heated at 250° C. for 165 hours is shown;
[0060] Fig.10 The SEM image of the shear cross section of the welded assembly according to the first embodiment of the present invention after being kept at 250° C. for 165 hours is shown;
[0061] Fig.11 A SEM image of a cross-section of a welded assembly according to a second embodiment of the present invention is shown;
[0062] Fig.12 A TEM image of a cross-section of a welded assembly according to a second embodiment of the present invention is shown;
[0063] Fig.13 The SEM image of the cross section of the welded assembly according to the second embodiment of the present invention after being kept at 250° C. for 165 hours is shown;
[0064] Fig.14 A partially enlarged TEM image of a cross section of a welded assembly according to a second embodiment of the present invention after being heated at 250° C. for 165 hours is shown;
[0065] Fig.15 A SEM image of a cross-section of a welded assembly according to a third embodiment of the present invention is shown;
[0066] Fig.16 A TEM image of a cross section of a welded assembly according to a third embodiment of the present invention is shown;
[0067] Fig.17 The SEM image of the cross section of the welded assembly according to the third embodiment of the present invention after being kept at 250° C. for 165 hours is shown;
[0068] Fig.18 A partially enlarged TEM image of a cross section of a welded assembly according to a third embodiment of the present invention after being heated at 250° C. for 165 hours is shown;
[0069] Fig.19 A first comparative example shows a welding assembly of a silicon-based IGBT chip and a copper-clad ceramic substrate welded by tin-based solder paste SAC305;
[0070] Fig. 20 shows a SEM image of a cross-section of the welded assembly of the first comparative example after being kept at 200° C. for 72 hours;
[0071] Fig.21 The SEM image of the shear section of the welded assembly of the first comparative example after being kept at 200° C. for 72 hours is shown;
[0072] Fig. 22 A SIM image of a cross section of a copper-clad ceramic substrate of a second comparative example after annealing of the pre-plated copper layer is shown;
[0073] Fig.23 An AFM image of the surface morphology of the pre-plated copper layer on the copper-clad ceramic substrate of the second comparative example after annealing is shown;
[0074] Fig.24 shows a SEM image of a cross-section of a welded assembly of a second comparative example; and
[0075] Fig.25 The SEM image of the cross section of the welded assembly of the second comparative example after being heated at 250° C. for 165 hours is shown. DETAILED DESCRIPTION
[0076] The present invention will be described below in conjunction with specific embodiments. Specific embodiments and the accompanying drawings show several embodiments, which are intended to illustrate the disclosure. It should be understood that, although one or more exemplary embodiments are shown below, the present disclosure should never be limited to the exemplary embodiments, drawings and techniques shown below, but can be modified within the scope of the appended claims and the full scope of their equivalents. It should be understood that any numbering (e.g., first, second, etc.) of the disclosed features and the directional terms (e.g., front, back, upper, lower, etc.) used with the disclosed features are relative terms representing the exemplary relationship between the related features or used to distinguish the related features. The word "example" is intended to be used as an example, instance or explanation when used in this article. Unless explicitly stated, all ranges include end values. It will be understood by those skilled in the art that the data and various parameters recorded in the embodiments are exemplary only and do not constitute a limitation of the present invention.
[0077] The inventors have found that tin-based welding components have the defect of low strength, mainly for the following reasons: on the one hand, tin metal is very active and will react with various components of the surface to be welded during the packaging process to generate brittle intermetallic compounds, such as reacting with Au to generate AuSn4, reacting with Ag to generate Ag3Sn, reacting with Cu to generate Cu3Sn, Cu6Sn5, and reacting with Ni to generate Ni3Sn, etc. Since the energy for the generation and growth of the above-mentioned intermetallic compounds is generally low, they can be quickly generated and grown in a low temperature environment, forming a weak interface with low strength and easy to break under stress, making the device prone to early failure during service. On the other hand, tin atoms and dissimilar metal atoms diffuse with each other at the welding interface. In the case where the diffusion rates of the two atoms are significantly different, a large number of Cockendall holes will be formed near the welding interface due to the rapid diffusion of atoms but the vacancies left by the atoms that diffuse away cannot be filled in time, which will grow with the extension of service time to form a stress concentration area. Under stress, the welded assembly is very likely to crack along these holes, becoming an additional mechanically weak layer, causing the strength of the welded assembly to gradually decrease during service. At the same time, a large number of holes reduce the electrical conductivity and thermal conductivity of the welded assembly, which is not conducive to improving the power of the device.
[0078] Similarly, the Cockendale effect also exists for the interdiffusion between the coarse-grained copper layer and the non-copper metal layer. In the present invention, the copper with a grain size greater than 400nm is defined as coarse-grained copper, and the grain size not greater than 400nm is defined as fine-grained. For example, at 250°C, the diffusion rate of copper atoms in the gold layer is D Cu / Au 2.2×10 -18 m 2 / s, the diffusion rate of gold atoms in the coarse-grained copper layer D Au / Cu 2.4×10 -21 m2 / s, the former is about 1000 times that of the latter. Therefore, for a welded assembly formed by a coarse-grained copper layer and a non-copper metal layer, during the welding process of its formation and its subsequent use at high temperature, due to the slow diffusion of dissimilar metal atoms (such as gold atoms), it is impossible to make up for the gaps left in the coarse-grained copper layer due to the fast-diffused copper atoms, thereby generating a large number of Cockendale holes in the coarse-grained copper layer near the welding interface between the non-copper metal layer and the coarse-grained copper layer, which not only become the weak part of the device containing the welded assembly, but also reduce the electrical conductivity and thermal conductivity of the welded assembly, adversely affecting the performance of the device.
[0079] In order to avoid or at least reduce the impact of Kokendall holes on the performance of welded components, the inventors of the present invention propose to increase the diffusion rate of dissimilar metal atoms in the copper layer connected to it to make it similar to the diffusion rate of copper atoms, so that the diffusion rates of different atoms entering and leaving the copper layer are basically balanced to avoid or reduce the generation of holes. The inventors of the present invention realize that the diffusion rate of dissimilar metals can be adjusted by controlling the volume fraction of grain boundaries. This is because the atoms at the grain boundaries are loosely arranged, so compared with the energy barriers required for atoms to migrate inside neatly arranged grains, the energy barriers required for atoms to break the arrangement at the grain boundaries are lower, so the diffusion rate is high, so that the grain boundaries can provide high-speed channels for atomic diffusion. Therefore, the present invention proposes to use the fast diffusion characteristics of atoms at the grain boundaries to solve the above-mentioned problems.
[0080] Specifically, for the copper layer with a smaller grain size, the diffusion length of the dissimilar metal is greater than the grain size, thus satisfying the Harrison A-type diffusion model, that is, grain boundary diffusion and lattice diffusion occur simultaneously. In this case, considering the effective diffusion rate D of the two diffusion modes, eff It can be calculated by the following formula (1):
[0081] D eff =f gb D gb +D l (1)
[0082] in,
[0083] f gb is the grain boundary volume fraction;
[0084] D gb is the grain boundary diffusion coefficient;
[0085] D1 is the lattice diffusion coefficient;
[0086] Because D gb For the same system (e.g., Cu-Au system), factors such as D1 can be considered as fixed values at the same temperature, so the grain boundary volume fraction f can be adjustedgb To control the diffusion rate of the dissimilar metal in the system (specifically depending on the surface metal layer of the first component for welding) in the copper layer connected thereto (such as the connecting copper layer in the aforementioned welding assembly) so that it at least roughly matches the diffusion rate of copper atoms. In the present application, roughly matching the diffusion rate means that the diffusion rate of the dissimilar metal atoms is between 1 / 6 and 6 times the diffusion rate of the copper atoms, more preferably between 0.5 and 2 times.
[0087] f gb Affected by the grain size and can be calculated by the following formula (2):
[0088]
[0089] Among them, Δ is the grain boundary thickness, which is 0.5nm, and d is the grain size.
[0090] According to the formula, the control of the grain boundary volume fraction can be achieved by controlling the grain size. Because the operating temperature of the third-generation SiC semiconductor chip high-power devices in future applications is between 200 and 300°C, and the higher the operating temperature, the more susceptible it is to the Cockendall effect, so the temperature adjustment range targeted by the present invention is within the range of 200 to 300°C. Within this temperature range, by controlling the grain size of the connecting copper layer connected to the dissimilar metal to be no more than 400nm (that is, the connecting copper layer is a fine-grained copper layer), a grain boundary volume fraction of at least 0.375% is obtained, and the grain boundary volume fraction increases with the decrease of the grain size. For example, when the grain size is 35nm, the grain boundary volume fraction is as high as about 4.3%, so that the diffusion coefficient of the dissimilar metal in the above copper layer and the diffusion coefficient of copper in the dissimilar metal satisfy 1 / 6D Cu / X ≤D X / Cu-eff ≤6D Cu / X , where D Cu / X is the diffusion coefficient of Cu atoms in metal X; D X / Cu-eff is the effective diffusion coefficient of metal X atoms in the connecting copper layer. By reducing the difference between the diffusion coefficient of dissimilar metal atoms and the diffusion coefficient of copper atoms, the generation and growth of Cockendale holes during service are reduced or even suppressed.
[0091] If the average grain size of the above copper layer is greater than 400nm, the grain boundary volume fraction of the copper layer is less than 0.375%, so that there are not enough grain boundaries as fast channels to promote the rapid diffusion of dissimilar metals, that is, the difference in diffusion coefficients between dissimilar metal atoms and copper atoms is still large, and thus the problem caused by Cockendale holes cannot be significantly alleviated. In addition, although smaller grains (i.e., larger grain boundary volume fractions) can further increase the diffusion rate of dissimilar metal atoms in the copper layer, when the grains are too small, the diffusion rate of dissimilar metal atoms may be excessively higher than the diffusion coefficient of copper atoms, so that the Cockendale effect may still be caused. For this reason, the average grain size of the connecting copper layer is required to be not less than 35nm in the present invention, that is, the average grain size of the connecting copper layer connected between the two welded components is 35nm to 400nm.
[0092] Taking the Cu-X system where the dissimilar metals X are Au, Ag, Al, Ti, and Ni as an example, the D under the preferred grain size is calculated according to the above equation (1-2). X / Cu-eff , where D gb , D1 are respectively X / Cu-gb and D X / Cu-1 Table 1 lists the preferred grain sizes of the connecting copper layers of these Cu-X systems and the corresponding diffusion coefficients of the dissimilar metal X atoms in the connecting copper layer calculated based on the grain sizes, which satisfy the 0.5D Cu / X ≤D X / Cu-eff ≤2D Cu / X . D Cu / X is the diffusion coefficient of Cu atoms in metal X; D X / Cu D is the diffusion coefficient of metal X atoms in the connecting copper layer; X / Cu-gb is the grain boundary diffusion coefficient of metal X atoms in the connecting copper layer; D X / Cu-1 is the lattice diffusion coefficient of metal X atoms in the connecting copper layer; D X / Cu-eff is the effective diffusion coefficient of metal X atoms in the connecting copper layer, 1 *D X / Cu-eff is the effective diffusion coefficient of metal X atoms in the connecting copper layer with an average grain size of 35 nm, 2 *D X / Cu-eff is the effective diffusion coefficient of metal X atoms in the connecting copper layer with an average grain size of 400 nm, 1 *D X / Cu-eff and 2 *D X / Cu-eff Meet 1 / 6D Cu / X ≤D X / Cu-eff ≤6D Cu / X .
[0093] Table 1 Preferred grain size and diffusion coefficient at 250°C for the connecting copper layer of the Cu-X system
[0094]
[0095] Taking Cu / Au as an example, it is known that the diffusion rate of Cu in Au at 250°C is Cu / Au 2.2×10 -18 m 2 s -1 , and the diffusion rate of Au in Cu is D Au / Cu 2.4×10 -21 m 2 s -1 , which is much lower than the former. If the average grain size of the connecting copper layer is controlled at 35nm, the grain boundary volume fraction is f gb =3×0.5×10 -9 / (35×10 -9 )=0.0429, substituting into formula (1) we can get the effective diffusion rate D of Au in Cu at this time: Au / Cu-eff =(0.0429×1.0×10 -16 )+5.0×10 -24 =4.3×10 -18 m 2 s -1 , about D Cu / Au 2 times; accordingly, when the average grain size of the connecting copper layer is 140nm, according to formula (1), D Au / Cu-eff 1.1×10 -18 m 2 s -1 , is D Cu / Au 0.5 times; further, when the average grain size of the connecting copper layer is 400nm, according to formula (1), D Au / Cu-eff 3.8×10 -19 m 2 s -1 , about D Cu / Au Therefore, when the average grain size of the copper layer connected at 250°C is 35nm to 400nm, the effective diffusion rate of Au in Cu is D Au / Cu-eff Meet 1 / 6D Cu / Au ≤D Au / Cu-eff ≤6D Cu / Au , so that the diffusion rates of Cu and Au are roughly matched, which can effectively weaken the Kirkendall effect. Furthermore, when the average grain size of the connecting copper layer is 35nm~140nm, the effective diffusion rate of Au in Cu is D Au / Cu-eff Meet 0.5D Cu / Au ≤D Au / Cu-eff ≤2D Cu / Au, the further reduction of the difference in diffusion rate between Cu and Au makes it possible to further weaken the Kirkendall effect and obtain a soldered assembly with better performance. Similarly, for other dissimilar metals X, making the average grain size of the connecting copper layer 35nm to 400nm can also effectively reduce the difference in diffusion rate between the dissimilar metal X and Cu; further, at the preferred grain size corresponding to various metals, the difference in diffusion rate between the dissimilar metal X and Cu can be further reduced. In addition, although only schematic data at 250°C are given, the preferred average grain size of the connecting copper layer will be applicable to the expected temperature range of 200 to 300°C.
[0096] Furthermore, in order to obtain the desired grain boundary volume fraction of the connecting copper layer (i.e., the fine-grained copper layer) in the welding assembly, i.e., the desired grain size, the manufacturing method of the present invention proposes to control the grain size of the pre-plated copper layer used for welding, so that the grain size of the connecting copper layer is 35nm to 400nm. In this case, whether during the formation of the welding assembly or during the service period of the obtained welding assembly, the small grain size of the pre-plated copper layer and the connecting copper layer increases the diffusion rate of the dissimilar metals to be welded in the pre-plated copper layer and the connecting copper layer, respectively, so that it is roughly close to the diffusion rate of copper in the dissimilar metals, thereby avoiding or at least reducing the generation and growth of Cockendale holes during the welding process and during service, thereby avoiding or at least weakening the performance degradation of the welding assembly caused by the Cockendale effect as a whole, and improving the performance of the welding assembly. At the same time, the stable nature of copper itself also avoids the generation of brittle intermetallic compounds during the welding process, thereby avoiding the influence of intermetallic compounds on the performance of the obtained welding assembly.
[0097] In the present invention, porosity is defined as the ratio of the total pore area to the sampling area. The method for measuring the porosity of a welded assembly is as follows: on the cross-sectional surface of the obtained welded assembly, sampling is performed within a range with a width of 1 μm extending outward from the aforementioned first interface and the aforementioned second interface respectively away from the aforementioned connecting copper layer (that is, the connecting copper layer is included) and a length of any 10 μm along the length direction of the first / second interface, and the total area of all visible pores within the sampling range at each position is measured by the image processing software ImageJ. Then, the porosity at each sampling position is calculated based on the measurement results and the average value is taken. Figure 4 As schematically shown, the width of the field of view extends 1 μm away from the interface between the gold layer and the connecting copper layer and the interface between the connecting copper layer and the coarse-grained copper layer, respectively, and the length is any 10 μm along the length direction of the interface.
[0098] In the present invention, the resistivity of the connecting copper layer is tested as follows: by simulating a welding scene, a pre-plated copper layer of the same thickness as the actual welding is deposited on the surface of the first copper layer of a silicon wafer having a first copper layer of 1 μm, a non-copper metal layer of the same thickness as the non-copper metal layer on the outermost surface of the component to be welded is directly sputtered on the pre-plated copper layer, and heating and pressurizing are performed to simulate the welded assembly obtained after welding. Then, a four-point probe thin film resistivity measurement is performed on the surface of the welded assembly, and the measured depth covers the non-copper metal layer, the connecting copper layer and a small amount of the first copper layer. The resistivity can reflect the influence of the Cockendale holes on the welded assembly.
[0099] In the present invention, the shear fracture test method is as follows: the bottom of the second part of the welded assembly is fixed on the test platform by resin, a movable mechanical part is pressed against the side of the first part of the welded assembly, and a shear force is applied parallel to the sample at a moving speed of 20 μm / min. Five samples of each product are tested and the average value is taken.
[0100] The excellent performance of the welding assembly of the present invention will be described below in conjunction with specific examples. It will be understood that the following embodiments are merely specific examples of the welding assembly of the present invention and are not intended to limit the present invention in any way.
[0101] Figure 1 The combined soldering assembly according to the present invention is schematically shown, which schematically shows various application scenarios to which the soldering assembly of the present invention can be applied, such as a soldering assembly consisting of a chip and a copper conductive film. It will be understood that the multiple scenarios shown can exist separately or in combination and will be schematically described in each embodiment.
[0102] First embodiment
[0103] The method for producing a welded assembly according to a first embodiment of the present invention is as follows:
[0104] Step 1.1 provides a copper-clad ceramic substrate and a silicon-based IGBT chip to be welded together, wherein the surface of the copper-clad ceramic substrate has an initial copper layer with a thickness of about 2.4 μm, which is composed of an average grain size of not less than 500 nm (see Figure 2 ) coarse crystal formation. When measuring the grain size, the maximum size of each grain shown in the figure is used; the back metal layer of the silicon-based IGBT chip is titanium layer, nickel layer and gold layer from the inside to the outside.
[0105] Step 1.2: The surface of the initial copper layer of the copper-clad ceramic substrate is cleaned with acetone, anhydrous ethanol and dilute hydrochloric acid (HCl:H2O=1:1, by volume fraction) in sequence by ultrasonic cleaning, and then rinsed with deionized water and dried to remove surface impurities and an oxide layer;
[0106] Step 1.3: Clean the surface of the gold layer of the silicon-based IGBT chip with acetone, anhydrous ethanol and isopropyl alcohol (IPA) in turn by ultrasonic cleaning, then rinse with deionized water and dry;
[0107] Step 1.4: Deposit a pre-plated copper layer in a 10 mm × 10 mm area on the surface of the initial copper layer by electrochemical deposition, wherein the electrochemical deposition parameters are as follows: direct current plating, current density 0.05-0.15 A / cm 2 The electrolyte solution contains 200-250 g / L of anhydrous copper sulfate, 10-50 ml / L of sulfuric acid and 0.01-0.05 g / L of thiourea. The deposition time is 60 seconds and the solution temperature is 30°C. Figure 2 The SIM image of the cross section of the copper-clad ceramic substrate after the pre-copper layer is deposited is shown, wherein the average thickness of the deposited pre-copper layer is about 100 nm. In actual production applications, the thickness of the connecting copper layer can be appropriately adjusted as needed. In order to protect the deposited pre-copper layer when making the cross section, a Pt protective layer is additionally deposited on the pre-copper layer before cutting. Figure 3 An AFM image of the surface morphology of the pre-plated copper layer on the copper-clad ceramic substrate after the pre-plated copper layer is deposited is shown, wherein the average grain size of the pre-plated copper layer is about 30nm, which is much smaller than the grain size of the initial copper layer below it. Preferably, similarly, the pre-plated copper layer can also be deposited on the gold layer of the silicon-based IGBT chip. Preferably, in order to avoid the influence of specific grain orientation in a single layer of grains on the atomic diffusion rate, the thickness of the pre-plated copper layer is at least 2 times the average grain size, more preferably 3 times.
[0108] Step 1.5: Cleaning the surface of the pre-plated copper layer of the copper-clad ceramic substrate with dilute hydrochloric acid (HCl:H2O=1:1, calculated by volume fraction) to remove the surface oxide layer;
[0109] Step 1.6: Lay the gold layer of the silicon-based IGBT chip and the pre-plated copper layer of the copper-clad ceramic substrate together in surface contact to form a stacked structure;
[0110] Step 1.7: in a helium protective environment at a temperature of 280° C., pressurizing the stacked structure from the top and bottom respectively, with a pressure of 20 MPa and a holding time of 10 minutes; and
[0111] Step 1.8: Air-cool the connected silicon-based IGBT chip and copper-clad ceramic substrate to room temperature to obtain a soldered assembly.
[0112] The resulting welded assembly was sectioned in order to better illustrate assembly details. Figure 4 FIG. 4 shows a SEM image of a cross-section of a welded assembly obtained by the above method according to a first embodiment of the present invention. Figure 5 for Figure 4A partial enlarged view of Figure 4 and Figure 5 As shown, the obtained welding assembly includes a silicon-based IGBT chip, a copper-clad ceramic substrate and a connecting copper layer between the two and fixing the two together, which is a fine-grained copper layer. The two sides of the fine-grained copper layer are respectively combined with the outermost gold layer of the chip and the coarse-grained copper layer (i.e., the first copper layer) of the copper-clad substrate to form a first interface and a second interface respectively. Figure 4 The middle circle is the pore location, and all pores are no larger than 200nm (based on the maximum size that can be measured for each pore shown in the figure). Figure 5 This is also confirmed by the white dotted line, which is the interface between the gold layer and the fine-grained copper layer identified by the software, and the black dotted line is the interface between the coarse-grained copper layer and the fine-grained copper layer identified by the software. Figure 5 As shown, there are several holes on the fine-grained copper layer side near the interface between the gold layer and the fine-grained copper layer. The holes will be measured later to calculate the porosity.
[0113] Figure 6 The TEM image of the cross section of the welding assembly according to the first embodiment of the present invention is shown, wherein the average grain diameter of the fine-grained copper layer is about 70nm and the thickness is about 100nm. Compared with the pre-copper layer before forming the welding assembly, the grain size of the connecting copper layer increases, but the thickness remains basically unchanged, because: during the welding process, the grains of the pre-copper layer grow by swallowing each other. This swallowing is carried out by the gradual movement of the grain boundaries, that is, the grain boundaries of some grains advance toward other grains around them, thereby swallowing up other grains. Therefore, the connecting copper layer of the obtained welding assembly can inherit the thickness of the pre-copper layer when the grains grow. Nanocrystals are very active, so they are very easy to grow through this swallowing at welding temperature. However, after the grain size exceeds 100nm, the activity of the nanocrystals decreases exponentially and grows slowly (see subsequent Examples 2 and 3).
[0114] According to formula (1), where D gb , D1 are respectively taken as D Au / Cu-gb and D Au / Cu-1 , at 200℃, D Au / Cu-gb =7.3×10 -19 m 2 s - 1, D Au / Cu-1 =1.0×10 -24 m 2 s - 1. The grain size of 70 nm makes the effective diffusion rate of gold atoms in the fine-grained copper layer at 200°C D Au / Cu-eff Reach 1.6×10 -20 m 2 s-1 , compared with the effective diffusion rate D of coarse-grained copper Au / Cu-eff′ =3.2×10 -23 m 2 s -1 (grain size greater than 500nm) and the diffusion rate of copper atoms in the gold layer (7.3×10 -21 m 2 s -1 ) is closer; at 300℃, D Au / Cu-gb =4.8×10 -15 m 2 s - 1, D Au / Cu-1 =9.0×10 -24 m 2 s - 1. Calculation of D Au / Cu-eff Reach 1.0×10 -16 m 2 s -1 , compared with the D Au / Cu-eff ′=9.4×10 -20 m 2 s -1 , and the diffusion rate of copper atoms in the gold layer (6.0×10 -17 m 2 s -1 ) is closer. Therefore, the soldered assembly with the above-mentioned connecting copper layer can avoid or at least weaken the influence of the Cockendall effect on its performance during subsequent use at 200-300°C. This is verified in the subsequent high temperature durability test results.
[0115] In order to calculate the porosity, five locations ( Figure 4 The sampling is performed within the following field of view: the width is 1 μm extending outward from the first interface between the gold layer and the connecting copper layer and the second interface between the connecting copper layer and the coarse-grained copper layer away from the connecting copper layer (i.e., the connecting copper layer is included), and the length is any 10 μm along the length direction of the first / second interface. In this example, the sampling range is about 22 μm. 2 , to measure the total pore area at each position, and the specific measurement results are listed in Table 2. According to Table 2, the average porosity of this embodiment is about 0.79±0.09%. In addition, the maximum size of the pores at each sampling position does not exceed 200nm.
[0116] In addition, the resistivity of the connecting copper layer was tested. Specifically, by simulating the welding scene, a pre-plated copper layer with a thickness of 100nm and a grain size of 30nm was deposited on the surface of a silicon wafer with a 1μm first copper layer, and a 100nm gold layer was directly sputtered on the pre-plated copper layer, and the welding assembly obtained after the welding was simulated according to the aforementioned heating and pressurization. The average resistivity of the connecting copper layer was 3.0±1.4μΩ·cm measured by the four-point probe thin film resistivity. This low resistivity corresponds to the low porosity, which is conducive to the high-power operation of the welding assembly.
[0117] Table 2 Porosity of the first embodiment according to the present invention (sampling area is about 22 μm 2 )
[0118] Position 1 Position 2 Location 3 Position 4 Location 5 <![CDATA[Pore area / μm 2 > 0.15 0.18 0.10 0.22 0.23 Porosity 0.68% 0.81% 0.45% 1.0% 1.0%
[0119] The welding assembly of this embodiment was subjected to a shear fracture test, and the shear strengths of the five samples were 35.8 MPa, 36.6 MPa, 38.2 MPa, 34.7 MPa and 36.2 MPa, respectively, and the average shear strength was 36.3±1.2 MPa. Figure 7 The SEM image of the shear section of the welded assembly of this embodiment is shown, wherein the section exhibits ductile fracture.
[0120] In addition, in order to verify the service stability of the welding assembly of the present invention, the welding assembly of this embodiment was subjected to a high temperature durability test, and the test parameters were as follows: the sample was kept at 250°C for 165 hours in a vacuum environment; after the heat preservation was completed, the sample was air-cooled. Afterwards, as described above, the porosity measurement, resistivity and shear fracture tests were performed on the sample that had undergone the high temperature durability test.
[0121] Figure 8 and Fig. 9 Both show images of the cross-section of the welded assembly according to the first embodiment of the present invention after the high temperature durability test, wherein no obvious Cockendale holes are observed and no intermetallic compounds are generated. The average porosity of the welded assembly after the high temperature durability test remains almost unchanged at 0.82±0.15%; the average resistivity is slightly increased at 3.5±1.2μΩ·cm. For the shear fracture test, the shear strengths of the five samples after the high temperature durability test were 32.7MPa, 35.2MPa, 33.8MPa, 34.5MPa and 31.3MPa, respectively, and the average shear strength was 33.5±1.3MPa, which was only about 7.7% lower than the shear strength before the high temperature durability test, and still exhibited excellent shear resistance. In addition, as Fig.10 As shown, the shear section of the welded assembly after the high temperature durability test still shows a ductile fracture without oxide concentration.
[0122] In combination with the above, it can be known that the welded assembly obtained according to the first embodiment of the present invention has a porosity of no more than 1%, a resistivity of the connecting copper layer of about 3.0±1.4μΩ·cm, and a shear strength of 36.3±1.2MPa; at the same time, even after the high temperature durability test, the welded assembly has low porosity and resistivity and high shear strength, achieving long-term reliable service of the welded assembly under high power use. This is attributed to the fact that in the welded assembly, there are very few Cockendale holes or even if they exist, they are very small in size, so that the embodiment can avoid or at least weaken the performance impact of Cockendale holes on the welded assembly.
[0123] Second embodiment
[0124] The method for producing a welded assembly according to the second embodiment of the present invention is similar to the method of the first embodiment, except for the following differences:
[0125] 1) The parts to be welded are a copper-clad ceramic substrate and an aluminum radiator, and the surface layer of the aluminum radiator is an aluminum layer;
[0126] 2) Current density in electrochemical deposition 0.01~0.04A / cm 2 The electrolyte solution contains 200-250 g / L of anhydrous copper sulfate, 10-50 ml / L of sulfuric acid and 0.005-0.01 g / L of thiourea, the deposition time is 250 seconds, and the solution temperature is 30°C. The average thickness of the deposited pre-plated copper layer is about 700 nm, and the average grain size is about 200 nm (the measurement method is the same as that of the first embodiment, so it will not be described in detail). This average thickness can avoid the appearance of single-layer grains during the welding process and the use of the obtained welded assembly to reduce the influence of specific grain orientation on the atomic diffusion rate. Similarly, the pre-plated copper layer can also be deposited on the aluminum layer of an aluminum heat sink.
[0127] 3) Welding steps: In a helium protective environment at a temperature of 280° C., pressurize the stacked structure from the top and bottom respectively, with a pressure of 20 MPa and a heat preservation time of 15 minutes.
[0128] Fig.11 The cross-sectional SEM image of the welding assembly of the second embodiment obtained by the above method is shown, wherein the welding assembly includes an aluminum heat sink, a copper-clad ceramic substrate, and a connecting copper layer between the two to fix the two together, which is a fine-grained copper layer, and the two sides of the fine-grained copper layer are respectively combined with the surface aluminum layer of the aluminum heat sink and the coarse-grained copper layer of the copper-clad substrate to form a first interface and a second interface, such as respectively Fig.11 As shown by the white dotted line and the black dotted line in .
[0129] Similar to the first embodiment, the welded assembly of the second embodiment was measured and tested accordingly. Fig.12 The TEM image of the cross section of the welded assembly according to the second embodiment of the present invention is shown, wherein the black dashed line shows several grains in the connecting copper layer. Due to the heat of welding, the average grain diameter of the connecting copper layer grows to about 220nm, but the thickness is still about 700nm. The average porosity of the welded assembly of the second embodiment is 0.76±0.05%, the average resistivity of the connecting copper layer is 3.8±0.8μΩ·cm, and the shear strength is 35.8±1.1MPa. Fig.13 and Fig.14 The SEM and TEM images of the cross-section of the welded assembly according to the second embodiment of the present invention after the high temperature durability test are respectively shown, wherein no obvious Kokendall holes are observed, and no intermetallic compound is observed. After the high temperature durability test, the average porosity is 0.83±0.10%, the average resistivity of the connecting copper layer is 4.3±1.0μΩ·cm, and the shear strength is 34.0±2.2MPa. The shear section of the welded assembly of the second embodiment shows ductile fracture characteristics both before and after the high temperature durability test.
[0130] Likewise, the welded assembly of the second embodiment also has low porosity and resistivity and high shear strength, thereby enabling the welded assembly to serve reliably for a long period of time under high power use.
[0131] Third embodiment
[0132] The method for producing a welded assembly according to the third embodiment of the present invention is similar to the method of the first embodiment, except for the following differences:
[0133] 1) The components to be welded are a copper conductive film and a silicon carbide MOSFET chip, wherein the copper conductive film is a coarse-grained copper film with a thickness of 20 μm, which is formed by coarse crystals with an average grain size of not less than 500 nm; the front metal layer of the silicon carbide-based MOSFET chip is a titanium layer, a nickel layer and a silver layer from the inside to the outside;
[0134] 2) The pre-plated copper layer is deposited on the copper conductive film, wherein the current density in the electrochemical deposition is 0.005 to 0.015 A / cm 2 The deposition time is 350 seconds, the electrolyte solution includes 200-250 g / L of anhydrous copper sulfate, 10-50 ml / L of sulfuric acid and 0.005-0.01 g / L of thiourea, so that the average thickness of the deposited pre-plated copper layer is about 1 μm and the average grain size is about 360 nm; similarly, the pre-plated copper layer can also be deposited on the gold layer of the silicon-based IGBT chip.
[0135] 3) Welding steps: In a helium protective environment at a temperature of 280° C., pressurize the stacked structure from the top and bottom respectively, with a pressure of 15 MPa and a heat preservation time of 20 minutes.
[0136] Fig.15 The cross-sectional SEM image of the welding assembly of the third embodiment obtained by the above method is shown, wherein the welding assembly includes a silicon carbide MOSFET chip, a copper conductive film, and a connecting copper layer between the two to fix the two together, which is a fine-grained copper layer, and the two sides of the fine-grained copper layer are respectively combined with the surface silver layer of the silicon carbide MOSFET chip and the coarse-grained copper layer of the copper conductive film to form a first interface and a second interface respectively, such as Fig.15 As shown by the white dotted line and the black dotted line in .
[0137] Similar to the first embodiment, the welding assembly of the third embodiment was measured and tested accordingly. Fig.16 A TEM image of a cross-section of a soldered assembly according to a third embodiment of the present invention is shown, wherein the average grain diameter of the connecting copper layer is about 380 nm. The average porosity of the soldered assembly of the third embodiment is 0.82±0.11%, the average resistivity of the connecting copper layer is 3.1±1.0 μΩ·cm, and the shear strength is 33.4±1.3 MPa. Fig.17 Fig.18 Both show SEM images of the cross-section of the welded assembly according to the third embodiment of the present invention after the high temperature durability test, wherein no obvious Kokendall holes are observed, and no intermetallic compound is generated. After the high temperature durability test, the average porosity of the welded assembly is 1.39±0.09%, the average resistivity of the connecting copper layer is 6.2±1.1μΩ·cm, and the shear strength is 32.8±1.2MPa. The shear section of the welded assembly of the third embodiment shows ductile fracture characteristics both before and after the high temperature durability test.
[0138] Likewise, the welding assembly of the third embodiment also has low porosity and resistivity and high shear strength, thereby enabling the welding assembly to serve reliably for a long time under high power use.
[0139] These embodiments show that the welding assembly of the present invention has excellent performance (high electrical conductivity and thermal conductivity and high shear strength), and can still maintain excellent performance after long-term use in a high-temperature environment, ensuring the stability and reliability of the device containing such welding assembly in long-term service. This is because, first, the welding assembly of the present invention itself contains very few defects such as Cockendale holes, so these defects have little effect on the subsequent service performance; second, the fine grains of the connecting copper layer in the welding assembly increase the diffusion rate of dissimilar metal atoms therein, thereby weakening the Cockendale effect caused by the difference in diffusion rate, thereby inhibiting or at least slowing down the generation and growth of Cockendale holes, thereby improving the stability of the welding assembly in service; and third, the stable nature of copper itself avoids the generation of brittle intermetallic compounds during the welding process and subsequent service, thereby avoiding the influence of intermetallic compounds on the performance of the obtained welding assembly.
[0140] The first comparison
[0141] The silicon-based IGBT chip and the copper-clad ceramic substrate are soldered using the tin-based solder paste SAC305 commonly used in the industry. The specific steps are as follows: the silicon-based IGBT chip and the copper-clad ceramic substrate are cleaned respectively to remove surface impurities and dried, wherein the back metal layer of the silicon-based IGBT chip is a titanium layer, a nickel layer and a gold layer from the inside to the outside, and the copper-clad ceramic substrate has an initial copper layer; the tin-based solder paste is printed on the surface of the initial copper layer of the copper-clad ceramic substrate with a tape to print 10mm×10mm, with a thickness of about 30μm; then, the gold layer of the chip is superimposed on the tin-based solder paste on the copper-clad ceramic substrate to be in surface contact, so as to form a stacked structure of chip-tin-based solder paste-copper-clad ceramic substrate; then, the above-mentioned stacked structure is maintained at a temperature of 250°C for 2 minutes in a vacuum environment; and finally, it is air-cooled to room temperature.
[0142] The welded assembly obtained by the above method is as follows Fig.19 As shown, the welding assembly includes a silicon-based IGBT chip, a copper-clad ceramic substrate and a joint between the two. The joint is composed of an intermetallic compound layer 1, a tin solder layer and an intermetallic compound layer 2 from top to bottom. The intermetallic compound layer 1 and the intermetallic compound layer 2 of the joint are respectively combined with the outermost gold layer of the chip and the coarse-grained copper layer of the copper-clad substrate to form a first interface and a second interface respectively. Fig.19As shown by the white dotted lines in the figure, these white dotted lines are the interfaces between the layers identified by the software. The area of the formed intermetallic compound in the cross-sectional view is calculated by the edge recognition, and the average thickness of the intermetallic compound is determined by the ratio of the area to the straight line length of the interface. Five positions on the cross-section of the same sample were sampled, and the average thickness of the intermetallic compound 1 layer of the joint was calculated to be 7.2μm, the average thickness of the intermetallic compound 2 layer was 5.3μm, the porosity sampling range length was 10μm, and the width was 1μm above the first interface between the gold layer on the chip surface and the intermetallic compound 1 layer to 1μm below the second interface between the intermetallic compound 2 layer and the coarse-grained copper layer. The sampling range includes at least the intermetallic compound 1 layer, the tin solder layer and the intermetallic compound 2 layer, and all three layers are Cockendale pore aggregation areas. The average porosity of the soldered assembly of this comparative example is 4.4±1.5% and the resistivity is 140±2μΩ·cm.
[0143] Table 3 Porosity of the first comparative example according to the present invention (sampling area is about 300 μm 2 )
[0144] Position 1 Position 2 Location 3 Position 4 Location 5 Pore area 7.5 14.1 16.5 8.0 19.5 Porosity 2.5% 4.7% 5.5% 2.6% 6.5%
[0145] Similarly, a shear fracture test was performed on the welding assembly of the comparative example. The shear strengths of the five samples were 22.1 MPa, 24.5 MPa, 23.8 MPa, 22.9 MPa and 26.2 MPa, respectively. The average shear strength was 23.9±0.6 MPa, which was significantly lower than the shear strength of the embodiments of the present application (approximately 33-36 MPa).
[0146] In addition, the comparative welding components were also subjected to a high temperature durability test, and the test parameters were as follows: the samples were kept at 200°C in a vacuum environment for 72 hours; after the insulation was completed, the samples were air-cooled.
[0147] After the high temperature durability test, the sections of the same sample were sampled at 5 different locations. Fig. 20 As shown, a large number of Cockendale pores are generated at the interface (porosity is 10.8±2.1%), which will adversely affect the shear performance of the welded assembly. It was measured that the average thickness of the intermetallic compound 1 layer was 7.8μm; and the average thickness of the intermetallic compound 2 layer was 9.5μm, which increased by about 79.2% compared to before the high temperature durability test. This is because the energy required for the generation of Cu / Sn metal compounds is less than that of Au / Sn, so the thickness of the intermetallic compound 2 layer close to the coarse-grained copper layer grows faster. The increase in the thickness of the intermetallic compound means that when the welded assembly obtained by tin-based solder paste is used at high temperature, the welded assembly will undergo significant changes, combined with the generation and growth of Cockendale pores, which will adversely affect the stability and durability of the welded assembly.
[0148] The shear fracture test results confirmed this adverse effect. The shear strengths of the five samples after the high temperature durability test were 18.0 MPa, 15.6 MPa, 23.8 MPa, 22.3 MPa and 20.6 MPa, respectively, with an average shear strength of 20.3 ± 1.3 MPa, which was about 15% lower than the shear strength before the high temperature durability test, much higher than the shear strength drop of the welding assemblies of the various embodiments of the present invention after the high temperature durability test. In addition, Fig.21 As shown, the shear section of the welded assembly of the comparative example after the high temperature durability test presents a rock candy-like fracture, which is an obvious brittle fracture feature.
[0149] The welded assembly of the comparative example not only has an intermetallic compound layer, but also contains more than 5% porosity, which disadvantageously reduces the shear strength of the obtained welded assembly. Furthermore, since these intermetallic compounds and pores will further form and grow during the service of the welded assembly, the electrical conductivity and thermal conductivity, service stability and durability of the welded assembly are adversely affected.
[0150] The second comparison
[0151] The method for producing the welded assembly of the second comparative example is similar to that of the first embodiment, except for the following differences:
[0152] 1) The copper-clad ceramic substrate has an initial copper layer with a thickness of about 1 μm and an average grain size of not less than 500 nm;
[0153] 2) After electrochemically depositing the pre-plated copper layer, annealing is performed to allow the grains to grow, wherein the electrochemical deposition parameters are as follows: direct current plating, current density 0.005-0.015A / cm 2 The electrolyte solution is 200-250g / L anhydrous copper sulfate, 10-50ml / L sulfuric acid, the deposition time is 400 seconds, and the solution temperature is 30°C. Fig. 22 SIM images of a cross-section of a copper-clad ceramic substrate after annealing of the pre-plated copper layer are shown, wherein the average thickness of the pre-plated copper layer is about 1 μm. Fig.23 As shown, the average grain size of the pre-plated copper layer is about 500 nm.
[0154] 3) Welding steps: In a helium protective environment and at a temperature of 400° C., pressurize the stacked structure from the top and bottom respectively, with a pressure of 20 MPa and a heat preservation time of 30 minutes.
[0155] Fig.24The SEM image of the cross-section of the welding assembly of the second comparative example obtained by the above method is shown, wherein the obtained welding assembly includes: a silicon-based IGBT chip, a copper-clad ceramic substrate, and a coarse-grained copper layer between the two and fixing the two together: the two sides of the coarse-grained copper layer are respectively combined with the outermost gold layer of the chip and the initial copper layer of the copper-clad substrate. Since the grain size of the coarse-grained copper layer and the initial copper layer of the copper-clad substrate are similar, migration through the grain boundaries at high temperatures causes the coarse-grained copper layer and the initial copper layer of the copper-clad ceramic substrate to be unable to be directly distinguished by the software. As mentioned above, during the welding process, the thickness of the pre-plating layer remains substantially unchanged. Therefore, during Fig.24 and Fig.25 In FIG. 1 , the boundary of the coarse-grained copper layer theoretically formed by the pre-plated copper layer is shown by the black dotted line 1 μm below the interface between the gold layer and the coarse-grained copper layer shown by the white dotted line. There is no connecting copper layer with fine grains in this soldered assembly.
[0156] Similar to the first embodiment, the welding assembly of the second comparative example was measured and tested accordingly. For the porosity measurement, the sampling range is as follows: the length is any 10 μm along the length direction of the interface, the width is 1 μm above the interface between the gold layer and the coarse-grained copper layer (i.e., the white dotted line) to 1 μm below the interface between the coarse-grained copper layer formed by the pre-plated copper layer and the initial copper layer of the copper-clad ceramic substrate (i.e., the black dotted line), and the measurement area is about 30 μm 2 The porosity of the welded assembly of the second comparative example was 0.95±0.20%, the average resistivity of the coarse-grained copper layer was 4.0±0.9 μΩ·cm, and the shear strength was 33.8±1.0 MP.
[0157] Fig.25 The SEM image of the cross-section of the welded assembly of the second comparative example after being kept at 250°C for 165 hours is shown, wherein a large number of Kokendall holes exist in the coarse-grained copper layer near the interface between the gold layer and the copper layer. It can be seen from the measurement that after the high temperature durability test, the maximum size of a single pore is up to about 460nm. The porosity and resistivity increased significantly, to about 8.53±0.12% and 58±2μΩ·cm, respectively, and the shear strength dropped sharply to 22.3±1.8Mpa. In addition, the shear section of the welded assembly of the second comparative example changed from the previous ductile fracture to brittle fracture after the high temperature durability test.
[0158] The relevant measurement data of each embodiment and comparative example are listed in Table 4.
[0159] Table 4 Porosity, resistivity and shear strength of each embodiment and comparative example (all average values)
[0160]
[0161] Note: 1Data measured before high temperature durability test; 2 Data measured after high temperature durability test.
[0162] Compared with the tin-based solder paste of the first comparative example, the soldering assemblies of the three embodiments using the pre-plated copper layer, whether when not in use or after the high temperature durability test, all show low porosity and resistivity and high shear strength, which is better than the soldering assemblies obtained by tin-based solder. This is because, on the one hand, the pre-plated copper layer itself is denser than the tin-based solder paste, which effectively eliminates the gaps between the particles in the solder paste; at the same time, the small grain size of the connecting copper layer makes the mutual diffusion rate between dissimilar metals (such as aluminum, gold, silver, nickel, etc.) and copper roughly the same, which greatly reduces the generation and growth of Cockendall holes, thereby weakening its adverse effects on the long-term stability and reliability of the soldering assembly; on the other hand, the stable nature of copper itself makes the soldering assembly free of brittle intermetallic compounds and can also inhibit the generation of the latter during use, thereby eliminating the adverse effects caused by the intermetallic compounds.
[0163] For the second comparative example, although its soldered assembly can have the same performance as the embodiment of the present invention when not in use, its durability test result is very poor, and it cannot achieve good stability and reliability in use. It can be seen that the use of a dense pre-plated copper layer does not necessarily result in a soldered assembly with good service performance.
[0164] By comparing the second comparative example with the embodiments of the present invention, it can be found that in order to achieve good service performance, there are requirements for the grain size of the connecting copper layer of the formed welding assembly. As shown in the second comparative example, when the grain size of the joint of the welding assembly is greater than 400nm, the service stability and conductivity of the welding assembly are insufficient. In contrast, as verified in the embodiments, when the average grain size of the connecting copper layer is 35nm to 400nm, the small grain size provides a fast diffusion channel for the dissimilar metals, so that the diffusion rate of the dissimilar metal atoms and the copper atoms meets 1 / 6D. Cu / X ≤D X / Cu-eff ≤6D Cu / X , so that the Cockendall effect can be effectively weakened during the service of the welded assembly, that is, the generation and growth of Cockendall holes are greatly reduced, ensuring the stability and conductivity of the welded assembly during the subsequent service period. Therefore, the present invention requires that the average grain size of the connecting copper layer obtained by the pre-copper plating layer is 35nm to 400nm on the basis of requiring the use of a pre-copper plating layer to weld the first component and the second component, so as to ensure the stability and durability of the welded assembly in a high-temperature service environment.
[0165] In addition, the results of each embodiment also show that within this range, the smaller the grain size, the better the effect of suppressing the Kokendall pores. For example, compared with a larger grain size, such as 380nm in the third embodiment, when the grain size is 70nm to 220nm, the porosity after high temperature insulation can still be maintained below 1%, the resistivity is below 5μΩ·cm, and the shear performance is above 33MPa, thereby further improving the performance. In addition, Table 1 shows that for different metals, due to differences in diffusion coefficients, their preferred average grain sizes will be different. Therefore, a more preferred average grain size can be selected for actual use conditions to further reduce the difference in diffusion rates between dissimilar metals and achieve better performance.
[0166] The present invention also includes a welding assembly for semiconductor chip packaging involving multiple components. For example, the welding assembly of the present invention includes a welding assembly formed by at least two of the first, second and third embodiments. For example, Figure 1 As shown, a welding assembly according to another embodiment of the present invention comprises:
[0167] A semiconductor chip, wherein a non-copper metal layer is disposed on the outermost layer on the first side and the second side of the semiconductor chip;
[0168] A copper-clad substrate, wherein a first copper layer and a second copper layer are respectively arranged on a first side and a second side of the copper-clad substrate;
[0169] an aluminum heat sink having an aluminum layer disposed on a first side of the heat sink;
[0170] a copper conductive film, wherein a third copper layer is disposed on a first side of the copper conductive film;
[0171] a first connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the first side of the semiconductor chip and the third copper layer to fix the semiconductor chip and the copper conductive film together;
[0172] A second connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the second side of the semiconductor chip and the first copper layer to fix the semiconductor chip and the copper-clad substrate together; and
[0173] a third connecting copper layer, two sides of which are respectively connected to the second copper layer and the aluminum layer to fix the copper-clad substrate and the aluminum heat sink together;
[0174] Wherein, the average grain size of the first, second and third connection copper layers is 35nm-400nm.
[0175] Preferably, the first, second and third connection copper layers may have a preferred grain size selected according to the metals actually connected and their thickness is at least one time of the grain size.
[0176] The above embodiments and experimental data are intended to illustrate the present invention by way of example. It should be clear to those skilled in the art that the present invention is not limited to these embodiments, and various changes may be made without departing from the scope of protection of the present invention. In addition, the steps in any of the above methods may not necessarily occur in the order depicted in the accompanying drawings, and in some cases, one or more of the depicted steps may occur substantially simultaneously, or may involve additional steps.
Claims
1. A welding assembly for power semiconductor module packaging, the welding assembly comprising: a first component, the outermost layer on the first side of the first component being a non-copper metal layer; a second component having a first copper layer disposed on a first side of the second component; A connecting copper layer, two sides of which are respectively connected to the non-copper metal layer and the first copper layer to form a first interface and a second interface, thereby fixing the first component and the second component together, Wherein, the average grain size of the connecting copper layer is 35nm-400nm.
2. The welding assembly according to claim 1, wherein: The average grain size of the connecting copper layer is 35 nm to 380 nm, and the average thickness thereof is 70 nm to 5 μm and is at least one time of the average grain size.
3. The welding assembly according to claim 1, wherein: Within a range of a width of 1 μm extending outward from the first interface and the second interface respectively away from the connection copper layer and a length of any 10 μm along the length direction of the first interface, the average porosity of the soldered assembly is ≤3%, and the pore size is ≤200 nm.
4. The welding assembly according to claim 1, wherein: Within a range of a width of 1 μm extending outward from the first interface and the second interface respectively away from the connection copper layer and a length of any 10 μm along the length direction of the first interface, the average porosity of the soldered assembly is ≤1%, and the pore size is ≤200 nm.
5. The welding assembly according to any one of claims 1 to 4, wherein: The first component is a semiconductor chip, and the second component is a copper-clad substrate; or the first component is a semiconductor chip, and the second component is a copper conductive film or a copper foil, wherein the average grain size of the first copper layer is ≥500nm, wherein the semiconductor chip comprises a functional chip with silicon, silicon carbide, or gallium nitride as the main material, one or more metal layers are arranged on the first side and the second side of the chip, and the outermost metal layer is a non-copper metal layer, wherein the non-copper metal layer is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer.
6. The welding assembly according to claim 5, wherein: The non-copper metal layer is a gold layer, and the average grain size of the connecting copper layer is 35nm-140nm.
7. The welding assembly according to claim 5, wherein: The non-copper metal layer is a silver layer, and the average grain size of the connecting copper layer is 100nm to 380nm.
8. The welding assembly according to claim 1, wherein: The average grain size of the connecting copper layer is 70nm-220nm.
9. The welding assembly according to any one of claims 1 to 4, wherein: The first component is a heat sink and its non-copper metal layer is an aluminum layer, and the second component is a copper-clad substrate, wherein the average grain size of the first copper layer is ≥500 nm.
10. The welding assembly according to any one of claims 1 to 4, wherein: The shear strength of the welding assembly is 30-40 MPa, and / or the resistivity of the connecting copper layer is ≤5 μΩ·cm.
11. The welding assembly according to any one of claims 1 to 4, wherein: The welding assembly further comprises: a second copper layer disposed on a second side of the second component; a third component, the outermost layer on the first side of the third component being a non-copper metal layer; Another connecting copper layer, two sides of which are respectively connected to the non-copper metal layer of the third component and the second copper layer, so as to fix the second component and the third component together; Wherein, the average grain size of the additional connecting copper layer is 35nm-400nm.
12. The welding assembly according to any one of claims 1 to 4, after being kept at 250°C for 165 hours, the shear strength of the welding assembly is 30-35 MPa, the resistivity of the connecting copper layer is ≤7 μΩ·cm, and / or the average porosity of the welding assembly is ≤3%, and the pore size is ≤200 nm.
13. A welding assembly for power semiconductor module packaging, comprising: A semiconductor chip, wherein a non-copper metal layer is disposed on the outermost layer on the first side and the second side of the semiconductor chip; A copper-clad substrate, wherein a first copper layer and a second copper layer are respectively arranged on a first side and a second side of the copper-clad substrate; a heat sink having an aluminum layer disposed on a first side of the heat sink; a copper conductive film, wherein a third copper layer is disposed on a first side of the copper conductive film; a first connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the first side of the semiconductor chip and the third copper layer to fix the semiconductor chip and the copper conductive film together; A second connecting copper layer, two sides of which are respectively connected to the non-copper metal layer on the second side of the semiconductor chip and the first copper layer to fix the semiconductor chip and the copper-clad substrate together; as well as a third connecting copper layer, two sides of which are respectively connected to the second copper layer and the aluminum layer to fix the copper-clad substrate and the heat sink together; The average grain sizes of the first, second and third connection copper layers are between 35nm and 400nm.
14. The welding assembly according to claim 13, wherein: The average grain size of the first, second and third connection copper layers is 70nm-380nm, and the average thickness thereof is 70nm-5μm and is at least one time of the average grain size.
15. The welding assembly according to claim 13 or 14, wherein: The non-copper metal layer of the semiconductor chip is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer, and / or the average porosity of the welding assembly is ≤3%, more preferably ≤1%, and the pore size is ≤200nm.
16. A method for producing a welded assembly, comprising the steps of: a) providing a first component and a second component to be welded together and cleaning and drying them, wherein: The second component has an initial copper layer on the first side, and the outermost layer of the first side of the first component is a non-copper metal layer; b) introducing a pre-plated copper layer on the surface of the initial copper layer of the cleaned second component or on the outermost layer of the first side of the cleaned first component and cleaning to remove an oxide layer on the surface of the pre-plated copper layer, wherein the average grain size of the pre-plated copper layer is 20 nm to 360 nm; c) laminating the second component or the pre-plated copper layer of the first component to the non-copper metal layer of the first component or the initial copper layer of the second component in surface contact to form a stacked structure; d) welding the first component and the second component together using diffusion welding.
17. The method according to claim 16, wherein: The average grain size of the pre-plated copper layer is 25nm to 360nm.
18. The method according to claim 16 or 17, wherein: The first component is a semiconductor chip, and its non-copper metal layer is a gold layer, an aluminum layer, a silver layer, a nickel layer, or a titanium layer; or the average grain size of the pre-plated copper layer is 30nm to 200nm.
19. The method according to claim 16 or 17, wherein: In step d), diffusion welding is performed as follows: in a helium protective environment at a temperature of 250-350° C., pressurizing is performed from the top and bottom of the stacked structure, the pressure is 15-40 MPa, and the insulation time is 10-30 minutes.
20. The method according to claim 16 or 17, wherein: The pre-plated copper layer is formed by electroplating, evaporation, sputtering, or ion plating.