Dynamic plated metal thickness for semiconductor packaging

Abstract

The present disclosure is directed to dynamic plated metal thickness for semiconductor packages. A semiconductor package (100) includes a semiconductor component (104) and a plurality of leads (106) electrically connected to the semiconductor component (104). Each of the leads (106) has a first surface (116) and a second surface (118) opposite the first surface (116), with the solderable metal (120) on the first surface (116) and the second surface (118). The weldable metal (120) has a first average thickness (122) on the first surface (116) and a second average thickness (124) on the second surface (118). The second average thickness (124) is from 10% to 80% of the first average thickness (122). The semiconductor package (100) is formed by simultaneously electroplating a solderable metal (120) on the first surface (116) and the second surface (118). The weldable metal (120) is electroplated on the first surface (116) with a first average current and on the second surface (118) with a second average current. The second average current is 10% to 80% of the first average current.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor packaging. More particularly, but not exclusively, the present disclosure relates to plated lead frames in semiconductor packaging. Background Art

[0002] An important aspect of semiconductor packaging is the integration of lead frames, which act as a bridge between internal semiconductor components and the outside world, thereby enabling the transmission of electrical signals and power. Lead frames are typically manufactured using a variety of methods, including stamping and etching processes of thin metal sheets or strips that form the basis of the lead frame. Patterned metal sheets or strips, typically made of materials such as copper and copper alloys, are then bent and shaped to suit the specific requirements of semiconductor packaging. However, the increase in demand for higher performance and miniaturization of semiconductor packaging, coupled with the need to enhance welding reliability, has promoted the development of novel technologies and materials for building lead frames. Electroplating is typically used to produce lead frames with improved performance characteristics, especially in terms of welding reliability. The quality of the welded joints is important for ensuring reliable electrical connections and long-term device functionality. Electroplated lead frames provide a way to address these needs. Summary of the invention

[0003] The present disclosure introduces a semiconductor package, which includes a semiconductor component and a plurality of leads electrically connected to the semiconductor component. The leads extend through an encapsulation material to the outside of the semiconductor package. Each of the leads has a first surface and a second surface opposite to the first surface, wherein a solderable metal is located on the first surface and the second surface. When the semiconductor package is assembled into an electronic device, a portion of the first surface provides an area for solder joints to a system substrate (such as a printed circuit board). The solderable metal has a first average thickness on the first surface and a second average thickness on the second surface. The second average thickness is 10% to 80% of the first average thickness. The semiconductor package is formed by electroplating the solderable metal on the first surface and the second surface simultaneously. The solderable metal is electroplated on the first surface using a first average current and on the second surface using a second average current. The second average current is 10% to 80% of the first average current. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 A cross-section of an example semiconductor package having a second average thickness of a solderable metal on a second surface of the leads that is less than a first average thickness of the solderable metal on a first surface of the leads.

[0005] Figure 2 A cross section of another example semiconductor package having a second average thickness of the solderable metal on the second surfaces of the leads that is less than a first average thickness of the solderable metal on the first surfaces of the leads.

[0006] Figure 3A and Figure 3B An example method of forming a semiconductor package having a second average thickness of a solderable metal on a second surface of the leads that is less than a first average thickness of the solderable metal on a first surface of the leads is described.

[0007] Figure 4A and Figure 4B Another example method of forming a semiconductor package having a second average thickness of a solderable metal on a second surface of the leads that is less than a first average thickness of the solderable metal on a first surface of the leads is described.

[0008] Figure 5 Yet another example method of forming a semiconductor package having a second average thickness of a solderable metal on a second surface of the leads that is less than a first average thickness of the solderable metal on a first surface of the leads is described.

[0009] Figure 6 For reference Figure 5 A graph of the current as a function of time for the disclosed plating system.

[0010] Figure 7 Another example method of forming a semiconductor package having a second average thickness of a solderable metal on a second surface of the leads that is less than a first average thickness of the solderable metal on a first surface of the leads is described.

[0011] Figure 8 For reference Figure 7 A graph of the current as a function of time for the disclosed plating system. DETAILED DESCRIPTION

[0012] The present disclosure is described with reference to the accompanying drawings. The figures are not drawn to scale and are provided only for the purpose of illustrating the present disclosure. Several aspects of the present disclosure are described below with reference to example applications for illustration. It should be understood that many specific details, relationships and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the order of description of actions or events, because some actions can occur in different orders and / or simultaneously with other actions or events. In addition, implementation of the method according to the present disclosure may not require all described actions or events.

[0013] In addition, although some of the embodiments described herein are shown in two-dimensional views of various regions having depth and width, it should be clearly understood that these regions are only illustrations of a portion of a device that is actually a three-dimensional structure. Therefore, when manufactured on an actual device, these regions will have three dimensions, including length, width, and depth. In addition, although the present invention has been described by embodiments directed to active devices, these descriptions are not intended to limit the scope or applicability of the present invention. The active devices of the present invention are not intended to be limited to the physical structures described. These structures are included to demonstrate the utility and application of the present invention to the currently preferred embodiments.

[0014] The semiconductor package includes a semiconductor component. The semiconductor package also includes leads of a lead frame. The semiconductor component is electrically connected to one or more of the leads. The leads each have a first surface and a second surface opposite to the first surface. A solderable metal (such as, mainly tin, silver, nickel, gold or palladium, or an alloy thereof) is electroplated on the first surface and the second surface. The solderable metal has a first average thickness on the first surface and a second average thickness on the second surface. The first average thickness and the second average thickness are the thickness of the solderable metal in the direction perpendicular to the instantaneous section of the first surface and the second surface of the lead, averaged over the areas of the first surface and the second surface, respectively. The second average thickness is 10% to 80% of the first average thickness. When the semiconductor package is assembled into an electronic device by soldering the leads to a system substrate (such as a printed circuit board), a portion of the first surface provides an area for a solder joint. By way of example, the first average thickness is sufficient to provide a reliable solder joint and may be 5 microns to 20 microns. The second average thickness is thick enough, i.e., at least 10% of the first average thickness, to reduce oxidation or corrosion of the leads, thereby improving the reliability of the semiconductor package. The second average thickness is thin enough, i.e., no more than 80% of the first average thickness, to achieve the desired reduction in material cost of the solderable metal. Another advantage can be achieved when a two-dimensional bar code is formed on the second surface of the lead frame before the solderable metal is electroplated. The bar code can be formed according to the SEMI T9 specification and has an array of 100 micron diameter bumps with a pitch of 100 microns. The thinner solderable metal on the bar code can improve the readability of the bar code compared to a bar code with a thicker solderable metal. The semiconductor component has an encapsulation material that contacts the semiconductor component and the leads. The leads extend through the encapsulation material to the outside of the semiconductor package.

[0015] A semiconductor package is formed by simultaneously electroplating a solderable metal on a first surface and a second surface. The solderable metal is electroplated on the first surface using a first plating current, which may be a direct current (DC). The solderable metal is electroplated on the second surface using a second plating current, which may be DC or modulated DC, i.e., cyclically switched on and off, or cyclically switched between a first DC level and a second DC level. The average current of the second plating current is 10% to 80% of the average current of the first plating current to obtain a desired thickness ratio of the solderable metal on the first surface and the second surface. Electroplating the solderable metal on the first surface and the second surface simultaneously can advantageously reduce the cycle time and thus reduce the manufacturing cost compared to plating the solderable metal on the first surface and the second surface in separate sequential operations. For the purposes of this disclosure, the term "simultaneous electroplating" includes modulated DC or any other method of providing a first plating current and a second plating current, wherein the first plating current and the second plating current flow simultaneously during at least a portion of the electroplating process for forming the solderable metal on the lead.

[0016] For purposes of this disclosure, a structure disclosed as comprising "primarily" a substance has more than 50% by weight of that substance. For example, a solderable metal disclosed as comprising primarily tin has more than 50% by weight of elemental tin.

[0017] Figure 1 A cross-section of an example semiconductor package having a second average thickness of a solderable metal on a second surface of a lead, the second average thickness being less than a first average thickness of the solderable metal on a first surface of the lead. Semiconductor package 100 includes a semiconductor component 102. By way of example, semiconductor component 102 may be embodied as an integrated circuit, a discrete semiconductor device, a micro-electromechanical system (MEMS) device, an electro-optical device, or a microfluidic device. Semiconductor package 100 of this example includes a die pad 104, which is part of a lead frame 108. Semiconductor component 102 is attached to die pad 104 by a die attach material 110, such as solder, a conductive adhesive, or an electrically insulating adhesive. Semiconductor package 100 also includes leads 106, which are part of lead frame 108. Semiconductor component 102 is electrically connected to leads 106 by electrical connectors 112. In this example, electrical connectors 112 may be embodied as wire bonds 112, such as Figure 1 Described in.

[0018] The semiconductor package 100 includes an encapsulation material 114 that contacts the semiconductor component 102 and the leads 106. The encapsulation material 114 may surround the semiconductor component 102, the electrical connector 112, and the die pad 104, such as Figure 1. The encapsulating material 114 may include epoxy or other polymer materials. The encapsulating material 114 may include filler materials such as silicon dioxide particles to reduce the thermal expansion coefficient of the encapsulating material 114. The leads 106 extend through the encapsulating material 114 to the exterior of the semiconductor package 100. In this example, the leads 106 may have a "gull wing" configuration, such as Figure 1 , and the semiconductor package 100 may have a small outline integrated circuit (SOIC) configuration or a small outline transistor (SOT) configuration.

[0019] The lead 106 has a first surface 116 outside the semiconductor package 100, which is to be positioned on a system substrate in an electronic device (not specifically shown) containing the semiconductor package 100. The lead 106 has a second surface 118 positioned opposite the first surface 116. The semiconductor package 100 includes a solderable metal 120, such as primarily tin, silver, nickel, gold, or palladium, or an alloy thereof, located on the first surface 116 and the second surface 118 of the lead 106. The solderable metal 120 covers the lead 106 located outside the semiconductor package 100, and in this example, may partially extend into the encapsulation material 114, such as Figure 1 . The solderable metal 120 may expose a portion of the lead 106 adjacent to the semiconductor component 102 to provide a suitable surface for the wire bond 112 on the lead 106. The solderable metal 120 has a first average thickness 122 on the first surface 116 and a second average thickness 124 on the second surface 118. The second average thickness 124 is 10% to 80% of the first average thickness 122, thereby bringing the advantages of reducing costs and reducing oxidation or corrosion. The first average thickness 122 is sufficient to provide a reliable solder joint to the circuit board. By way of example, the first average thickness 122 may be 5 microns to 20 microns.

[0020] Figure 2 2 is a cross-section of another example semiconductor package having a second average thickness of solderable metal on a second surface of the leads, the second average thickness being less than a first average thickness of solderable metal on a first surface of the leads. Semiconductor package 200 includes semiconductor component 202. Semiconductor package 200 includes leads 206, which are part of a lead frame 208. Semiconductor component 202 is electrically connected to leads 206 via electrical connectors 212, which may be embodied as solder bump joints 212, such as Figure 2 Described in.

[0021] The semiconductor package 200 includes an encapsulation material 214 that contacts the semiconductor component 202 and the leads 206. The encapsulation material 214 may surround the semiconductor component 202 and the electrical connector 212, such as Figure 2Lead 206 extends through encapsulation material 214 to the exterior of semiconductor package 200. In this example, lead 206 may have a "j-shaped lead" configuration, such as Figure 2 , and the semiconductor package 200 may have a j-lead surface mount technology (SMT) semiconductor package.

[0022] The lead 206 has a first surface 216 outside the semiconductor package 200 and has a second surface 218 located opposite the first surface 216. The semiconductor package 200 includes a solderable metal 220 located on the first surface 216 and the second surface 218 of the lead 206. The solderable metal 220 covers the lead 206 located outside the semiconductor package 200, and in this example, covers the lead 206 in the encapsulation material 214, such as Figure 2 . The weldable metal 220 has a first average thickness 222 on the first surface 216 and a second average thickness 224 on the second surface 218. The second average thickness 224 is 10% to 80% of the first average thickness 222, thereby bringing the advantages of reducing costs and reducing oxidation or corrosion. By way of example, the first average thickness 222 can be 5 microns to 20 microns.

[0023] Figure 3A and Figure 3B An example method of forming a semiconductor package having a second average thickness of a solderable metal on a second surface of the leads that is less than a first average thickness of the solderable metal on a first surface of the leads is depicted. A lead frame 308 for semiconductor package 300 has a first surface 316 on one face of lead frame 308, and has a second surface 318 on a face opposite first surface 316. A portion of lead frame 308 may be masked with tape or a polymer coating (not specifically shown) to prevent plating on the surface for wire bonding.

[0024] The lead frame 308 is immersed in a plating system 326. The plating system 326 includes a plating solution 328 having metal ions (such as tin ions, silver ions, nickel ions, gold ions, or palladium ions) that are electroplated onto the lead frame 308, respectively, to form a solderable metal 320 (such as tin, silver, nickel, gold, or palladium, or alloys thereof). The plating system 326 also includes a first anode 330 facing the first surface 316, and includes a second anode 332 facing the second surface 318. The first anode 330 and the second anode 332 can be implemented as anode bags containing a metal plate or wire of the solderable metal 320. Other embodiments of the first anode 330 and the second anode 332 are within the scope of this example.

[0025] The plating system 326 can include a first screen 334 positioned between the first surface 316 and the first anode 330. The first screen 334 is positioned so as not to significantly block metal ions from drifting from the first anode 330 to the first surface 316. The first screen 334 is located below the centerline 336 of the lead frame 308. In one version of this example, the first screen 334 can be located below the bottom of the lead frame 308, such as Figure 3A Described in.

[0026] The plating system 326 includes a second screen 338 positioned between the second surface 318 and the second anode 332. The second screen 338 can be solid, that is, can be free of apertures. The second screen 338 is located above the centerline 336 of the lead frame 308. In one version of this example, the second screen 338 can extend near the top of the lead frame 308, such as Figure 3A Described in.

[0027] The plating system 326 includes a first power source 340 configured to supply current from the lead frame 308 to the first anode 330. The first power source 340 can be implemented as a constant voltage source, such as Figure 3A Alternatively, the first power source 340 may be implemented as a regulated current source.

[0028] The plating system 326 includes a second power source 342 configured to supply current from the lead frame 308 to the second anode 332. The second power source 342 can be implemented as another constant voltage source. Alternatively, the second power source 342 can be implemented as a modulated voltage source, a regulated current source, or a modulated current source.

[0029] During the electroplating process using the plating system 326, the first power source 340 causes metal ions in the plating solution 328 between the first anode 330 and the lead frame 308 to drift to the first surface 316 and plate the solderable metal 320 onto the first surface 316 of the lead frame 308. In this example, the position of the first screen 334 is below the centerline 336 of the lead frame 308 so that the metal ions can flow to the first surface 316 relatively unimpeded.

[0030] The second power source 342 causes metal ions in the plating solution 328 between the second anode 332 and the lead frame 308 to drift over the second screen 338 to the second surface 318 and electroplate the solderable metal 320 onto the second surface 318. In this example, the location of the second screen 338 over the centerline 336 reduces the flow of metal ions to the second surface 318 compared to the unimpeded flow of metal ions to the first surface 316. The first power source 340 and the second power source 342 operate simultaneously.

[0031] As a result, a first average current flows from the first anode 330 to the first surface 316, and a second average current flows from the second anode 332 to the second surface 318. The second average current is 10% to 80% of the first average current, thereby causing the solderable metal 320 to be electroplated on the second surface 318 at a lower rate than the first surface 316. The lower electroplating rate on the second surface 318 compared to the first surface 316 produces a smaller thickness of the solderable metal 320 on the second surface 318, as shown in reference Figure 1 and Figure 2 The height of the second screen 338 can be adjusted to obtain the desired thickness of the weldable metal 320 on the second surface 318, thereby advantageously enabling the use of the second power supply 342 in a constant voltage mode. The first power supply 340 and the second power supply 342 can advantageously be operated at the same constant voltage by appropriately adjusting the second screen 338.

[0032] Figure 4A and Figure 4B Another example method of forming a semiconductor package having a second average thickness of a solderable metal on a second surface of a lead, the second average thickness being less than a first average thickness of the solderable metal on a first surface of the lead, is depicted. A lead frame 408 for a semiconductor package has a first surface 416 located on one face of the lead frame 408, and has a second surface 418 located on a face opposite to the first surface 416. The lead frame 408 is immersed in a plating system 426. The plating system 426 includes a plating solution 428 having metal ions that are electroplated to the solderable metal 420 on the lead frame 408. The plating system 426 also includes a first anode 430 facing the first surface 416, and includes a second anode 432 facing the second surface 418.

[0033] The plating system 426 can include a first screen 434 positioned between the first surface 416 and the first anode 430. The first screen 434 is positioned so as not to significantly block metal ions from drifting from the first anode 430 to the first surface 416. The first screen 434 is positioned below the centerline 436 of the lead frame 408, such as below the bottom of the lead frame 408. Figure 4A Described in.

[0034] The plating system 426 further includes a second screen 438 positioned between the second surface 418 and the second anode 432. In this example, the second screen 438 can be implemented as a perforated screen 438 having an orifice 444 to allow for reduced flow of metal ions from the second anode 432 to the second surface 418. The second screen 438 is located above the centerline 436 of the lead frame 408 and can extend near the top of the lead frame 408, such as Figure 4A Described in.

[0035] The plating system 426 includes a first power source 440 configured to supply current from the lead frame 408 to the first anode 430 and a second power source 442 configured to supply current from the lead frame 408 to the second anode 432. The first power source 440 and the second power source 442 can be implemented as a constant voltage source, such as Figure 4A , or may be implemented as a regulated current source.

[0036] During an electroplating process using the plating system 426, the first power source 440 and the second power source 442 are operated simultaneously, so that the metal ions in the plating solution 428 drift unimpeded to the first surface 416, and drift to the second surface 418 at a slower rate due to the second screen 438. Due to the holes 444 on the second screen 438, the flow of metal ions to the second surface 418 can be advantageously more uniform compared to a solid screen. As a result, a first average current flows from the first anode 430 to the first surface 416, and a second average current flows from the second anode 432 to the second surface 418. The second average current is 10% to 80% of the first average current.

[0037] The solderable metal 420 is plated onto the first surface 416 at a first rate and onto the second surface 418 at a second rate that is lower than the first rate. The lower plating rate on the second surface 418 produces a smaller thickness of the solderable metal 420 on the second surface 418 than on the first surface 416, as shown in FIG. Figure 1 and Figure 2 The size and distribution of the apertures 444 of the second screen 438 may be adjusted to obtain a desired plating rate of the solderable metal 420 on the second surface 418, advantageously enabling the use of the second power supply 442 at the same voltage as the first power supply 440 in a constant voltage mode.

[0038] Figure 5 A further example method of forming a semiconductor package having a second average thickness of a solderable metal on a second surface of a lead, the second average thickness being less than a first average thickness of the solderable metal on a first surface of the lead, is depicted. A lead frame 508 for a semiconductor package has a first surface 516 located on one face of the lead frame 508, and has a second surface 518 located on a face opposite to the first surface 516. The lead frame 508 is immersed in a plating system 526. The plating system 526 includes a plating solution 528 having metal ions that are electroplated to the solderable metal 520 on the lead frame 508. The plating system 526 also includes a first anode 530 facing the first surface 516, and includes a second anode 532 facing the second surface 518.

[0039] In this example, the plating system 526 includes a first power source 540 and a second power source 542, wherein the first power source is configured to supply a constant first average current from the lead frame 508 to the first anode 530, and the second power source is configured to supply a constant second average current from the lead frame 508 to the second anode 532. The second average current is 10% to 80% of the first average current. The first power source 540 and the second power source 542 of this example are implemented as constant current sources, such as Figure 5 By way of example, the first power source 540 may be configured to provide 40 amps and the second power source 542 may be configured to provide 20 amps, such as Figure 5 As indicated in .

[0040] During an electroplating process using the plating system 526, the first power source 540 and the second power source 542 are operated simultaneously, so that the metal ions in the plating solution 528 drift unimpeded to the first surface 516, and drift to the second surface 518 at a slower rate due to the second average current being less than the first average current. The solderable metal 520 is electroplated onto the first surface 516 at a first rate, and onto the second surface 518 at a second rate that is lower than the first rate. The lower plating rate on the second surface 518 produces a smaller thickness of the solderable metal 520 on the second surface 518 as compared to the first surface 516, as shown in FIG. Figure 1 and Figure 2 The second average current from the second power source 542 can be adjusted to provide a desired thickness of the weldable metal 520 on the second surface 518. Using the first power source 540 and the second power source 542 in a constant current mode can advantageously enable the plating system 526 to form the weldable metal 520 having a desired thickness on the first surface 516 and the second surface 518 without using a screen in the plating solution 528.

[0041] Figure 6 For reference Figure 5 A graph of the current varying with time for the disclosed plating system. Figure 6 The first average current, labeled "FIRST AVERAGE CURRENT" in FIG. 1 , is constant during the electroplating operation. Similarly, Figure 6 The second average current labeled "SECOND AVERAGE CURRENT" in FIG. 1 is also constant during the electroplating operation. During the electroplating operation, the first average current and the second average current are provided simultaneously and may be provided for the same length of time, thereby advantageously reducing the cycle time of the electroplating operation compared to providing the currents for different overlapping lengths of time.

[0042] Figure 7Another example method of forming a semiconductor package having a second average thickness of a solderable metal on a second surface of a lead, the second average thickness being less than a first average thickness of the solderable metal on a first surface of the lead, is depicted. A lead frame 708 for a semiconductor package has a first surface 716 located on one face of the lead frame 708, and has a second surface 718 located on a face opposite to the first surface 716. The lead frame 708 is immersed in a plating system 726. The plating system 726 includes a plating solution 728 having metal ions that are electroplated to a solderable metal 720 on the lead frame 708. The plating system 726 also includes a first anode 730 facing the first surface 716, and includes a second anode 732 facing the second surface 718.

[0043] The plating system 726 includes a first power supply 740 configured to supply a constant first average current from the lead frame 708 to the first anode 730. In this example, the plating system 726 includes a second power supply 742 configured to supply a second current modulated by a switch 746 from the lead frame 708 to the second anode 732. By way of example, the switch 746 can be implemented as a solid-state relay. The switch 746 is configured to modulate between an on state and an off state. When the switch 746 is in the off state, the second current alternates between substantially zero, and when the switch 746 is in the on state, the second current alternates between current magnitudes comparable to the first average current. The average value of the second current, i.e., the second average current, is 10% to 80% of the first average current. The duty cycle of the switch 746 (i.e., the ratio of the total time in the on state to the sum of the total time in the on state and the total time in the off state) can be adjusted to provide the desired value of the second average current. The first power supply 740 and the second power supply 742 of this example are implemented as constant current sources, such as Figure 7 By way of example, the first power source 740 may be configured to provide 40 amps, and the second power source 742 may be configured to provide 40 amps, such as Figure 7 As indicated in .

[0044] During an electroplating process using the plating system 726, the first power source 740 and the second power source 742 modulated by the switch 746 are operated simultaneously, so that the metal ions in the plating solution 728 drift unimpeded to the first surface 716, and drift to the second surface 718 at a slower rate due to the second average current being less than the first average current. The solderable metal 720 is electroplated onto the first surface 716 at a first rate, and onto the second surface 718 at a second rate that is lower than the first rate. The lower plating rate on the second surface 718 produces a smaller thickness of the solderable metal 720 on the second surface 718 than on the first surface 716, as shown in FIG. Figure 1 and Figure 2The second average current from the second power source 742 can be adjusted to provide a desired thickness of the weldable metal 720 on the second surface 718. Using the switch 746 to modulate the second current can advantageously facilitate adjusting the second average current to a desired value without requiring adjustment of the second power source 742.

[0045] Figure 8 For reference Figure 7 A graph of the current varying with time for the disclosed plating system. Figure 8 The first average current, labeled "FIRST AVERAGE CURRENT" in FIG. 1 , is constant during the electroplating operation. During the electroplating operation, when switch 746 is in the on state, Figure 8 The second current marked as "SECOND CURRENT" is substantially zero and is Figure 7 The first power supply 740 alternates between the values ​​supplied. Figure 8 The second average current labeled as “SECOND AVERAGE CURRENT” in FIG. 1 is 10% to 80% of the first average current.

[0046] Various features of the examples disclosed herein may be combined in other manifestations of example semiconductor packages. Figure 3A , Figure 4A , Figure 5 and Figure 7 Any of the disclosed methods can be used to form a SOIC or SOT semiconductor package, as shown in FIG. Figure 1 Reference Figure 3A , Figure 4A , Figure 5 and Figure 7 Any of the disclosed methods may be used to form a j-lead semiconductor package, such as that described in reference Figure 2 Reference Figure 3A The disclosed method can implement the first power source 340 and the second power source 342 as constant current sources instead of Figure 3A The constant voltage source depicted in . Figure 3A The disclosed method may implement the second power source 342 modulated by the switch, such as Figure 7 Reference is made to the second power source 742 modulated by the switch 746. Figure 4A The disclosed method can implement the first power source 440 and the second power source 442 as constant current sources instead of Figure 4A The constant voltage source depicted in . Figure 4A The disclosed method may implement the second power source 442 modulated by the switch, such as Figure 7 Reference is made to the second power source 742 modulated by the switch 746. Figure 5The disclosed method can implement the first power supply 540 and the second power supply 542 as constant voltage sources instead of Figure 5 The constant current source depicted in . Figure 5 The disclosed method may implement the second power source 542 modulated by the switch, such as Figure 7 Reference is made to the second power source 742 modulated by the switch 746. Figure 5 The disclosed method can implement a solid screen between the second anode 532 and the second surface 518, as described in reference Figure 3A The second screen 338 is disclosed. Figure 5 The disclosed method may implement a perforated screen between the second anode 532 and the second surface 518, as described in reference Figure 4A and Figure 4B The second screen 438 is disclosed. Figure 7 The disclosed method can implement the first power supply 740 and the second power supply 742 as constant voltage sources instead of Figure 7 The constant current source depicted in . Figure 7 The disclosed method can implement a solid screen between the second anode 732 and the second surface 718, as described in reference Figure 3A The second screen 338 is disclosed. Figure 7 The disclosed method may implement a perforated screen between the second anode 732 and the second surface 718, as described in reference Figure 4A and Figure 4B The second screen 438 is disclosed.

[0047] Although various embodiments of the present disclosure have been described above, it should be understood that the embodiments have been presented by way of example and are not limiting. Without departing from the spirit or scope of the present disclosure, many changes may be made to the disclosed embodiments according to the disclosure herein. Therefore, the breadth and scope of the present invention should not be limited by any of the above embodiments. In fact, the scope of the present disclosure should be defined according to the attached claims and their equivalents.

Claims

1. A semiconductor package, comprising: Semiconductor components; a plurality of leads electrically connected to the semiconductor component; an encapsulation material contacting the semiconductor component and the leads, wherein the leads extend through the encapsulation material to the exterior of the semiconductor package, each of the leads having a first surface and a second surface opposite the first surface; and A solderable metal is disposed on the lead, the solderable metal having a first average thickness on the first surface and a second average thickness on the second surface, wherein the second average thickness is 10% to 80% of the first average thickness.

2. The semiconductor package of claim 1, wherein the solderable metal consists essentially of a metal selected from the group consisting of tin, silver, nickel, gold, palladium, and alloys thereof. The semiconductor package of claim 1 , wherein the solderable metal consists essentially of tin. 4 . The semiconductor package of claim 1 , wherein the first average thickness of the solderable metal is 5 μm to 20 μm. The semiconductor package according to claim 1 , wherein the leads have a gull-wing configuration. The semiconductor package according to claim 1 , wherein the leads have a j-shaped lead configuration. 7 . The semiconductor package of claim 1 , wherein the solderable metal exposes a portion of the lead adjacent to the semiconductor component.

8. A method of forming a semiconductor package, comprising: A solderable metal is simultaneously electroplated on a lead frame having a plurality of leads, each of the leads having a first surface and a second surface opposite the first surface, wherein: The solderable metal is electroplated on the first surface with a first average plating current, and the solderable metal is electroplated on the second surface with a second average plating current that is 10% to 80% of the first average plating current.

9. The method of claim 8, wherein electroplating the solderable metal is performed using a solid screen located between an anode and the lead frame, wherein the second surface faces the solid screen.

10. The method of claim 9, wherein the solid screen extends beyond the center of the lead frame.

11. The method of claim 8, wherein electroplating the solderable metal is performed using a perforated screen located between an anode and the lead frame, wherein the second surface faces the perforated screen.

12. The method of claim 11, wherein the perforated screen extends beyond the center of the lead frame.

13. The method of claim 8, wherein electroplating the weldable metal is performed using a first constant current through a first anode facing the first surface and a second constant current through a second anode facing the second surface, the second constant current being 10% to 80% of the first constant current.

14. The method of claim 8, wherein electroplating the solderable metal is performed using a first current through a first anode facing the first surface and a second current through a second anode facing the second surface, the second current being modulated by a switch. 15 . The method of claim 14 , wherein an average value of the second current is 10% to 80% of an average value of the first current.

16. The method of claim 8, wherein the solderable metal consists essentially of a metal selected from the group consisting of tin, silver, nickel, gold, and palladium.

17. The method of claim 8, wherein the solderable metal consists essentially of tin.

18. The method of claim 8, wherein the solderable metal is plated on the first surface to a first average thickness and on the second surface to a second average thickness, the second average thickness being 10% to 80% of the first average thickness. The method of claim 18 , wherein the first average thickness is 5 μm to 20 μm.

20. The method of claim 8, wherein the solderable metal exposes a portion of the lead adjacent to a semiconductor component of the semiconductor package.

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