Average inductor current sensing and regulation

Abstract

The invention relates to average inductor current sensing and regulation. A circuit includes a voltage regulator circuit (112), current sense circuitry (114a), and a current control loop (130). The voltage regulator circuit (112) is coupled to an output terminal (106) of the DC-DC power converter (100) and is configured to generate a regulation signal (VERR-V) based on a voltage (VFB) at the regulator input terminal. The current sense circuitry (114a) is coupled to a switching terminal (SW1, SW2) of the DC-DC power converter (100) and is configured to generate a pulse signal (DCOMP) based on a voltage at a switching input terminal and a threshold set by the regulation signal (VERR-V). The current control loop (130) is coupled to a control terminal of a switching transistor of the DC-DC power converter (100) and is configured to generate a switching control signal (136) based on the pulse signal (DCOMP) to control the switching transistor to drive an average value of current flowing through the switching terminals (SW1, SW2) to a target average current value corresponding to the threshold.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 591,144, filed on October 18, 2023, and entitled “Continuous Inductor Average Current Sensing and Current Loop Control,” which is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The present description relates to power converters, and more particularly to current sensing and control in DC-DC power converters. Background Art

[0004] Power conversion circuits are used in a wide range of applications. For example, in battery management systems, power conversion circuits can be used to control battery charging with regulated voltage and / or current. In some applications, accurate average input or output current regulation may be required. However, there are still many important issues regarding providing accurate and effective average current regulation. Summary of the invention

[0005] According to one example, a circuit includes: a voltage regulator circuit having a regulator input terminal for coupling to an output terminal of a DC-DC power converter and a regulator output terminal, the voltage regulator circuit being configured to generate a regulation signal at the regulator output terminal based on a voltage at the regulator input terminal. The circuit may further include: a current sensing circuit system having at least one switch input terminal, a sensing input terminal, and a sensing output terminal, the at least one switch input terminal being used to couple to at least one switch terminal of the DC-DC power converter, and the sensing input terminal being coupled to the regulator output terminal, the current sensing circuit system being configured to generate a pulse signal at the sensing output terminal, wherein the pulse signal is based on the voltage at the at least one switch input terminal and an adjustable threshold set by the regulation signal. The circuit may further include: a current control loop circuit having a loop input terminal coupled to the sensing output terminal and one or more control output terminals each for coupling to a control terminal of a corresponding switching transistor of the DC-DC power converter, the current control loop circuit being configured to generate a switch control signal at the one or more control output terminals based on the pulse signal, wherein the switch control signal is a pulse width modulated signal to control the one or more switching transistors to drive an average value of a current flowing through the at least one switching terminal to a target average current value corresponding to the adjustable threshold.

[0006] According to another example, a DC-DC power converter has an input terminal and an output terminal, and includes: a power conversion circuit, which includes a plurality of power transistors and has at least one switch terminal for coupling to at least one of the input terminal or the output terminal via an inductor, the plurality of power transistors being configured to generate a current through the at least one switch terminal based on a control signal received via an individual control terminal; and a voltage regulator circuit, which has a regulator input coupled to the output terminal and a regulator output, the voltage regulator circuit being configured to generate a regulation signal at the regulator output based on a voltage at the output terminal. The DC-DC power converter may further include: a current sensing circuit system coupled to the power conversion circuit and having a sensing output and a sensing input, the sensing input coupled to the regulator output, the current sensing circuit system configured to generate a pulse signal at the sensing output having a duty cycle representing the percentage of time that the current flowing through the at least one switch terminal is above a target value; and a current control loop circuit having a control loop input and multiple control loop outputs, the control loop input coupled to the sensing output, and each of the control loop outputs coupled to a corresponding one of the control terminals, the current control loop circuit configured to generate the control signal as a pulse width modulation signal based on the pulse signal to control the multiple power transistors to adjust the current through the at least one switch terminal to the target value.

[0007] According to another example, a buck-boost DC-DC converter includes: a first power transistor coupled between an input terminal and a first switch terminal; a second power transistor coupled between an output terminal and a second switch terminal; and a voltage regulator having a first regulator input coupled to the output terminal, a second regulator input for receiving a reference voltage, and a regulator output. The buck-boost DC-DC converter may further include: a first variable current source coupled between the input terminal and a ground terminal and having a first current control input coupled to the regulator output; a first sensing transistor coupled between the input terminal and the first variable current source and having a control terminal coupled to a first control terminal of the first power transistor; and a first comparator having first and second comparator inputs and a first comparator output, the first comparator input coupled to the first switch terminal, and the second comparator input coupled to the first sensing transistor and the first variable current source, such that the first variable current source is coupled between the second comparator input and the ground terminal. The buck-boost DC-DC converter may further include: a second variable current source coupled between the second switch terminal and the ground terminal and having a second current control input terminal coupled to the regulator output; a second sensing transistor coupled between the second variable current source and the second switch terminal and having a control terminal coupled to the second control terminal of the second power transistor; and a second comparator having a second comparator output, a third comparator input coupled to the output terminal, and a fourth comparator input coupled to the second sensing transistor and the second variable current source, such that the second variable current source is coupled between the fourth comparator input and the ground terminal. The buck-boost DC-DC converter may further include: a current control loop coupled to the first and second comparator outputs and to the first and second control terminals of the first and second power transistors, respectively, the current control loop being configured to generate first and second control signals at the first and second control terminals, respectively, based on signals at the first and second comparator outputs.

[0008] According to another example, a control circuit for a DC-DC power converter includes: a voltage regulator circuit having a first regulator input terminal for coupling to an output terminal of the DC-DC power converter, a second regulator input terminal for receiving a reference voltage, and a regulator output terminal, wherein the voltage regulator circuit is configured to generate a regulation signal at the regulator output terminal based on a difference between a voltage at the first regulator input terminal and a reference voltage. The control circuit may further include: a current sensing circuit system having at least one sensing terminal for coupling to at least one switch terminal of the DC-DC power converter, a sensing output terminal, and at least one sensing control terminal coupled to the regulator output terminal, the current sensing circuit system being configured to generate a pulse signal at the sensing output terminal having a duty cycle representing the percentage of time that the current through the at least one switch terminal is higher than a target value based on the regulation signal; and a current control loop circuit having a loop input terminal coupled to the sensing output terminal and one or more control output terminals for coupling to a power transistor, the current control loop circuit being configured to generate a control signal at the one or more control output terminals based on the pulse signal to control the power transistor so as to adjust the current through the at least one switch terminal to the target value.

[0009] According to another example, a buck-boost DC-DC power converter includes: an input terminal, an output terminal, a power conversion circuit system coupled to the input terminal and the output terminal and having first and second switch terminals for coupling to an inductor, the power conversion circuit system including a plurality of power transistors; and a current control circuit coupled to the power conversion circuit system and configured to generate one or more control signals based on a regulation signal to control the plurality of power transistors to provide a regulated current. The buck-boost DC-DC power converter may further include: a regulator circuit coupled to the output terminal and coupled to the power conversion circuit system, the regulator circuit having a regulator output terminal and configured to generate the regulation signal at the regulator output terminal representing an average inductor current flowing through the first and second switch terminals; and a current conversion circuit coupled to the regulator output terminal and coupled to the current control circuit, the current conversion circuit configured to adjust the regulation signal based on a limit signal representing a limit value of the regulated current.

[0010] According to one example, a buck-boost DC-DC power converter includes: an input terminal, an output terminal, first and second switch terminals for coupling to an inductor, and a plurality of power transistors, the plurality of power transistors including a first power transistor coupled between the input terminal and the first switch terminal. The buck-boost DC-DC power converter may further include: a voltage regulator circuit including a first regulator input terminal coupled to the output terminal, a second regulator input terminal for receiving a reference voltage, and a regulator output terminal, the voltage regulator circuit being configured to provide a regulation signal at the regulator output terminal representing a target average inductor current flowing through the first and second switch terminals; a current control circuit configured to regulate an input current at the input terminal to maintain the input current below a limit, the current control circuit having a control output terminal coupled to a control terminal of the first power transistor and configured to provide a first control signal at the control output terminal; and a current conversion circuit. The current conversion circuit may include: a switching circuit having a switch control terminal coupled to the control output terminal; a first transconductance amplifier having a first amplifier input terminal coupled to the switching circuit, a second amplifier input terminal for receiving a limit signal, and a first amplifier output terminal, wherein the limit signal represents the limit value for the input current at the input terminal; a second transconductance amplifier having a third amplifier input terminal coupled to the regulator output terminal, a fourth amplifier input terminal coupled to the first amplifier output terminal, and a second amplifier output terminal; and a transistor coupled between the regulator output terminal and a ground terminal and having a control terminal coupled to the second amplifier output terminal.

[0011] According to another example, a buck-boost DC-DC power converter includes: an input terminal, an output terminal, first and second switch terminals for coupling to an inductor, and a plurality of power transistors, the plurality of power transistors including a first power transistor coupled between the output terminal and the second switch terminal. The buck-boost DC-DC power converter may further include: a voltage regulator circuit including a first regulator input terminal coupled to the output terminal, a second regulator input terminal for receiving a reference voltage, and a regulator output terminal, the voltage regulator circuit being configured to provide a regulation signal at the regulator output terminal representing a target average inductor current flowing through the first and second switch terminals; a current control circuit configured to regulate an output current at the output terminal to maintain the output current below a limit, the current control circuit having a control output terminal coupled to a control terminal of the first power transistor and configured to provide a first control signal at the control output terminal; and a current conversion circuit. The current conversion circuit may include: a switch circuit having a switch control terminal coupled to the control output terminal; a transconductance amplifier having a first amplifier input terminal coupled to the switch circuit, a second amplifier input terminal for receiving a limit signal, and an amplifier output terminal, wherein the limit signal represents the limit value for the output current at the output terminal; and a transistor coupled between the regulator output terminal and a ground terminal and having a control terminal coupled to the amplifier output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A is a block diagram of a power conversion system in an example.

[0013] Figure 1B is a block diagram of a power conversion system in another example.

[0014] Figure 2A It is shown in the example Figure 1A Circuit diagram of a portion of the power conversion system.

[0015] Figure 2B It is shown in the example Figure 1A Circuit diagram of other parts of the power conversion system.

[0016] Figure 3 is a graph showing an inductor current signal and a corresponding pulse signal in an example.

[0017] Figure 4 It is shown in the example Figure 1B Circuit diagram of a portion of the power conversion system.

[0018] Figure 5is a circuit diagram showing a current conversion circuit in a buck-boost power converter in an example.

[0019] Figure 6 is a circuit diagram showing another current conversion circuit in a buck-boost power converter in an example. DETAILED DESCRIPTION

[0020] Techniques for current regulation in DC-DC power converter circuits are described. As described in more detail below, techniques are disclosed so that average inductor current (e.g., as opposed to peak or valley values) can be sensed in an accurate and lossless manner, and the techniques are used to adjust a selected quantity (e.g., average input or output current) in a DC-DC power converter. An inductor is coupled to at least one switch terminal of a DC-DC power converter. According to certain examples, a control loop is provided that allows a threshold value that can be used to generate a signal representing the average inductor current to be adjusted continuously. This control loop can be used in a feedback loop to adjust the selected quantity without the need for a lossy sensing element (e.g., a sensing resistor). In some examples, an error voltage from the feedback loop is converted into a target average inductor current, which is passed to the control loop to adjust the threshold. The control loop can modulate the duty cycle of one or more of the power converter transistors to adjust the average inductor current to a target value, thereby adjusting the selected quantity (e.g., the input or output current of the DC-DC power converter).

[0021] In an example, the circuit includes a voltage regulator circuit having a regulator input terminal for coupling to an output terminal of a DC-DC power converter, and a regulator output terminal. The voltage regulator circuit may be configured to generate a regulation signal at the regulator output terminal based on a voltage at the regulator input terminal. In some examples, the voltage at the regulator input terminal represents a voltage at the output terminal of the DC-DC power converter. In an example, the circuit further includes a current sensing circuit system, the current sensing circuit system having at least one switch input terminal, a sensing input terminal, and a sensing output terminal, the at least one switch input terminal being used to couple to at least one switch terminal of the DC-DC power converter, and the sensing input terminal being coupled to the regulator output terminal. The current sensing circuit system may be configured to generate a pulse signal at the sensing output terminal, the pulse signal being based on a voltage at at least one switch input terminal and an adjustable threshold set by the regulation signal. The circuit may further include a current control loop circuit having a loop input terminal coupled to the sensing output terminal, and one or more control output terminals each for coupling to a control terminal of a corresponding switching transistor of the DC-DC power converter. The current control loop circuit can be configured to generate a switch control signal at one or more control output terminals based on the pulse signal, wherein the switch control signal is a pulse width modulated signal to control one or more switching transistors to drive an average value of a current flowing through at least one switch terminal to a target average current value corresponding to an adjustable threshold value. These and other aspects are described in more detail below.

[0022] Overall Overview

[0023] Monitoring and regulating the inductor current in a DC-DC power converter can be advantageous in many applications. However, as noted above, there are still many important issues regarding inductor current monitoring and control in a DC-DC power converter. For example, some methods for monitoring and controlling the inductor current are based on peak current detection or simulation of the inductor current by using a resistor-capacitor (RC) filter across the inductor. Such methods may be complex and / or inaccurate. For example, the use of a sensing element, such as a resistor or RC filter across the inductor, can result in inefficiency, loss, and additional cost. In addition, the use of an RC filter across the inductor may be extremely inaccurate because the inductor DC resistance (DCR) may not be known and may vary with the temperature of the device to the device. Another method of inductor current sensing involves continuously sensing the current through the switching transistor coupled to the inductor via the switch terminal of the DC-DC converter, and then integrating the current (or corresponding voltage) to reconstruct the inductor current. However, there is considerable complexity in continuously sensing the current (e.g., monitoring the complete waveform of the current). Additionally, when the switching transistor is turned on and off at a relatively fast switching rate, significant switching noise may be introduced into the measurement, further increasing the complexity and / or inaccuracy of current monitoring.

[0024] Therefore, disclosed herein is a technique by which an average (e.g., as opposed to a peak or valley value) inductor current can be accurately sensed in a lossless manner. In addition, the techniques disclosed herein enable accurate average inductor current information to be used for a variety of purposes, as further described below. For example, various applications including regulation of a DC-DC converter input or output current do not require, for example, continuous inductor current information. In fact, knowledge of the inductor current at a specific time in a switching cycle or knowledge of the average inductor current is sufficient. In addition, accurate average inductor current sensing according to certain instances may allow more efficient use of the full capacity of the inductor (e.g., providing more output power), which may be advantageous in applications such as power management, current limiting, and / or phase management in the case of a multi-phase converter. More efficient use of the inductor allows the use of a smaller inductor, thereby saving die area and / or height and associated costs. The circuit system may be used for a variety of different DC-DC power converter configurations, including, for example, a buck converter or a buck-boost converter. As described in more detail below, the circuit system may include a control loop that regulates the average inductor current to a target value and a feedback loop that uses the average inductor current to regulate another quantity in the DC-DC power converter, such as the average input or output current.

[0025] Example Architecture

[0026] Figure 1A and 1B1 is a block diagram of a DC-DC power converter 100 including circuitry for average inductor current sensing and control according to certain examples. The DC-DC power converter 100 includes a power conversion circuit 102 including a plurality of transistors, such as those described below with reference to Figure 2A and 4 The power conversion circuit 102 includes an input voltage terminal 104 for receiving an input voltage (Vin) and an output voltage terminal 106 for providing a regulated output voltage (Vout). Figure 1A In the example of , the DC-DC power converter 100 may be, for example, a two-stage buck-boost converter (e.g., Figure 2A ). Thus, in this example, the power conversion circuit 102 includes two switch terminals SW1 and SW2 for coupling to the external inductor 108. Figure 1B In the example of , the DC-DC power converter 100 may be, for example, a two-stage buck converter (e.g., Figure 4 ). Thus, in this example, the power conversion circuit 102 includes a switch terminal SW for coupling to an external inductor 108. In other examples, the DC-DC converter 100 may be another type of multi-level switching power converter, such as a boost converter or a three-level or higher-order switching converter.

[0027] According to some examples, the DC-DC power converter 100 includes a voltage control and current sensing loop 110 and a current control loop 130. The voltage control and current sensing loop 110 includes a voltage regulator 112 and a current sensing circuit system 114a ( Figure 1A ) or 114b( Figure 1B In some examples, the voltage regulator 112 includes a transconductance amplifier 116 having a voltage (referred to as a feedback voltage V ) for receiving a voltage representative of the output voltage Vout. FB ) and a second input terminal coupled to the reference terminal 118 for receiving the reference voltage Vref. The voltage regulator 112 may be configured to generate a voltage based on the feedback voltage V FB The difference between the reference voltage Vref and the error voltage V ERR-V , also referred to herein as a modulation signal. In some examples, the modulation signal V ERR-V A transresistance-capacitance (RC) filter is created at the output terminal of the transconductance amplifier 116. Figure 1A and 1BIn the example shown in , the RC filter includes a first capacitor 120 coupled between the output terminal of the transconductance amplifier 116 and a ground terminal, and a series combination of a resistor 122 and a second capacitor 124, which are coupled in parallel with the first capacitor 120 between the output terminal of the transconductance amplifier 116 and the ground terminal. ERR-V It can be used as a feedback signal in the voltage control and current sensing loop 110 to regulate the output voltage Vout to a selected value based on the reference voltage Vref.

[0028] refer to Figure 1A In some examples, the current sensing circuit system 114a is coupled to the input voltage terminal 104, the output voltage terminal 106 and the two switch terminals SW1, SW2. The current sensing circuit system 114a is further coupled to the output terminal of the transconductance amplifier 116 to receive the regulation signal V ERR-V According to some examples, the current sensing circuit system 114a is configured to compare the inductor current with the regulation signal V ERR-V The current sensing circuit system 114a may include a sensing transistor that is controlled by a control signal 136 (e.g., HS ON1 , HS ON3 ) drive, the control signal is also used to drive the high-side switching transistor in the power conversion circuit 102, as described below with reference to Figure 2A and 2B In some examples, the current sensing circuit system 114a generates a pulse output signal (“pulse signal”) D based on the average inductor current. COMP , as further described below.

[0029] According to some examples, the current control loop 130 includes a charge pump circuit 132 and a current control circuit system 134. The charge pump circuit 132 may receive a pulse signal D from the current sensing circuit system 114a. COMP , and the signal D COMP The charge pump output voltage VCP is converted into a voltage VCP provided to the current control circuit system 134. Based on the charge pump output voltage VCP, which represents the average inductor current, the current control circuit system 134 can generate a control signal 136 for driving the switching transistors in the power conversion circuit 102. The control signal 136 can adjust the on / off duty cycle of one or more of the switching transistors in the power conversion circuit 102, thereby regulating the inductor current to a value corresponding to the value set by the regulation signal VCP. ERR-V The target value of the threshold to be set. Figure 2A and 2BExamples of charge pump circuit 132 and current control circuitry 134 and their operation are described in further detail.

[0030] refer to Figure 1B In some examples, the current sensing circuit system 114b is coupled to the input voltage terminal 104, the output voltage terminal 106, the switch terminal SW, and the output terminal of the transconductance amplifier 116. The current sensing circuit system 114b can be configured to detect the inductor current by comparing it with the adjustment signal V based on the above-described ERR-V The current sensing circuitry may include a sensing transistor that is controlled by a control signal 136 (eg, HS in this example). DRV LS DRV ) drive, the control signal is also used to drive the switching transistor in the power conversion circuit 102, as described below with reference to Figure 4 Describe in more detail.

[0031] exist Figure 1B In the example of FIG. 1 , the current control circuit system 134 generates a control signal 136 (eg, a signal HS ) based on the voltage VCP from the charge pump circuit 132. DRV and LS DRV ), as referenced above Figure 1A described.

[0032] Reference Figure 2A , according to one example, a buck-boost configuration is shown Figure 1A 106. In the example shown, a load 202 is coupled to the output voltage terminal 106. The DC-DC converter 100 can be configured to deliver an output signal, such as an output voltage Vout, to drive the connected load 202. As described above, the DC-DC converter 100 can receive an input signal, such as an input voltage Vin, at the input voltage terminal 104, and when powered, convert the input voltage Vin to provide an output voltage signal Vout. The output capacitor 204 is coupled between the output voltage terminal 106 and the ground terminal. In the example shown, one input terminal of the transconductance amplifier 116 is coupled to the output voltage terminal 106 via a resistor divider to receive a feedback voltage Vout. FB , as described above. The resistor divider may include resistors 206 and 208 coupled in series between the output voltage terminal 106 and the ground terminal. Therefore, the feedback voltage V FB The feedback voltage V may be generated at the center terminal joining the two resistors 206, 208, as shown. In other examples, the feedback voltage V may be taken directly from the output voltage terminal 106. FBIn some examples, the DC-DC converter 100 is configured to provide closed-loop regulation of the output voltage Vout according to a voltage reference signal Vref supplied at the reference terminal 118. As described above, the voltage regulator 112 is based on the feedback voltage V FB The difference between the reference voltage Vref supplied at the reference terminal 118 generates the regulation signal V ERR-V .

[0033] exist Figure 2A In the example of , the power conversion circuit 102 includes a first high-side transistor Q1, a first low-side transistor Q2, a second high-side transistor Q3 and a second low-side transistor Q4. The first high-side transistor Q1 is coupled between the input voltage terminal 104 and the first switch terminal SW1, and the first low-side transistor Q2 is coupled between the first switch terminal SW1 and the ground terminal. Similarly, the second high-side transistor Q3 is coupled between the output voltage terminal 106 and the second switch terminal SW2, and the second low-side transistor Q4 is coupled between the second switch terminal SW2 and the ground terminal. The inductor 108 is coupled between the first switch terminal SW1 and the second switch terminal SW2. The control terminals (e.g., gates) of the four transistors Q1, Q2, Q3 and Q4 are driven by a control signal 136, which in this example are HS ON1 LS ON2 , HS ON3 and LS ON4 In some examples, transistors Q1, Q2, Q3, Q4 are power FETs (e.g., n-channel or p-channel MOSFET devices); however, other transistor technologies may be used in other examples. When transistors Q1-Q4 are turned on and off according to control signal 136, current flows into inductor 108 and from inductor 108 to connected load 202, thereby generating a changing inductor current i that can be sensed at switch terminals SW1, SW2. L .

[0034] According to some examples, the current sensing circuit system 114a includes a first sensing transistor 210 coupled to the first high-side transistor Q1 and a second sensing transistor 212 coupled to the second high-side transistor Q3. The current sensing circuit system 114a may further include a first adjustable current source 214 and a second adjustable current source 216. In the example shown, the first sensing transistor 210 is coupled between the input voltage terminal 104 and the first adjustable current source 214 and has a control terminal coupled to the first high-side transistor Q1 and is controlled by the control signal HS ON1 In the example shown, the first high-side transistor Q1 is coupled to be driven according to the corresponding high first control signal 136 (HS ON1) is turned on. Therefore, in this example, the first high-side transistor Q1 has a drain terminal coupled to the input voltage terminal 104, a source terminal coupled to the first switch terminal SW1, and a first control signal HS ON1 In some examples, the first sensing transistor 210 is a transistor of the same type as the first high-side transistor Q1, and the ratio of transistor size (e.g., gate width) between the first sensing transistor 210 and the first high-side transistor Q1 is 1:M (e.g., the first high-side transistor Q1 is M times the first sensing transistor 210). Therefore, in the example shown, the first sensing transistor 210 has a drain terminal coupled to the input voltage terminal 104, a source terminal coupled to the first adjustable current source 214, and a gate control terminal coupled to the first high-side transistor Q1 to receive the first control signal HS ON1 The gate control terminal.

[0035] Similarly, in the example shown, the second high-side transistor Q3 is coupled to be switched according to the corresponding high second control signal 136 (HS ON3 ) is turned on. Therefore, in this example, the second high-side transistor Q3 has a drain terminal coupled to the output voltage terminal 106, a source terminal coupled to the second switch terminal SW2, and a second control signal HS ON3 In some examples, the second sensing transistor 212 is a transistor of the same type as the second high-side transistor Q3, and the ratio of transistor size (e.g., gate width) between the second sensing transistor 212 and the second high-side transistor Q3 is 1:M (e.g., the second high-side transistor Q3 is M times the second sensing transistor 212). In the example shown, the second sensing transistor 212 has a drain terminal coupled to the second adjustable current source 216, a source terminal coupled to the second switch terminal SW2, and a gate control terminal coupled to the second high-side transistor Q3 to receive the second control signal HS ON3 Therefore, the first sensing transistor 210 and the second sensing transistor 212 can be switched synchronously with the first high-side transistor Q1 and the second high-side transistor Q3, respectively, and used to sense the current flowing in the first and second high-side transistors and thereby sense the corresponding inductor current i L .

[0036] Still refer to Figure 2AIn the example shown, the first low-side transistor Q2 and the second low-side transistor Q4 are NMOS switch transistors respectively coupled between the first switch terminal SW1 and the second switch terminal SW2 and the ground terminal. Therefore, in one example, the first low-side transistor Q2 has a drain terminal coupled to the first switch terminal SW1, a source terminal coupled to the ground terminal, and a third control signal LS1. ON2 Similarly, the second low-side transistor Q4 has a drain terminal coupled to the second switch terminal SW2, a source terminal coupled to the ground terminal, and a gate control terminal for receiving a fourth control signal LS ON4 The gate control terminal.

[0037] In some examples, the current sensing circuit system 114a further includes a first comparator 218 and a second comparator 220. The first comparator 218 has a first comparator input terminal (labeled “+”) coupled to the source terminal of the first sensing transistor 210 and coupled to the first adjustable current source 214, and a second comparator input terminal (labeled “-”) coupled to the first switch terminal SW1. The first comparator 218 is configured to generate a first comparator output signal DC1 based on the difference between the signals at its two input terminals. The second comparator 220 has a first comparator input terminal (labeled “+”) coupled to the drain terminal of the second sensing transistor 212 and coupled to the second adjustable current source 216, and a second comparator input terminal (labeled “-”) coupled to the output voltage terminal 106, as shown in FIG. Figure 2A Similar to the first comparator 218, the second comparator 220 is configured to generate a second comparator output signal DC2 based on the difference between the signals at its two input terminals.

[0038] According to some embodiments, when the inductor current i L Above threshold I TH When , the respective comparator 218, 220 generates a corresponding comparator output signal DC1, DC2 that is high (eg, logical or binary 1). Figure 3 , showing the inductor current i represented by trace 302 L During a first mode 304 (e.g., a buck operating mode in an example where the DC-DC converter 100 has a buck-boost configuration), current flows from the input voltage terminal 104 via the first high-side transistor Q1 into the inductor 108, and during a second mode 306 (e.g., a boost operating mode), current flows from the inductor 108 via the second high-side transistor Q3 to the connected load 202 at the output voltage terminal 106. Thus, during the first mode 304, the inductor current i is sensed using the first sensing transistor 210. L, and when the inductor current i L Above threshold I TH During the second mode 306, the inductor current i is sensed using the second sensing transistor 212. L , and when the inductor current i L Above threshold I TH When the second comparator 220 generates a second comparator output signal DC2 which is high, the inductor current i can be controlled by controlling the switching duty cycle of the high-side transistors Q1 and Q3 via the control signal 136. L Exceeding threshold I TH The amount of time during a given switching or commutation cycle (a combination of the two modes 304, 306).

[0039] like Figure 2A As shown in FIG. 1 , in some examples, the current sensing circuit system 114 a further includes receiving two comparator output signals DC1 and DC2 and generating a pulse signal D COMP Digital logic gate 224 (in Figure 2A In some examples, because the pulse signal D COMP has a value corresponding to the OR combination of the comparator output signals DC1 and DC2, so when the inductor current i L Above threshold I TH When the pulse signal D COMP Therefore, the reference Figure 3 , pulse signal D COMP (represented by trace 308) has a value representing the inductor current i L Above the threshold (I TH ) is the percentage of time that the pulse signal is high. Thus, if the pulse signal has a 50% duty cycle 310, then the average inductor current i L Corresponding to the threshold I TH .

[0040] According to some embodiments, the threshold value I TH is set by adjustable current sources 214 and 216. Figure 2A As shown in FIG. , the adjustable current sources 214 and 216 can be adjusted by the adjustment signal V ERR-V control, and therefore the threshold I TH As described above, in some examples, the voltage regulator 112 adjusts the output voltage Vout at the output voltage terminal 106 based on the reference voltage Vref at the reference voltage terminal 118 and generates the adjustment signal V ERR-V, as a feedback signal in the voltage control and current sensing loop 110. According to some examples, by using the adjustment signal V ERR-V To set the threshold I TH , the regulation signal becomes the average inductor current i L In some examples, the current control loop 130 can be configured to convert the pulse signal D COMP The duty cycle of the inductor current i is compared with 50%, and a control signal 136 is generated to adjust the switching duty cycle of the transistors Q1 to Q4 so as to reduce the switching duty cycle of the inductor current i L driven by the regulated signal V ERR-V The target average value (I TH ). Thus, as described above, the example of the DC-DC converter 100 operates two control loops to implement a current mode control technique using average inductor current information. The first control loop implemented by the voltage control and current sensing loop 110 controls the parameter / quantity to be regulated (e.g., the output voltage Vout or the input or output current at the input voltage terminal 104 or the output voltage terminal 106, respectively, as further described below), and the second control loop implemented by the current control loop 130 controls the regulation signal Vout obtained from the first control loop based on the regulation signal Vout obtained from the first control loop. ERR-V The control inductor current i L .

[0041] As described above, the current control loop 130 generates the control signal 136, which is used to control the transistors Q1 to Q4 (in Figure 2A ) or Q1 to Q2 (described further below Figure 4 In some examples, the control signal 136 is a pulse width modulated (PWM) signal, each of which has a pulse signal D COMP The controllable duty cycle is further described below.

[0042] refer to Figure 2B , shows an example of the current control loop 130. According to some examples, the charge pump circuit 132 is configured to convert the pulse signal D COMP The duty cycle 310 of is compared with 50%, as described above. Therefore, in some examples, the charge pump circuit 132 is coupled to the output terminal of the digital logic gate 224 to receive the pulse signal D COMP , as shown. The charge pump circuit can output the pulse signal D at its output terminal 260 COMPThe charge pump voltage signal VCP is generated by the duty cycle 310 of the charge pump circuit 132. In the example shown, the charge pump circuit 132 includes a first transistor 226, a second transistor 228, a third transistor 230, and a fourth transistor 232. In some examples, the control terminals of the first transistor 226 and the third transistor 230 are connected together and connected to a first reference current source 236. The filter capacitor 234 can be connected between the power supply voltage rail Vcc and the control terminals of the first transistor 226 and the third transistor 230. In some examples, the first transistor 226, the third transistor 230, and the fourth transistor 232 are p-channel MOSFET switches (e.g., PMOS devices), and the second transistor 228 is an NMOS device. Therefore, in the example shown, the first transistor 226 includes a source terminal coupled to the power supply voltage rail Vcc and a drain terminal coupled to the drain terminal of the second transistor 228. The source terminal of the second transistor 228 is coupled to the second reference current source 238. The first reference current source and the second reference current source have I REF The third transistor 230 has a source terminal coupled to the power supply voltage rail Vcc and a drain terminal coupled to the source terminal of the fourth transistor 232. In some examples, the second transistor 228 and the fourth transistor 232 of the charge pump circuit 132 have gate control terminals that are connected together and coupled to the zero crossing detector (ZCD) circuit 222 ( Figure 2A ) to receive the Hi-Z control signal from the ZCD circuit 222. The drain terminal of the fourth transistor 232 can generate a charge pump voltage signal VCP at the charge pump output terminal 260.

[0043] In some examples, the ZCD circuit 222 is coupled to the first switch terminal SW1 and the second switch terminal SW2, such as Figure 2A The ZCD circuit 222 compares the voltage at the switch terminal SW1 or SW2 with the ground voltage (e.g., zero volts). In operation, the ZCD circuit 222 compares the voltage at the switch terminal SW1 or SW2 to the inductor current i L The control signal Hi-Z is provided to the charge pump circuit 132. For example, the ZCD circuit 222 can be configured to control the inductor current i L When the inductor current i L When the Hi-Z signal is greater than zero, the Hi-Z signal is provided in a second state (e.g., low). As further described below, in one example, the charge pump circuit 132 uses the Hi-Z signal in both the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) operating modes of the DC-DC power converter 100 to implement a control operation based on the pulse signal D COMP Current regulation.

[0044] Reference again Figure 2B According to some examples, the charge pump circuit 132 includes a fifth transistor 240, which may be an NMOS device having a drain terminal coupled to the charge pump output terminal 260 and an output terminal coupled to the digital logic gate 224 to receive the pulse signal D COMP The charging circuit 132 may further include a third reference current source 242 connected between the source terminal of the fifth transistor 240 and the ground terminal. The charge pump circuit 132 may further include an RC filter including a capacitor 244 and a resistor 246 coupled in series between the charge pump output terminal 260 and the ground terminal and an integrating capacitor 248 connected between the charge pump output terminal 260 and the ground terminal. In this configuration, when the pulse signal D COMP When the pulse signal D is high, the fifth transistor 240 is turned on and conducts current from the charge pump output terminal 260 at an amplitude set by the third reference current source 242. COMP When is low, the fifth transistor 240 is turned off. The error current flows from the charge pump output terminal 260 to the integrating capacitor 248. This error current is the current from the fourth transistor 232. and the current 2I flowing from the charge pump output terminal 260 to the fifth transistor 240 REF D comp The sum of .

[0045] According to some embodiments, the charge pump circuit 132 is used to generate a pulse signal D COMP The third reference current source 242 conducts a current having a value of 2I REF And, when the fourth transistor 232 is turned on (for example, when the control signal Hi-Z is low), the current passing through the fourth transistor 232 is set by the current mirror circuit formed with the second transistor 226. This mirror current flowing in the fourth transistor 232 is determined by the reference current value I REF (from the first reference current source 236 and the second reference current source 238) and the duty cycle of the control signal Hi-Z. For CCM operation of the DC-DC converter 100, the control signal HI-Z is kept low (e.g., because the inductor current i L The fourth transistor 232 is thus turned on, and the current flowing in the fourth transistor 232 has a current I REF In CCM operation, the voltage VCP across the integrating capacitor 248 is regulated to the value determined by the pulse signal D COMP For example, when the pulse signal D COMPWhen the duty cycle of the DC-DC converter 100 is 50%, the fifth transistor 240 is turned on for half the duration of each switching cycle of the DC-DC converter 100 .

[0046] When the fifth transistor 240 is turned on, the value of REF A current flows through the fifth transistor 240 and has a value of I REF The current flows through the fourth transistor 232. In this state, the error current at the charge pump output terminal 260 has a current of -I2 which is used to discharge the integration capacitor 248. REF The fifth transistor 240 is turned off for the remaining half of the switching cycle. When the fifth transistor 240 is turned off, the error current at the charge pump output terminal 260 has a value of +I used to charge the integration capacitor 248. REF When the pulse signal D COMP When the duty cycle of the pulse signal D is 50%, the integral capacitor 248 is alternately charged and discharged for an equal amount of time, and the average amplitude of the charge pump output voltage signal VCP is substantially constant. COMP The duty cycle deviates from 50% (indicating that the average inductor current i L Above or below target value I TH ), then the charging and discharging of the integrating capacitor 248 is unbalanced, and the average voltage VCP changes accordingly.

[0047] The charge pump circuit 132 may also accommodate DCM operation, as described above. In some examples, in response to a high Hi-Z signal state (eg, when the inductor current i L =0), the second transistor 228 is turned on and the fourth transistor 232 is turned off. In this state, the error current at the charge pump output terminal 260 is based on the pulse signal D from the digital logic gate 224. COMP The duty cycle of the current 2I flowing through the fifth transistor 240 is determined according to the REF D comp For DCM operation, the inductor current i L reaches zero during a portion of an individual switching cycle of the DC-DC converter 100. For CCM operation and for a portion of a switching cycle in DCM operation, the inductor current i L is non-zero. In response to the inductor current i L is non-zero, the Hi-Z signal is low, as described above, the second transistor 228 is turned off, and the fourth transistor 232 is turned on. In this state, the current flowing through the fourth transistor 232 to the charge pump output terminal 260 has I REF (1+D Hi-Z ) value. During the period when the Hi-Z signal is low, the current flowing through the fourth transistor 232 is IREF (1+D Hi-Z ). Therefore, on average, the current flowing is As described above.

[0048] According to some examples, the charge pump output voltage VCP is provided from the charge pump circuit 132 to the current control circuit system 134. The current control circuit system 134 can be configured to generate a control signal 136 based on the charge pump output voltage VCP, which is representative of the average inductor current i described above. L Still refer to Figure 2B In some examples, the current control circuit system 134 includes a transistor 250 having a control terminal coupled to a charge pump output terminal 260 to receive the charge pump output voltage VCP. The current control circuit system 134 may further include a PWM control circuit 262 configured to generate a control signal 136. The PWM control circuit 262 generates the signal 136 based in part on the charge pump output voltage VCP to control the switching duty cycle of the transistors Q1 to Q4 so as to set the average inductor current i L Adjusted to the value determined by the adjustment signal V ERR-V Set the target threshold I TH , as described above.

[0049] In the example where the DC-DC converter 100 has a buck-boost configuration, the PWM control circuit 262 includes a first hysteretic comparator 252 and a second hysteretic comparator 254 that generate control signals 136 for the boost and buck operating modes, respectively. In some examples, the first hysteretic comparator 252 includes a first input terminal coupled to receive an input voltage Vin from the input voltage terminal 104, and a first input terminal coupled to receive a boost mode ramp carrier signal V RMP_BST The first hysteresis comparator 252 further includes a second input terminal coupled to receive a current control reference voltage V REFi The third input terminal is coupled to receive the current control error voltage V ERRi The fourth input of the current control error voltage is based on the charge pump output voltage VCP (and thus represents the error current flowing at the charge pump output terminal 260 described above). In operation, the first hysteresis comparator 252 is based on the input voltage Vin and the current control reference voltage V REFi While modulating the boost mode ramp carrier signal V RMP_BST , where the duty cycle is controlled by the current error voltage V ERRi Control to provide boost mode control signal GD BSTThe PWM control circuit 262 may further include a first dual output buffer 256 coupled to the output terminal of the first hysteresis comparator 252 and having an inverter on one output. Thus, the PWM control circuit 262 controls the signal GD from the boost mode. BST Generates two complementary control signals HS for controlling the second high-side transistor Q3 and the second low-side transistor Q4 ON3 and LS ON4 (eg, two of control signals 136).

[0050] Similarly, in some examples, the second hysteresis comparator 254 includes a first input terminal coupled to receive the output voltage Vout from the output voltage terminal 106 and a first input terminal coupled to receive the buck mode ramp carrier signal V RMP_BUK The second hysteresis comparator 254 further includes a second input terminal coupled to receive a current control reference voltage V REFi The third input terminal is coupled to receive the current control error voltage V ERRi In operation, the second hysteresis comparator 254 controls the current based on the output voltage Vout and the reference voltage V REFi While modulating the buck mode ramp carrier signal V RMP_BUK , where the duty cycle is controlled by the current error voltage V ERRi Control to provide buck mode control signal GD BUK The PWM control circuit 262 may further include a second dual output buffer 258 coupled to the output terminal of the second hysteresis comparator 254 and having an inverter on one output. Therefore, the PWM control circuit 262 further controls the voltage drop from the buck mode control signal GD BUK Two additional complementary control signals HS are generated for controlling the first high-side transistor Q1 and the first low-side transistor Q2 ON1 and LS ON2 (eg, the other two of control signals 136).

[0051] According to some embodiments, the output signal HS ON3 and LS ON4 The duty cycle of represents the ratio or proportion of the time that the second high-side transistor Q3 and the second low-side transistor Q4 are turned on in a given switching cycle. As described above, this duty cycle in turn controls the inductor current i during the second mode 306. L , and when the inductor current is higher than the threshold I TH Similarly, the output signal HS ON1 and LS ON2The duty cycle of represents the ratio or proportion of the time that the first high-side transistor Q1 and the first low-side transistor Q2 are turned on in a given switching cycle. This duty cycle in turn controls the inductor current i during the first mode 304. L , and when the inductor current is higher than the threshold I TH Therefore, because the duty cycle of the control signal 136 is controlled by the charge pump output voltage VCP, the charge pump output voltage represents the amount of time relative to the threshold I TH The average inductor current is therefore adjusted by the current control circuit system 134 to a target threshold value I TH Since the target threshold I TH The regulation signal V from the voltage control and current sensing loop 110 ERR-V The current control circuit system 134 regulates the inductor current according to the adjustment of the parameter (e.g., output voltage Vout, output current, or input current) controlled by the feedback loop. Therefore, as described above, the combination of the voltage control and current sensing loop 110 and the current control loop 130 can operate as two linked feedback and control loops within the DC-DC converter 100. The "external" feedback loop (including the voltage regulator 112) adjusts the selected parameter / quantity (e.g., output voltage, output current, or input current) of the DC-DC converter 100, thereby generating a regulation signal, which is then passed to the "internal" current control loop 130 to adjust the average inductor current accordingly.

[0052] exist Figure 1A , 2A In the examples of FIG. 2B and FIG. 3B , the DC-DC converter 100 has a buck-boost configuration. However, the average inductor current sensing and control techniques described herein can be applied to other DC-DC converter topologies. For example, as described above with reference to FIG. Figure 1B As described, the voltage control and current sensing loop 110 and the current control circuitry 134 may be implemented in a DC-DC converter 100 having a buck configuration.

[0053] refer to Figure 4 , an example of a DC-DC converter 100 having a buck configuration and including the current sensing circuit system 114b described above is shown. In this example, the power conversion circuit 102 includes a high-side transistor Q1 and a low-side transistor Q2. The high-side transistor Q1 is coupled between the input voltage terminal 104 and the switch terminal SW, and the low-side transistor Q2 is coupled between the switch terminal SW and the ground terminal. The inductor 108 is coupled between the switch terminal SW and the output voltage terminal 106. The control terminals (e.g., gates) of the transistors Q1 and Q2 are controlled by a control signal 136 (in this example, HS DRV and LSDRV ) drive. In some examples, transistors Q1 and Q2 are power FETs (e.g., n-channel or p-channel MOSFET devices); however, other transistor technologies may be used in other examples. When transistors Q1 and Q2 are turned on and off according to control signal 136, current flows into inductor 108 and from inductor 108 to connected load 202, thereby generating a changing inductor current i that can be sensed at switch terminal SW L (For example, Figure 3 ), as described above.

[0054] According to some examples, the current sensing circuit system 114b includes a first sensing transistor 410 coupled to the high-side transistor Q1 and a second sensing transistor 412 coupled to the low-side transistor Q2. The current sensing circuit system 114b may further include a first adjustable current source 414 and a second adjustable current source 416. The adjustable current sources 414 and 416 have a current source regulated by the regulation signal V ERR-V Controlled current I TH , as described above. In the example shown, the first sensing transistor 410 is coupled between the input voltage terminal 104 and the first adjustable current source 414 and has a control terminal coupled to the high-side transistor Q1 and is controlled by the control signal HS DRV In the example shown, the high-side transistor Q1 is coupled to drive the control terminal according to the corresponding high first control signal 136 (HS DRV ) is turned on. Thus, in this example, the high-side transistor Q1 has a drain terminal coupled to the input voltage terminal 104, a source terminal coupled to the switch terminal SW, and a first control signal HS DRV In some examples, the first sensing transistor 410 is a transistor of the same type as the high-side transistor Q1, and the ratio of transistor size (e.g., gate width) between the first sensing transistor 410 and the high-side transistor Q1 is 1:M (e.g., the high-side transistor Q1 is M times the first sensing transistor 410). Therefore, in the example shown, the first sensing transistor 410 has a drain terminal coupled to the input voltage terminal 104, a source terminal coupled to the first adjustable current source 414, and a gate control terminal coupled to the high-side transistor Q1 to receive the first control signal HS ON1 The gate control terminal.

[0055] Similarly, in Figure 4 In the illustrated example, the low-side transistor Q2 is coupled to be controlled according to the corresponding high second control signal 136 (LS DRV) is turned on. Therefore, in this example, the low-side transistor Q2 has a drain terminal coupled to the switch terminal SW, a source terminal coupled to the ground terminal, and a second control signal LS1. DRV In some examples, the second sensing transistor 412 is a transistor of the same type as the low-side transistor Q2, and the ratio of transistor size (e.g., gate width) between the second sensing transistor 412 and the low-side transistor Q2 is 1:M (e.g., the low-side transistor Q2 is M times the second sensing transistor 412). In the example shown, the second sensing transistor 412 has a source terminal coupled to the second adjustable current source 416, a drain terminal coupled to the switch terminal SW, and a gate control terminal coupled to the low-side transistor Q2 to receive the second control signal LS DRV Therefore, the first sensing transistor 410 and the second sensing transistor 412 can be switched synchronously with the high-side transistor Q1 and the low-side transistor Q2, respectively, and used to sense the current flowing in the high-side and low-side transistors and thereby sense the corresponding inductor current i L .

[0056] Still refer to Figure 4 In some examples, the current sensing circuit system 114b further includes a first comparator 418 and a second comparator 420, similar to the current sensing circuit system 114a described above. The first comparator 418 has a first comparator input terminal (labeled as "+") coupled to the source terminal of the first sensing transistor 410 and coupled to the first adjustable current source 414, and a second comparator input terminal (labeled as "-") coupled to the switch terminal SW. The first comparator 418 is configured to generate a first comparator output signal DC1 based on the difference between the signals at its two input terminals. The second comparator 420 has a first comparator input terminal (labeled as "+") coupled to the ground terminal, and a second comparator input terminal (labeled as "-") coupled to the source terminal of the second sensing transistor 412 and coupled to the second adjustable current source 416. Similar to the first comparator 418, the second comparator 420 is configured to generate a second comparator output signal DC2 based on the difference between the signals at its two input terminals.

[0057] According to some examples, the voltage at the first comparator input terminal of the first comparator 418 is determined by the voltage from the first adjustable current source 414 (I TH) and the on-state resistance of the first sensing transistor 410. The first comparator 418 provides a first comparator output signal DC1, which is in a first state (e.g., high) in response to the voltage signal at the first comparator input terminal of the first comparator being greater than the voltage at the switch terminal SW, or in a second state (e.g., low) in response to the voltage at the first comparator input terminal of the first comparator being less than the voltage at the switch terminal SW. Because the voltage at the switch terminal SW is proportional to the inductor current i L Therefore, the state (eg, high or low) of the first comparator output signal DC1 depends on the inductor current i at the switch terminal SW. L Is it above or below the threshold I set by the first adjustable current source 414? TH Similarly, the second comparator 420 determines the current i at the switch terminal SW based on the inductor current i L Is it above or below the threshold I set by the second adjustable current source 416? TH A second comparator output signal DC2 having a state (eg, high or low) is generated.

[0058] In buck configuration, similar to the reference above Figure 2A , 3 In the buck-boost configuration described in FIG4, the switching of transistors Q1 and Q2 produces a varying inductor current i L , which has a similar Figure 3 The outline shown in Figure 4 In the example of , the first sensing transistor 410 senses the inductor current during the first mode 304 (eg, Q1 is on and Q2 is off), and the second sensing transistor 412 senses the inductor current during the second mode 306 (eg, Q1 is off and Q2 is on). L Above threshold I TH When the respective comparators 418, 420 may thus generate respective comparator output signals DC1, DC2 that are high. As in the example of the current sensing circuit system 114a discussed above, the current sensing circuit system 114b may include receiving the two comparator output signals DC1 and DC2 and generating a pulse signal D COMP Digital logic gate 224 (in Figure 4 Therefore, as described above, since the pulse signal D COMP has a value corresponding to the OR combination of the comparator output signals DC1 and DC2, so the pulse signal D COMP The inductor current i L Above threshold I TH is high and has a value indicating the inductor current i L Above the threshold (ITH )'s time percentage duty cycle 310( Figure 3 ). In the inductor current i L Exceeding threshold I TH The amount of time during a given switching cycle of can be controlled by controlling the switching duty cycle of transistors Q1 and Q2 via control signal 136. Figure 2A and 2B In the example, the threshold I TH The current is set by the adjustable current sources 414 and 416, which are adjusted by the adjustment signal V ERR-V control.

[0059] Still refer to Figure 4 In this example, the pulse signal D COMP Provided to the charge pump circuit 132, the charge pump circuit is as described above (refer to Figure 2B ) to generate the charge pump output voltage VCP. The current control circuit system 134 generates a control signal 136 (in this example, HS DRV and LS DRV ) as a PWM signal having a duty cycle controlled by the charge pump output voltage VCP. Therefore, as described above, the current sensing circuit system 114b provides information about the inductor current i L The average value of the information (for example, the pulse signal D COMP ), and the current control circuit system 134 generates a control signal 136 to control the switching cycle of transistors Q1 and Q2 to drive the average inductor current to the value determined by the regulation signal V ERR-V Set the target threshold I TH .

[0060] The DC-DC power converter 100 and its control circuitry may be implemented in whole or in part using a control integrated circuit (IC). In one example, the power conversion circuit 102, the voltage control and current sensing loop 110, and the current control loop 130 are formed in a single IC (not shown). In various alternative implementations, one or more components of these circuits may be implemented outside the IC. In addition, for example, one or more system components such as an inductor 108 may be disposed "off chip" and coupled to the IC.

[0061] As described above, because the current sensing circuitry 114a, 114b provides access to the average inductor current, in some instances this information can be used to adjust selected parameters of the DC-DC converter, such as the average output current or the average input current. This can provide the advantage of being able to adjust the average input or output current without requiring lossy sensing elements to sense the input or output current to provide feedback information, which can improve accuracy and / or reduce cost. In the case of a buck configuration of the DC-DC converter 100, for example, Figure 4 In the example, the inductor current i L corresponds to the output current delivered to the load via the output voltage terminal 106. Therefore, the average inductor current can be used directly to regulate the average output current. However, in a buck-boost configuration of the DC-DC converter 100, for example Figure 2A In the example, the inductor current i L is about the input current at the input voltage terminal 104 and about the output current at the output voltage terminal 106, but does not directly correspond to either. Therefore, in some examples, the conversion circuit can be used to convert the average inductor current sensed using the current sensing circuit system 114a described above to regulate the average input current or the average output current of the DC-DC converter 100.

[0062] refer to Figure 5 , shows a method for using the DC-DC power converter 100 to calculate the average inductor current i L 1 and 2. The example of a conversion circuit 500 for regulating an input current at an input voltage terminal 104 is shown. An optional sense resistor 502 is coupled between the output voltage terminal 106 and the load 202. In this example, the conversion circuit 500 includes a first transconductance amplifier 504 having a first amplifier input terminal (labeled “-”) coupled to an output terminal of a transconductance amplifier 116 of a voltage regulator 112 to receive a regulation signal V ERR-V The first transistor 506 is coupled between the output terminal of the transconductance amplifier 116 of the voltage regulator 112 and a ground terminal, and has a control terminal coupled to the output terminal of the first transconductance amplifier 504 of the conversion circuit 500. In the example shown, the first transistor 506 is a PMOS device; however, in other examples, other transistor technologies may be used. A current limiting capacitor 508 may be coupled between the control terminal of the first transistor 506 (and the output terminal of the first transconductance amplifier 504) and a ground terminal, as shown.

[0063] The conversion circuit 500 may include a first switching transistor 512 and a second switching transistor 514 having control terminals coupled together and coupled to an inverter 510 to receive a first control signal HS controlling the switching of the first high-side transistor Q1 described above. ON1 , a complementary version of (e.g., having inverted high and low states). In the example shown, the first switch transistor 512 is a PMOS device and the second switch transistor is an NMOS device. Thus, in this example, the first switch transistor 512 and the second switch transistor 514 have drain terminals coupled together and coupled to a first amplifier input terminal (labeled “-”) of the second transconductance amplifier 518 via a first RC filter. In some examples, the first RC filter includes a resistor 520 coupled in series between control terminals of the first switch transistor 512 and the second switch transistor 514 and the first amplifier input terminal of the second transconductance amplifier 518. The first RC filter may further include a parallel capacitor 522 coupled between the first amplifier input terminal of the second transconductance amplifier 518 and a ground terminal. The second transconductance amplifier 518 has a limit signal (I20) coupled to receive a target value of the input current at the specified input voltage terminal 104. LIM_DAC ) is coupled to a second amplifier input terminal (labeled “+”) of the first transconductance amplifier 504. In some examples, the limiting signal is supplied from a digital-to-analog converter (DAC), which may be part of the current control circuitry 134 or another on-chip or off-chip component of the DC-DC converter 100. The output terminal of the second transconductance amplifier 518 is coupled to the source terminal of the first switching transistor 512 via a buffer 516, and to the second amplifier input terminal (labeled “+”) of the first transconductance amplifier 504. The second RC filter may be coupled between the second amplifier input terminal of the first transconductance amplifier 504 (and therefore the output terminal of the second transconductance amplifier 518) and a ground terminal. In the example shown, the second RC filter includes a series combination of a resistor 524 and a capacitor 526. The source terminal of the second switching transistor 514 is coupled to the ground terminal.

[0064] In operation, the first and second switching transistors are controlled by the first control signal HS ON1 Therefore, the switching transistors 512, 514 generate an inductor current i at the first amplifier input terminal of the second transconductance amplifier 518 that is reflected back to the input voltage terminal 104. L In some instances, this is accomplished by setting the inductor current i L Multiplied by the control signal HS ON1 The second transconductance amplifier 518 converts the limit signal I representing the target input current value into a limit signal I LIM_DACThe actual input reflected average inductor current (represented by the voltage at the first amplifier input terminal of the second transconductance amplifier 518) is compared. LIM_DAC The conversion circuit 500 further adjusts the signal V through the first transconductance amplifier 504. ERR-V The input current is regulated by the operation of the control signal, which is used as described above for the average inductor current i L Set target value I TH , which in turn is partially generated by the input current flowing through the first high-side transistor Q1.

[0065] refer to Figure 6 , shows a method for using the DC-DC power converter 100 to calculate the average inductor current i L An example of a conversion circuit 600 for regulating an output current at an output voltage terminal 106 is shown. In this example, the conversion circuit 600 includes a transconductance amplifier 602 having a limit signal (I ) coupled to receive a target value of the output current at the output voltage terminal 106. CHG_DAC ). In some examples, the limit signal is supplied from a DAC, which may be part of the current control circuitry 134 or another on-chip or off-chip component of the DC-DC converter 100. The conversion circuit 600 further includes a first transistor 506 and a first switching transistor 512 and a second switching transistor 514. In this example, the first transistor 506 is coupled between the output terminal of the transconductance amplifier 116 of the voltage regulator 112 and a ground terminal, and has a control terminal coupled to the output terminal of the transconductance amplifier 602 of the conversion circuit 600. The second RC filter (resistor 524 and capacitor 526) is coupled between the output terminal of the transconductance amplifier 602 (and therefore the control terminal of the first transistor 506) and the ground terminal.

[0066] exist Figure 6 In the example, the control terminals of the first switch transistor 512 and the second switch transistor 514 are coupled together and coupled to the inverter 510 to receive the second control signal HS that controls the switching of the second high-side transistor Q3 described above. ON3, which is a complementary version of (e.g., having inverted high and low states). In this example, the first switch transistor 512 and the second switch transistor 514 have drain terminals that are coupled together and coupled to the second amplifier input terminal (labeled “-”) of the transconductance amplifier 602 via the first RC filter (resistor 520 and capacitor 522 connected as described above). The source terminal of the first switch transistor 512 is coupled to the output terminal of the transconductance amplifier 116 (and to the source terminal of the first transistor 506) via the buffer 604 to receive the regulation signal V ERR-V ,like Figure 6 The source terminal of the second switch transistor 514 is coupled to the ground terminal.

[0067] In operation, the first and second switching transistors are controlled by the second control signal HS ON3 Therefore, the switching transistors 512, 514 generate an average inductor current i at the first amplifier input terminal of the transconductance amplifier 602 that is equal to the average inductor current i reflected to the output voltage terminal 106. L In some instances, this is accomplished by setting the inductor current i L Multiplied by the control signal HS ON3 The transconductance amplifier 602 converts the limit signal I representing the target output current value into a limit signal I CHG_DAC is compared with the actual output reflected average inductor current (represented by the voltage at the first amplifier input terminal of the transconductance amplifier 602). In addition, because the source terminal of the first switching transistor 512 receives the regulation signal V ERR-V , so the current flowing through resistor 520 to the second amplifier input terminal of transconductance amplifier 602 has a current equal to that for the average inductor current i L Thus, based on the portion of the inductor current corresponding to the output current (flowing through the second high-side transistor Q3 when turned on), the output current is represented in the conversion circuit 600 by conversion of the target inductor current. The conversion circuit 600 is then used to set the output current based on the limit signal I CHG_DAC And adjust the output current.

[0068] Therefore, using conversion circuit 500 and / or 600, the input current and / or output current in DC-DC converter 100 can be adjusted by using average inductor current information and thus without the need for sensing element to directly sense input and / or output current. As described above, in some instances, current sensing circuit system 114a can be used to obtain average inductor current information in an accurate and lossless manner. Therefore, the examples disclosed herein promote accurate control and / or limitation of average input and / or output current in DC-DC power converter 100 to achieve various benefits, such as improved system performance, reduced device degradation and / or improved power efficiency and power density. In addition, the examples disclosed herein can provide the following advantages: protecting the power supply at the input of DC-DC power converter 100 while delivering maximum power via input current regulation, or delivering a constant current to the connected load 202 via output current regulation. In some cases, the advantages associated with output current regulation can be particularly beneficial, for example, in battery charger applications.

[0069] Other Examples

[0070] Example 1 is a circuit comprising: a voltage regulator circuit having a regulator input terminal for coupling to an output terminal of a DC-DC power converter and a regulator output terminal, the voltage regulator circuit being configured to generate a regulation signal at the regulator output terminal based on a voltage at the regulator input terminal; a current sensing circuit system having at least one switch input terminal, a sensing input terminal and a sensing output terminal, the at least one switch input terminal being used to couple to at least one switch terminal of the DC-DC power converter, and the sensing input terminal being coupled to the regulator output terminal, the current sensing circuit system being configured to generate a pulse signal at the sensing output terminal, wherein the The pulse signal is based on the voltage at the at least one switch input terminal and the adjustable threshold set by the regulation signal; and a current control loop circuit having a loop input terminal coupled to the sensing output terminal and one or more control output terminals each for coupling to a control terminal of a corresponding switching transistor of the DC-DC power converter, the current control loop circuit being configured to generate a switch control signal at the one or more control output terminals based on the pulse signal, wherein the switch control signal is a pulse width modulated signal to control the one or more switching transistors to drive the average value of the current flowing through the at least one switch terminal to a target average current value corresponding to the adjustable threshold.

[0071] Example 2 includes the circuit of Example 1, wherein the pulse signal has a duty cycle that represents a percentage of time that the current flowing through the at least one switch terminal is above the adjustable threshold.

[0072] Example 3 includes a circuit of one of Examples 1 or 2, wherein the one or more switching transistors include a first switching transistor coupled to the at least one switching terminal and a second switching transistor coupled to the at least one switching terminal, and wherein the current sensing circuit system includes: a first comparator circuit having a first comparator output terminal and configured to provide a first comparator signal at the first comparator output terminal, the first comparator signal having a first state in response to a first switching current flowing through the first switching transistor being greater than the adjustable threshold, or having a second state in response to the first switching current being less than the adjustable threshold; a second comparator circuit having a second comparator signal; The invention relates to a comparator output terminal and is configured to provide a second comparator signal at the second comparator output terminal, the second comparator signal having the first state in response to the second switch current flowing through the second switch transistor being greater than the adjustable threshold, or having the second state in response to the second switch current being less than the adjustable threshold; and an OR gate having first and second OR gate input terminals and an OR gate output terminal, the first OR gate input terminal being coupled to the first comparator output terminal, the second OR gate input terminal being coupled to the second comparator output terminal, and the OR gate output terminal being coupled to the sensing output terminal, the OR gate being configured to provide the pulse signal.

[0073] Example 4 includes the circuit of Example 3, wherein the at least one switch terminal includes a first switch terminal and a second switch terminal, wherein the first comparator circuit includes: a first variable current source having a current value corresponding to the adjustable threshold and controlled by the adjustment signal; a first sensing transistor for sensing the first switch current; and a first comparator having the first comparator output terminal, a first comparator input terminal coupled to the first sensing transistor and the first variable current source, and a second comparator input terminal coupled to the first switch terminal, and wherein the second comparator circuit includes: a second variable current source having a current value corresponding to the adjustable threshold and controlled by the adjustment signal; a second sensing transistor for sensing the second switch current; and a second comparator having the second comparator output terminal, a third comparator input terminal coupled to the second sensing transistor and the second variable current source, and a fourth comparator input terminal coupled to the output terminal.

[0074] Example 5 includes the circuit of any one of Examples 1 to 4, wherein the current control loop circuit includes a charge pump circuit having the loop input terminal and a charge pump output terminal, and the charge pump circuit is configured to generate a control voltage signal at the charge pump output terminal based on the pulse signal.

[0075] Example 6 includes the circuit of Example 5, wherein the current control loop circuit includes a current control circuit system, which is coupled to the charge pump output terminal and is configured to generate the switch control signal based on the control voltage signal and one or more reference signals.

[0076] Example 7 includes the circuit of Example 6, wherein the current control circuitry includes at least one hysteretic comparator circuit.

[0077] Example 8 includes the circuit of any one of Examples 1 to 7, wherein the voltage regulator circuit comprises: a transconductance amplifier having the regulator input terminal, an amplifier input terminal for receiving a reference voltage, and the regulator output terminal; and a resistor-capacitor filter coupled between the regulator output terminal and a ground terminal; wherein the voltage regulator circuit is configured to generate the regulation signal based on a difference between the voltage at the regulator input terminal and the reference voltage.

[0078] Example 9 is a DC-DC converter including the circuit of any one of Examples 1 to 8.

[0079] Example 10 includes the DC-DC converter of Example 9, wherein the DC-DC converter is a buck-boost power converter.

[0080] Example 11 is a DC-DC power converter having an input terminal and an output terminal, and comprising: a power conversion circuit including a plurality of power transistors and having at least one switch terminal for coupling to at least one of the input terminal or the output terminal via an inductor, the plurality of power transistors being configured to generate a current through the at least one switch terminal based on a control signal received via a respective control terminal; a voltage regulator circuit having a regulator input coupled to the output terminal and a regulator output, the voltage regulator circuit being configured to generate a regulation signal at the regulator output based on a voltage at the output terminal; a current sensing circuit system coupled to the power conversion circuit and having a sensing output and a sensing input coupled to the regulator output, the current sensing circuit system being configured to generate a pulse signal at the sensing output having a duty cycle representing a percentage of time that the current flowing through the at least one switch terminal is above a target value; and a current control loop circuit having a control loop input and a plurality of control loop outputs, the control loop input being coupled to the sensing output and each of the control loop outputs being coupled to a corresponding one of the control terminals, the current control loop circuit being configured to generate the control signal as a pulse width modulated signal based on the pulse signal to control the plurality of power transistors to adjust the current through the at least one switch terminal to the target value.

[0081] Example 12 includes the DC-DC power converter of Example 11, wherein the current control loop circuit includes a charge pump circuit having the control loop input and a charge pump output, and the charge pump circuit is configured to generate a control voltage signal at the charge pump output based on the pulse signal.

[0082] Example 13 includes a DC-DC power converter of one of Examples 11 or 12, wherein the plurality of power transistors include a first power transistor and a second power transistor, and wherein the current sensing circuitry includes: a first comparator circuit having a first comparator output and configured to provide a first comparator signal at the first comparator output, the first comparator signal having a first state in response to a first switch current flowing through the first power transistor being greater than the target value, or having a second state in response to the first switch current being less than the target value; a second comparator circuit having a second comparator output and configured to provide a first comparator signal at the second comparator output; A second comparator signal is provided, the second comparator signal having a first state in response to a second switch current flowing through the second power transistor being greater than the target value, or having a second state in response to the second switch current being less than the target value; and an OR gate having first and second OR gate inputs and an OR gate output, the first OR gate input being coupled to the first comparator output, the second OR gate input being coupled to the second comparator output, and the OR gate output being coupled to the sense output, the OR gate being configured to provide the pulse signal at the sense output based on an OR combination of the first comparator signal and the second comparator signal.

[0083] Example 14 includes the DC-DC power converter of Example 13, wherein the DC-DC power converter is a buck-boost power converter, wherein the at least one switch terminal includes a first switch terminal and a second switch terminal, wherein the first power transistor is coupled between the input terminal and the first switch terminal, and wherein the second power transistor is coupled between the output terminal and the second switch terminal.

[0084] Example 15 includes the DC-DC power converter of Example 14, wherein the plurality of power transistors comprises: a third power transistor coupled between the first switch terminal and a ground terminal; and a fourth power transistor coupled between the second switch terminal and the ground terminal.

[0085] Example 16 includes a DC-DC power converter of one of Examples 14 or 15, wherein the first comparator circuit includes: a first variable current source coupled between the input terminal and the ground terminal and having a current value corresponding to the target value and controlled by the adjustment signal; a first sensing transistor coupled between the input terminal and the first variable current source and having a control terminal coupled to the control terminal of the first power transistor; and a first comparator having the first comparator output, a first comparator input coupled to the first sensing transistor and the first variable current source, and a second comparator input coupled to the first switch terminal. In addition, the second comparator circuit includes: a second variable current source coupled between the second switch terminal and the ground terminal and having a current value corresponding to the target value and controlled by the adjustment signal; a second sensing transistor coupled between the second switch terminal and the second variable current source and having a control terminal coupled to the control terminal of the second power transistor; and a second comparator having the second comparator output, a third comparator input coupled to the second sensing transistor and the second variable current source, and a fourth comparator input coupled to the output terminal.

[0086] Example 17 includes a DC-DC power converter of any one of Examples 14 to 16, wherein the control loop output includes a first control output coupled to the control terminal of the first power transistor, and the control signal includes a first control signal provided at the first control output, and the DC-DC power converter includes: a current conversion circuit coupled to the regulator output and to the first control output, the current conversion circuit being configured to adjust the regulation signal based on a limit of an input current at the input terminal.

[0087] Example 18 includes a DC-DC power converter of any one of Examples 14 to 16, wherein the control loop output includes a first control output coupled to the control terminal of the second power transistor, and the control signal includes a first control signal provided at the first control output, and the DC-DC power converter includes: a current conversion circuit coupled to the regulator output and to the first control output, the current conversion circuit being configured to adjust the regulation signal based on a limit of the output current at the output terminal.

[0088] Example 19 is a buck-boost DC-DC converter comprising: a first power transistor coupled between an input terminal and a first switch terminal; a second power transistor coupled between an output terminal and a second switch terminal; a voltage regulator having a first regulator input coupled to the output terminal, a second regulator input for receiving a reference voltage, and a regulator output; a first variable current source coupled between the input terminal and a ground terminal and having a first current control input coupled to the regulator output; and a first sensing transistor coupled between the input terminal and the first variable current source and having a control terminal coupled to a first control terminal of the first power transistor. The buck-boost DC-DC converter further includes: a first comparator having first and second comparator inputs and a first comparator output, the first comparator input being coupled to the first switch terminal, and the second comparator input being coupled to the first sensing transistor and the first variable current source, such that the first variable current source is coupled between the second comparator input and the ground terminal; a second variable current source being coupled between the second switch terminal and the ground terminal and having a second current control input terminal coupled to the regulator output; and a second sensing transistor being coupled between the second variable current source and the second switch terminal and having a control terminal coupled to a second control terminal of the second power transistor. The buck-boost DC-DC converter further includes: a second comparator having a second comparator output, a third comparator input coupled to the output terminal, and a fourth comparator input coupled to the second sensing transistor and the second variable current source, such that the second variable current source is coupled between the fourth comparator input and the ground terminal; and a current control loop coupled to the first and second comparator outputs and to the first and second control terminals of the first and second power transistors, respectively, the current control loop being configured to generate first and second control signals at the first and second control terminals, respectively, based on signals at the first and second comparator outputs.

[0089] Example 20 includes the buck-boost DC-DC converter of Example 19, wherein the current control loop comprises: an OR gate having a first gate input coupled to the first comparator output, a second gate input coupled to the second comparator output, and a gate output; a charge pump circuit having a charge pump input coupled to the gate output, and a charge pump output; and a control circuit system coupled to the charge pump output and configured to generate the first and second control signals.

[0090] Example 21 includes the buck-boost DC-DC converter of Example 20, further comprising: a third power transistor coupled between the first switch terminal and the ground terminal and having a third control terminal; and a fourth power transistor coupled between the second switch terminal and the ground terminal and having a fourth control terminal; wherein the current control loop is coupled to the third and fourth control terminals and is configured to generate third and fourth control signals at the third and fourth control terminals, respectively, based on the signals at the first and second comparator outputs.

[0091] Example 22 includes the buck-boost DC-DC converter of any one of Examples 19 to 21, wherein the voltage regulator is configured to generate a regulation signal at the regulator output based on a difference between the reference voltage and the voltage signal at the first regulator input, and wherein the regulation signal controls the current value of the first and second variable current sources.

[0092] Example 23 includes the buck-boost DC-DC converter of any of Examples 19 to 22, comprising a resistor-capacitor filter coupled between the regulator output and the ground terminal.

[0093] Example 24 includes the buck-boost DC-DC converter of any of Examples 19-23, wherein the first regulator input is coupled to the output terminal via a voltage divider circuit.

[0094] Example 25 is a control circuit for a DC-DC power converter, the control circuit comprising: a voltage regulator circuit having a first regulator input terminal for coupling to an output terminal of the DC-DC power converter, a second regulator input terminal for receiving a reference voltage, and a regulator output terminal, the voltage regulator circuit being configured to generate a regulation signal at the regulator output terminal based on a difference between a voltage at the first regulator input terminal and the reference voltage; a current sensing circuit system having at least one sensing terminal for coupling to at least one switch terminal of the DC-DC power converter, a sensing output terminal, and a current sensing circuit system coupled to the regulator. at least one sensing control terminal of an output terminal, the current sensing circuit system being configured to generate a pulse signal at the sensing output terminal having a duty cycle representing a percentage of time that the current through the at least one switch terminal is above a target value based on the regulation signal; and a current control loop circuit having a loop input terminal coupled to the sensing output terminal and one or more control output terminals for coupling to a power transistor, the current control loop circuit being configured to generate a control signal at the one or more control output terminals based on the pulse signal to control the power transistor so as to adjust the current through the at least one switch terminal to the target value.

[0095] Example 26 is a buck-boost DC-DC power converter comprising: an input terminal; an output terminal; a power conversion circuit system coupled to the input terminal and the output terminal and having a first and a second switch terminal for coupling to an inductor, the power conversion circuit system including a plurality of power transistors; a current control circuit coupled to the power conversion circuit system and configured to generate one or more control signals based on a regulation signal to control the plurality of power transistors to provide a regulated current; a regulator circuit coupled to the output terminal and to the power conversion circuit system, the regulator circuit having a regulator output terminal and configured to generate the regulation signal at the regulator output terminal representing an average inductor current flowing through the first and second switch terminals; and a current conversion circuit coupled to the regulator output terminal and to the current control circuit, the current conversion circuit being configured to adjust the regulation signal based on a limit signal representing a limit value of the regulated current.

[0096] Example 27 includes the buck-boost DC-DC power converter of Example 26, wherein the plurality of power transistors include: a first power transistor coupled between the input terminal and the first switch terminal and having a first control terminal coupled to the current control signal to receive a first control signal of the one or more control signals; a second power transistor coupled between the first switch terminal and a ground terminal and having a second control terminal coupled to the current control circuit to receive a second control signal of the one or more control signals; a third power transistor coupled between the output terminal and the second switch terminal and having a third control terminal coupled to the current control circuit to receive a third control signal of the one or more control signals; and a fourth power transistor coupled between the second switch terminal and the ground terminal and having a fourth control terminal coupled to the current control circuit to receive a fourth control signal of the one or more control signals.

[0097] Example 28 includes the buck-boost DC-DC power converter of Example 27, wherein the regulated current is an input current at the input terminal.

[0098] Example 29 includes the buck-boost DC-DC power converter of Example 28, wherein the current conversion circuit includes: a switching circuit having a control input terminal coupled to the current control circuit to receive the first control signal; a first transconductance amplifier having a first amplifier input terminal for receiving the limiting signal, a second amplifier input terminal coupled to the switching circuit, and a first amplifier output terminal; a second transconductance amplifier having a third amplifier input terminal coupled to the regulator output terminal, a fourth amplifier input terminal coupled to the first amplifier output terminal, and a second amplifier output terminal; and a transistor coupled between the regulator output terminal and the ground terminal and having a control terminal coupled to the second amplifier output terminal.

[0099] Example 30 includes the buck-boost DC-DC power converter of Example 29, wherein the current conversion circuit includes a limiting capacitor coupled between the second amplifier output terminal and the ground terminal.

[0100] Example 31 includes the buck-boost DC-DC power converter of Example 30, wherein the current conversion circuit includes: a first resistor-capacitor filter comprising a first resistor coupled in series with a first capacitor between the first amplifier output terminal and the ground terminal; and a second resistor-capacitor filter comprising a second resistor coupled between the switching circuit and the second amplifier input terminal and a second capacitor coupled between the second amplifier input terminal and the ground terminal.

[0101] Example 32 includes the buck-boost DC-DC power converter of Example 31, wherein the switching circuit includes a buffer coupled to the first amplifier output terminal, a first switching transistor coupled between the buffer and the second resistor and having a control terminal coupled to the control input terminal, and a second switching transistor coupled between the second resistor and the ground terminal and having a second control terminal coupled to the control input terminal.

[0102] Example 33 includes the buck-boost DC-DC power converter of Example 27, wherein the regulated current is an output current at the output terminal.

[0103] Example 34 includes the buck-boost DC-DC power converter of Example 33, wherein the current conversion circuit includes: a switching circuit having a control input terminal coupled to the current control circuit to receive the third control signal; a transconductance amplifier having a first amplifier input terminal for receiving the limiting signal, a second amplifier input terminal coupled to the switching circuit, and an amplifier output terminal; and a transistor coupled between the regulator output terminal and the ground terminal and having a control terminal coupled to the amplifier output terminal.

[0104] Example 35 includes the buck-boost DC-DC power converter of Example 34, wherein the current conversion circuit includes: a first resistor-capacitor filter comprising a first resistor coupled in series with a first capacitor between the amplifier output terminal and the ground terminal; and a second resistor-capacitor filter comprising a second resistor coupled between the switching circuit and the second amplifier input terminal and a second capacitor coupled between the second amplifier input terminal and the ground terminal.

[0105] Example 36 includes the buck-boost DC-DC power converter of Example 35, wherein the switching circuit includes a buffer coupled to the regulator output terminal, a first switching transistor coupled between the buffer and the second resistor and having a control terminal coupled to the control input terminal, and a second switching transistor coupled between the second resistor and the ground terminal and having a second control terminal coupled to the control input terminal.

[0106] Example 37 is a buck-boost DC-DC power converter comprising: an input terminal; an output terminal; a first and a second switch terminal for coupling to an inductor; a plurality of power transistors, including a first power transistor coupled between the input terminal and the first switch terminal; a voltage regulator circuit, including a first regulator input terminal coupled to the output terminal, a second regulator input terminal for receiving a reference voltage, and a regulator output terminal, the voltage regulator circuit being configured to provide a regulation signal at the regulator output terminal representing a target average inductor current flowing through the first and second switch terminals; a current control circuit configured to regulate an input current at the input terminal to maintain the input current below a limit, the current control circuit having a control output terminal, the control output terminal being coupled to a control terminal of the first power transistor and being configured to provide a first control signal at the control output terminal; and a current conversion circuit. The current conversion circuit includes: a switch circuit having a switch control terminal coupled to the control output terminal; a first transconductance amplifier having a first amplifier input terminal coupled to the switch circuit, a second amplifier input terminal for receiving a limit signal, and a first amplifier output terminal, wherein the limit signal represents the limit value for the input current at the input terminal; a second transconductance amplifier having a third amplifier input terminal coupled to the regulator output terminal, a fourth amplifier input terminal coupled to the first amplifier output terminal, and a second amplifier output terminal; and a transistor coupled between the regulator output terminal and a ground terminal and having a control terminal coupled to the second amplifier output terminal.

[0107] Example 38 is a buck-boost DC-DC power converter comprising: an input terminal; an output terminal; first and second switch terminals for coupling to an inductor; a plurality of power transistors, including a first power transistor coupled between the output terminal and the second switch terminal; a voltage regulator circuit, including a first regulator input terminal coupled to the output terminal, a second regulator input terminal for receiving a reference voltage, and a regulator output terminal, the voltage regulator circuit being configured to provide a regulation signal at the regulator output terminal representing a target average inductor current flowing through the first and second switch terminals; a current control circuit configured to regulate an output current at the output terminal to maintain the output current below a limit, the current control circuit having a control output terminal, the control output terminal being coupled to a control terminal of the first power transistor and being configured to provide a first control signal at the control output terminal; and a current conversion circuit. The current conversion circuit includes: a switch circuit having a switch control terminal coupled to the control output terminal; a transconductance amplifier having a first amplifier input terminal coupled to the switch circuit, a second amplifier input terminal for receiving a limit signal, and an amplifier output terminal, wherein the limit signal represents the limit value for the output current at the output terminal; and a transistor coupled between the regulator output terminal and a ground terminal and having a control terminal coupled to the amplifier output terminal.

[0108] Example 39 is a method for controlling a DC-DC power converter, the method comprising: generating an adjustment signal based on an adjusted parameter of the DC-DC power converter; generating a pulse signal having a duty cycle representing the percentage of time that an inductor current flowing at one or more switch terminals of the DC-DC converter is higher than a target value set by the adjustment signal; based on the pulse signal, generating one or more control signals; and controlling one or more power transistors of the DC-DC power converter by the control signal to drive the average value of the inductor current to the target value.

[0109] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0110] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof.

[0111] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0112] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0113] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively. For example, a p-channel field effect transistor (PFET) may be used instead of an n-channel field effect transistor (NFET) with little or no change to the circuit. In addition, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used. In addition, the device may be implemented in / above a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs). In addition, references to transistor features such as a gate, source, or drain are not intended to exclude any suitable transistor technology. For example, features such as a source, drain, and gate are commonly used to refer to a FET, while an emitter, collector, and base are commonly used to refer to a BJT. Such features may be used interchangeably herein. For example, a reference to the gate of a transistor may refer to the gate of a FET or the base of a BJT, and vice versa. In some examples, a control terminal may refer to the gate of a FET or the base of a BJT. Any other suitable transistor technology may be used. Any such transistor may be used as a switch, with the gate or base or other comparable feature acting as a switch select input which may be driven to connect the source and drain (or emitter and collector as the case may be).

[0114] Reference herein to a field effect transistor (FET) being "on" (or the switch being closed) means that there is a conductive channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" (or the switch being open) means that there is no conductive channel and drain current does not flow through the FET. However, an off FET may have current flowing through the body diode of the transistor.

[0115] The circuits described herein may be reconfigured to include additional or different components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0116] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "substantially" or "substantially" before a parameter means within + / -10% of the parameter.

[0117] Modifications are possible in the examples described, and other examples are possible within the scope of the claims.

Claims

1. A circuit comprising: a voltage regulator circuit having a regulator input terminal for coupling to an output terminal of a DC-DC power converter and a regulator output terminal, the voltage regulator circuit being configured to generate a regulation signal at the regulator output terminal based on a voltage at the regulator input terminal; a current sensing circuit system having at least one switch input terminal for coupling to at least one switch terminal of the DC-DC power converter, a sense input terminal, and a sense output terminal, the at least one switch input terminal being coupled to the regulator output terminal, the current sensing circuit system being configured to generate a pulse signal at the sense output terminal, wherein the pulse signal is based on a voltage at the at least one switch input terminal and an adjustable threshold value set by the regulation signal; as well as a current control loop circuit having a loop input terminal coupled to the sensing output terminal and one or more control output terminals for coupling to respective control terminals of corresponding one or more switching transistors of the DC-DC power converter, the current control loop circuit being configured to generate a switch control signal at the one or more control output terminals based on the pulse signal, wherein the switch control signal is a pulse width modulated signal to control the one or more switching transistors to drive an average value of a current flowing through the at least one switching terminal to a target average current value corresponding to the adjustable threshold value.

2. The circuit of claim 1, wherein the pulse signal has a duty cycle that represents a percentage of time that the current flowing through the at least one switch terminal is above the adjustable threshold.

3. The circuit of claim 1 , wherein the one or more switching transistors include a first switching transistor coupled to the at least one switch terminal and a second switching transistor coupled to the at least one switch terminal, and wherein the current sensing circuitry comprises: a first comparator circuit having a first comparator output terminal and configured to provide a first comparator signal at the first comparator output terminal, the first comparator signal having a first state in response to a first switch current flowing through the first switch transistor being greater than the adjustable threshold value, or having a second state in response to the first switch current being less than the adjustable threshold value; a second comparator circuit having a second comparator output terminal and configured to provide a second comparator signal at the second comparator output terminal, the second comparator signal having the first state in response to a second switch current flowing through the second switch transistor being greater than the adjustable threshold or having the second state in response to the second switch current being less than the adjustable threshold; as well as an OR gate having first and second OR gate input terminals and an OR gate output terminal, the first OR gate input terminal being coupled to the first comparator output terminal, the second OR gate input terminal being coupled to the second comparator output terminal, and the OR gate output terminal being coupled to the sense output terminal, the The OR gate is configured to provide the pulse signal.

4. The circuit of claim 3, wherein the at least one switch terminal comprises a first switch terminal and a second switch terminal, wherein: The first comparator circuit includes a first variable current source having a current value corresponding to the adjustable threshold and controlled by the regulating signal, a first sensing transistor for sensing the first switch current, and a first comparator having the first comparator output terminal, a first comparator input terminal coupled to the first sensing transistor and the first variable current source, and a second comparator input terminal coupled to the first switch terminal; and The second comparator circuit includes a second variable current source having a current value corresponding to the adjustable threshold and controlled by the regulating signal, a second sensing transistor for sensing the second switch current, and A second comparator has the second comparator output terminal, a third comparator input terminal coupled to the second sensing transistor and the second variable current source, and a fourth comparator input terminal coupled to the output terminal.

5. The circuit of claim 1 , wherein the current control loop circuit comprises: A charge pump circuit has the loop input terminal and a charge pump output terminal, the charge pump circuit being configured to generate a control voltage signal at the charge pump output terminal based on the pulse signal.

6. The circuit of claim 5, wherein the current control loop circuit comprises a current control circuit system coupled to the charge pump output terminal and configured to generate the switch control signal based on the control voltage signal and one or more reference signals.

7. The circuit of claim 6, wherein the current control circuitry comprises at least one hysteretic comparator circuit.

8. The circuit of claim 1 , wherein the voltage regulator circuit comprises: a transconductance amplifier having the regulator input terminal, an amplifier input terminal for receiving a reference voltage, and the regulator output terminal; as well as a resistor-capacitor filter coupled between the regulator output terminal and a ground terminal; Wherein the voltage regulator circuit is configured to generate the regulation signal based on a difference between the voltage at the regulator input terminal and the reference voltage.

9. A DC-DC power converter having an input terminal and an output terminal, and comprising: a power conversion circuit including a plurality of power transistors and having at least one switch terminal for coupling to at least one of the input terminal or the output terminal via an inductor, the plurality of power transistors being configured to generate a current through the at least one switch terminal based on a control signal received via a respective control terminal; a voltage regulator circuit having a regulator input coupled to the output terminal and a regulator output, the voltage regulator circuit being configured to generate a regulation signal at the regulator output based on a voltage at the output terminal; current sensing circuitry coupled to the power conversion circuitry and having a sense output and a sense input coupled to the regulator output, the current sensing circuitry configured to generate a pulse signal at the sense output having a duty cycle representative of a percentage of time that current flowing through the at least one switch terminal is above a target value; as well as a current control loop circuit having a control loop input and a plurality of control loop outputs, the control loop input being coupled to the sense output and each of the control loop outputs being coupled to a corresponding one of the control terminals, the current control loop circuit being configured to generate the control signal as a pulse width modulation signal based on the pulse signal to control the plurality of power transistors to adjust the current through the at least one switch terminal to the target value.

10. The DC-DC power converter according to claim 9, wherein the current control loop circuit comprises: A charge pump circuit has the control loop input and a charge pump output, the charge pump circuit being configured to generate a control voltage signal at the charge pump output based on the pulse signal.

11. The DC-DC power converter of claim 9, wherein the plurality of power transistors include a first power transistor and a second power transistor, and wherein the current sensing circuitry comprises: a first comparator circuit having a first comparator output and configured to provide a first comparator signal at the first comparator output, the first comparator signal having a first state in response to a first switch current flowing through the first power transistor being greater than the target value or having a second state in response to the first switch current being less than the target value; a second comparator circuit having a second comparator output and configured to provide a second comparator signal at the second comparator output, the second comparator signal having a first state in response to a second switch current flowing through the second power transistor being greater than the target value or having the second state in response to the second switch current being less than the target value; as well as an OR gate having first and second OR gate inputs and an OR gate output, wherein the first OR gate input is coupled to the first comparator output, the second OR gate input is coupled to the second comparator output, and the OR gate output is coupled to the sense output, the OR gate being configured to provide the pulse signal at the sense output based on an OR combination of the first comparator signal and the second comparator signal.

12. The DC-DC power converter of claim 11, wherein the DC-DC power converter is a buck-boost power converter, wherein the at least one switch terminal comprises a first switch terminal and a second switch terminal, wherein the first power transistor is coupled between the input terminal and the first switch terminal, and wherein the second power transistor is coupled between the output terminal and the second switch terminal.

13. The DC-DC power converter of claim 12, wherein the plurality of power transistors comprises: a third power transistor coupled between the first switch terminal and a ground terminal; as well as A fourth power transistor is coupled between the second switch terminal and the ground terminal.

14. The DC-DC power converter of claim 12, wherein: The first comparator circuit includes a first variable current source coupled between the input terminal and a ground terminal and having a current value corresponding to the target value and controlled by the adjustment signal, a first sensing transistor coupled between the input terminal and the first variable current source and having a control terminal coupled to the control terminal of the first power transistor, and A first comparator having the first comparator output, coupled to the first sensing transistor and the a first comparator input of a first variable current source, and a second comparator input coupled to the first switch terminal; and The second comparator circuit includes a second variable current source coupled between the second switch terminal and the ground terminal and having a current value corresponding to the target value and controlled by the adjustment signal, a second sense transistor coupled between the second switch terminal and the second variable current source and having a control terminal coupled to the control terminal of the second power transistor, and A second comparator has the second comparator output, a third comparator input coupled to the second sense transistor and the second variable current source, and a fourth comparator input coupled to the output terminal.

15. The DC-DC power converter of claim 12, wherein the control loop output comprises a first control output coupled to the control terminal of the first power transistor, and the control signal comprises a first control signal provided at the first control output, the DC-DC power converter comprising: A current conversion circuit is coupled to the regulator output and to the first control output, the current conversion circuit being configured to adjust the regulation signal based on a limit of an input current at the input terminal.

16. The DC-DC power converter of claim 14, wherein the control loop output comprises a first control output coupled to the control terminal of the second power transistor, and the control signal comprises a first control signal provided at the first control output, the DC-DC power converter comprising: A current conversion circuit is coupled to the regulator output and to the first control output, the current conversion circuit being configured to adjust the regulation signal based on a limit of an output current at the output terminal.

17. A buck-boost DC-DC converter, comprising: a first power transistor coupled between the input terminal and the first switch terminal; a second power transistor coupled between the output terminal and the second switch terminal; a voltage regulator having a first regulator input coupled to the output terminal, a second regulator input for receiving a reference voltage, and a regulator output; a first variable current source coupled between the input terminal and a ground terminal and having a first current control input coupled to the regulator output; a first sense transistor coupled between the input terminal and the first variable current source and having a control terminal coupled to a first control terminal of the first power transistor; a first comparator having first and second comparator inputs and a first comparator output, the first comparator input being coupled to the first switch terminal and the second comparator input being coupled to the first sense transistor and the first variable current source such that the first variable current source is coupled between the second comparator input and the ground terminal; a second variable current source coupled between the second switch terminal and the ground terminal and having a second current control input terminal coupled to the regulator output; a second sense transistor coupled between the second variable current source and the second switch terminal and having a control terminal coupled to a second control terminal of the second power transistor; a second comparator having a second comparator output, a third comparator input coupled to the output terminal, and a fourth comparator input coupled to the second sense transistor and the second variable current source such that the second variable current source is coupled between the fourth comparator input and the ground terminal; as well as a current control loop coupled to the first and second comparator outputs and to the first and second control terminals of the first and second power transistors, respectively, the current control loop being configured to generate first and second control signals at the first and second control terminals, respectively, based on signals at the first and second comparator outputs.

18. The buck-boost DC-DC converter of claim 17, wherein the current control loop comprises: an OR gate having a first gate input coupled to the first comparator output, a second gate input coupled to the second comparator output, and a gate output; a charge pump circuit having a charge pump input coupled to the gate output, and a charge pump output; as well as Control circuitry is coupled to the charge pump output and configured to generate the first and second control signals.

19. The buck-boost DC-DC converter of claim 17, further comprising: a third power transistor coupled between the first switch terminal and the ground terminal and having a third control terminal; as well as a fourth power transistor coupled between the second switch terminal and the ground terminal and having a fourth control terminal; Wherein the current control loop is coupled to the third and fourth control terminals and is configured to generate third and fourth control signals at the third and fourth control terminals, respectively, based on the signals at the first and second comparator outputs.

20. The buck-boost DC-DC converter of claim 17, wherein the voltage regulator is configured to generate a regulation signal at the regulator output based on a difference between the reference voltage and a voltage signal at the first regulator input, and wherein the regulation signal controls current values ​​of the first and second variable current sources.

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