Electrostatic discharge protection circuit

Abstract

The invention provides an ESD protection circuit which does not operate when a normal power supply is started and does not operate even when a power supply voltage changes during a normal operation. The RC circuit (110) is connected in series between the VDD and the GND. An RC circuit (120) is connected in series between the VDD and the GND, and a time constant different from that of the RC circuit is set. The inverter circuit (210) inputs a potential between the resistive element (111) and the capacitive element (112). The inverter circuit (220) inputs a potential between the resistive element (121) and the capacitive element (122). An NMOS transistor inputs the output of the inverter circuit to a gate terminal, and connects a drain terminal to a VDD. The NMOS transistor (320) inputs the output of the inverter circuit to the gate terminal, connects the drain terminal to the source terminal of the NMOS transistor (310), and connects the source terminal to GND.

Description

Technical Field

[0001] The present invention relates to an electrostatic discharge (ESD) protection circuit. Background Art

[0002] In order to protect the internal circuit from being destroyed by electrostatic discharge (ESD) noise, an ESD protection circuit is provided in the semiconductor integrated circuit. As the ESD protection circuit, a resistor-capacitor (RC) triggered power supply clamping method ESD protection circuit is often used (for example, refer to Patent Document 1).

[0003] This ESD protection circuit has the following circuit structure: when ESD noise (ESD surge noise) is generated, a clamping metal oxide semiconductor (MOS) transistor that clamps the power supply and ground for a period determined by the time constant of the RC series circuit is turned on, and the power supply and ground are set to a connected state, thereby protecting the internal circuit from damage by the ESD noise.

[0004] [Prior art literature]

[0005] [Patent Document]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2012-253241 Summary of the invention

[0007] [Problems to be solved by the invention]

[0008] Here, if the time constant of the RC series circuit is too large, the ESD protection circuit will also operate during normal operation. Therefore, in the ESD protection circuit as described above, the time constant of the RC series circuit is set to a value that is small to a certain extent to avoid the clamp MOS transistor from becoming conductive when the power supply is normally started. Moreover, the larger the time constant of the RC series circuit, the longer the time it takes for the clamp MOS transistor to become conductive. Therefore, if the time constant of the RC series circuit is too large, there is the possibility that the time it takes for the clamp MOS transistor to become conductive is too long, the clamp current flowing between the power supply and the ground is too large, and the circuit elements are damaged.

[0009] However, if the time constant of the RC series circuit is too small, when the power supply voltage fluctuates due to noise generated in the power supply during normal operation, the ESD protection circuit may operate and connect the power supply and the ground, causing an unnecessary large current to flow.

[0010] An object of the present invention is to provide an ESD protection circuit which does not operate during normal power startup and does not operate even when the power supply voltage fluctuates during normal operation.

[0011] [Technical means to solve the problem]

[0012] In order to solve the above-mentioned problem, the ESD protection circuit of the present invention includes: a first RC circuit connected in series between a power supply wiring and a ground wiring;

[0013] a first inverter circuit, which has as input a potential between a resistance element and a capacitance element constituting the first RC circuit and is connected between the power supply wiring and the ground wiring;

[0014] A second RC circuit is connected in series between the power wiring and the ground wiring and is set to a time constant different from that of the first RC circuit;

[0015] a second inverter circuit, which has as input a potential between the resistance element and the capacitance element constituting the second RC circuit and is connected between the power supply wiring and the ground wiring;

[0016] a first N-channel metal oxide semiconductor (NMOS) transistor, inputting the output of the first inverter circuit to a gate terminal and connecting a drain terminal to the power supply wiring; and

[0017] The second NMOS transistor has the output of the second inverter circuit input to a gate terminal, a drain terminal connected to the source terminal of the first NMOS transistor, and a source terminal connected to the ground wiring.

[0018] Furthermore, in the ESD protection circuit of the present invention, the second RC circuit may be set to have a time constant greater than that of the first RC circuit and of such a magnitude that the second RC circuit will not react to noise mixed into the power supply wiring.

[0019] Furthermore, in the ESD protection circuit of the present invention, the drain terminal of the first NMOS transistor and the drain terminal of the second NMOS transistor may be formed by removing the salicide film.

[0020] Furthermore, in order to solve the above-mentioned problem, another ESD protection circuit of the present invention includes: a first capacitor resistor (CR) circuit connected in series between a power wiring and a ground wiring;

[0021] a first inverter circuit, which has a potential between a capacitor and a resistor constituting the first CR circuit as an input and is connected between the power supply wiring and the ground wiring;

[0022] A second CR circuit is connected in series between the power supply wiring and the ground wiring and is set to a time constant different from that of the first CR circuit;

[0023] a second inverter circuit, which has as input a potential between a capacitor and a resistor constituting the second CR circuit and is connected between the power supply wiring and the ground wiring;

[0024] a first P-channel metal oxide semiconductor (PMOS) transistor, inputting the output of the first inverter circuit to a gate terminal and connecting a source terminal to the power supply wiring; and

[0025] The second PMOS transistor has the output of the second inverter circuit input to a gate terminal, a source terminal connected to the drain terminal of the first PMOS transistor, and a drain terminal connected to the ground wiring.

[0026] Furthermore, in the ESD protection circuit of the present invention, the second CR circuit may be set to have a time constant larger than that of the first CR circuit and of such a magnitude that the second CR circuit does not react to noise mixed into the ground wiring.

[0027] Furthermore, in the ESD protection circuit of the present invention, the source terminal of the first PMOS transistor and the source terminal of the second PMOS transistor may be formed by removing the salicide film.

[0028] [Effects of the Invention]

[0029] According to the present invention, it is possible to provide an ESD protection circuit which does not operate during normal power startup and does not operate even when the power supply voltage fluctuates during normal operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a diagram showing a circuit configuration of an ESD protection circuit as a comparative example.

[0031] Figure 2 Yes means Figure 1 FIG. 4 is a diagram of operation waveforms in the ESD protection circuit of the comparative example shown.

[0032] Figure 3 It is a diagram showing a circuit configuration of an ESD protection circuit according to a first embodiment of the present invention.

[0033] Figure 4 Yes means Figure 3 FIG. 2 is a diagram showing operation waveforms in the ESD protection circuit of the first embodiment.

[0034] Figure 5 It is a diagram showing a circuit configuration of an ESD protection circuit according to a second embodiment of the present invention.

[0035] [Explanation of Symbols]

[0036] 110, 120: RC circuit

[0037] 111, 121: Resistor

[0038] 112, 122: Capacitor element

[0039] 210, 220: Inverter circuit

[0040] 211, 221: PMOS transistor

[0041] 212, 222: NMOS transistor

[0042] 310, 320: NMOS transistors

[0043] 400: Internal circuit

[0044] 410, 420: RC circuit

[0045] 510, 520: PMOS transistors

[0046] 600: RC Circuit

[0047] 601: Resistor

[0048] 602: Capacitor element

[0049] 610: Inverter Circuit

[0050] 611: PMOS transistor

[0051] 612: NMOS transistor

[0052] 620: NMOS transistor DETAILED DESCRIPTION

[0053] Next, embodiments of the present invention will be described in detail with reference to the drawings.

[0054] First, before describing the ESD protection circuit of the present embodiment, a circuit configuration of a general RC trigger type inter-power supply clamping method ESD protection circuit will be described as a comparative example.

[0055] Figure 1It is a diagram showing a circuit configuration of the ESD protection circuit as the comparative example.

[0056] like Figure 1 As shown, the ESD protection circuit as a comparative example includes: an RC circuit 600, connected in series between a power wiring (VDD) and a ground wiring (GND); an inverter circuit 610, which uses the potential between a resistor element 601 and a capacitor element (capacitor element) 602 constituting the RC circuit 600 as input and is connected between VDD and GND; and an NMOS transistor 620.

[0057] The ESD protection circuit functions to protect the internal circuit 400 from ESD noise applied to the power supply terminal.

[0058] The RC circuit 600 connects a resistor 601 and a capacitor 602 in series between VDD and GND. The output of the inverter circuit 610 is input to the gate terminal of the NMOS transistor 620, and the drain terminal and the source terminal are connected to VDD and GND, respectively.

[0059] The inverter circuit 610 is a complementary metal oxide semiconductor (CMOS) type inverter circuit in which a PMOS transistor 611 and an NMOS transistor 612 are connected in series between VDD and GND.

[0060] Next, Figure 1 The operation waveform of the ESD protection circuit of the comparative example shown is shown in FIG. Figure 2 .

[0061] When ESD noise is applied to VDD from the outside, the potential of the node A as the input of the inverter circuit 610 is 0V in the initial state, so when the potential of VDD becomes higher than the threshold of the PMOS transistor 611, the PMOS transistor 611 becomes conductive, and the potential of VDD is applied to the gate terminal of the NMOS transistor 620. Therefore, the NMOS transistor 620 becomes conductive, electrically connects VDD-GND, and operates by clamping the ESD noise to avoid direct application of the ESD noise to the internal circuit 400. Thus, the internal circuit 400 is protected from ESD noise damage by the ESD protection circuit.

[0062] That is, when ESD noise is applied to VDD from the outside, Figure 2In the operation waveform shown, at time T1 when the potential of the node X exceeds the threshold of the NMOS transistor 620 , the NMOS transistor 620 turns on to clamp the voltage between VDD and GND so that the voltage does not exceed the withstand voltage of the internal circuit 400 .

[0063] Here, the potential at the node A, which is the input of the inverter circuit 610, starts later than VDD by a time constant R1×C1 minutes obtained by the resistance value R1 of the resistor 601 and the capacitance value C1 of the capacitor 602 in the RC circuit 600. Therefore, as time passes, the potential of the node A rises, and when the potential of the node A becomes higher than the logic threshold of the inverter circuit 610, the NMOS transistor 612 becomes on and the PMOS transistor 611 becomes off. As a result, the potential of the node X becomes L level (low level), and the NMOS transistor 620 becomes off.

[0064] Specifically, in Figure 2 In the operation waveform shown, at time T2 when the potential of the node A becomes equal to or higher than the logic threshold of the inverter circuit 610, the NMOS transistor 620 is turned off.

[0065] In the case of normal VDD activation, VDD activation is not so rapid, so the potential of the node A rises almost as fast as VDD, and the NMOS transistor 620 does not become conductive but transitions to a normal operation state.

[0066] However, in the ESD protection circuit of this structure, in the normal operation state where VDD is a certain voltage, when some noise is mixed into VDD, there is a possibility that the NMOS transistor 620 becomes conductive for a moment. Specifically, when the noise waveform mixed into VDD is larger than the time constant R1×C1 determined by the resistance value R1 of the resistor element 601 and the capacitance value C1 of the capacitor element 602, the RC circuit 600 reacts. As a result, Figure 2 As shown, the potential of the node A becomes lower than the logic threshold of the inverter circuit 610 at time T3, and the potential of the node X, which is the output of the inverter circuit 610, becomes H level (high level). Therefore, the NMOS transistor 620 becomes conductive, and an unnecessary large current flows between the power supply (VDD) and the ground (GND), which increases the power consumption of the semiconductor integrated circuit, or causes the circuit elements to be destroyed due to the large current.

[0067] If the time constant R1×C1 in the RC circuit 600 is increased, this problem in the normal operation state can be solved. However, if the time constant R1×C1 of the RC circuit 600 is set too large, there is a problem that the ESD protection circuit also operates in the normal operation, or when ESD noise is generated, the NMOS transistor 620 is turned on for too long, and the clamp current flowing between the power supply and the ground is too large, and the circuit element may be damaged.

[0068] Therefore, in the first embodiment of the present invention, by adopting the circuit configuration described below, an ESD protection circuit is realized which does not operate during normal power startup and does not operate even when the power supply voltage fluctuates during normal operation.

[0069] [First embodiment]

[0070] Next, the ESD protection circuit according to the first embodiment of the present invention will be described. Figure 3 .

[0071] like Figure 3 As shown, the ESD protection circuit in this embodiment includes an RC circuit 110 , an RC circuit 120 , an inverter circuit 210 , an inverter circuit 220 , and two NMOS transistors 310 , 320 .

[0072] In the RC circuit 110 , a resistor 111 and a capacitor 112 are connected in series between VDD, which is a power supply wiring, and GND, which is a ground wiring.

[0073] The RC circuit 120 has a resistor 121 and a capacitor 122 connected in series between VDD and GND. The time constant R2×C2 in the RC circuit 120 is set to a value different from the time constant R1×C1 in the RC circuit 110. In the present embodiment, the time constant R2×C2 in the RC circuit 120 is set to a value greater than the time constant R1×C1 in the RC circuit 110 and to a value that does not react to noise mixed into VDD. In addition, the time constant R1×C1 in the RC circuit 110 is set to a value different from the time constant R1×C1 in the RC circuit 110. Figure 1 The time constant of the RC circuit 600 in the ESD protection circuit of the comparative example shown has the same value.

[0074] The inverter circuit 210 is a CMOS type inverter circuit in which a PMOS transistor 211 and an NMOS transistor 212 are connected in series between VDD and GND, with the potential between the resistor 111 and the capacitor 112 constituting the RC circuit 110 being input.

[0075] The inverter circuit 220 is a CMOS type inverter circuit in which a PMOS transistor 221 and an NMOS transistor 222 are connected in series between VDD and GND, with the potential between the resistor 121 and the capacitor 122 constituting the RC circuit 120 being input.

[0076] The NMOS transistor 310 and the NMOS transistor 320 are connected in series between VDD and GND. Specifically, the NMOS transistor 310 inputs the output of the inverter circuit 210 to the gate terminal, and connects the drain terminal to VDD. In addition, the NMOS transistor 320 inputs the output of the inverter circuit 220 to the gate terminal, connects the drain terminal to the source terminal of the NMOS transistor 310, and connects the source terminal to GND.

[0077] In the ESD protection circuit of this embodiment, two NMOS transistors 310 and 320 are connected in series between VDD and GND, so that VDD and GND are connected only when the two NMOS transistors 310 and 320 are turned on at the same time.

[0078] Next, Figure 3 The operation waveform of the ESD protection circuit of this embodiment shown in FIG. Figure 4 .

[0079] When a voltage that starts up suddenly, such as ESD noise, is applied to VDD from the outside, the voltages of nodes B and C start up gradually relative to the start-up of VDD due to the presence of RC circuits 110 and RC120. Furthermore, the time constant R2×C2 of RC circuit 120 becomes greater than the time constant R1×C1 of RC circuit 110, so the potential of node C starts up more gradually relative to the potential of node B.

[0080] Furthermore, the potential of the node Y1, which is the output of the inverter circuit 210, continues to rise along with the potential rise of VDD until the potential of the node B becomes equal to or higher than the logic threshold of the inverter circuit 210. Furthermore, the potential of the node Y2, which is the output of the inverter circuit 220, continues to rise along with the potential rise of VDD until the potential of the node C becomes equal to or higher than the logic threshold of the inverter circuit 220.

[0081] Therefore, at time T4 when the potential of the node Y1 becomes equal to or higher than the threshold of the NMOS transistor 310 and the potential of the node Y2 becomes equal to or higher than the threshold of the NMOS transistor 320 , both the NMOS transistors 310 and 320 are turned on.

[0082] As a result, the ESD protection circuit in this embodiment operates as follows: VDD-GND is connected, and the potential difference between VDD and GND is reduced by flowing current from VDD to GND, thereby clamping the ESD noise and avoiding direct application of the ESD noise to the internal circuit 400. Thus, the internal circuit 400 is protected from damage by the ESD noise by the ESD protection circuit.

[0083] In addition, as time passes, the potential of the node B rises, and at time T5, when the potential of the node B becomes equal to or higher than the logic threshold of the inverter circuit 210, the NMOS transistor 212 becomes on and the PMOS transistor 211 becomes off. As a result, the potential of the node Y1 becomes L level and the NMOS transistor 310 becomes off.

[0084] As time passes, the potential of the node C rises, and at time T6, when the potential of the node C becomes equal to or higher than the logic threshold of the inverter circuit 220, the NMOS transistor 222 becomes on and the PMOS transistor 221 becomes off. As a result, the potential of the node Y2 becomes L level and the NMOS transistor 320 becomes off.

[0085] Then, VDD-GND is clamped during the period from time T4 to time T5 when both the NMOS transistor 310 and the NMOS transistor 320 are in the on state.

[0086] Here, if Figure 1 The time constant R1×C1 of the RC circuit 600 in the ESD protection circuit of the comparative example shown in FIG. 1 is the same as the time constant R1×C1 of the RC circuit 110 in the ESD protection circuit of the present embodiment. Figure 2 The period from time T1 to time T2 in Figure 4 The time period from time T4 to time T5 in the embodiment becomes the same length. It can be seen that the ESD protection circuit of this embodiment also achieves protection against Figure 1 The ESD protection circuit of the comparative example shown has an equivalent ESD noise protection function.

[0087] Next, the operation when noise is mixed into VDD in the normal operation state where a normal voltage is applied to VDD will be described.

[0088] like Figure 4As shown in FIG. 1 , when noise is mixed into VDD in the normal operation state, when the noise waveform mixed is larger than the time constant R1×C1 determined by the resistance value R1 of the resistor 111 and the capacitance value C1 of the capacitor 112, the RC circuit 110 reacts. As a result, the potential of the node B becomes lower than the logic threshold of the inverter circuit 210 at time T7, and the potential of the node Y1 as the output of the inverter circuit 210 rises from the GND level to the H level. Therefore, the NMOS transistor 310 becomes conductive.

[0089] However, since the time constant R2×C2 of the RC circuit 120 is set to a value greater than the time constant R1×C1 of the RC circuit 110, when noise of the same magnitude is mixed into VDD, it is difficult for the RC circuit 102 to react to the voltage change of VDD. Figure 4 As shown in the operation waveform, when the potential of the node B becomes lower than the logic threshold of the inverter circuit 210 at time T7, the potential of the node C does not become lower than the logic threshold of the inverter circuit 220. Therefore, the potential of the node Y2 is maintained at the L level, and the NMOS transistor 320 remains in the off state.

[0090] Through the above-described operation, when noise is mixed into VDD, although NMOS transistor 310 is turned on, NMOS transistor 320 is kept off. In addition, in the ESD protection circuit of this embodiment, the circuit structure is as follows, that is, if both NMOS transistors 310 and 320 are not turned on, VDD-GND will not be connected. Therefore, when noise that does not react to RC circuit 120 is mixed into VDD, VDD-GND will not be connected, and normal operation can be maintained without being affected by noise.

[0091] As described above, according to the ESD protection circuit of the present embodiment, the circuit structure is such that two RC circuits 110 and 120 having different time constants are connected in parallel between VDD and GND, and the potentials of the RC circuits 110 and 120 (the potentials of the nodes B and C) are applied to the gate terminals of the NMOS transistors 310 and 320 via the inverter circuits 210 and 220. Furthermore, by connecting the NMOS transistors 310 and 320 in series between VDD and GND, the circuit structure is such that the ESD protection function is activated only when the two NMOS transistors 310 and 320 are turned on at the same time.

[0092] As a result, when ESD noise is applied to VDD, the two NMOS transistors 310 and 320 are turned on at the same time, and current flows between the power supply (VDD) and the ground (GND), thereby reducing the potential difference between VDD and GND. That is, the so-called ESD protection function is performed in the same way as the ESD protection circuit of the comparative example.

[0093] On the other hand, when noise is mixed into VDD and VDD fluctuates during normal operation, the RC circuit 120 having a larger time constant operates without responding to the VDD fluctuation, and thus the NMOS transistor 320 connected to the RC circuit 120 also remains in the off state.

[0094] That is, according to the ESD protection circuit of this embodiment, when VDD changes due to the mixing of noise, it is also possible to prevent problems such as unnecessary large current flowing between the power supply (VDD) and the ground (GND) and increasing the power consumption of the semiconductor integrated circuit, or circuit elements being damaged due to the flow of large current.

[0095] [Second embodiment]

[0096] Next, an ESD protection circuit according to a second embodiment of the present invention will be described. Figure 5 In addition, Figure 5 In, with Figure 3 The same structures as shown are denoted by the same reference numerals and the description thereof will be omitted.

[0097] like Figure 5 As shown, the ESD protection circuit in this embodiment includes a CR circuit 410 , a CR circuit 420 , an inverter circuit 210 , an inverter circuit 220 , and two PMOS transistors 510 , 520 .

[0098] In the CR circuit 410 , a capacitor 112 and a resistor 111 are connected in series between VDD, which is a power supply wiring, and GND, which is a ground wiring.

[0099] The CR circuit 420 has a capacitor 122 and a resistor 121 connected in series between VDD and GND. The time constant R2×C2 in the CR circuit 420 is set to a value different from the time constant R1×C1 in the CR circuit 410. In the present embodiment, the time constant R2×C2 in the CR circuit 420 is set to a value greater than the time constant R1×C1 in the CR circuit 410 and to a value that does not react to noise mixed into GND. In addition, the time constant R1×C1 in the RC circuit 110 is set to be equal to the time constant R1×C1 in the CR circuit 410. Figure 1The time constant of the RC circuit 600 in the ESD protection circuit of the comparative example shown in FIG. Figure 3 The time constant of the RC circuit 110 in the ESD protection circuit of the first embodiment shown has the same value.

[0100] The inverter circuit 210 is a CMOS type inverter circuit in which a PMOS transistor 211 and an NMOS transistor 212 are connected in series between VDD and GND, with the potential between the capacitor 112 and the resistor 111 constituting the CR circuit 410 being input.

[0101] The inverter circuit 220 is a CMOS type inverter circuit in which a PMOS transistor 221 and an NMOS transistor 222 are connected in series between VDD and GND, with the potential between the capacitor 122 and the resistor 121 constituting the CR circuit 420 being input.

[0102] The PMOS transistor 510 and the PMOS transistor 520 are connected in series between VDD and GND. Specifically, the PMOS transistor 310 inputs the output of the inverter circuit 210 to the gate terminal, and connects the source terminal to VDD. In addition, the PMOS transistor 520 inputs the output of the inverter circuit 220 to the gate terminal, connects the source terminal to the drain terminal of the PMOS transistor 510, and connects the drain terminal to GND.

[0103] Furthermore, in the ESD protection circuit of this embodiment, the two PMOS transistors 510 and 520 are connected in series between VDD and GND, so that VDD and GND are connected only when the two PMOS transistors 510 and 520 are turned on at the same time.

[0104] Relative to Figure 3 The ESD protection circuit in the first embodiment shown in the figure becomes a circuit structure in which the RC circuit 110 and the RC circuit 210 are replaced by the CR circuit 410 and the CR circuit 420 respectively, and the NMOS transistor 310 and the NMOS transistor 320 are replaced by the PMOS transistor 510 and the PMOS transistor 520 respectively.

[0105] In the ESD protection circuit of this embodiment, the operation when ESD noise is applied to VDD is performed only by logical AND. Figure 3 The ESD protection circuit in the first embodiment shown operates in the opposite manner.

[0106] Furthermore, in the ESD protection circuit of the present embodiment, when some noise is mixed into GND, in the CR circuit 410, since the time constant C1×R1 is small, there is a possibility that the potential of the node D will react to the noise mixed into GND and become higher than the logic threshold of the inverter circuit 210. However, since the time constant C2×R2 of the CR circuit 420 is set to a large value, the potential of the node E can be prevented from becoming higher than the logic threshold of the inverter circuit 220.

[0107] Therefore, even when the potential of the node Z1 as the output of the inverter circuit 210 decreases due to noise mixed into GND and the PMOS transistor 510 is turned on, the potential of the node Z2 as the output of the inverter circuit 220 is maintained at the H level. Therefore, the PMOS transistor 520 remains in the off state, and the connection between VDD and GND due to noise mixed into GND can be prevented.

[0108] [other]

[0109] Furthermore, the NMOS transistors 310 and 320 in the first embodiment and the PMOS transistors 510 and 520 in the second embodiment operate to protect the internal circuit 400 from ESD noise by allowing the ESD noise to flow in the form of on-state current.

[0110] Here, the drain terminals of the NMOS transistors 310 and 320 in the first embodiment and the source terminals of the PMOS transistors 510 and 520 in the second embodiment may also have a low resistance film called a silicide film as a normal MOS structure. However, in order to further improve ESD resistance, the drain terminals of the NMOS transistors 310 and 320 may be formed by removing the silicide film. Similarly, the source terminals of the PMOS transistors 510 and 520 may be formed by removing the silicide film.

[0111] As described above, by using a device having a structure in which the salicide film is removed and operating a parasitic NPN transistor or a parasitic PNP transistor of a MOS transistor, the ESD protection function can be further improved.

Claims

1. An electrostatic discharge protection circuit, comprising: A first resistor and capacitor circuit is connected in series between the power wiring and the ground wiring; a first inverter circuit, which has as input a potential between a resistor and a capacitor constituting the first resistor-capacitor circuit and is connected between the power supply wiring and the ground wiring; A second resistor and capacitor circuit is connected in series between the power supply wiring and the ground wiring and is set to have a time constant different from that of the first resistor and capacitor circuit; a second inverter circuit, which has as input a potential between a resistor and a capacitor constituting the second resistor-capacitor circuit, and is connected between the power supply wiring and the ground wiring; a first N-channel metal oxide semiconductor transistor, inputting the output of the first inverter circuit to a gate terminal and connecting a drain terminal to the power supply wiring; and The second N-channel MOS transistor has the output of the second inverter circuit input to a gate terminal, a drain terminal connected to the source terminal of the first N-channel MOS transistor, and a source terminal connected to the ground wiring.

2. The electrostatic discharge protection circuit according to claim 1, wherein the second resistor-capacitor circuit is set to have a time constant greater than that of the first resistor-capacitor circuit and of a size that does not react to noise mixed into the power supply wiring.

3. The electrostatic discharge protection circuit according to claim 1, wherein the drain terminal of the first N-channel metal oxide semiconductor transistor and the drain terminal of the second N-channel metal oxide semiconductor transistor are both formed by removing a salicide film. 4 . The electrostatic discharge protection circuit according to claim 1 , wherein the second resistor-capacitor circuit is connected in parallel between the first resistor-capacitor circuit and the first inverter circuit. 5 . The electrostatic discharge protection circuit according to claim 1 , wherein the first inverter circuit is connected in parallel between the second resistor-capacitor circuit and the second inverter circuit.

6. The electrostatic discharge protection circuit according to claim 1, wherein the first inverter circuit includes a first P-channel metal oxide semiconductor connected to the power wiring and a third N-channel metal oxide semiconductor connected to the ground wiring, The second inverter circuit includes a second P-channel metal oxide semiconductor connected to the power wiring and a fourth N-channel metal oxide semiconductor connected to the ground wiring.

7. An electrostatic discharge protection circuit, comprising: A first capacitor-resistor circuit is connected in series between the power wiring and the ground wiring; a first inverter circuit, which has as input a potential between a capacitor and a resistor constituting the first capacitor-resistance circuit and is connected between the power supply wiring and the ground wiring; A second capacitor-resistance circuit is connected in series between the power supply wiring and the ground wiring and is set to have a time constant different from that of the first capacitor-resistance circuit; a second inverter circuit, which has as input a potential between a capacitor and a resistor constituting the second capacitor-resistance circuit and is connected between the power supply wiring and the ground wiring; a first P-channel metal oxide semiconductor transistor, inputting the output of the first inverter circuit to a gate terminal and connecting a source terminal to the power supply wiring; and The second P-channel MOS transistor has the output of the second inverter circuit input to a gate terminal, a source terminal connected to the drain terminal of the first P-channel MOS transistor, and a drain terminal connected to the ground wiring.

8. The electrostatic discharge protection circuit according to claim 7, wherein the second capacitor-resistance circuit is set to have a time constant greater than that of the first capacitor-resistance circuit and of a size that does not react to noise mixed into the ground wiring. 9 . The electrostatic discharge protection circuit according to claim 7 , wherein a source terminal of the first P-channel metal oxide semiconductor transistor and a source terminal of the second P-channel metal oxide semiconductor transistor are both formed by removing a salicide film. 10 . The electrostatic discharge protection circuit according to claim 7 , wherein the second capacitor-resistor circuit is connected in parallel between the first capacitor-resistor circuit and the first inverter circuit.

11. The electrostatic discharge protection circuit according to claim 7, wherein the first inverter circuit is connected in parallel between the second capacitor-resistor circuit and the second inverter circuit.

12. The electrostatic discharge protection circuit according to claim 7, wherein the first inverter circuit includes a third P-channel metal oxide semiconductor connected to the power wiring and a first N-channel metal oxide semiconductor connected to the ground wiring, The second inverter circuit includes a fourth P-channel metal oxide semiconductor connected to the power wiring and a second N-channel metal oxide semiconductor connected to the ground wiring.

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