Oscillator

Abstract

The invention provides an oscillator. The oscillator comprises a plurality of oscillation sub-modules; the plurality of oscillation sub-modules are divided into at least two columns, the output end of the previous oscillation sub-module of the at least two columns of oscillation sub-modules is connected with the input end of the next oscillation sub-module to form an annular circuit, and the length difference value of the connecting lines of the adjacent mutually connected oscillation sub-modules is within a preset length range. Thus, it can be guaranteed that the similarity of the circuit conditions of all the oscillation sub-modules in the oscillator is high, the phase deviation of signals output by the oscillator is small, and then the signal output precision of the oscillator is improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to an oscillator. Background Art

[0002] The oscillator is used to generate the required signal. The internal arrangement and routing of the current oscillator are irregular, which may cause a large phase deviation of the output signal.

[0003] With the development of circuits, the performance requirements for oscillators are getting higher and higher. The current oscillators can no longer meet the needs of circuit development. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide an oscillator to solve or partially solve the above technical problems.

[0005] Based on the above purpose, the present application provides an oscillator, including: a plurality of oscillator modules;

[0006] The multiple oscillator submodules are divided into at least two columns, and the output end of the upper oscillator submodule of the at least two columns of oscillator submodules is connected to the input end of the next oscillator submodule to form a ring circuit, and the length difference of the connecting lines of each interconnected adjacent oscillator submodule is within a predetermined length range.

[0007] From the above, it can be seen that if the multiple oscillator modules in the oscillator have only one column, it is impossible to meet the standard that the length difference of the connecting wires of adjacent oscillator modules in the ring circuit of the oscillator is within the predetermined length range. Therefore, the oscillator of the present application divides the multiple oscillator modules therein into at least two columns, so that the output end of the previous oscillator module can be connected to the input end of the next oscillator module according to the standard that the length difference of the connecting wires of adjacent oscillator modules is within the predetermined length range, and the ring circuit formed ensures that the circuit conditions of each oscillator module are highly similar, so that the phase deviation of the signal output by the oscillator is small, thereby improving the signal output accuracy of the oscillator. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 is a circuit diagram of an oscillator in the related art;

[0010] Figure 2A first row layout of an oscillator in the related art;

[0011] Figure 3 A second row layout of an oscillator in the related art;

[0012] Figure 4 Schematic diagram of an oscillator of four oscillator sub-circuits (C0 to C3) according to an embodiment of the present application;

[0013] Figure 5 A schematic diagram of an oscillator in which eight oscillator sub-circuits (C0 to C7) are arranged in a serpentine pattern with cross-wiring according to an embodiment of the present application;

[0014] Figure 6 A schematic diagram of an oscillator in which eight oscillator sub-circuits (C0 to C7) are arranged in a serpentine manner in differential pairs according to an embodiment of the present application;

[0015] Figure 7 Another schematic diagram of an oscillator in which eight oscillator sub-circuits (C0 to C7) are arranged in a serpentine manner in differential pairs according to an embodiment of the present application;

[0016] Figure 8 A schematic diagram of an oscillator in which 16 oscillator sub-circuits (C0 to C15) are arranged in a serpentine manner in differential pairs according to an embodiment of the present application;

[0017] Fig. 9 Schematic diagram showing connection lines at output ends of two oscillator sub-circuits (C0 and C4) corresponding to a set of differential signals (CLK0 and CLK4) according to an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0019] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0020] In the related art, a ring circuit is formed by connecting a plurality of oscillator modules (each oscillator module includes an input terminal IN, an output terminal OUT and a signal output terminal CLK).

[0021] For example, technical solution 1:

[0022] The eight oscillator modules C0 to C7 form a ring circuit, such as Figure 1 As shown, Figure 1 CLK0~CLK7 in the figure are the 8-phase clock signals output by the 8 oscillator modules. In the actual layout, the 8 oscillator modules C0 to C7 can be arranged as follows: Figure 2 The stacked arrangement shown in the figure. CLK0 and CLK4, CLK1 and CLK5, CLK2 and CLK6, CLK3 and CLK7 are four pairs of differential clocks. This layout prioritizes the placement of differential clocks together and the alignment of the 8-phase clocks. After the output clock position is determined, the placement order of the oscillator modules is determined, and the alignment from the output of the previous oscillator module to the input of the next oscillator module is basically determined.

[0023] Disadvantages of technical solution 1:

[0024] Disadvantage 1: Each output line of C0~C7 is consistent, and the differential clocks are placed together, but the distance from the previous oscillator module OUT to the next oscillator module IN is different. The longest line C7 to C0 is at least 5 oscillator modules higher than the shortest line, which makes it difficult to make the interconnection lines between the oscillator modules consistent, and the output clock signal phase mismatch will be large.

[0025] Disadvantage 2: If the routing between oscillator modules directly crosses the oscillator module, the routing environment will be inconsistent and additional clock signal phase mismatch will be introduced. If the routing is placed outside the oscillator module, the horizontal routing will be elongated due to the presence of multiple lines, resulting in increased parasitic capacitance and parasitic resistance of the routing and a decrease in the oscillation frequency.

[0026] For example, technical solution 2:

[0027] The ring circuit formed by the eight oscillator modules C0 to C7 is arranged according to the signal flow of the schematic diagram. The layout is as follows: Figure 3 As shown, the eight oscillator modules are arranged in sequence from top to bottom as CLK0-CLK1-CLK2-CLK3-CLK4-CLK5-CLK6-CLK7.

[0028] Disadvantages of Technical Solution 2:

[0029] The output wiring is not placed according to the differential, and the anti-interference ability is poor. In order to ensure the output of the differential clock signal, the output end of the previous oscillator module is placed together according to the differential clock, and the input end of the next oscillator module is generally placed together according to the differential clock, so it is necessary to connect them in a cross-wiring manner, which will lead to inconsistent lengths and easy differential clock signal phase mismatch. In addition, the wiring from the OUT end of C7 to the IN end of C0 is the longest, which is equal to the height of 7 oscillator modules, while the wiring between other oscillator modules is consistent, which is equal to the height of one oscillator module, and the final clock phase mismatch will be large.

[0030] Based on the above description, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] The oscillator proposed in the embodiment of the present application is as follows: Figures 4 to 7 As shown ( Figures 4 to 7 It is only a representative example of the embodiment of the present application), comprising: a plurality of oscillator modules;

[0032] The multiple oscillator submodules are divided into at least two columns, and the output end of the upper oscillator submodule of the at least two columns of oscillator submodules is connected to the input end of the next oscillator submodule to form a ring circuit, and the length difference of the connecting lines of each interconnected adjacent oscillator submodule is within a predetermined length range.

[0033] In specific implementation, the oscillator module includes: an inverter and / or a NOT gate. The total number of oscillator modules is 2 n , where n ≥ 2. For example, 4, 8, 16, 32, 64, 128, etc.

[0034] The plurality of oscillator modules are sorted, so that the plurality of oscillator modules are divided into at least two columns (for example, two columns or four columns) according to the sorting. The specific number of columns can be determined according to the total number of oscillator modules. The output end (OUT) of the previous oscillator module is connected to the input end (IN) of the next oscillator module according to the sorting, so that the plurality of oscillator modules can form a ring circuit, so that the oscillator forms a ring oscillator. And the length difference of the connecting wires of adjacent oscillator modules needs to be within a predetermined length range, so that the ring circuit can ensure the consistency of the connecting wires.

[0035] The predetermined length range may be a length range determined based on actual experience (e.g., -x 1 to x 2 , where x 1 and x 2 can be the same or different).

[0036] In addition, when determining the length difference of the connecting line, the length difference can be taken as an absolute value, so that the corresponding predetermined length range can be a set positive range interval (for example, 0 to x 1 ).

[0037] As a preferred embodiment, the predetermined length range is preferably 0, that is, all connecting lines have the same length.

[0038] The method for ensuring that the length difference of the connecting lines of adjacent oscillator submodules is within the predetermined length range is to arrange the oscillator submodules in a sorted order, and when arranging, the distance difference between the spacing distances of two adjacent oscillator submodules in each group is kept within a predetermined distance error range (for example, -y 1 To 2 , where y 1 and 2 can be the same or different).

[0039] Through the above scheme, multiple oscillator modules in the oscillator are divided into at least two columns, so that the output end of the previous oscillator module can be connected to the input end of the next oscillator module according to the standard that the length difference of the connecting lines of adjacent oscillator modules is within a predetermined length range, and the ring circuit formed ensures that the circuit conditions of each oscillator module are highly similar, so that the phase deviation of the signal output by the oscillator is small, thereby improving the signal output accuracy of the oscillator.

[0040] In some embodiments, the plurality of oscillator modules are sorted and divided into odd columns and even columns according to the sorting, and the oscillator modules in the odd columns and the even columns are connected according to the output end of the previous oscillator module and the input end of the next oscillator module (i.e., serpentine connection) to form a ring circuit.

[0041] In specific implementation, this embodiment preferably divides a plurality of oscillator modules into two columns, and in order to ensure that the oscillator modules in the two columns are evenly distributed, they are divided into odd columns and even columns according to the sorting sequence. Among them, the arrangement of each layer (one row in two columns is one layer) of the odd columns and the even columns only needs to satisfy that a ring circuit can be formed according to the sorting connection, and the length difference of the connection line of adjacent oscillator modules is within a predetermined length range, and there is no limitation on the specific order of the number of layers.

[0042] Through the above scheme, multiple oscillator modules are divided into odd columns and even columns according to the order, so that when the two columns are connected, the distance between the adjacent oscillator modules connected to each other can be relatively close, and the connecting lines can be close, thereby further ensuring that the phase of the output signal of the oscillator keeps the deviation small and reduces the phase mismatch.

[0043] In some embodiments, the connecting lines of adjacent oscillator modules connected to each other have an inclination angle of a predetermined angle relative to the outer side surface of the oscillator module.

[0044] In a specific implementation, the predetermined angle is an angle value set so as to ensure that the point-to-point connection line is short and conforms to the physical design rules of general electronic power technology.

[0045] Through the above solution, it can be ensured that the connection line between two adjacent oscillator submodules is an inclined line, so that the connection can be made with a shorter connection line length, so that the parasitic resistance and parasitic capacitance of the connection line are smaller, and the consistency of the length between the connection lines can be effectively guaranteed.

[0046] In some embodiments, the connection lines connecting adjacent oscillator sub-modules to each other include: an inclined line and / or a folded line.

[0047] During specific implementation, the distance between each group of adjacent oscillator submodules is determined, and the adjacent oscillator submodules with the farthest distance are connected by an inclined line; the adjacent oscillator submodules with a smaller distance relative to the farthest distance are connected by a broken line, and the length difference between the broken line and the inclined line is within a predetermined length range; preferably, the length of the broken line is equal to that of the inclined line.

[0048] The fold line is based on the standard that the connecting lines can cross but not overlap, and the corresponding inflection point and the corresponding bending angle of the fold line are determined according to the arrangement requirements of the specific oscillator sub-circuit.

[0049] The bending angle is an angle value set so as to satisfy the requirement that the length difference between the fold line and the inclined line is within a predetermined length range and conforms to the physical rules of a common electronic circuit process.

[0050] Through the above solution, it is possible to ensure that the connection lines between the oscillator sub-modules in the oscillator do not overlap, and at the same time, it is possible to ensure that the lengths of the connection lines of adjacent oscillator sub-modules are uniform and arranged in a more aesthetically pleasing wiring manner.

[0051] As a preferred embodiment, the connecting wires are selected to be of the same type.

[0052] In some embodiments, for the odd columns and the even columns: a serpentine arrangement is performed according to a crossover routing, or a serpentine arrangement is performed according to a differential pairing method.

[0053] In specific implementation, the corresponding cross wiring is arranged in a serpentine pattern as follows:

[0054] According to the sequence numbers corresponding to the sorting marks, the oscillator modules are arranged in the corresponding odd-numbered columns and even-numbered columns to determine the positions of the oscillator modules with the starting sequence numbers;

[0055] Determine the position of the oscillator module with the starting number as the top, and arrange them in a serpentine shape from top to bottom according to the number, and then arrange them in a serpentine shape from bottom to top according to the number; or,

[0056] Determine the position of the oscillator module with the starting number as the bottom, and arrange them in a serpentine shape from bottom to top according to the number, and then arrange them in a serpentine shape from top to bottom according to the number;

[0057] Determine that the position of the oscillator module with the starting serial number is in the middle, and arrange them in a serpentine shape from top to bottom according to the serial number, then arrange them in a serpentine shape from bottom to top according to the serial number, and then arrange them from top to bottom to the position of the oscillator module with the starting serial number; or, arrange them in a serpentine shape from bottom to top according to the serial number, then arrange them in a serpentine shape from top to bottom according to the serial number, and then arrange them from bottom to top to the corresponding position of the oscillator module with the starting serial number.

[0058] For example, Figure 4 As shown, for an oscillator composed of four oscillator submodules: the even-numbered columns are C0→C2, and the odd-numbered columns are C3→C1.

[0059] Figure 5 As shown, for an oscillator composed of 8 oscillator sub-modules: the even-numbered columns are C0→C6→C2→C4, and the odd-numbered columns are C7→C1→C5→C3.

[0060] In specific implementation, the corresponding differential pairs are arranged in a serpentine manner: first, the differential pairs are determined according to the sorting sequence of the oscillator modules, and each differential pair is placed together in the same column (the same odd column or the same even column), and arranged in a serpentine manner into odd columns and even columns.

[0061] For example, Figure 6 As shown, for an oscillator composed of 8 oscillator sub-modules: the even-numbered columns are C0→C4→C6→C2, and the odd-numbered columns are C7→C3→C1→C5.

[0062] Figure 7 As shown, for an oscillator composed of 8 oscillator sub-modules: the even-numbered columns are C2→C6→C0→C4, and the odd-numbered columns are C1→C5→C3→C7.

[0063] Figure 8 As shown, for an oscillator composed of 16 oscillator sub-modules: the even-numbered columns are C0→C8→C14→C6→C2→C10→C12→C4, and the odd-numbered columns are C15→C7→C1→C9→C13→C5→C3→C11.

[0064] Above Figures 4 to 8 The arrangement of the corresponding oscillators is not a unique arrangement. The corresponding odd-numbered columns and even-numbered columns can be arranged in a serpentine arrangement in the above-mentioned cross-routing or differential pairing manner.

[0065] Through the above scheme, it can be ensured that when the corresponding signal output requirements are met, the distance between the two oscillator modules with adjacent serial numbers between the odd columns and the even columns that need to be connected can be minimized, the value of the parasitic capacitance or parasitic resistance can be minimized, and the influence of the parasitic capacitance or parasitic resistance on the signal output can be avoided.

[0066] In some embodiments, each of the oscillator modules outputs at least one phase signal, wherein the signal may include: a discrete signal or a continuous signal; a digital signal or an analog signal, wherein the digital signal may include a clock signal.

[0067] Through the above solution, it can be ensured that the oscillator can output the corresponding required signal and improve the signal output accuracy.

[0068] In some embodiments, for every two oscillator sub-modules capable of outputting differential signals in the plurality of oscillator sub-modules, the following conditions are satisfied:

[0069] The difference between the total parasitic capacitance values ​​of the traces corresponding to the two oscillator submodules (for example, the first oscillator submodule and the second oscillator submodule) (that is, the difference between the total parasitic capacitance value of the first oscillator submodule and the total parasitic capacitance value of the second oscillator submodule) is within a predetermined capacitance error range; and / or,

[0070] The difference between the total parasitic resistance values ​​of the traces corresponding to the two oscillator modules (for example, the first oscillator module and the second oscillator module) (that is, the difference between the total parasitic resistance value of the first oscillator module and the total parasitic resistance value of the second oscillator module) is within a predetermined resistance error range.

[0071] In specific implementation, the differential signal is a signal with opposite phases and a phase difference of 180°. The output line of the differential signal (such as a differential clock signal) is arranged in a manner that the output line is perpendicular to the outer side where the output port is located, and the output ends of the oscillator modules corresponding to the differential signal are connected, so that the anti-interference is stronger and the phase mismatch introduced by the surrounding environment is smaller.

[0072] For example, in an oscillator composed of 8 oscillator modules, differential C0 and C4, C1 and C5, C2 and C6, C3 and C7 are placed together in pairs, such as Figure 6 and Figure 7 As shown; in the oscillator composed of 16 oscillator modules, C0 and C8, C1 and C9, C2 and C10, C3 and C11, C4 and C12, C5 and C13, C6 and C14, C7 and C15 are placed together in pairs, as shown in FIG. Figure 8 shown.

[0073] As a preferred embodiment, the differential signal includes: a differential clock signal.

[0074] Among them, differential clock signals have obvious advantages over single-ended clock signal transmission: 1. Common-mode noise suppression: Since the differential receiver is only sensitive to the difference between the two line signals, it can suppress the same noise on the two lines, that is, common-mode noise, which improves the signal's anti-interference ability and reduces clock mismatch. 2. Improve signal integrity: Differential signals can better maintain signal integrity and stability, reduce the impact of reflection and crosstalk, which is especially important for high-speed signals. 3. Lower electromagnetic radiation: Since the currents on the two lines are in opposite directions, the magnetic fields they generate will also cancel each other out, thereby reducing electromagnetic interference to the outside world.

[0075] In specific implementation, in order to ensure the phase effect of the differential signal, the difference between the total parasitic capacitance values ​​of the two oscillator modules of a pair of differential signals should be within a predetermined capacitance error range, so that the total parasitic capacitance values ​​of the two oscillator modules remain consistent. The predetermined capacitance error range can be set according to actual needs.

[0076] And / or, the difference between the total parasitic resistance values ​​of the two oscillator modules of a pair of differential signals should be within a predetermined resistance error range, so that the total parasitic resistance values ​​of the two oscillator modules remain consistent. The predetermined resistance error range can be set according to actual needs.

[0077] Through the above solution, it can be ensured that the generated differential signal has an accurate differential phase effect.

[0078] In some embodiments, the two oscillator modules capable of outputting differential signals are determined to be: a first oscillator module and a second oscillator module.

[0079] The total parasitic capacitance of the wiring of the first oscillator module is the cumulative sum of the parasitic capacitance of the connection line from the first oscillator module to the ground and the parasitic capacitance of the connection line from the first oscillator module to the second oscillator module.

[0080] And / or, the total parasitic capacitance of the wiring of the second oscillator module is the cumulative sum of the parasitic capacitance of the connection line from the second oscillator module to ground and the parasitic capacitance of the connection line from the second oscillator module to the first oscillator module.

[0081] During specific implementation, each oscillator module has a corresponding input terminal (IN), an output terminal (OUT) and a ground (VSS).

[0082] As shown in Figures 6 and 7, the output end (OUT) of the oscillator module is connected to the output port of the signal from the middle output line of the oscillator module, and shielding ground (i.e., grounding) is added on both sides of the differential clock signal (for example, CLK0 and CLK4) to reduce the interference of adjacent non-differential clock signals.

[0083] like Fig. 9 , no matter how the oscillator module is mirrored, the connection line of the first oscillator module (such as Fig. 9 The connection line marked CLK0 in FIG. 1 is connected to the ground (VSS) by a distance S1, and the connection line of the second oscillator module (such as Fig. 9 The distance S1 from the connection line marked CLK4 in the figure to the ground (VSS) is consistent. The connection line of the first oscillator module and the connection line of the second oscillator module are two layers of metal of the same or similar type.

[0084] According to the parasitic capacitance calculation formula C = ε0*S / d. Among them, ε0 is the dielectric constant of vacuum, S is the area directly opposite to the two connecting lines, and d is the distance between the two connecting lines. Since the type, spacing and length of the connecting lines of the first oscillator module and the second oscillator module are the same, the values ​​of ε0, S and d are consistent. The total parasitic capacitance of the connecting line of the first oscillator module is the sum of the parasitic capacitance value of the connecting line from the first oscillator module to the ground (for example, Cg) and the parasitic capacitance value of the connecting line from the first oscillator module to the second oscillator module (for example, CC).

[0085] like Fig. 9 As shown, the total parasitic capacitance of the traces corresponding to the CLK0 connection line and the CLK4 connection line is Ctotal = Cg + CC. Among them, Cg of the CLK0 connection line refers to the parasitic capacitance from the CLK0 connection line to the ground (VSS). CC of the CLK0 connection line refers to the parasitic capacitance between the CLK0 connection line and the CLK4 connection line. The total parasitic capacitance Ctotal of the CLK0 connection line is the sum of the two values ​​of Cg and CC. Similarly, Cg of the CLK4 connection line refers to the parasitic capacitance from the CLK4 connection line to the ground (VSS). CC of the CLK4 connection line refers to the parasitic capacitance between the CLK0 connection line and the CLK4 connection line.

[0086] Through the above solution, the total parasitic capacitance of the wiring corresponding to the first oscillator module and the second oscillator module can be accurately calculated.

[0087] In some embodiments, two oscillator modules capable of outputting differential signals are determined to be: a first oscillator module and a second oscillator module (for example, C0 and C4), wherein the first oscillator module is connected to a first signal terminal (for example, CLK0), and the second oscillator module is connected to a second signal terminal (for example, CLK4), wherein the first signal and the second signal are differential signals.

[0088] The total parasitic resistance value of the wiring of the first oscillator module is the parasitic resistance value between the output end (OUT) of the first oscillator module and the first signal end.

[0089] and / or,

[0090] The total parasitic resistance value of the wiring of the second oscillator module is the parasitic resistance value between the output end and the second signal end of the second oscillator module.

[0091] Through the above scheme, the total parasitic resistance value of the routing of the two oscillator modules of each group outputting differential signals can be accurately determined, and then it can be accurately determined whether the parasitic resistance values ​​between the output ends and the signal ends of the two oscillator modules tend to be consistent, making the phase of the differential signal more accurate.

[0092] In some embodiments, the two oscillator modules capable of outputting differential signals are determined to be: a first oscillator module and a second oscillator module, wherein the output end of the first oscillator module is connected to the output end of the first oscillator module through a first through hole (eg, Fig. 9 The output end of the second oscillator module is connected to the first signal end through the second through hole (for example, Fig. 9 The through hole 2) is connected to the second signal terminal;

[0093] The total parasitic resistance value R of the wiring of the first oscillator module is the parasitic resistance value from the output end of the first oscillator module to the first through hole (for example, Fig. 9 R0 in ), and the parasitic resistance value of the first through hole (for example, Fig. 9 R1 in ), and the parasitic resistance value from the first through hole to the first signal terminal (for example, Fig. 9 The cumulative sum of R0+R1+R2) in (for example, R=R0+R1+R2).

[0094] And / or, the total parasitic resistance value R' of the wiring of the second oscillator module is the parasitic resistance value from the output end of the second oscillator module to the second through hole (for example, Fig. 9 R0' in ), and the parasitic resistance value of the second through hole (for example, Fig. 9 R1' in ), and the parasitic resistance value from the second through hole to the second signal terminal (for example, Fig. 9 The cumulative sum of R2' in (for example, R'=R0'+R1'+R2').

[0095] Through the above solution, all situations that may generate parasitic resistance are statistically accumulated, so that the calculated total parasitic resistance value of the wiring of the two oscillator modules of each group of output differential signals is more comprehensive and accurate.

[0096] To sum up, the multiple oscillator sub-modules in the oscillator of the embodiment of the present application can be arranged according to the rules described in the above embodiment. The specific number and position of the arrangement are not limited to the examples in the accompanying drawings, and can be any arrangement form that conforms to the rules described in the above embodiment, and no specific limitation is made here.

[0097] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0098] A person skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0099] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0100] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0101] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the present application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the present application.

Claims

1. An oscillator, characterized in that: include: Multiple oscillator modules; The multiple oscillator submodules are divided into at least two columns, and the output end of the upper oscillator submodule of the at least two columns of oscillator submodules is connected to the input end of the next oscillator submodule to form a ring circuit, and the length difference of the connecting lines of each interconnected adjacent oscillator submodule is within a predetermined length range.

2. The oscillator according to claim 1, characterized in that The plurality of oscillator modules are sorted and divided into odd columns and even columns according to the sorting, and the oscillator modules in the odd columns and the even columns are connected according to the output end of the previous oscillator module and the input end of the next oscillator module to form a ring circuit.

3. The oscillator according to claim 2, characterized in that The connecting lines of the mutually connected adjacent oscillator modules have an inclination angle of a predetermined angle relative to the outer side surface of the oscillator module.

4. The oscillator according to claim 3, characterized in that The connection lines of mutually connected adjacent oscillator submodules include: inclined lines and / or folded lines.

5. The oscillator according to any one of claims 2 to 4, characterized in that: For the odd-numbered columns and the even-numbered columns: a serpentine arrangement is performed according to a crossover routing, or a serpentine arrangement is performed according to a differential pairing method.

6. The oscillator according to any one of claims 1 to 5, characterized in that: Each of the oscillator modules correspondingly outputs at least one phase signal.

7. The oscillator according to claim 6, characterized in that For each two oscillator modules capable of outputting differential signals among the multiple oscillator modules, the following conditions are satisfied: The difference between the total parasitic capacitance values ​​of the wirings corresponding to the two oscillator modules is within a predetermined capacitance error range; and / or, The difference between the total parasitic resistance values ​​of the wirings corresponding to the two oscillator modules is within a predetermined resistance error range.

8. The oscillator according to claim 7, characterized in that Determine that two oscillator modules capable of outputting differential signals are: a first oscillator module and a second oscillator module; The total parasitic capacitance of the wiring of the first oscillator module is the cumulative sum of the parasitic capacitance of the connection line from the first oscillator module to the ground and the parasitic capacitance of the connection line from the first oscillator module to the second oscillator module; and / or, The total parasitic capacitance of the wiring of the second oscillator module is the cumulative sum of the parasitic capacitance of the connection line from the second oscillator module to the ground and the parasitic capacitance of the connection line from the second oscillator module to the first oscillator module.

9. The oscillator according to claim 7 or 8, characterized in that Determine that two oscillator modules capable of outputting differential signals are: a first oscillator module and a second oscillator module, wherein the first oscillator module is connected to the first signal terminal, and the second oscillator module is connected to the second signal terminal, wherein the first signal and the second signal are differential signals; The total parasitic resistance value of the wiring of the first oscillator module is the parasitic resistance value between the output end and the first signal end of the first oscillator module; and / or, The total parasitic resistance value of the wiring of the second oscillator module is the parasitic resistance value between the output end and the second signal end of the second oscillator module.

10. The oscillator according to any one of claims 7 to 9, characterized in that: Determine that two oscillator modules capable of outputting differential signals are: a first oscillator module and a second oscillator module, wherein an output end of the first oscillator module is connected to a first signal end through a first through hole, and an output end of the second oscillator module is connected to a second signal end through a second through hole; The total parasitic resistance of the wiring of the first oscillator module is the cumulative sum of the parasitic resistance from the output end of the first oscillator module to the first through hole, the parasitic resistance of the first through hole, and the parasitic resistance from the first through hole to the first signal end; and / or, The total parasitic resistance of the wiring of the second oscillator module is the cumulative sum of the parasitic resistance from the output end of the second oscillator module to the second through hole, the parasitic resistance of the second through hole, and the parasitic resistance from the second through hole to the second signal end.

Images