A quad common-mode loop full-differential amplifier and method of application

Abstract

The application relates to the technical field of differential amplifiers, and discloses a four-stage common-mode loop full-differential amplifier and an application method. The four-stage common-mode loop full-differential amplifier comprises: a two-stage full-differential main amplifier which receives a differential mode signal, amplifies the differential mode signal in two stages, and outputs a differential signal; a common-mode level sensing unit which is used for capturing a common-mode level output by the two-stage full-differential main amplifier; and a two-stage common-mode feedback amplifier which simultaneously receives the common-mode level and a common-mode reference signal, is used for amplifying an error signal between the common-mode level and the common-mode reference signal, and outputs the amplified error signal to the gate of a current source load possessed by an input stage of the two-stage full-differential main amplifier. The four-stage common-mode loop provided by the application significantly improves the value of CMRR, simultaneously realizes good isolation of the common-mode feedback loop and the differential loop, and the gain of the main amplifier is not constrained.

Description

Technical Field

[0001] This invention relates to the field of differential amplifier technology, and more particularly to a four-stage common-mode loop fully differential amplifier and its application method. Background Technology

[0002] Common-mode negative feedback (CMFB) is a classic and widely used technique in fully differential amplifier design. In high-gain amplifiers, the output common-mode level is highly sensitive to changes in input voltage, device characteristics, and mismatches, and cannot be stabilized by differential feedback alone. Therefore, a common-mode feedback (CMFB) network must be added to stabilize the circuit's common-mode level and quiescent operating point. This prevents devices from deviating from their saturation state and losing their signal amplification function. Essentially, CMFB is a negative feedback network that stabilizes the output DC voltage by detecting the common-mode levels at both output terminals and adjusting the amplifier's bias current accordingly. This capability is measured by the common-mode rejection ratio (CMRR). A higher CMRR indicates stronger suppression of common-mode interference, a more stable output DC operating point, and better amplifier performance.

[0003] Currently, most common CMFB (Common Mode Rejection Ratio) technology structures use an output common mode level sensing circuit to track the output common mode level, compare it with a reference level, and feed the comparison result back to a bias current of the amplifier to stabilize the amplifier's DC operating point and improve the common mode rejection ratio.

[0004] The above process involves comparing the common-mode level and the reference level, which can be achieved using a feedback amplifier. Currently, feedback amplifier designs mostly employ single-stage amplifiers, and there is a mutual constraint between CMRR and main amplifier gain. This is because the feedback amplifier and main amplifier form a closed loop in the common-mode signal path. To achieve high gain and high CMRR, both the main amplifier and feedback amplifier theoretically need to employ multi-stage structures (generally two stages). However, multi-stage structures would cause the common-mode loop to form a ring oscillator, leading to oscillation and instability. Therefore, current technologies mostly employ single-stage main amplifiers or single-stage feedback amplifiers, or other complex structures. The former creates a trade-off between CMRR and amplifier gain, limiting the simultaneous improvement of these two metrics; the latter is difficult to promote and design. Summary of the Invention

[0005] The purpose of this invention is to provide a four-stage common-mode loop fully differential amplifier and its application method, aiming to solve the constraint relationship between common-mode rejection ratio and gain. The fully differential amplifier adopts an architecture of two-stage main amplifier and two-stage feedback amplifier, and simultaneously applies frequency compensation to ensure output stability. The four-stage common-mode loop provided by this invention significantly improves the CMRR value, while achieving good isolation between the common-mode feedback loop and the differential loop, and the gain of the main amplifier is not constrained.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a four-stage common-mode loop fully differential amplifier, comprising:

[0008] A two-stage fully differential main amplifier receives differential signals and amplifies the differential signals in two stages before outputting differential signals;

[0009] A common-mode level sensing unit is used to capture the common-mode level of the output of the two-stage fully differential main amplifier.

[0010] It also includes a two-stage common-mode feedback amplifier that simultaneously receives the common-mode level and the common-mode reference signal. This amplifier amplifies the error signal between the common-mode level and the common-mode reference signal and outputs the amplified error signal to the gate of the current source load of the input stage of the two-stage fully differential main amplifier.

[0011] As one possible implementation, the two-stage common-mode feedback amplifier includes a first bias circuit, a first-stage common-mode error amplifier circuit, a coupling circuit, a second-stage common-mode error amplifier circuit, and a first frequency compensation circuit. The first bias circuit provides bias voltages to both the first-stage and second-stage common-mode error amplifier circuits. The first-stage common-mode error amplifier circuit receives and pre-amplifies the error signal. The pre-amplified error signal is coupled to the second-stage common-mode error amplifier circuit via the coupling circuit, and then amplified and output by the second-stage common-mode error amplifier circuit. The first frequency compensation circuit is connected across the input and output terminals of the second-stage common-mode error amplifier circuit to perform frequency compensation on the two-stage common-mode feedback amplifier.

[0012] As one possible implementation, the first-stage common-mode error amplifier circuit adopts an input rail-to-rail structure; the second-stage common-mode error amplifier circuit adopts an output Class AB rail-to-rail structure.

[0013] As one possible implementation, the first frequency compensation circuit is a Miller frequency compensation circuit with a zero-adjustment resistor, which is composed of a resistor and an NMOS transistor connected in series. One end of the resistor is connected to the output terminal of the first-stage common-mode error amplifier circuit, and the other end of the resistor is connected to the gate of the NMOS transistor. The source, drain, and substrate of the NMOS transistor are connected to the input terminal of the second-stage common-mode error amplifier circuit.

[0014] As one possible implementation, the two-stage fully differential main amplifier includes a second bias circuit, a first-stage main amplifier circuit, a second-stage main amplifier circuit, a second frequency compensation circuit, and a third frequency compensation circuit. The second bias circuit provides bias voltages to both the first and second-stage main amplifier circuits. The input transistor of the first-stage main amplifier circuit receives the differential-mode signal, and the gate of the current source load in the input stage of the first-stage main amplifier circuit receives the error signal. The differential-mode signal is pre-amplified and then input to the second-stage main amplifier circuit. The second-stage main amplifier circuit amplifies the pre-amplified differential-mode signal a second time and outputs a differential signal. The second frequency compensation circuit consists of two paths, each connected between the input and output terminals of the second-stage main amplifier circuit. The third frequency compensation circuit is connected between the output terminal of the second-stage common-mode error amplifier circuit and the output terminal of the first-stage main amplifier circuit.

[0015] As one possible implementation, both the first bias circuit and the second bias circuit are full MOSFET low-voltage bandgap reference circuits, outputting 1uA and 200uA temperature-independent current output ports.

[0016] As one possible implementation, the first-stage main amplifier circuit consists of NMOS transistor (0), NMOS transistor (1), PMOS transistor (1), and PMOS transistor (2); wherein the gates of NMOS transistor (0) and NMOS transistor (1) are connected, the drains of NMOS transistor (1) and PMOS transistor (1) are connected, the sources of PMOS transistor (1) and PMOS transistor (2) are connected, and the drains of PMOS transistor (2) and NMOS transistor (0) are connected; the second-stage main amplifier circuit consists of two identical circuits, one of which... It is composed of an NMOS transistor (3) and a PMOS transistor (3); wherein the drains of the NMOS transistor (3) and the PMOS transistor (3) are connected, the source of the NMOS transistor (3) is grounded, and the gate of the NMOS transistor (3) is connected to the output of the first-stage main amplifier circuit; another circuit is composed of an NMOS transistor (4) and a PMOS transistor (4); wherein the drains of the NMOS transistor (4) and the PMOS transistor (4) are connected, the source of the NMOS transistor (4) is grounded, and the gate of the NMOS transistor (4) is connected to the output of the first-stage main amplifier circuit.

[0017] As one possible implementation, the second frequency compensation circuit is composed of a series resistor and a capacitor. That is, capacitor C(1) and resistor R(2) constitute one second frequency compensation circuit, and capacitor C(0) and resistor R(3) constitute another second frequency compensation circuit.

[0018] As one possible implementation, the third frequency compensation circuit consists of capacitor C(14), NMOS(4), NMOS(9), and capacitor C(14) connected in series.

[0019] Secondly, the present invention also provides an application method for a four-stage common-mode loop fully differential amplifier, wherein the first-stage main amplifier circuit receives the differential-mode signal under the control of the second bias circuit and pre-amplifies the differential-mode signal;

[0020] The second-stage main amplifier circuit receives the pre-amplified differential signal under the control of the second bias circuit, amplifies it a second time, and then uses the second frequency compensation circuit to perform a frequency compensation on the amplified differential signal before outputting the differential signal.

[0021] The common-mode level sensing unit receives the initial common-mode signal, averages it, and outputs the common-mode level.

[0022] The first-stage common-mode error amplifier circuit, under the control of the first bias circuit, simultaneously receives the common-mode level and the common-mode reference signal, and pre-amplifies the error signal;

[0023] The coupling circuit receives the pre-amplified error signal and couples it to the second common-mode error amplifier circuit.

[0024] The second common-mode error amplifier circuit amplifies the error signal a second time, and the first frequency compensation circuit performs frequency compensation on the two-stage common-mode feedback amplifier before outputting the error signal. The amplified error signal is then input to the gate of the current source load of the input stage of the first-stage main amplifier circuit, and undergoes a third frequency compensation before being input.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] 1. In traditional solutions, since the common-mode loop typically has no more than three stages, either the main amplifier or the feedback amplifier must be a single-stage structure. The main amplifier determines the gain, and the feedback amplifier determines the CMRR (Common Mode Reduction). Therefore, there is a mutual constraint between gain and CMRR. This invention successfully achieves four-stage loop stability, so both the main amplifier and the auxiliary amplifier are implemented in two stages. This means that compared to existing technologies, it is possible to simultaneously achieve higher CMRR and higher main amplifier gain.

[0027] 2. The four-stage common-mode loop fully differential amplifier provided by this invention combines a two-stage common-mode feedback amplifier and a two-stage fully differential main amplifier, and employs three-stage Miller compensation to stabilize the four-stage common-mode loop, thereby achieving an ultra-high common-mode rejection ratio of 198.75dB. Simultaneously, because the output of the common-mode feedback amplifier acts on the input stage of the main amplifier, the output power can remain unchanged regardless of changes in the output common-mode level.

[0028] 3. The four-stage common-mode loop fully differential amplifier provided by the present invention also includes a common-mode level sensing unit, which is used to block the differential-mode path (two-stage fully differential main amplifier) ​​and the common-mode loop (two-stage common-mode feedback amplifier), while reducing the influence of the common-mode loop on the differential loop. Attached Figure Description

[0029] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0030] Figure 1 This is a schematic diagram of the structure of a four-stage common-mode loop fully differential amplifier provided in an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the structure of a two-stage common-mode feedback amplifier circuit provided in an embodiment of the present invention;

[0032] Figure 3 The figure shows the simulation results of the common-mode rejection ratio of the four-stage common-mode loop fully differential amplifier provided in the embodiment of the present invention.

[0033] Figure 4 Simulation results of common-mode rejection ratio (CMRR) of a four-stage common-mode loop fully differential amplifier for three process angles (tt, ss, ff) provided in an embodiment of the present invention;

[0034] Figure 5 The simulation waveform diagram of the stb loop stability of the four-stage common-mode fully differential amplifier provided in the embodiment of the present invention;

[0035] Figure 6 A summary diagram of the stb loop stability simulation of the four-stage common-mode fully differential amplifier provided in this embodiment of the invention.

[0036] Figure Labels

[0037] A0 - First bias circuit, A1 - First stage common-mode error amplifier circuit, A2 - Coupling circuit, A3 - Second stage common-mode error amplifier circuit, A4 - First frequency compensation circuit;

[0038] B-Common-mode level sensing unit;

[0039] D0 - Second bias circuit, D1 - First stage main amplifier circuit, D2 - Second stage main amplifier circuit, D3 - Second frequency compensation circuit, D4 - Third frequency compensation circuit. Detailed Implementation

[0040] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0041] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0042] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one" or similar expressions refer to any combination of these items, including any combination of singular or plural items. For example, "at least one of a, b, or c" can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0043] This invention provides a four-stage common-mode loop fully differential amplifier with ultra-high common-mode rejection ratio (CMRR), further improving the CMRR of traditional fully differential amplifiers while ensuring the stability of the four-stage common-mode loop. Specifically, a low-power two-stage rail-to-rail amplifier is designed as the feedback amplifier in the common-mode negative feedback. Furthermore, to stabilize the four-stage common-mode loop, Miller capacitor compensation technology with zero-adjustment resistors is employed between the two stages of the fully differential amplifier, between the two stages of the feedback amplifier, and between the feedback output of the feedback amplifier and the output of the first stage of the fully differential amplifier, thus achieving stability of the common-mode loop.

[0044] In traditional two-stage fully differential amplifiers with common-mode negative feedback, feedback amplifiers are needed to improve the common-mode rejection ratio (CMRR), determine the output common-mode level, and reduce active load malfunctions caused by mismatch. This structure is simple in principle and easy to implement, but the gain of a single-stage feedback amplifier is limited, failing to guarantee sufficiently high DC common-mode rejection and stable output common-mode level, leading to output common-mode level deviation, manifested as a lower DC common-mode rejection ratio (CMRR). While multi-stage feedback amplifiers can effectively improve the loop CMRR and output common-mode level stability, multi-stage common-mode loops may cause common-mode loop oscillations. This invention provides a fully differential amplifier with ultra-high CMRR. Addressing the four-stage common-mode loop generated during the design process, it proposes a frequency compensation technique suitable for stabilizing the four-stage common-mode loop. By using two-stage feedback amplifiers and two-stage fully differential amplifiers, the stability of the multi-stage common-mode loop is significantly improved, while simultaneously providing high DC common-mode rejection capability, thus significantly improving the amplifier's CMRR. Furthermore, the output of the feedback amplifier is fed back to the first stage of the two-stage fully differential amplifier, while the output stage is biased separately by the current mirror. Therefore, the output power does not change with the output common-mode level and remains constant.

[0045] See Figure 1 and Figure 2 This invention provides a four-stage common-mode loop fully differential amplifier, comprising: two stages of fully differential main amplifiers for receiving differential-mode signals and amplifying the differential-mode signals in two stages to output differential signals; a common-mode level sensing unit B for capturing the common-mode level output by the two stages of fully differential main amplifiers; and two stages of common-mode feedback amplifiers for simultaneously receiving the common-mode level and a common-mode reference signal, amplifying the error signal between the common-mode level and the common-mode reference signal, and outputting the amplified error signal to the gate of the current source load of the input stage of the two stages of fully differential main amplifiers.

[0046] Existing technologies typically offer common-mode loops with no more than three stages. Therefore, either the main amplifier or the feedback amplifier must be a single-stage structure. The main amplifier determines the gain, and the feedback amplifier determines the common-mode rejection ratio (CMRR), resulting in a mutual constraint between gain and CMRR. The four-stage common-mode loop fully differential amplifier provided by this invention is the first to combine two stages of common-mode feedback amplifiers and two stages of fully differential main amplifiers. Compared to existing technologies, it can simultaneously achieve higher CMRR and main amplifier gain, specifically achieving an ultra-high common-mode rejection ratio of 198.75 dB. Furthermore, because the common-mode feedback output acts on the main amplifier input stage, the output power remains unchanged regardless of the output common-mode level.

[0047] The two-stage common-mode feedback amplifier provided by this invention includes a first bias circuit A0, a first-stage common-mode error amplifier circuit A1, a coupling circuit A2, a second-stage common-mode error amplifier circuit A3, and a first frequency compensation circuit A4. Specifically, the first bias circuit A0 provides bias voltages to the first-stage common-mode error amplifier circuit A1 and the second-stage common-mode error amplifier circuit A3; the first-stage common-mode error amplifier circuit A1 receives the error signal and pre-amplifies it; the pre-amplified error signal is coupled to the second-stage common-mode error amplifier circuit A3 via the coupling circuit A2, and then amplified and output by the second-stage common-mode error amplifier circuit A3; the first frequency compensation circuit A4 is connected across the input and output terminals of the second-stage common-mode error amplifier circuit A3, and is used to perform frequency compensation on the two-stage common-mode feedback amplifier.

[0048] The first-stage common-mode error amplifier circuit A1 adopts an input rail-to-rail structure, which can receive all possible common-mode levels from 0 to VDD and pre-amplify the differential signal input. The second-stage common-mode error amplifier circuit A3 adopts an output Class AB rail-to-rail structure, which further amplifies the output of the input rail-to-rail structure and provides an output voltage range from 0 to VDD.

[0049] The first frequency compensation circuit A4 consists of two paths, each a Miller frequency compensation circuit including a zero-adjustment resistor. One path comprises a resistor R4 and an NMOS transistor 10 connected in series. One end of resistor R4 is connected to the output of the first-stage common-mode error amplifier circuit A1, and the other end is connected to the gate of the NMOS transistor 10. The source, drain, and substrate of the NMOS transistor 10 are then connected to the input of the second-stage common-mode error amplifier circuit A3. The other path consists of a resistor R5 and an NMOS transistor 11 connected in series. The NMOS transistors 10 and 11 replace capacitors, which helps improve compensation accuracy.

[0050] The two-stage common-mode feedback amplifier used in this invention can achieve common-mode negative feedback, determine the output common-mode level, and also improve the common-mode rejection ratio of the amplifier.

[0051] The two-stage fully differential main amplifier includes a second bias circuit D0, a first-stage main amplifier circuit D1, a second-stage main amplifier circuit D2, a second frequency compensation circuit D3, and a third frequency compensation circuit D4. The second bias circuit D0 provides bias voltages to both the first-stage and second-stage main amplifier circuits D1 and D2. The input transistor of the first-stage main amplifier circuit D1 receives the differential-mode signal, and the gate of the current source load in the input stage of D1 receives the error signal. This differential-mode signal is pre-amplified and then input to the second-stage main amplifier circuit D2. The second-stage main amplifier circuit D2 amplifies the pre-amplified differential-mode signal a second time and outputs a differential signal. The second frequency compensation circuit D3 has two paths, each connected between the input and output of the second-stage main amplifier circuit D2. The third frequency compensation circuit D4 is connected between the output of the second-stage common-mode error amplifier circuit A3 and the output of the first-stage main amplifier circuit D1. This invention employs a three-stage Miller compensation to stabilize a four-stage common-mode loop, which not only achieves an ultra-high common-mode rejection ratio but also prevents common-mode loop oscillations to ensure the stability of the common-mode feedback.

[0052] The first bias circuit A0 and the second bias circuit D0 are both full MOSFET low-voltage bandgap reference circuits, with output ports for 1uA and 200uA temperature-independent current.

[0053] The first-stage main amplifier circuit D1 consists of NMOS transistor 0, NMOS transistor 1, PMOS transistor 1, and PMOS transistor 2. The gates of NMOS transistor 0 and NMOS transistor 1 are connected, the drains of NMOS transistor 1 and PMOS transistor 1 are connected, the sources of PMOS transistor 1 and PMOS transistor 2 are connected, and the drains of PMOS transistor 2 and NMOS transistor 0 are connected.

[0054] The second-stage main amplifier circuit D2 consists of two identical circuits, one of which is composed of NMOS transistor 3 and PMOS transistor 3. The drains of NMOS transistor 3 and PMOS transistor 3 are connected, the source of NMOS transistor 3 is grounded, and the gate of NMOS transistor 3 is connected to the output of the first-stage main amplifier circuit D1.

[0055] Another route consists of NMOS transistor 4 and PMOS transistor 4; the drains of NMOS transistor 4 and PMOS transistor 4 are connected, the source of NMOS transistor 4 is grounded, and the gate of NMOS transistor 4 is connected to the output of the first-stage main amplifier circuit D1.

[0056] The second frequency compensation circuit D3 is composed of resistors and capacitors connected in series. Specifically, capacitor C1 and resistor R2 constitute one second frequency compensation circuit D3, and capacitor C0 and resistor R3 constitute another second frequency compensation circuit D3.

[0057] The third frequency compensation circuit D4 consists of a capacitor C14, an NMOS transistor 4, an NMOS transistor 9, and a capacitor C15 connected in series. In the third frequency compensation circuit D4, NMOS transistors (4 and 9) are used instead of resistors to reduce the area.

[0058] As an example, see Figure 1 NMOS transistors 4 and 9 are used to implement the zero-adjustment resistor in the third compensation of the common-mode loop; OPAR2R1 is a two-stage low-power feedback amplifier; PMOS transistors 4, 2, 3, and 4 form the output stage of the main amplifier. NMOS transistors 0, 1, 1, and 2 constitute the input stage of the main amplifier; R2, C1 and R3, C0 form the Miller compensation unit of the main amplifier with zero-adjustment resistors, which, along with the compensation unit of the feedback amplifier (see...), form the Miller compensation unit of the main amplifier. Figure 3 NMOS transistors 4, 9, C0, and C1 together form a three-stage compensation circuit in a four-stage common-mode loop. PMOS transistors 5 and 0 are bias MOSFETs. Vcc represents the power supply, gnd represents ground, ib1 represents the bias of the two-stage common-mode feedback amplifier, and vcm represents the common-mode reference signal.

[0059] Common-mode level sensing unit B includes two matched large-value resistors (R0 and R1), two input ports, and one output port. The two input ports are connected to the output terminals of the second-stage main amplifier circuit D2 of the two fully differential amplifiers, respectively. The output port is connected to one input terminal of the two-stage common-mode feedback amplifier. Common-mode level sensing unit B is used to block the differential-mode path (two-stage fully differential main amplifier) ​​and the common-mode loop (two-stage common-mode feedback amplifier), while reducing the impact of the common-mode loop on the differential loop.

[0060] Figure 3 The common-mode rejection ratio (CMRR) verification results based on the Cadence Virtuoso simulation tool are presented. The simulation results of the common-mode rejection ratio of this invention under the Cadence Virtuoso simulation tool are shown. The process library used is SMIC's 180nm CMOS process. The simulation results show that the DC common-mode rejection ratio (CMRR) is 198.75dB.

[0061] Figure 4 The simulation results for the common-mode rejection ratio (CMRR) of the fully differential amplifier (CMRR) are shown for three process angles (tt, ss, ff). The simulation results show that the common-mode rejection ratio of the present invention changes little with the process angle. The minimum value among the three process angles is 190.42dB, which is obtained at the ss process angle. The fluctuation of the CMRR does not exceed 10dB. Therefore, the above simulation results show that the present invention has superior PVT characteristics.

[0062] Figure 5Simulation waveforms of STB loop stability based on Cadence Virtuoso. Figure 5 The loop gain curve represents the gain-frequency change of the common-mode loop, and the loop phase curve represents the phase-frequency change of the common-mode loop. A necessary condition for loop stability is that when the loop gain drops to 0 dB with frequency, the loop phase shift cannot reach -180 degrees. The difference between the actual phase margin and -180 degrees is called the phase margin; the larger the phase margin, the more stable the loop. Based on the above principles, one can... Figure 5 The phase margin is read from the simulation curve to determine whether the common-mode loop of the present invention is stable. The Cadence Virtuoso tool provides a convenient method for displaying the phase margin of the above simulation curves. The phase margin result based on this method is as follows: Figure 6 ,Right now Figure 6 The simulation results are presented in numerical form. The simulation results show that the four-stage common-mode loop has sufficient phase margin and gain margin, so the four-stage common-mode loop is stable, which proves the effectiveness of the invention.

[0063] In comparison, the results of this invention are compared with those of related products from Texas Instruments, a world-leading company. Texas Instruments' OPA1637 fully differential amplifier has a CMRR of 140dB, the OPA862 amplifier has a CMRR of 120dB, the THS4567 fully differential amplifier has a CMRR of 80dB, and the THP210 has a CMRR of 140dB. Therefore, the common-mode rejection ratio achieved by this invention is at a leading level in the industry.

[0064] Table 1 Comparison of core performance indicators of this invention and products from Texas Instruments series.

[0065]

[0066] Secondly, the present invention also provides an application method for a four-stage common-mode loop fully differential amplifier, wherein the first-stage main amplifier circuit receives the differential-mode signal under the control of the second bias circuit and pre-amplifies the differential-mode signal;

[0067] The second-stage main amplifier circuit receives the pre-amplified differential signal under the control of the second bias circuit, amplifies it a second time, and then uses the second frequency compensation circuit to perform a frequency compensation on the amplified differential signal before outputting the differential signal.

[0068] The common-mode level sensing unit receives the initial common-mode signal, averages it, and outputs the common-mode level.

[0069] The first-stage common-mode error amplifier circuit, under the control of the first bias circuit, simultaneously receives the common-mode level and the common-mode reference signal, and pre-amplifies the error signal;

[0070] The coupling circuit receives the pre-amplified error signal and couples it to the second common-mode error amplifier circuit.

[0071] The second common-mode error amplifier circuit amplifies the error signal a second time, and the first frequency compensation circuit performs frequency compensation on the two-stage common-mode feedback amplifier before outputting the error signal. The amplified error signal is then input to the gate of the current source load of the input stage of the first-stage main amplifier circuit, and undergoes a third frequency compensation before being input.

[0072] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and other materials. In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit can implement several of the functions listed in the specification. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0073] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely illustrative of the invention and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications fall within the scope of the invention and its equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A four-stage common-mode fully differential amplifier, characterized in that, include: A two-stage fully differential main amplifier receives differential signals and amplifies the differential signals in two stages before outputting differential signals; A common-mode level sensing unit is used to capture the common-mode level of the output of the two-stage fully differential main amplifier. And two stages of common-mode feedback amplifiers, which simultaneously receive common-mode level and common-mode reference signal, are used to amplify the error signal between the common-mode level and the common-mode reference signal, and output the amplified error signal to the gate of the current source load of the input stage of the two stages of fully differential main amplifiers; The two-stage common-mode feedback amplifier includes a first bias circuit, a first-stage common-mode error amplifier circuit, a coupling circuit, a second-stage common-mode error amplifier circuit, and a first frequency compensation circuit. The first bias circuit provides bias voltage to the first-stage common-mode error amplifier circuit and the second-stage common-mode error amplifier circuit; the first-stage common-mode error amplifier circuit receives the error signal and pre-amplifies it; the pre-amplified error signal is coupled to the second-stage common-mode error amplifier circuit via a coupling circuit, and is output after being amplified by the second-stage common-mode error amplifier circuit; the first frequency compensation circuit is connected across the input and output terminals of the second-stage common-mode error amplifier circuit and is used to perform frequency compensation on the two-stage common-mode feedback amplifier. The two-stage fully differential main amplifier includes a second bias circuit, a first-stage main amplifier circuit, a second-stage main amplifier circuit, a second frequency compensation circuit, and a third frequency compensation circuit. The second bias circuit provides bias voltage for the first-stage main amplifier circuit and the second-stage main amplifier circuit. The input tube of the first-stage main amplifier circuit receives the differential signal, and the gate of the current source load of the input stage of the first-stage main amplifier circuit receives the error signal. After pre-amplifying the differential signal, it is input to the second-stage main amplifier circuit. The second-stage main amplifier circuit amplifies the pre-amplified differential signal a second time and outputs the differential signal. The second frequency compensation circuit consists of two paths, each of which is connected between the input and output of the second-stage main amplifier circuit; the third frequency compensation circuit is connected between the output of the second-stage common-mode error amplifier circuit and the output of the first-stage main amplifier circuit.

2. The four-stage common-mode fully differential amplifier according to claim 1, characterized in that, The first-stage common-mode error amplifier circuit adopts an input rail-to-rail structure; the second-stage common-mode error amplifier circuit adopts an output Class AB rail-to-rail structure.

3. The four-stage common-mode fully differential amplifier according to claim 1, characterized in that, The first frequency compensation circuit is a Miller frequency compensation circuit with a zero-adjustment resistor, which is composed of a resistor and an NMOS transistor connected in series. One end of the resistor is connected to the output terminal of the first-stage common-mode error amplifier circuit, and the other end of the resistor is connected to the gate of the NMOS transistor. The source, drain, and substrate of the NMOS transistor are connected to the input terminal of the second-stage common-mode error amplifier circuit.

4. The four-stage common-mode fully differential amplifier according to claim 1, characterized in that, Both the first bias circuit and the second bias circuit are full MOSFET low-voltage bandgap reference circuits, with output ports for 1uA and 200uA temperature-independent current.

5. The four-stage common-mode fully differential amplifier according to claim 1, characterized in that, The first-stage main amplifier circuit consists of NMOS transistor (0), NMOS transistor (1), PMOS transistor (1), and PMOS transistor (2); wherein the gates of NMOS transistor (0) and NMOS transistor (1) are connected, the drains of NMOS transistor (1) and PMOS transistor (1) are connected, the sources of PMOS transistor (1) and PMOS transistor (2) are connected, and the drains of PMOS transistor (2) and NMOS transistor (0) are connected. The second-stage main amplifier circuit consists of two identical circuits, one of which is composed of an NMOS transistor (3) and a PMOS transistor (3); wherein the drains of the NMOS transistor (3) and the PMOS transistor (3) are connected, the source of the NMOS transistor (3) is grounded, and the gate of the NMOS transistor (3) is connected to the output of the first-stage main amplifier circuit. Another route consists of an NMOS transistor (4) and a PMOS transistor (4); the drains of the NMOS transistor (4) and the PMOS transistor (4) are connected, the source of the NMOS transistor (4) is grounded, and the gate of the NMOS transistor (4) is connected to the output of the first-stage main amplifier circuit.

6. The four-stage common-mode fully differential amplifier according to claim 1, characterized in that, The second frequency compensation circuit is composed of a series resistor and a capacitor. Specifically, capacitor C(1) and resistor R(2) constitute one second frequency compensation circuit, and capacitor C(0) and resistor R(3) constitute another second frequency compensation circuit.

7. The four-stage common-mode fully differential amplifier according to claim 1, characterized in that, The third frequency compensation circuit consists of a capacitor C (14), an NMOS transistor (4), an NMOS transistor (9), and a capacitor C (15) connected in series.

8. A method for applying the four-stage common-mode loop fully differential amplifier as described in any one of claims 1 to 7, characterized in that, Includes the following steps: The first-stage main amplifier circuit receives the differential signal under the control of the second bias circuit and pre-amplifies the differential signal. The second-stage main amplifier circuit receives the pre-amplified differential signal under the control of the second bias circuit, amplifies it a second time, and then uses the second frequency compensation circuit to perform a frequency compensation on the amplified differential signal before outputting the differential signal. The common-mode level sensing unit receives the initial common-mode signal, averages it, and outputs the common-mode level. The first-stage common-mode error amplifier circuit, under the control of the first bias circuit, simultaneously receives the common-mode level and the common-mode reference signal, and pre-amplifies the error signal; The coupling circuit receives the pre-amplified error signal and couples it to the second common-mode error amplifier circuit. The second common-mode error amplifier circuit amplifies the error signal a second time, and the first frequency compensation circuit performs frequency compensation on the two-stage common-mode feedback amplifier before outputting the error signal. The amplified error signal is then input to the gate of the current source load of the input stage of the first-stage main amplifier circuit, and undergoes a third frequency compensation before being input.

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