Level control circuit and electric equipment

Abstract

The invention relates to a level control circuit and electric equipment. The level control circuit comprises a level shift circuit, an enable signal processing circuit and a level determination circuit. The level shift circuit is used for receiving a first control signal corresponding to the first voltage domain, converting the first control signal into a second control signal corresponding to the second voltage domain, and outputting the second control signal. The enable signal processing circuit is connected with a first positive power supply end of the first voltage domain and a second positive power supply end of the second voltage domain, and outputs an enable signal on the basis of a second power supply voltage provided by the second positive power supply end under the condition that the first power supply voltage is not connected to the first positive power supply end. And the level determining circuit is connected with the enable signal processing circuit and the output end of the level shifting circuit, and is used for controlling the level of the output end of the level shifting circuit to be in a preset state according to the received enable signal. The level shift circuit is clear in output state and high in output reliability under the condition that the second positive power supply end provides the second power supply voltage.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a level control circuit and an electrical device. Background Art

[0002] In electrical equipment, in order to enable signals to cross different voltage domains to drive or control corresponding circuit modules, it is usually necessary to set up a level shift circuit to achieve the task of converting signal voltage domains. The level shift circuit is connected between the first voltage domain and the second voltage domain, and converts the voltage level of the signal from the first voltage domain to a voltage level that meets the requirements of the second voltage domain. The converted signal is used to control or drive a specific module in the second voltage domain.

[0003] However, in practical applications, when the first voltage domain is powered off while the second voltage domain remains powered on, the output end of the level shift circuit will be in a floating state, resulting in insufficient output reliability of the level shift circuit. Summary of the invention

[0004] Based on this, it is necessary to provide a level control circuit and an electrical device that can improve the output reliability of the level shift circuit.

[0005] A level control circuit, comprising:

[0006] a level shift circuit, configured to access a first voltage domain and a second voltage domain, convert a received first control signal of the first voltage domain into a second control signal corresponding to the second voltage domain, and output the second control signal;

[0007] an enable signal processing circuit, connected to the first positive power supply terminal of the first voltage domain and the second positive power supply terminal of the second voltage domain respectively; the enable signal processing circuit is used to output an enable signal when receiving the second power supply voltage provided by the second positive power supply terminal and the first positive power supply terminal is not connected to the first power supply voltage;

[0008] A level determination circuit is connected to the enable signal processing circuit and the output end of the level shift circuit; the level determination circuit is used to control the level of the output end of the level shift circuit to a preset state according to the received enable signal.

[0009] In one embodiment, the enable signal processing circuit includes:

[0010] a first voltage conversion unit connected to the second positive power supply terminal; the first voltage conversion unit is used to obtain and output a third power supply voltage according to the second power supply voltage provided by the second positive power supply terminal; the third power supply voltage is lower than the second power supply voltage;

[0011] a first signal processing unit, connected to the first voltage conversion unit and the first positive power supply terminal respectively; the first signal processing unit is used to output an inverted signal of the first power supply voltage of the first positive power supply terminal when the third power supply voltage is received and the first positive power supply terminal is not connected to the first power supply voltage;

[0012] An inverting output unit is connected to the first voltage conversion unit and the first signal processing unit respectively; the inverting output unit is used to output the enable signal according to the received inverting signal when receiving the third power supply voltage.

[0013] In one embodiment, the enable signal processing circuit is further used to output the enable signal according to the received initial enable signal when the second power supply voltage is received and the first positive power supply terminal is connected to the first power supply voltage, and the enable signal has the same level state as the initial enable signal.

[0014] In one embodiment, the enable signal processing circuit further includes:

[0015] a second signal processing unit, connected to the first voltage conversion unit, the first positive power supply terminal and the inverting output unit respectively; the second signal processing unit is used to generate and output an inverting enable signal according to the received initial enable signal when the third power supply voltage is received and the first positive power supply terminal is connected to the first power supply voltage; the level state of the inverting enable signal is opposite to that of the initial enable signal;

[0016] The inverting output unit is further configured to output an enable signal according to the received inverting enable signal when the third power supply voltage is received.

[0017] In one embodiment, the enable signal processing circuit also includes a first buffer; the power supply end of the first buffer is connected to the first positive power supply end, and the ground end of the first buffer is connected to the first negative power supply end of the first voltage domain; the input end of the first buffer is used to receive the initial enable signal, and the output end of the first buffer is connected to the second signal processing unit.

[0018] In one embodiment, the second signal processing unit includes:

[0019] a signal trigger unit connected to the first positive power supply terminal; the signal trigger unit is used to generate and output a first intermediate enable signal having a different level state from the initial enable signal and a second intermediate enable signal having the same level state as the initial enable signal according to the received initial enable signal when the first positive power supply terminal is connected to the first power supply voltage;

[0020] A cross latch unit is respectively connected to the first voltage conversion unit, the signal trigger unit and the inverting output unit, and the cross latch unit is used to generate and output the inverting enable signal according to the received first intermediate enable signal and the second intermediate enable signal when the third power supply voltage is received.

[0021] In one embodiment, the signal trigger unit includes a first inverter and a second inverter; the power supply terminal of the first inverter and the power supply terminal of the second inverter are both connected to the first positive power supply terminal, and the ground terminal of the first inverter and the ground terminal of the second inverter are both connected to the first negative power supply terminal of the first voltage domain; the input terminal of the first inverter is used to receive the initial enable signal, and the output terminal of the first inverter is connected to the input terminal of the second inverter; the output terminal of the first inverter and the output terminal of the second inverter are both connected to the cross latch unit;

[0022] The first inverter is used to generate and output a first intermediate enable signal having a level state different from that of the received initial enable signal;

[0023] The second inverter is used to generate and output a second intermediate enable signal having a level state different from that of the received first intermediate enable signal.

[0024] In one embodiment, the cross latch unit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first end of the first transistor and the first end of the second transistor are both connected to the first voltage conversion unit, the second end of the first transistor is respectively connected to the controlled end of the second transistor and the first end of the third transistor, and the second end of the second transistor is respectively connected to the controlled end of the first transistor and the first end of the fourth transistor; the controlled end of the third transistor is used to receive the first intermediate enable signal, the controlled end of the fourth transistor is used to receive the second intermediate enable signal, and the second end of the third transistor and the second end of the fourth transistor are both grounded; the common end connected to the second transistor and the fourth transistor serves as the output end of the cross latch unit and is connected to the inverting output unit.

[0025] In one embodiment, the first signal processing unit includes a third inverter and a fifth transistor; the power supply terminal of the third inverter is connected to the first voltage conversion unit, and the ground terminal of the third inverter is connected to the first negative power supply terminal of the first voltage domain; the input terminal of the third inverter is used to connect to the first positive power supply terminal, and the output terminal of the third inverter is connected to the controlled terminal of the fifth transistor; the first terminal of the fifth transistor is connected to the inverting output unit, and the second terminal of the fifth transistor is connected to the first negative power supply terminal.

[0026] In one embodiment, the inverting output unit includes a fourth inverter; the power supply terminal of the fourth inverter is connected to the first voltage conversion unit, and the ground terminal of the fourth inverter is connected to the first negative power supply terminal of the first voltage domain; the input terminal of the fourth inverter serves as the input terminal of the inverting output unit, and the output terminal of the fourth inverter serves as the output terminal of the inverting output unit.

[0027] In one embodiment, the first voltage conversion unit includes a resistor, a Zener diode and a sixth transistor; the first end of the resistor and the first end of the sixth transistor are both connected to the second positive power supply terminal, the second end of the resistor is respectively connected to the controlled end of the sixth transistor and the cathode of the Zener diode, and the anode of the Zener diode is connected to the first negative power supply terminal of the first voltage domain; the second end of the sixth transistor is used to output the third power supply voltage.

[0028] In one embodiment, the level control circuit also includes a second voltage conversion unit, which is used to connect the first positive power supply terminal and the load power supply terminal of the load voltage domain, and obtain a second voltage domain according to the first power supply voltage connected to the first positive power supply terminal and the load power supply voltage connected to the load power supply terminal, wherein the load voltage domain is used to power the load.

[0029] In one embodiment, the second voltage conversion unit includes a bootstrap diode and a bootstrap capacitor; the anode of the bootstrap diode is used to connect to the first positive power supply terminal, and the cathode of the bootstrap diode is connected to the first end of the bootstrap capacitor; the second end of the bootstrap capacitor is used to connect to the load power supply terminal; the first end of the bootstrap capacitor serves as the second positive power supply terminal of the second voltage domain and is connected to the level shift circuit; the second end of the bootstrap capacitor serves as the second negative power supply terminal of the second voltage domain and is connected to the level shift circuit.

[0030] In one embodiment, the level control circuit also includes a second buffer; the power supply end of the second buffer is connected to the first positive power supply end, and the ground end of the second buffer is connected to the first negative power supply end of the first voltage domain; the input end of the second buffer is used to receive the first control signal, and the output end of the second buffer is connected to the level shift circuit.

[0031] In one of the embodiments, the level determination circuit includes a pull-down unit; a controlled end of the pull-down unit is used to receive the enable signal, a first end of the pull-down unit is connected to an output end of the level shift circuit, and a second end of the pull-down unit is connected to a first negative power supply end of the first voltage domain;

[0032] The pull-down unit is used to pull down the level of the output end of the level shift circuit to a preset state according to the enable signal.

[0033] In one embodiment, the pull-down unit includes a seventh transistor, a controlled end of the seventh transistor is used to receive the enable signal, a first end of the seventh transistor is connected to the output end of the level shift circuit, and a second end of the seventh transistor is connected to the first negative power supply end of the first voltage domain.

[0034] An electrical device includes a load, a power tube module connected to the load, and a level control circuit as described above, wherein the output end of the level shift circuit in the level control circuit is connected to the power tube module, and the second control signal is used to control the load through the power tube module.

[0035] In one embodiment, the power tube module includes a driving circuit and a power tube; the power supply end of the driving circuit is connected to the second positive power supply end of the second voltage domain, the ground end of the driving circuit is connected to the second negative power supply end of the second voltage domain, the input end of the driving circuit is connected to the output end of the level shift circuit, the output end of the driving circuit is connected to the controlled end of the power tube, the first end of the power tube is used to connect to the load power supply end, and the second end of the power tube is used to connect to the load.

[0036] The above-mentioned level control circuit and electric equipment include a level shift circuit, an enable signal processing circuit and a level determination circuit. The level shift circuit is used to receive a first control signal corresponding to a first voltage domain, convert the first control signal into a second control signal corresponding to a second voltage domain, and output a second control signal for controlling a subsequent circuit. The enable signal processing circuit is respectively connected to a first positive power supply terminal of the first voltage domain and a second positive power supply terminal of the second voltage domain, and based on a second power supply voltage provided by the second positive power supply terminal, outputs an enable signal when the first positive power supply terminal is not connected to the first power supply voltage. The level determination circuit is connected to the output terminal of the enable signal processing circuit and the level shift circuit, and is used to control the level of the output terminal of the level shift circuit to a preset state according to the received enable signal. Thus, when the second positive power supply terminal provides the second power supply voltage, even if the first positive power supply voltage terminal no longer provides the first power supply voltage, the enable signal processing circuit can still provide an enable signal with enabling capability, so that the level determination circuit can control the level of the output terminal of the level shift circuit to a preset state, thereby improving the output reliability of the level shift circuit by clarifying the output state of the level shift circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] FIG1 is a schematic diagram of a module of a level control circuit according to an embodiment;

[0039] FIG2 is a schematic diagram of a module of a level control circuit according to another embodiment;

[0040] FIG3 is a schematic diagram of a module of a level control circuit according to another embodiment;

[0041] FIG4 is a schematic diagram of a module of a level control circuit according to another embodiment;

[0042] FIG5 is a schematic diagram of a module of a level control circuit according to another embodiment;

[0043] FIG6 is a schematic diagram of a module of a second signal processing unit according to an embodiment;

[0044] FIG7 is a schematic diagram of a circuit structure of an enable signal processing circuit according to an embodiment;

[0045] FIG8 is a schematic diagram of a module of a level control circuit according to another embodiment;

[0046] FIG9 is a schematic diagram of a module of a level control circuit according to another embodiment;

[0047] FIG10 is a schematic diagram of the structure of a level control circuit according to an embodiment;

[0048] FIG. 11 is a schematic diagram of an electrical equipment module according to an embodiment. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0052] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0053] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0054] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0055] As described in the background art, the level shift circuit in the related art has the technical problem of low output reliability.

[0056] In electronic devices, level shift circuits are usually used to achieve signal voltage domain conversion tasks. For example, in audio power amplifier equipment, the voltage domain of the control signal sent by the main control module is different from the voltage domain of the power amplifier module (the power amplifier module is usually controlled by a high-voltage power tube module). Therefore, a high-voltage level shift circuit is required to transfer the control signal of the first voltage domain sent by the main control module to a signal of the second voltage domain where the driving circuit of the high-voltage power tube module is located. This signal is used to drive and control the high-voltage power tube, and then control the power amplifier module.

[0057] During the power-on and power-off process of the first voltage domain, the output of the high-voltage level shift circuit will float (that is, the output level is in an uncertain state). In order to prevent the output of the high-voltage level shift circuit from floating, a pull-down tube is often set at its output end, and it is controlled by an enable signal. When the system is working normally, the enable signal controls the pull-down tube to turn off, and the signal output by the high-voltage level shift circuit changes with the input signal; when the system is turned off, the enable signal controls the pull-down tube to turn on, pulling the output of the high-voltage level shift circuit down.

[0058] However, if the first voltage domain is powered off while the second voltage domain remains powered on, the output of the level shift circuit will still be in a floating state, resulting in insufficient output reliability of the high-voltage level shift circuit. Taking the audio power amplifier device as an example, when the output of the high-voltage level shift circuit is floating, the high-voltage power tube will not be completely turned off, which will cause leakage, increasing the static power consumption of the audio power amplifier device.

[0059] Therefore, how to improve the output reliability of the level shift circuit is an urgent problem to be solved.

[0060] Based on the above technical problems, the inventors have found after long-term research that when the first voltage domain is powered off and the second voltage domain is not powered off, the output end of the level shift circuit is floating because after the first voltage domain is powered off, the enable signal is immediately in an invalid state, so the pull-down tube cannot be pulled down, and the output end of the high-voltage level shift circuit is floating. After the first voltage domain is powered off, the enable signal is still in a valid state, which can effectively control the output end level of the level shift circuit, thereby improving the output reliability of the level shift circuit by clarifying the output state of the level shift circuit. Specifically, an embodiment of the present invention provides a level control circuit, including a level shift circuit, an enable signal processing circuit and a level determination circuit. Among them, the level shift circuit is used to access the first voltage domain and the second voltage domain, and convert the first control signal received from the first voltage domain into a second control signal corresponding to the second voltage domain, and output the second control signal. The enable signal processing circuit is connected to the first positive power supply end of the first voltage domain and the second positive power supply end of the second voltage domain respectively; the enable signal processing circuit is used to output an enable signal when the second power supply voltage provided by the second positive power supply end is received and the first positive power supply end is not connected to the first power supply voltage. The level determination circuit is connected to the output end of the enable signal processing circuit and the level shift circuit; the level determination circuit is used to control the level of the output end of the level shift circuit to a preset state according to the received enable signal.

[0061] By adopting the above technical solution, when the second positive power supply terminal provides the second power supply voltage, even if the first positive power supply voltage terminal no longer provides the first power supply voltage, the enable signal processing circuit can still provide an enable signal with enabling capability, so that the level determination circuit can control the level of the output end of the level shift circuit to a preset state, thereby improving the output reliability of the level shift circuit by clarifying the output state of the level shift circuit.

[0062] The above is the core idea of ​​the present invention. The technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] FIG1 is a schematic diagram of the structure of a level control circuit provided in an embodiment of the present invention. As shown in FIG1 , the level control circuit provided in an embodiment of the present invention includes: a level shift circuit 100 , an enable signal processing circuit 200 and a level determination circuit 300 .

[0064] The level shift circuit 100 is used to access the first voltage domain and the second voltage domain, convert the received first control signal DIN into a second control signal DOUT corresponding to the second voltage domain, and output the second control signal DOUT.

[0065] The enable signal processing circuit 200 is connected to the first positive power supply terminal of the first voltage domain and the second positive power supply terminal of the second voltage domain respectively. The enable signal processing circuit 200 is used to output the enable signal ENB_LS to the level determination circuit 300 when receiving the second power supply voltage BSVDD provided by the second positive power supply terminal and the first positive power supply terminal is not connected to the first power supply voltage VDDL.

[0066] The level determination circuit 300 is connected to the enable signal processing circuit 200 and the output end of the level shift circuit 100 , and is used to control the level of the output end of the level shift circuit 100 to a preset state according to the received enable signal ENB_LS.

[0067] Among them, the first positive power supply terminal of the first voltage domain is used to connect to the first power supply voltage VDDL, and the first negative power supply terminal of the first voltage domain is used to connect to the first negative voltage. The second positive power supply terminal of the second voltage domain is used to connect to the second power supply voltage BSVDD, and the second negative power supply terminal of the second voltage domain is used to connect to the second negative voltage. The voltage magnitudes of the second power supply voltage BSVDD and the first power supply voltage VDDL are different, and can be specifically set according to actual conditions.

[0068] In practical applications, the level control circuit is used for electrical equipment, and the electrical equipment may include but is not limited to audio equipment, motor drive equipment, LED (Light Emitting Diode) drive equipment, etc. For the sake of convenience of explanation, the following description is based on the example of the level control circuit being used for audio equipment. The audio equipment includes a control module, a power amplifier module, and a power tube module for controlling the power amplifier module. The control module is in a first voltage domain, the power tube module is in a second voltage domain, and the power amplifier module is in a load voltage domain. The first power supply voltage VDDL of the first positive power supply terminal may be a low voltage, such as 3.8V-5V. The load power supply voltage in the load voltage domain may be a high voltage, such as 10V, 12V, 24V, etc. The second power supply voltage BSVDD of the second positive power supply terminal may be determined according to the adaptation voltage of the power tube module. In actual implementation, the second power supply voltage BSVDD may be converted between low voltage and high voltage. For example, when the power tube module is connected to the load power supply voltage, the second power supply voltage BSVDD may be a high voltage; when the power tube module is not connected to the load power supply voltage, the second power supply voltage BSVDD may be a low voltage.

[0069] The connection mode of the level shift circuit 100 to access the first voltage domain and the second voltage domain can be determined according to actual conditions. When accessing the first voltage domain, the first positive power supply terminal can be connected to access the first power supply voltage VDDL, or the first negative power supply terminal can be connected to access the first negative voltage, or both the first positive power supply terminal and the first negative power supply terminal can be connected. When accessing the second voltage domain, the second positive power supply terminal can be connected to access the second power supply voltage BSVDD, or the second negative power supply terminal can be connected to access the second negative voltage, or both the second positive power supply terminal and the second negative power supply terminal can be connected.

[0070] The level shift circuit 100 is also used to receive a first control signal DIN in the first voltage domain, and convert the first control signal DIN into a second control signal DOUT corresponding to the second voltage domain. When the level control circuit is used in an audio device, the first control signal DIN can be output by the front-end control module. After receiving the first control signal DIN, the level shift circuit 100 performs voltage domain transfer processing on it to obtain and output the second control signal DOUT corresponding to the second voltage domain. The second control signal DOUT is output to the power tube module to control the power amplifier module through the power tube module. It should be noted that the structure of the level shift circuit 100 does not need to be limited, and those skilled in the art can refer to the commonly used technology in the field for setting, and only need to implement the above-mentioned corresponding functions.

[0071] The enable signal processing circuit 200 is powered by the second power supply voltage BSVDD provided by the second positive power supply terminal. When receiving the second power supply voltage BSVDD, the enable signal processing circuit 200 operates normally and outputs the enable signal ENB_LS according to the state of the first positive power supply terminal being connected to the first power supply voltage VDDL. Specifically, when the first power supply terminal is a lower voltage, such as 0V or close to 0V, it is confirmed that the first positive power supply terminal is not connected to the first power supply voltage VDDL. At this time, the enable signal processing circuit 200 outputs the enable signal ENB_LS to the level determination circuit 300.

[0072] The level determination circuit 300 is connected to the output end of the level shift circuit 100. Under the control of the enable signal ENB_LS, the level determination circuit 300 can make the level of the output end of the level shift circuit 100 a preset state. The preset state can be a high level, a low level or a specific voltage value, which can be set in combination with actual conditions. For example, when the second control signal DOUT is at a high level, the power tube in the power tube module is turned on; when the second control signal DOUT is at a low level, the power tube in the power tube module is turned off. In the use scenario, when the first positive power supply terminal is not connected to the first power supply voltage VDDL, the level determination circuit 300 can be controlled by the enable signal ENB_LS. Make the level of the output end of the level shift circuit 100 a preset low level, thereby turning off the power tube in the power tube module at the back end. Among them, the specific voltage value of the preset low level does not need to be limited, it only needs to be able to achieve the above function.

[0073] It can be understood that when the first voltage domain is powered off and the load voltage domain that supplies power to the power amplifier module is still powered on, if the power tube is not completely turned off, leakage will occur and may affect the power amplifier module. In this embodiment, when the second positive power supply terminal provides the second power supply voltage BSVDD, even if the first voltage domain is powered off, a valid enable signal ENB_LS can still be output, thereby turning off the power tube in the power tube module. This can prevent leakage problems caused by the power tube not being completely turned off, thereby reducing the static power consumption of the audio device and improving the reliability of the control of the power amplifier module.

[0074] Those skilled in the art will appreciate that, in actual implementation, the level determination circuit 300 can be integrated with the level shift circuit 100 in the level shift circuit. When the integrated level shift circuit receives the enable signal ENB_LS, its output terminal is no longer in a floating state, but in a preset level state.

[0075] The level control circuit described above realizes reliable transmission and processing of control signals between different voltage domains.

[0076] When the second positive power supply terminal normally provides the second power supply voltage BSVDD, even if the first positive power supply voltage terminal no longer provides the first power supply voltage VDDL, the enable signal processing circuit 200 can still provide the enable signal ENB_LS with the enable capability, so that the level determination circuit 300 can control the level of the output end of the level shift circuit 100 to a preset state, thereby improving the output reliability of the level shift circuit 100 by clarifying the output state of the level shift circuit 100. In turn, the reliability of the control of the electric device can be improved, and the static power consumption of the electric device can be reduced.

[0077] In one embodiment, as shown in FIG. 2 , the enable signal processing circuit 200 may include a first voltage conversion unit 210 , a first signal processing unit 220 , and an inverting output unit 230 .

[0078] The first voltage conversion unit 210 is connected to the second positive power supply terminal, and is used to obtain and output a third power supply voltage VS according to the second power supply voltage BSVDD provided by the second positive power supply terminal. The third power supply voltage VS can be a stable voltage signal less than the second power supply voltage BSVDD.

[0079] The first signal processing unit 220 is connected to the first voltage conversion unit 210 and the first positive power supply terminal respectively; the first signal processing unit 220 is used to output an inverted signal when receiving the third power supply voltage VS and the first positive power supply terminal is not connected to the first power supply voltage VDDL.

[0080] The inverting output unit 230 is connected to the first voltage conversion unit 210 and the first signal processing unit 220 respectively; the inverting output unit 230 is used for outputting the enable signal ENB_LS according to the received inverting signal when receiving the third power supply voltage VS.

[0081] Specifically, the first voltage conversion unit 210 can convert the second power supply voltage BSVDD into the third power supply voltage VS, and provide the power supply voltage for the first signal processing unit 220 and the inverting output unit 230, thereby realizing the conversion from the second voltage domain to the third voltage domain, so that the inverting output unit 230 outputs the enable signal ENB_LS of the third voltage domain. The magnitude of the third power supply voltage VS of the third voltage domain needs to be determined according to actual needs. For example, the third power supply voltage VS can be a voltage magnitude adapted by the level determination circuit 300.

[0082] When the third power supply voltage VS is used for power supply, the first signal processing unit 220 monitors the state of the first positive power supply terminal, that is, whether the first power supply voltage VDDL is connected. If the first positive power supply terminal is not connected to the first power supply voltage VDDL, the first signal processing unit 220 outputs a low-level signal (i.e., an inverted signal) opposite to the state of the first power supply voltage VDDL to the inverting output unit 230, and the inverting output unit 230 outputs a high-level enable signal ENB_LS according to the received low-level inverted signal.

[0083] In this embodiment, the conversion of the voltage domain is realized by the first voltage conversion unit 210, and an adaptive and reliable third power supply voltage VS is provided for the first signal processing unit 220 and the inverting output unit 230. When the third power supply voltage VS is supplied, the first signal processing unit 220 can enable the inverting output unit 230 to output the enable signal ENB_LS when monitoring that the first power supply voltage VDDL is not connected. This ensures that when the first power supply voltage VDDL is powered off, a valid enable signal ENB_LS can still be output, so that the level control of the output end of the level shift circuit 100 is in a preset state, so as to improve the output reliability of the level shift circuit 100.

[0084] In one embodiment, as shown in FIG. 3 , the enable signal processing circuit 200 is further configured to receive an initial enable signal ENB_LS_IN, and when the second power supply voltage BSVDD is received and the first positive power supply terminal is connected to the first power supply voltage VDDL, the enable signal ENB_LS is output according to the received initial enable signal ENB_LS_IN, and the level state of the enable signal ENB_LS is the same as that of the initial enable signal ENB_LS_IN.

[0085] Among them, the initial enable signal ENB_LS_IN can be a signal of the first voltage domain, and the level state of the enable signal ENB_LS is the same as that of the initial enable signal ENB_LS_IN, that is, when the initial enable signal ENB_LS_IN is a high level in the first voltage domain, the enable signal ENB_LS is a high level in the third voltage domain; when the initial enable signal ENB_LS_IN is a low level in the first voltage domain, the enable signal ENB_LS is a low level in the third voltage domain.

[0086] The initial enable signal ENB_LS_IN can be output by the control module or other functional modules. In some embodiments, the control module also outputs the initial enable signal ENB_LS_IN. In other embodiments, a detection module connected to the enable signal processing circuit 200 is provided in the electrical device, and the detection module outputs the initial enable signal ENB_LS_IN when the power amplifier module is detected to be abnormal. Furthermore, the enable signal processing circuit 200 outputs the enable signal ENB_LS according to the initial enable signal ENB_LS_IN, and the level determination circuit 300 controls the level of the output end of the level shift circuit 100 to a preset low level under the action of the enable signal ENB_LS, thereby turning off the power tube in the power tube module at the back end, avoiding the power tube leakage and increasing the static power consumption of the device, and also ensuring that the power amplifier module is effectively turned off.

[0087] In this embodiment, when the enable signal processing circuit 200 receives the second power supply voltage BSVDD, if the first positive power supply terminal is connected to the first power supply voltage VDDL, the enable signal ENB_LS of the same phase is output when the initial enable signal ENB_LS_IN is received; if the first positive power supply terminal is not connected to the first power supply voltage VDDL, the enable signal ENB_LS is also output. Thus, the validity of the enable signal ENB_LS can be guaranteed when the second power supply voltage BSVDD is used for power supply, thereby improving the output reliability of the level shift circuit 100.

[0088] In one embodiment, as shown in FIG4 , the enable signal processing circuit 200 further includes a second signal processing unit 240. The second signal processing unit 240 is respectively connected to the first voltage conversion unit 210, the first positive power supply terminal and the inverting output unit 230. The second signal processing unit 240 is also used to receive the initial enable signal ENB_LS_IN, and when the third power supply voltage VS is received and the first positive power supply terminal is connected to the first power supply voltage VDDL, the second signal processing unit 240 generates and outputs an inverted enable signal according to the received initial enable signal ENB_LS_IN; the level state of the inverted enable signal is opposite to that of the initial enable signal ENB_LS_IN.

[0089] The inverting output unit 230 is further configured to output an enable signal ENB_LS according to the received inverting enable signal when receiving the third power supply voltage VS.

[0090] In this embodiment, the conversion of the voltage domain is realized by the first voltage conversion unit 210, and an adaptive and reliable third power supply voltage VS is provided for the first signal processing unit 220, the second signal processing unit 240 and the inverting output unit 230. The first signal processing unit 220 can output an inverted signal of the first power supply voltage VDDL at the first positive power supply terminal when monitoring that the first power supply voltage VDDL is not connected, and the inverting output unit 230 can output an enable signal ENB_LS according to the inverted signal.

[0091] When receiving the first power supply voltage VDDL, the second signal processing unit 240 generates and outputs an inverted enable signal of the third voltage domain according to the received initial enable signal ENB_LS_IN, and the inverted output unit 230 can output the enable signal ENB_LS according to the inverted enable signal. The level states of the inverted enable signal and the initial enable signal ENB_LS_IN are opposite, that is, when the initial enable signal ENB_LS_IN is a high level of the first voltage domain, the inverted enable signal is a high level of the third voltage domain; when the initial enable signal ENB_LS_IN is a low level of the first voltage domain, the inverted enable signal is a low level of the third voltage domain.

[0092] Thus, when the second voltage domain is powered on, the first voltage conversion unit 210 can output the third power supply voltage VS, so that the first signal processing unit 220, the second signal processing unit 240 and the inverting output unit 230 can work normally. In this process, if the first positive power supply terminal is connected to the first power supply voltage VDDL, the second signal processing unit 240 combined with the inverting output unit 230 can output the enable signal ENB_LS. If the first power supply voltage VDDL is not connected, the first signal processing unit 220 combined with the inverting output unit 230 can still output the enable signal ENB_LS. Therefore, when the second power supply voltage BSVDD is supplied, the validity of the enable signal ENB_LS can be guaranteed.

[0093] In one embodiment, as shown in FIG5 , the enable signal processing circuit further includes a first buffer 250. A power supply terminal of the first buffer 250 is connected to a first positive power supply terminal (not shown), and a ground terminal of the first buffer 250 is connected to a first negative power supply terminal (not shown) of the first voltage domain; an input terminal of the first buffer 250 is used to receive an initial enable signal ENB_LS_IN, and an output terminal of the first buffer 250 is connected to the second signal processing unit 240.

[0094] A buffer is an electronic component that can temporarily store signals or data and transmit them to the next level circuit when needed. In this embodiment, a first buffer 250 is connected to the front end of the second signal processing unit 240. When the initial enable signal ENB_LS_IN output by the control module or other functional modules is input to the first buffer 250, the first buffer 250 can amplify, shape or delay it to ensure that it has the expected driving capability and reliability when it is transmitted to the second signal processing unit 240, thereby improving the effectiveness of the enable signal ENB_LS.

[0095] In one embodiment, as shown in FIG. 6 , the second signal processing unit 240 includes a signal triggering unit 241 and a cross latching unit 242 .

[0096] The signal trigger unit 241 is connected to the first positive power supply terminal; the signal trigger unit 241 is used to generate and output a first intermediate enable signal having a different level state from the initial enable signal ENB_LS_IN and a second intermediate enable signal having the same level state as the initial enable signal ENB_LS_IN according to the received initial enable signal ENB_LS_IN when the first positive power supply terminal is connected to the first power supply voltage VDDL.

[0097] The cross latch unit 242 is respectively connected to the first voltage conversion unit 210, the signal trigger unit 241 and the inverting output unit 230. The cross latch unit 242 is used to generate an inverting enable signal according to the received first intermediate enable signal and the second intermediate enable signal when receiving the third power supply voltage VS, and output the inverting enable signal to the inverting output unit 230.

[0098] Specifically, when the first power supply voltage VDDL is connected, the first power supply voltage VDDL supplies power to the signal trigger unit 241, so that the signal trigger unit 241 works normally. The trigger unit 241 processes the initial enable signal ENB_LS_IN to obtain the first intermediate enable signal and the second intermediate enable signal in the first voltage domain.

[0099] The level states of the first intermediate enable signal and the second intermediate enable signal are always opposite. Specifically, the level state of the second intermediate enable signal is the same as the level state of the initial enable signal ENB_LS_IN, and the level state of the first intermediate enable signal is inverted to the level state of the initial enable signal ENB_LS_IN. Thus, when the initial enable signal ENB_LS_IN is in a valid level state, the second intermediate enable signal is also in a valid level state, and the first intermediate enable signal is in a failed level state. Vice versa. With regard to the initial enable signal ENB_LS_IN being in a valid level state and a failed level state, it can be understood that if the initial enable signal ENB_LS_IN is at a high level, the enable signal ENB_LS finally obtained is at a high level, at which time the level determination circuit 300 can control the level of the output end of the level shift circuit 100 to be a preset state, then the high level state is the valid level state of the initial enable signal ENB_LS_IN, and the low level state is the failed level state of the initial enable signal ENB_LS_IN.

[0100] The first intermediate enable signal and the second intermediate enable signal with opposite level states are used for subsequent cross latch control. After receiving the third power supply voltage VS, the cross latch unit 242 obtains an inverted enable signal according to the first intermediate enable signal or the second intermediate enable signal, and the inverted enable signal has an opposite level state to the initial enable signal ENB_LS_IN. After being processed by the inverted output unit 230, the inverted enable signal is converted into an enable signal ENB_LS with the same level state as the initial enable signal ENB_LS_IN.

[0101] In this embodiment, the coordinated operation of the signal trigger unit 241 and the cross latch unit 242 enables the second signal processing unit 240 to more accurately control the generation and transmission of the inverted enable signal, and the circuit has high reliability and flexibility.

[0102] In actual implementation, the circuit structure of the signal trigger unit 241 and the cross latch unit 242 can be set according to specific circumstances. In one embodiment, as shown in Figure 7, the signal trigger unit 241 may include a first inverter INV1 and a second inverter INV2. The power supply terminal of the first inverter INV1 and the power supply terminal of the second inverter INV2 are both connected to the first positive power supply terminal, and the ground terminal of the first inverter INV1 and the ground terminal of the second inverter INV2 are both connected to the first negative power supply terminal of the first voltage domain. The input terminal of the first inverter INV1 is used to receive the initial enable signal ENB_LS_IN, and the output terminal of the first inverter INV1 is connected to the input terminal of the second inverter INV2; the output terminal of the first inverter INV1 and the output terminal of the second inverter INV2 are both connected to the cross latch unit 242.

[0103] The first inverter INV1 is used to generate and output a first intermediate enable signal having a different level state from the received initial enable signal ENB_LS_IN. The second inverter INV2 is used to generate and output a second intermediate enable signal having a different level state from the received first intermediate enable signal. Thus, the second inverter INV2 inverts the first intermediate enable signal output by the first inverter INV1 again, generates and outputs a second intermediate enable signal, and the level of the second intermediate enable signal is the same as the level of the initial enable signal ENB_LS_IN.

[0104] In this embodiment, the first inverter INV1 and the second inverter INV2 operate in the first voltage domain (first power supply voltage VDDL / first negative voltage GND), and the first inverter INV1 can perform preliminary inversion processing on the input initial enable signal ENB_LS_IN to obtain the first intermediate enable signal. The first inverter INV1 can also play a role in signal shaping, and can shape the waveform of the input signal into a more regular and stable waveform, so that the output first intermediate enable signal has a more stable logic state.

[0105] The second inverter INV2 inverts the first intermediate enable signal again, and the second intermediate enable signal obtained and outputted will be restored to the same level state as the initial enable signal ENB_LS_IN. The stability of the second intermediate enable signal is further enhanced, ensuring the stable logic state of the signal output to the cross latch unit 242. The first intermediate enable signal and the second intermediate enable signal with stable logic state are conducive to improving the reliability of subsequent cross latch unit 242 processing.

[0106] In one embodiment, the cross latch unit 242 may include a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. The first end of the first transistor M1 and the first end of the second transistor M2 are both connected to the first voltage conversion unit 210, the second end of the first transistor M1 is respectively connected to the controlled end of the second transistor M2 and the first end of the third transistor M3, and the second end of the second transistor M2 is respectively connected to the controlled end of the first transistor M1 and the first end of the fourth transistor M4. The controlled end of the third transistor M3 is used to receive the first intermediate enable signal INB, the controlled end of the fourth transistor M4 is used to receive the second intermediate enable signal IN, and the second end of the third transistor M3 and the second end of the fourth transistor M4 are both grounded. The common end connected to the second transistor M2 and the fourth transistor M4 is used as the output end of the cross latch unit 242, and is connected to the inverting output unit 230.

[0107] Among them, the types of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 can be set in combination with specific circumstances, and the controlled end, the first end and the second end of each transistor also need to be determined in combination with the type of the transistor. In one embodiment, the third transistor M3 and the fourth transistor M4 are high-level conductive transistors, such as NMOS tubes (N-channel Metal-Oxide-Semiconductor Field-Effect Transistor, N-channel metal oxide semiconductor field effect transistor), the gate of the NMOS tube is used as the controlled end, the drain can be used as the first end, and the source is used as the second end. The first transistor M1 and the second transistor M2 are low-level conductive transistors, such as PMOS tubes (P-channel Metal Oxide Semiconductor Field-Effect Transistor, P-channel metal oxide semiconductor field effect transistor), the gate of the PMOS tube is used as the controlled end, the source can be used as the first end, and the drain is used as the second end.

[0108] In this embodiment, the cross latch unit 242 operates in the third voltage domain (third power supply voltage VS / GND). When the initial enable signal ENB_LS_IN is at a high level, the first intermediate enable signal INB is at a low level, and the second intermediate enable signal IN is at a high level. At this time, the fourth transistor M4 is turned on, and the drain of the fourth transistor M4 is pulled low, that is, the common terminal connected to the second transistor M2 and the fourth transistor M4 is pulled low to GND, and the inverted enable signal output by the cross latch unit 242 is in a low level state.

[0109] When the initial enable signal ENB_LS_IN is at a low level, the first intermediate enable signal INB is at a high level, and the second intermediate enable signal IN is at a low level. At this time, the third transistor M3 is turned on, the gate of the second transistor M2 is pulled down, and the second transistor M2 is turned on; the common terminal connected to the second transistor M2 and the fourth transistor M4 is pulled up to the third power supply voltage VS, and the inverted enable signal output by the cross latch unit 242 is in a high level state.

[0110] The cross latch unit 242 can lock its output state until receiving a new control signal, and thus is less sensitive to external interference, thereby making the output stability of the inverted enable signal higher, thereby improving the output stability of the enable signal ENB_LS.

[0111] In one embodiment, the first signal processing unit 220 may include a third inverter INV3 and a fifth transistor M5. The power supply terminal of the third inverter INV3 is connected to the first voltage conversion unit 210, and the ground terminal of the third inverter INV3 is connected to the first negative power supply terminal of the first voltage domain. The input terminal of the third inverter INV3 is used to connect to the first positive power supply terminal, and the output terminal of the third inverter INV3 is connected to the controlled terminal of the fifth transistor M5; the first terminal of the fifth transistor M5 is connected to the inverting output unit 230, and the second terminal of the fifth transistor M5 is connected to the first negative power supply terminal.

[0112] The type of the fifth transistor M5 can be set according to specific circumstances. For example, the fifth transistor M5 can be an NMOS transistor.

[0113] In this embodiment, the fifth transistor M5 and the third inverter INV3 operate in the third voltage domain (VS / GND). When the first power supply voltage VDDL is powered off, the input terminal of the third inverter INV3 is at a low level, and its output terminal is at a high level. The fifth transistor M5 is turned on, and the input terminal of the inverting output unit 230 is pulled low. At this time, the inverting output unit 230 outputs a high-level enable signal ENB_LS according to the low level of the input terminal. Therefore, when the first power supply voltage VDDL is powered off, the enable signal ENB_LS with the enable capability can still be output.

[0114] When the first power supply voltage VDDL is powered on, the third inverter INV3 outputs a low level signal when receiving the first power supply voltage VDDL, turning off the fifth transistor M5. At this time, the inverted output unit 230 outputs the enable signal ENB_LS according to the inverted enable signal output by the second signal processing unit 240, that is, the enable signal ENB_LS follows the level state change of the initial enable signal ENB_LS_IN. In the scenario where the control module outputs the initial enable signal ENB_LS_IN, the final enable signal ENB_LS can be synchronized with the signal output by the control module in the level state.

[0115] In one embodiment, the inverting output unit 230 includes a fourth inverter INV4. The power supply terminal of the fourth inverter INV4 is connected to the first voltage conversion unit 210, and the ground terminal of the fourth inverter INV4 is connected to the first negative power supply terminal of the first voltage domain. The input terminal of the fourth inverter INV4 is connected to the first signal processing unit 220 and the second signal processing unit 230 as the input terminal of the inverting output unit 230, and the output terminal of the fourth inverter INV4 is used as the output terminal of the inverting output unit 230.

[0116] The fourth inverter INV4 operates in the third voltage domain (third power supply voltage VS / GND). When the input end of the fourth inverter INV4 is at a low level (such as receiving an inverted signal or an inverted enable signal in a low level state), the output end serves as the output end of the inverted output unit 230, and the output enable signal ENB_LS is in a valid level state. When the input end of the fourth inverter INV4 is at a high level (such as receiving an inverted enable signal in a high level state when the first power supply voltage VDDL is powered on), the output enable signal ENB_LS is in an invalid level state.

[0117] The fourth inverter INV4 can flexibly receive and process signals from the first signal processing unit 220 and the second signal processing unit 240 , and can also shape and enhance the signals during signal transmission, thereby enhancing the driving capability of the enable signal ENB_LS output to the level determination circuit 300 .

[0118] In one embodiment, the first voltage conversion unit 210 includes a resistor R1, a Zener diode D1, and a sixth transistor M6. The first end of the resistor R1 and the first end of the sixth transistor M6 are both connected to the second positive power supply terminal to access the second power supply voltage BSVDD. The second end of the resistor R1 is respectively connected to the controlled end of the sixth transistor M6 and the cathode of the Zener diode D1, and the anode of the Zener diode D1 is connected to the first negative power supply terminal of the first voltage domain; the second end of the sixth transistor M6 is used to output the third power supply voltage VS.

[0119] In this embodiment, the third power supply voltage VS is generated by using the second power supply voltage BSVDD of the second voltage domain, so as to convert the voltage domain of the initial enable signal ENB_LS_IN from VDDL / VDD to the enable signal ENB_LS of the voltage domain VS / GND.

[0120] The type of the sixth transistor M6 and the parameters of the resistor R1 and the Zener diode D1 can be set according to specific circumstances. For example, the sixth transistor M6 can be an NMOS transistor, and the clamping voltage of the Zener diode D1 can be 5V.

[0121] In actual use, the second power supply voltage BSVDD may reach a high voltage. By setting the Zener diode D1, the gate voltage VG of the sixth transistor M6 can be clamped in a stable state of about 5V. When the gate voltage VG is stable, the conduction state of the sixth transistor M6 also becomes stable, thereby allowing current to flow from the source to the drain, and in this process, a stable output voltage is generated, that is, a stable third power supply voltage VS. Moreover, it can be ensured that the source voltage of the sixth transistor M6 (that is, the third power supply voltage VS) is within 5V, so that the effective level of the enable signal ENB_LS is more compatible with the level determination circuit 300.

[0122] It should be noted that, in actual implementation, different power modules may provide the first voltage domain and the second voltage domain respectively, and one power module may provide one of the voltage domains, which may then be converted into the other voltage domain by a specific circuit.

[0123] In one embodiment, as shown in Figure 8, the level control circuit also includes a second voltage conversion unit 400, which is used to connect the first positive power supply terminal and the load power supply terminal of the load voltage domain (not shown in the figure), and obtain the second voltage domain according to the first power supply voltage VDDL connected to the first positive power supply terminal and the load power supply voltage connected to the load power supply terminal.

[0124] Among them, the load voltage domain is used to supply power to the load in the electrical equipment, and the load is the circuit controlled by the power tube in the power tube module, such as the power amplifier module.

[0125] It can be understood that when the power tube in the power tube module is turned on, the load power supply voltage is transmitted to the second voltage conversion unit 400 through the power tube, and the second voltage conversion unit 400 can obtain the second power supply voltage BSVDD according to the first power supply voltage VDDL and the load power supply voltage. Therefore, in the electric device, there is no need to set power modules for the first voltage domain and the second voltage domain respectively, which can reduce the cost of the electric device.

[0126] In one embodiment, as shown in FIG9 , the level control circuit further includes a second buffer 500 . A power supply terminal of the second buffer 500 is connected to a first positive power supply terminal GND (not shown), and a ground terminal of the second buffer 500 is connected to a first negative power supply terminal GND (not shown) of the first voltage domain. An input terminal of the second buffer 500 is used to receive a first control signal VIN, and an output terminal of the second buffer 500 is connected to the level shift circuit 100 .

[0127] In this embodiment, a second buffer 500 is connected to the front end of the level shift circuit 100, and the first control signal VIN can be amplified, shaped or delayed by the second buffer 500 to ensure that it has the expected driving capability and reliability when transmitted to the level shift circuit 100, thereby improving the reliability of the level shift circuit 100.

[0128] Further, in one embodiment, as shown in FIG10 , the second voltage conversion unit 400 includes a bootstrap diode D2 and a bootstrap capacitor C_BS. The anode of the bootstrap diode D2 is used to connect to the first positive power supply terminal to access the first power supply voltage VDDL, and the cathode of the bootstrap diode D2 is connected to the first end of the bootstrap capacitor C_BST. The second end of the bootstrap capacitor C_BST is used to connect to the load power supply terminal of the load voltage domain to access the load power supply voltage VDDH.

[0129] The common end of the bootstrap diode D2 and the bootstrap capacitor C_BST is used as the second positive power supply end of the second voltage domain, for providing the second power supply voltage BSVDD. The second end of the bootstrap capacitor C_BST is used as the second negative power supply end of the second voltage domain, for providing the second negative voltage VO. The level shift circuit 100 is connected to both ends of the bootstrap capacitor C_BST.

[0130] In actual implementation, the second end of the bootstrap capacitor C_BST can be directly connected to the load power supply voltage VDDH, or indirectly connected to the load power supply voltage VDDH. Exemplarily, the power tube module in the electrical equipment includes a connected drive circuit and a power tube M0, the drive circuit is respectively connected to the second power supply voltage BSVDD and the second negative voltage VO, and the drive module is used to drive and control the power tube M0 according to the received second control signal DOUT. The first end of the power tube M0 is connected to the load power supply end, and the second end of the power tube M0 is connected to the second end of the bootstrap capacitor C_BST. When the power tube M0 is turned on, the load power supply voltage VDDH provided by the load power supply end is connected to the second end of the bootstrap capacitor C_BST through the power tube M0. It can be understood that in actual application, the second end of the power tube M0 is also connected to the power supply end of the load, and the ground end of the load is connected to the negative power supply end of the load voltage domain, so as to realize the control of the load through the power tube M0.

[0131] Specifically, when the second negative voltage VO is 0V, the first power supply voltage VDDL charges the second power supply voltage BSVDD through the bootstrap diode D2, and the voltage of the second power supply voltage BSVDD is approximately the first power supply voltage VDDL-VDIO, where VDIO represents the difference in the conduction threshold voltage of the diode D2.

[0132] When the second negative voltage VO is the load power voltage VDDH, the second power voltage BSVDD will be raised to about VDDL-VDIO+VDDH through the C_BST capacitor.

[0133] From this we can get:

[0134] The voltage difference between the second power supply voltage BSVDD and the second negative voltage VO is basically the same as the first power supply voltage VDDL, so the driving circuit in the power tube module can use ordinary low-voltage tubes, which can greatly reduce the number of high-voltage tubes in the equipment and thus reduce the overall cost.

[0135] When the device is powered on, the first positive power supply terminal provides the first power supply voltage VDDL, and the second positive power supply terminal provides the second power supply voltage BSVDD. At this time, the level determination circuit 300 can make the output terminal level of the level shift circuit 100 be a preset state.

[0136] When the device is powered off, the first positive power supply terminal no longer provides the first power supply voltage VDDL, but because the second power supply voltage BSVDD is generated by the bootstrap capacitor C_BST, when the first positive power supply terminal is out of power, the voltage of the second power supply voltage BSVDD will be maintained for a period of time. In this process, the second power supply voltage BSVDD supplies power to the enable signal processing circuit 200. When the enable signal processing circuit 200 detects that the first power supply voltage VDDL is not connected, it outputs an enable signal ENB_LS with enabling capability, so that the level determination circuit 300 controls the output terminal level of the level shift circuit 100 to a preset state. Thereby, it can be ensured that when the first voltage domain is powered off and the second voltage domain is still powered on, the output terminal of the level shift circuit 100 is no longer in a floating state, thereby improving the output reliability of the level shift circuit 100.

[0137] In this embodiment, the second voltage conversion unit 400 is a bootstrap circuit, which has a simple structure and high reliability, and can reduce the number of high-voltage tubes in the electrical equipment.

[0138] Under the control of the enable signal ENB_LS, the level determination circuit 300 can make the level of the output end of the level shift circuit 100 a preset high level, low level or a specific voltage state. In specific implementation, the level determination circuit 300 can be set according to actual needs.

[0139] In one embodiment, when the high-voltage power tube M0 in the power tube module is an N-type tube, the level determination circuit 300 may include a pull-down unit. The controlled end of the pull-down unit is used to receive the enable signal ENB_LS, the first end of the pull-down unit is connected to the output end of the level shift circuit 100, and the second end of the pull-down unit is connected to the first negative power supply end of the first voltage domain. The pull-down unit is used to pull down the level of the output end of the level shift circuit 100 to a preset state according to the enable signal ENB_LS.

[0140] Specifically, the pull-down unit starts working when it receives the enable signal ENB_LS, and can pull down the output end of the level shift circuit 100 to the first negative voltage GND of the first negative power supply end, thereby turning off the high-voltage power tube M0 in the power tube module to prevent leakage when the load power supply voltage VDDH is powered on.

[0141] In a specific embodiment, the pull-down unit includes a seventh transistor M7, a controlled end of the seventh transistor M7 is used to receive an enable signal ENB_LS, a first end of the seventh transistor M7 is connected to the output end of the level shift circuit 100, and a second end of the seventh transistor M7 is connected to the first negative power supply end of the first voltage domain to access the first negative voltage GND.

[0142] Exemplarily, the seventh transistor M7 can be an NMOS tube. When the enable signal ENB_LS at the output end of the enable signal processing circuit 200 is in a high-level valid state, the seventh transistor M7 is turned on, so that the output end of the level shift circuit 100 is pulled down to the first negative voltage GND. When the enable signal ENB_LS at the output end of the enable signal processing circuit 200 is in a low-level invalid state, the seventh transistor M7 is turned off, so that the second control signal DOUT output at the output end of the level shift circuit 100 is consistent with the level state of the first control signal DIN, and the second control signal DOUT controls the power amplifier module through the power tube module.

[0143] In order to better understand the above embodiment, a detailed explanation is given below in conjunction with a specific embodiment. In one embodiment, the level control circuit is used for an audio device, and as shown in FIG10 , the level control circuit includes a level shift circuit 100 , an enable signal processing circuit 200 , a level determination circuit 300 , a second voltage conversion unit 400 and a second buffer 500 , and the enable signal processing circuit 200 can be set as shown in FIG7 .

[0144] The entire level control circuit involves four voltage domains, namely the first voltage domain (VDDL / GND), the second voltage domain (BSVDD / V0), the third voltage domain (VS / GND) and the load voltage domain (VDDH / GND). The level shift circuit 100 converts the first control signal DIN of the first voltage domain output by the control module into the second control signal DOUT of the second voltage domain. The second control signal DOUT is a high-voltage drive signal for controlling the power tube M0 in the power tube module.

[0145] The second voltage domain (BSVDD / V0) is a variable voltage domain. When the load voltage domain is not connected, the second voltage conversion unit 400 can generate the second voltage domain (BSVDD / V0) according to the first power supply voltage VDDL. At this time, the second power supply voltage is about BSVDD VDDL-VDIO. When the load voltage domain is connected, the second voltage domain (BSVDD / V0) can be generated according to the first power supply voltage VDDL and the load power supply voltage VDDH. At this time, the second power supply voltage is BSVDD VDDL-VDIO+VDDH.

[0146] When the first power supply voltage VDDL is powered on, the front-end control module also outputs the initial enable signal ENB_LS_IN of the first voltage domain, and the initial enable signal ENB_LS_IN is transmitted to the signal trigger unit 241 through the first buffer 250. The first inverter INV1 and the second inverter INV2 in the signal trigger unit 241 respectively generate the first intermediate enable signal INB and the second intermediate enable signal IN. Then, the first intermediate enable signal INB and the second intermediate enable signal IN control the cross latch unit 242 to generate the inverted enable signal, and the level state of the inverted enable signal is inverted with the initial enable signal ENB_LS_IN.

[0147] The enable signal ENB_LS output by the fourth inverter INV4 is in phase with the initial enable signal ENB_LS_IN, and the seventh transistor M7 can be controlled by the enable signal ENB_LS. When the seventh transistor M7 is turned off, the second control signal DOUT output by the level shift circuit 100 is in phase with the first control signal DIN. When the seventh transistor M7 is turned on, the output end of the level shift circuit 100 is pulled low, so that the power tube M0 in the rear-end driving circuit is turned off.

[0148] When the first power supply voltage VDDL is powered off, since the third power supply voltage VS is generated by the second power supply voltage BSVDD, the third power supply voltage VS is maintained at a high level during the period when the second power supply voltage BSVDD is powered, and since the first power supply voltage VDDL is powered off, the fifth transistor M5 works at this time, making the enable signal ENB_LS at a high level. In this way, the seventh transistor M7 can work normally, thereby ensuring that the output end of the level shift circuit 100 can be maintained at 0 during this period of time, ensuring that the power tube at the back end will not be turned on, and even if the load power supply voltage VDDH is powered, there will be no leakage problem, effectively reducing the risk of leakage.

[0149] The level control circuit can clearly determine the output state of the level shift circuit 100 when the first power supply voltage VDDL is powered off and the second power supply voltage BSVDD is powered on, thereby improving the output reliability of the level shift circuit 100, thereby improving the control reliability of the power-consuming device and reducing the static power consumption of the power-consuming device.

[0150] In one embodiment, as shown in FIG. 11 , an electrical device is provided, including a load 10, a power tube module 20 connected to the load, and a level control circuit 30. The level control circuit 30 can be configured with reference to the above embodiments and will not be described in detail. The output end of the level shift circuit 100 in the level control circuit 30 is connected to the power tube module 20, and the second control signal DOUT output by the level shift circuit 100 is used to control the load 10 through the power tube module 20.

[0151] The electric device is a device that involves voltage domain transfer of signals, such as an audio device, a motor drive device, an LED drive device, etc. The load 10 can be determined according to the electric device. For example, if the electric device is an audio device, the load 10 can be an amplifier module.

[0152] In actual implementation, the electric device may further include a control module connected to the level control circuit 30, the control module is used to output the first control signal DIN of the first voltage domain and the initial enable signal ENB_LS_IN. The level control circuit 30 is used to convert the first control signal DIN of the first voltage domain into the second control signal DOUT of the second voltage domain.

[0153] The power tube module 20 is connected to the second voltage domain. When the power tube module 20 receives the second control signal DOUT, it can control the load 10 in the load voltage domain according to the second control signal DOUT.

[0154] When the first power supply voltage VDDL of the first voltage domain is not connected and the second voltage domain is still powered on, the level of the output end of the level control circuit 30 is in a preset state, and its output reliability is high.

[0155] In one embodiment, the power tube module 20 includes a driving circuit and a power tube. The power supply end of the driving circuit is connected to the second positive power supply end of the second voltage domain, the ground end of the driving circuit is connected to the second negative power supply end of the second voltage domain, the input end of the driving circuit is connected to the output end of the level shift circuit, and the output end of the driving circuit is connected to the controlled end of the power tube; the first end of the power tube is connected to the load power supply end of the load voltage domain to access the load power supply voltage VDDH; the second end of the power tube is used to connect to the load 10.

[0156] It can be understood that in actual implementation, the load 10 is also connected to the load voltage domain, the first end of the power tube is connected to the load power supply voltage VDDH, and the second end is connected to the negative power supply end of the load voltage domain through the load 10.

[0157] When the first power supply voltage VDDL of the first voltage domain is not connected and the second voltage domain is still powered on, the level of the output end of the level control circuit 30 is in a preset state. The preset level state can turn off the power tube, thereby avoiding leakage of the power tube when the load power supply voltage VDDH is powered on, thereby reducing the static power consumption of the electrical equipment.

[0158] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0159] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0160] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A level control circuit, characterized in that: include: a level shift circuit, configured to access a first voltage domain and a second voltage domain, convert a received first control signal of the first voltage domain into a second control signal corresponding to the second voltage domain, and output the second control signal; an enable signal processing circuit, connected to the first positive power supply terminal of the first voltage domain and the second positive power supply terminal of the second voltage domain respectively; the enable signal processing circuit is used to output an enable signal when receiving the second power supply voltage provided by the second positive power supply terminal and the first positive power supply terminal is not connected to the first power supply voltage; A level determination circuit connected to the output end of the enable signal processing circuit and the level shift circuit; The level determination circuit is used to control the level of the output end of the level shift circuit to a preset state according to the received enable signal.

2. The level control circuit according to claim 1, characterized in that: The enabling signal processing circuit comprises: a first voltage conversion unit connected to the second positive power supply terminal; the first voltage conversion unit is used to obtain and output a third power supply voltage according to the second power supply voltage provided by the second positive power supply terminal; the third power supply voltage is lower than the second power supply voltage; a first signal processing unit, connected to the first voltage conversion unit and the first positive power supply terminal respectively; the first signal processing unit is used to output an inverted signal when the third power supply voltage is received and the first positive power supply terminal is not connected to the first power supply voltage; An inverting output unit is connected to the first voltage conversion unit and the first signal processing unit respectively; the inverting output unit is used to output the enable signal according to the received inverting signal when receiving the third power supply voltage.

3. The level control circuit according to claim 2, characterized in that: The enable signal processing circuit is also used to output the enable signal according to the received initial enable signal when the second power supply voltage is received and the first positive power supply terminal is connected to the first power supply voltage, and the level state of the enable signal is the same as that of the initial enable signal.

4. The level control circuit according to claim 3, characterized in that: The enabling signal processing circuit further includes: a second signal processing unit, connected to the first voltage conversion unit, the first positive power supply terminal and the inverting output unit respectively; the second signal processing unit is used to generate and output an inverting enable signal according to the received initial enable signal when the third power supply voltage is received and the first positive power supply terminal is connected to the first power supply voltage; the level state of the inverting enable signal is opposite to that of the initial enable signal; The inverting output unit is further configured to output an enable signal according to the received inverting enable signal when the third power supply voltage is received.

5. The level control circuit according to claim 4, characterized in that: The enable signal processing circuit also includes a first buffer; a power supply end of the first buffer is connected to the first positive power supply end, and a ground end of the first buffer is connected to the first negative power supply end of the first voltage domain; an input end of the first buffer is used to receive the initial enable signal, and an output end of the first buffer is connected to the second signal processing unit.

6. The level control circuit according to claim 4, characterized in that: The second signal processing unit comprises: a signal trigger unit connected to the first positive power supply terminal; the signal trigger unit is used to generate and output a first intermediate enable signal having a different level state from the initial enable signal and a second intermediate enable signal having the same level state as the initial enable signal according to the received initial enable signal when the first positive power supply terminal is connected to the first power supply voltage; A cross latch unit is respectively connected to the first voltage conversion unit, the signal trigger unit and the inverting output unit, and the cross latch unit is used to generate and output the inverting enable signal according to the received first intermediate enable signal and the second intermediate enable signal when the third power supply voltage is received.

7. The level control circuit according to claim 6, characterized in that: The signal trigger unit includes a first inverter and a second inverter; the power supply end of the first inverter and the power supply end of the second inverter are both connected to the first positive power supply end, and the ground end of the first inverter and the ground end of the second inverter are both connected to the first negative power supply end of the first voltage domain; the input end of the first inverter is used to receive the initial enable signal, and the output end of the first inverter is connected to the input end of the second inverter; the output end of the first inverter and the output end of the second inverter are both connected to the cross latch unit; The first inverter is used to generate and output a first intermediate enable signal having a level state different from that of the received initial enable signal; The second inverter is used to generate and output a second intermediate enable signal having a level state different from that of the received first intermediate enable signal.

8. The level control circuit according to claim 6, characterized in that: The cross latch unit includes a first transistor, a second transistor, a third transistor and a fourth transistor; the first end of the first transistor and the first end of the second transistor are both connected to the first voltage conversion unit, the second end of the first transistor is respectively connected to the controlled end of the second transistor and the first end of the third transistor, and the second end of the second transistor is respectively connected to the controlled end of the first transistor and the first end of the fourth transistor; the controlled end of the third transistor is used to receive the first intermediate enable signal, the controlled end of the fourth transistor is used to receive the second intermediate enable signal, and the second end of the third transistor and the second end of the fourth transistor are both grounded; the common end connected to the second transistor and the fourth transistor serves as the output end of the cross latch unit and is connected to the inverting output unit.

9. The level control circuit according to claim 2, characterized in that: The first signal processing unit includes a third inverter and a fifth transistor; the power supply end of the third inverter is connected to the first voltage conversion unit, and the ground end of the third inverter is connected to the first negative power supply end of the first voltage domain; the input end of the third inverter is used to connect to the first positive power supply end, and the output end of the third inverter is connected to the controlled end of the fifth transistor; the first end of the fifth transistor is connected to the inverting output unit, and the second end of the fifth transistor is connected to the first negative power supply end.

10. The level control circuit according to claim 2, characterized in that: The inverting output unit includes a fourth inverter; the power supply end of the fourth inverter is connected to the first voltage conversion unit, and the ground end of the fourth inverter is connected to the first negative power supply end of the first voltage domain; the input end of the fourth inverter serves as the input end of the inverting output unit, and the output end of the fourth inverter serves as the output end of the inverting output unit.

11. The level control circuit according to claim 2, characterized in that: The first voltage conversion unit includes a resistor, a Zener diode and a sixth transistor; the first end of the resistor and the first end of the sixth transistor are both connected to the second positive power supply terminal, the second end of the resistor is respectively connected to the controlled end of the sixth transistor and the cathode of the Zener diode, and the anode of the Zener diode is connected to the first negative power supply terminal of the first voltage domain; the second end of the sixth transistor is used to output the third power supply voltage.

12. The level control circuit according to any one of claims 1 to 11, characterized in that: It also includes a second voltage conversion unit, which is used to connect the first positive power supply terminal and the load power supply terminal of the load voltage domain, and obtain a second voltage domain according to the first power supply voltage connected to the first positive power supply terminal and the load power supply voltage connected to the load power supply terminal, wherein the load voltage domain is used to power the load.

13. The level control circuit according to claim 12, characterized in that: The second voltage conversion unit includes a bootstrap diode and a bootstrap capacitor; the anode of the bootstrap diode is used to connect to the first positive power supply terminal, and the cathode of the bootstrap diode is connected to the first end of the bootstrap capacitor; The second end of the bootstrap capacitor is used to connect to the load power supply end; The first end of the bootstrap capacitor is used as the second positive power supply end of the second voltage domain and is connected to the level shift circuit; The second end of the bootstrap capacitor serves as a second negative power supply end of the second voltage domain and is connected to the level shift circuit.

14. The level control circuit according to any one of claims 1 to 11, characterized in that: It also includes a second buffer; the power supply end of the second buffer is connected to the first positive power supply end, and the ground end of the second buffer is connected to the first negative power supply end of the first voltage domain; the input end of the second buffer is used to receive the first control signal, and the output end of the second buffer is connected to the level shift circuit.

15. The level control circuit according to any one of claims 1 to 11, characterized in that: The level determination circuit comprises a pull-down unit; a controlled end of the pull-down unit is used to receive the enable signal, a first end of the pull-down unit is connected to the output end of the level shift circuit, and a second end of the pull-down unit is connected to the first negative power supply end of the first voltage domain; The pull-down unit is used to pull down the level of the output end of the level shift circuit to a preset state according to the enable signal.

16. The level control circuit according to claim 15, characterized in that: The pull-down unit includes a seventh transistor, a controlled end of the seventh transistor is used to receive the enable signal, a first end of the seventh transistor is connected to the output end of the level shift circuit, and a second end of the seventh transistor is connected to the first negative power supply end of the first voltage domain.

17. An electrical equipment, characterized in that: It includes a load, a power tube module connected to the load, and a level control circuit according to any one of claims 1-16, wherein the output end of the level shift circuit in the level control circuit is connected to the power tube module, and the second control signal is used to control the load through the power tube module.

18. The electrical equipment according to claim 17, characterized in that: The power tube module includes a driving circuit and a power tube; the power supply end of the driving circuit is connected to the second positive power supply end of the second voltage domain, the ground end of the driving circuit is connected to the second negative power supply end of the second voltage domain, the input end of the driving circuit is connected to the output end of the level shift circuit, the output end of the driving circuit is connected to the controlled end of the power tube, the first end of the power tube is used to connect to the load power supply end, and the second end of the power tube is used to connect to the load.

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