Four-phase clock buffer and two-stage four-phase clock buffer
By using a common source ring structure configuration of a four-phase clock buffer in the clock buffer, the problem of operating cycle deviation and error accumulation of inverter clock buffer in high-speed clock applications is solved, and the stability and independence of the output clock operating cycle are achieved.
Patent Information
- Application Number
- CN202411164765.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-25
- Filing Date
- 2024-08-23
- Publication Date
- 2025-02-25
AI Technical Summary
In high-speed clock applications, existing inverter clock buffers have different rise and fall times of PMOST and NMOST, resulting in deviations in the working cycle of the output clock, and errors will accumulate in multi-stage configurations, seriously affecting the stability of the working cycle.
Using a four-phase clock buffer, the common source ring structure configuration of PMOST and NMOST ensures that the working cycle of the four-phase output clock is independent of the working cycle of the input clock, and avoids error accumulation.
The stability of the output clock working cycle under different processes, supply voltages and temperature conditions is achieved, and the accumulation of working cycle errors in multi-stage configurations is avoided, and the needs of high-speed clock applications are met.
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Figure CN119519694A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to clock buffers, and more particularly to a four-phase clock buffer with a 25% duty cycle. Background Art
[0002] As understood by those skilled in the art, a signal is a voltage of a variable level that carries specific information and can change over time. At a given moment, the level of a signal represents the state of the signal at that moment. A logic signal is a signal with two states (low state and high state). When the voltage level of the logic signal is higher than the trip point, the logic signal is in a high state, otherwise it is in a low state. Regarding the logic signal Q, "Q is high" or "Q is low" represents "Q is in a high state" or "Q is in a low state". The first logic signal does not necessarily have the same trip point as the second logic signal. If the first logic signal and the second logic signal are always in opposite states, the first logic signal is called the logical inversion of the second logic signal. In other words, when the first logic signal is low (high), the second logic signal is high (low). When the logic signal is converted from low to high (Low-to-High, L2H), a rising edge is generated; when the logic signal is converted from high to low (High-to-Low, H2L), a falling edge is generated.
[0003] A clock is a logic signal that switches periodically between a low state and a high state. The duty cycle of a clock represents the percentage of time that the clock remains in a high state. A four-phase clock represents a set of four clocks with the same waveform but uniformly distributed in time, including a first clock, a second clock, a third clock, and a fourth clock. The first clock, the second clock, the third clock, and the fourth clock are respectively referred to as the first phase, the second phase, the third phase, and the fourth phase of the four-phase clock.
[0004] A clock buffer receives an input clock and outputs an output clock such that the output clock has a larger amplitude, a sharper state transition, or both than the input clock. Clock buffers can be inverting or non-inverting. For an inverting clock buffer, the output clock is the logical inversion of the input clock. For a non-inverting clock buffer, the output clock is logically the same as the input clock, but has a larger amplitude, a sharper state transition, or both.
[0005] An inverter is a circuit that receives an input clock and outputs an output clock that is the inversion of the input clock and can be used to implement an inverting clock buffer. Due to the inversion of the signal, the duty cycle of the output clock is one hundred percent minus the duty cycle of the input clock. For example, if the duty cycle of the input clock is 25% (75%), the duty cycle of the output clock will be 75% (25%), because if the input clock is in a high state 25% (75%) of the time, the output clock will be in a low state 25% (75%) of the time, and therefore will be in a high state 75% (25%) of the time. A cascade of two inverters can be used to implement a non-inverting clock buffer, where the duty cycle of the output clock will be the same as the duty cycle of the input clock.
[0006] Four-phase clocks are widely used in radio transceivers. In many applications, a four-phase clock with a duty cycle of 25% is required. An inverting clock buffer with a four-phase input clock with a 25% duty cycle can be realized using four inverters, wherein each of the four inverters receives a respective phase in the four-phase input clock and outputs a respective phase in the four-phase output clock, wherein the four-phase output clock has a 75% duty cycle. The series connection of two such inverting clock buffers can realize a non-inverting clock buffer, which has a four-phase input clock with a 25% duty cycle and outputs a four-phase output clock with a 25% duty cycle.
[0007] The clock buffer can be integrated and manufactured on a silicon substrate using a complementary metal oxide semiconductor (CMOS) process, wherein the inverter includes an N-channel metal oxide semiconductor (NMOS) transistor and a P-channel metal oxide semiconductor (PMOS) transistor; this technology is common to those skilled in the art and will not be described in further detail. The problem with using an inverter to implement a clock buffer is that the L2H transition of the output clock is caused by the pull-up of the PMOST, while the L2H transition of the output clock is caused by the pull-down of the NMOST. The strength of the PMOST pull-up is usually different from the strength of the NMOST pull-down. Even if the two can be designed to be the same as each other under normal circumstances, they will still change and differ under changes in process, supply voltage and temperature. Therefore, the rise time (of the rising edge) and the fall time (of the falling edge) are usually different, so the duty cycle of the inverter output clock will be deviated. This problem is more serious for high-speed clocks. Since the cycle of high-speed clocks is very short, small errors in the rise time and / or fall time may cause significant errors in the working cycle. In addition, in a multi-stage configuration with multiple stages of clock buffers connected in series, each stage of the clock buffer will produce an error in the working cycle. After the errors of each stage are accumulated, they will eventually lead to a serious deviation in the working cycle.
[0008] A clock buffer designed with a 25% duty cycle four-phase clock that can better tolerate process, supply voltage, and temperature variations, and in which errors do not accumulate in a multi-stage configuration, is desirable. Summary of the invention
[0009] An object of the present invention is to have a four-phase clock buffer that can output a four-phase output clock with a duty cycle of approximately 75% in response to a four-phase input clock with a duty cycle of approximately 25% (not necessarily exactly 25%).
[0010] Another object of the present invention is to have a four-phase clock buffer that can output a four-phase output clock with a duty cycle of approximately 25% in response to a four-phase input clock with a duty cycle of approximately 75% (not necessarily exactly 75%).
[0011] Another object of the present invention is to have a two-stage clock buffer that receives a four-phase input clock with a duty cycle of approximately 25% (not necessarily exactly equal to 25%) and outputs a four-phase output clock with a duty cycle of approximately 25% without accumulating the duty cycle errors in the aforementioned multi-stage configuration.
[0012] Another object of the present invention is to have a multi-stage clock buffer, which includes a multi-stage series connection, which can output a four-phase output clock with a duty cycle of approximately 25% and will not accumulate the duty cycle error in the aforementioned multi-stage configuration.
[0013] In one embodiment, the four-phase clock buffer includes a first P-channel metal oxide semiconductor transistor (PMOST), a second PMOST, a third PMOST and a fourth PMOST, which are configured in a common-source ring topology to send a first phase, a second phase, a third phase and a fourth phase of a four-phase output clock, respectively. The four-phase clock buffer also includes a first N-channel metal oxide semiconductor transistor (NMOST), a second NMOST, a third NMOST and a fourth NMOST, which are configured in a common-source structure to respond to the first phase, the second phase, the third phase and the fourth phase of the four-phase input clock, respectively, and control the first phase, the second phase, the third phase and the fourth phase of the four-phase output clock, respectively.
[0014] In one embodiment, the four-phase clock buffer includes a first NMOST, a second NMOST, a third NMOST and a fourth NMOST, which are configured in a common source ring structure to send the first phase, the second phase, the third phase and the fourth phase of the four-phase output clock respectively. The four-phase clock buffer also includes a first PMOST, a second PMOST, a third PMOST and a fourth PMOST, which are configured in a common source structure to respond to the first phase, the second phase, the third phase and the fourth phase of the four-phase input clock respectively, and control the first phase, the second phase, the third phase and the fourth phase of the four-phase output clock respectively.
[0015] In one embodiment, a two-stage four-phase clock buffer includes a first stage and a second stage connected in series, wherein the first stage includes four PMOSTs and four NMOSTs, the four PMOSTs of the first stage are configured in a common source ring structure to send a first four-phase clock, the four NMOSTs of the first stage are configured in a common source structure to control the first four-phase clock in response to the second four-phase clock, and the second stage includes four PMOSTs and four NMOSTs, the four NMOSTs of the second stage are configured in a common source ring structure to send a third four-phase clock, and the four PMOSTs of the second stage are configured in a common source structure to control the third four-phase clock in response to the first four-phase clock. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more obvious and understandable, the description of the accompanying drawings is as follows:
[0017] Figure 1 A schematic diagram of a four-phase clock buffer according to an embodiment of the present disclosure is shown;
[0018] Figure 2 Shows Figure 1 An exemplary timing diagram of a four-phase clock buffer of
[0019] Figure 3 A schematic diagram of a four-phase clock buffer according to another embodiment of the present disclosure is shown.
[0020] Explanation of symbols
[0021] 100: Four-phase clock buffer
[0022] 300: Four-Phase Clock Buffer
[0023] A1~A4: Phase
[0024] B1~B4: Phase
[0025] CCP: Cross-coupled pairs
[0026] E1, E3, E5: Low to High (L2H) transition
[0027] E2, E4: High to Low (H2L) conversion
[0028] NM1~NM4: N-type metal oxide semiconductor transistor (NMOST)
[0029] NM1'~NM8': N-type metal oxide semiconductor transistor (NMOST)
[0030] PM1~PM8: P-type metal oxide semiconductor transistor (PMOST)
[0031] PM1'~PM4': P-type metal oxide semiconductor transistor (PMOST)
[0032] T, T / 4: cycle / time
[0033] V DD : Power supply node
[0034] V SS : Ground node
[0035] X1~X4: Phase
[0036] Y1~Y4: Phase DETAILED DESCRIPTION
[0037] This disclosure relates to clock buffers. Although this disclosure describes several embodiments that are considered to be preferred implementations, it should be noted that the invention can be implemented in a variety of ways and is not limited to the specific embodiments described below or the specific implementation of any features in these examples. In other examples, details that are well known to those skilled in the art are not shown or described to avoid obscuring the focus of this disclosure.
[0038] The present disclosure document uses a number of terms and basic concepts related to microelectronics that are well known to those skilled in the art, such as "voltage", "signal", "logic signal", "clock", "phase", "duty cycle", "cycle", "common source", "power supply", "ground", "noise", "complementary metal oxide semiconductor (CMOS)", "N-type metal oxide semiconductor transistor (NMOST)", "P-type metal oxide semiconductor transistor (PMOST)" and "cross-coupling". Terms and basic concepts similar to these terms can be understood by those skilled in the art, and therefore will not be explained in detail here.
[0039] For PMOST and NMOST, a person skilled in the art can identify the symbol of a Metal Oxide Semiconductor Transistor (MOST) and its "source", "gate" and "drain" terminals. A person skilled in the art can read a circuit diagram containing an NMOST and a PMOST without a detailed description of how one component in the circuit diagram is connected to another component.
[0040] This disclosure document is disclosed from an engineering perspective. For example, regarding variables X and Y, when it is said that "X is equal to Y", it means "X is approximately equal to Y", that is, "the difference between X and Y is less than a specified engineering tolerance". When it is said that "X is 0", it means "X is approximately 0", that is, "X is less than a specified engineering tolerance". When it is said that "X is significantly less than Y", it means "X is negligible with respect to Y", that is, "the ratio between X and Y is less than the engineering tolerance, so X can be ignored when compared with Y".
[0041] A power supply node is a circuit node whose voltage is approximately equal to the power supply voltage, which is higher than 0 but may have small high-frequency fluctuations. A ground node is a circuit node whose voltage is approximately equal to 0 but may have small high-frequency fluctuations. In this disclosure, “V DD ” represents the power supply node, and “V SS ” represents the ground node.
[0042] When the gate of the NMOST receives an input, the drain of the NMOST outputs an output, and the source of the NMOST is connected to a ground node (eg, V SS ), it means that this NMOST is configured in a “common source” structure (Topology).
[0043] When the gate of PMOST receives an input, the drain of PMOST outputs an output, and the source of PMOST is connected to a power supply node (e.g., V DD ), it means that this PMOST is configured in a “common source” structure.
[0044] Figure 1 A schematic diagram of a four-phase clock buffer 100 according to an embodiment of the present invention is shown. The four-phase clock buffer 100 receives a four-phase input clock including four phases, namely, phases X1, X2, X3, and X4, and outputs a four-phase output clock including four phases, namely, phases Y1, Y2, Y3, and Y4. The four-phase clock buffer 100 includes four PMOSTs, namely, PMOSTs PM1, PM2, PM3, and PM4, and four NMOSTs, namely, NMOSTs NM1, NM2, NM3, and NM4. The PMOSTs PM1, PM2, PM3, and PM4 are configured in a common source ring structure to send phases Y1, Y2, Y3, and Y4, respectively. The NMOSTs NM1, NM2, NM3, and NM4 are configured in a common source structure to control phases Y1, Y2, Y3, and Y4 according to phases X1, X2, X3, and X4, respectively. The PMOSTs PM1, PM2, PM3 and PM4 have the form of a four-stage ring oscillator, but cannot maintain oscillation because these PMOSTs can pull up but not pull down phases Y1, Y2, Y3 and Y4. The pull-down of phases Y1, Y2, Y3 and Y4 is performed by NMOSTs NM1, NM2, NM3 and NM4 according to phases X1, X2, X3 and X4, respectively.
[0045] In one embodiment, the duty cycle of the four-phase input clock is nominally 25%. Figure 2 An exemplary timing diagram of the four-phase clock buffer 100 is shown. Figure 2As shown, phases X1, X2, X3 and X4 are four phases of a four-phase input clock with a period T, and are evenly distributed in time at intervals of T / 4. Phases Y1, Y2, Y3 and Y4 are four phases of a four-phase output clock with a period T and a 75% duty cycle, and are evenly distributed in time at intervals of T / 4. The low-to-high (Low-to-High, L2H) transition E1 of phase X1 causes NMOST NM1 to pull down phase Y1, resulting in a high-to-low (High-to-Low, H2L) transition E2 of phase Y1. The L2H transition E3 of phase X2 follows the L2H transition E1 of phase X1 at a time of T / 4, and causes NMOST NM2 to pull down phase Y2, resulting in an H2L transition E4 of phase Y2, which in turn causes PMOST PM1 to pull up phase Y1, resulting in an L2H transition E5 of phase Y1. By this method, phase Y1 is pulled down by NMOST NM1 and pulled up by PMOST PM1 after an interval of about T / 4, thereby ensuring a duty cycle of about 75%. The same analysis applies to phases Y2, Y3, and Y4. Since the H2L transition E2 of phase Y1 is driven by the L2H transition E1 of phase X1, and the subsequent L2H transition E5 of phase Y1 is driven by the L2H transition E3 of phase X2, as long as the pull-up of PMOST PM1 is stronger than the pull-down of NMOST NM1 when phase X1 is high and phase Y2 is low, the time interval between the H2L transition E2 and the L2H transition E5 of phase Y1 and the duty cycle of phase Y1 will be determined by the time interval between the L2H transition E1 of phase X1 and the L2H transition E3 of phase X2 (T / 4 due to the four-phase characteristic of the input clock), and has nothing to do with the duty cycles of phases X1 and X2. In other words, if the pull-up of PMOST PM1, PM2, PM3 and PM4 is stronger than the pull-down of NMOST NM1, NM2, NM3 and NM4, even if the duty cycle of the four-phase input clock (including phases X1, X2, X3 and X4) is not 25%, the duty cycle of the four-phase output clock (including phases Y1, Y2, Y3 and Y4) is still about 75%. However, it is better that the duty cycle of the four-phase input clock (including phases X1, X2, X3 and X4) is not greater than 25% to avoid the pull-up of NMOST NM1, NM2, NM3 and NM4 competing with the pull-down of PMOST PM1, PM2, PM3 and PM4 respectively.
[0046] In an optional embodiment, the four-phase clock buffer 100 further includes four additional PMOSTs PM5, PM6, PM7, and PM8. PMOSTs PM5 and PM7 form a first cross-coupling pair (CCP) to cross-couple phases Y1 and Y3, and PMOSTs PM6 and PM8 form a second CCP to cross-couple phases Y2 and Y4. Due to the cross-coupling, PMOSTs PM5 and PM7 ensure that both phases Y1 and Y3 are not low at the same time, while PMOSTs PM6 and PM8 ensure that both phases Y2 and Y4 are not low at the same time. In this way, any of the phases Y1, Y2, Y3, and Y4 cannot remain in a low state for more than 50% of the time, thereby ensuring that the duty cycle of the four-phase output clock does not exceed 50% regardless of the period of the four-phase input clock.
[0047] The four-phase clock buffer 100 can be used to generate a four-phase output clock with a duty cycle of about 75% in response to a four-phase input clock with a duty cycle of about 25% (not necessarily exactly 25%), as described above. If a four-phase output clock with a duty cycle of 25% is required, it can be used Figure 3 . The four-phase clock buffer 300 is modified from the four-phase clock buffer 100 by applying the following changes: (1) replacing NMOST and PMOST, that is, replacing NMOST NM1, NM2, NM3 and NM4 with PMOSTPM1', PM2', PM3' and PM4', respectively, and replacing PMOST PM1, PM2, PM3, PM4, PM5, PM6, PM7 and PM8 with NMOST NM1', NM2', NM3', NM4', NM5', NM6', NM7' and NM8', respectively; and (2) replacing the power supply node V DD and ground node V SS In addition, for the sake of distinction, the phases X1, X2, X3, X4, Y1, Y2, Y3 and Y4 are replaced by the phases A1, A2, A3, A4, B1, B2, B3 and B4, respectively. It can be easily understood by those skilled in the art that the four-phase clock buffer 300 is functionally the same as the four-phase clock buffer 100, but the high state and the low state are swapped (because the power supply node V DD and ground node V SS Therefore, the four-phase output clock (including phases B1, B2, B3 and B4) of the four-phase clock buffer 300 has a duty cycle of approximately 25%, and the duty cycle of the four-phase input clock (including phases A1, A2, A3 and A4) is nominally 75% (not necessarily exactly 75%).
[0048] By using the four-phase clock buffer 100 and the four-phase clock buffer 300 that follows it, a two-stage clock buffer can be implemented, which can output an output clock with a duty cycle of about 25% in response to an input clock with a duty cycle of 25%. By using the four-phase clock buffer 300 and the four-phase clock buffer 100 that follows it, a two-stage clock buffer can be implemented, which can output an output clock with a duty cycle of about 75% in response to an input clock with a duty cycle of 75%. In any case, a multi-stage clock buffer can be constructed by alternately instantiating the four-phase clock buffer 100 and the four-phase clock buffer 300, so that an instance of the four-phase clock buffer 100 follows an instance of the four-phase clock buffer 300, and / or an instance of the four-phase clock buffer 300 follows an instance of the four-phase clock buffer 100.
[0049] In one embodiment, a two-stage four-phase clock buffer includes a first stage and a second stage connected in series. The first stage is exemplified by a four-phase clock buffer 100, and thus includes four PMOSTs (e.g., PMOSTs PM1, PM2, PM3, and PM4) and four NMOSTs (e.g., NMOSTs NM1, NM2, NM3, and NM4), the four PMOSTs of the first stage are configured in a common source ring structure to send a first four-phase clock (e.g., phases Y1, Y2, Y3, and Y4), and the four NMOSTs of the first stage are configured in a common source structure to control the first four-phase clock in response to a second four-phase clock (e.g., phases X1, X2, X3, and X4); the second stage is exemplified by a four-phase clock buffer 300, and includes four NMOSTs (e.g., NMOSTs The four NMOSTs of the second stage are configured in a common source ring structure to send a third four-phase clock (e.g., phases B1, B2, B3 and B4), and the four PMOSTs of the second stage are configured in a common source structure to control the third four-phase clock in response to the first four-phase clock.
[0050] The four-phase clock buffer 100 and the four-phase clock buffer 300 are superior to the inverter buffer in that the duty cycle of the output clock is independent of the duty cycle of the input clock (or at least extremely insensitive to the duty cycle of the input clock). Therefore, in a multi-stage clock buffer constructed by the exemplary four-phase clock buffer 100 and the four-phase clock buffer 300, the errors in the duty cycles of the constituent clock buffers will not be accumulated, and thus the duty cycle of the output clock is extremely insensitive to process, supply voltage and temperature variations.
[0051] Those skilled in the art can easily understand that various changes and modifications can be made to the devices and methods in the present disclosure without departing from the teachings of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only by the scope and limits of the attached claims.
Claims
1. A four-phase clock buffer, comprising: a first P-channel metal oxide semiconductor transistor, a second P-channel metal oxide semiconductor transistor, a third P-channel metal oxide semiconductor transistor, and a fourth P-channel metal oxide semiconductor transistor, arranged in a common source ring structure, respectively used to send a first phase, a second phase, a third phase, and a fourth phase of a four-phase output clock; and A first N-channel metal oxide semiconductor transistor, a second N-channel metal oxide semiconductor transistor, a third N-channel metal oxide semiconductor transistor and a fourth N-channel metal oxide semiconductor transistor are arranged in a common source structure to respectively respond to a first phase, a second phase, a third phase and a fourth phase of a four-phase input clock to respectively control the first phase, the second phase, the third phase and the fourth phase of the four-phase output clock.
2. The four-phase clock buffer as claimed in claim 1, wherein a duty cycle of the four-phase input clock is approximately 25%.
3. The four-phase clock buffer of claim 1 , further comprising a fifth P-channel metal oxide semiconductor transistor, a sixth P-channel metal oxide semiconductor transistor, a seventh P-channel metal oxide semiconductor transistor, and an eighth P-channel metal oxide semiconductor transistor, wherein the fifth P-channel metal oxide semiconductor transistor and the seventh P-channel metal oxide semiconductor transistor are arranged in a cross-coupling structure to cross-couple the first phase and the third phase of the four-phase output clock, and the sixth P-channel metal oxide semiconductor transistor and the eighth P-channel metal oxide semiconductor transistor are arranged in a cross-coupling structure to cross-couple the second phase and the fourth phase of the four-phase output clock.
4. The four-phase clock buffer of claim 1 , wherein a drain of the first P-channel MOS transistor is coupled to a drain of the first N-channel MOS transistor, a drain of the second P-channel MOS transistor is coupled to a drain of the second N-channel MOS transistor, a drain of the third P-channel MOS transistor is coupled to a drain of the third N-channel MOS transistor, and a drain of the fourth P-channel MOS transistor is coupled to a drain of the fourth N-channel MOS transistor.
5. The four-phase clock buffer of claim 4 , wherein the first phase of the four-phase input clock is sent to a gate of the first N-channel metal oxide semiconductor transistor, the second phase of the four-phase input clock is sent to a gate of the second N-channel metal oxide semiconductor transistor, the third phase of the four-phase input clock is sent to a gate of the third N-channel metal oxide semiconductor transistor, and the fourth phase of the four-phase input clock is sent to a gate of the fourth N-channel metal oxide semiconductor transistor.
6. A four-phase clock buffer comprising: a first N-channel metal oxide semiconductor transistor, a second N-channel metal oxide semiconductor transistor, a third N-channel metal oxide semiconductor transistor and a fourth N-channel metal oxide semiconductor transistor, arranged in a common source ring structure, respectively used to send a first phase, a second phase, a third phase and a fourth phase of a four-phase output clock; and A first P-channel metal oxide semiconductor transistor, a second P-channel metal oxide semiconductor transistor, a third P-channel metal oxide semiconductor transistor and a fourth P-channel metal oxide semiconductor transistor are arranged in a common source structure to respectively respond to a first phase, a second phase, a third phase and a fourth phase of a four-phase input clock to respectively control the first phase, the second phase, the third phase and the fourth phase of the four-phase output clock.
7. The four-phase clock buffer of claim 6 , further comprising a fifth N-channel metal oxide semiconductor transistor, a sixth N-channel metal oxide semiconductor transistor, a seventh N-channel metal oxide semiconductor transistor, and an eighth N-channel metal oxide semiconductor transistor, wherein the fifth N-channel metal oxide semiconductor transistor and the seventh N-channel metal oxide semiconductor transistor are arranged in a cross-coupling structure to cross-couple the first phase and the third phase of the four-phase output clock, and the sixth N-channel metal oxide semiconductor transistor and the eighth N-channel metal oxide semiconductor transistor are arranged in a cross-coupling structure to cross-couple the second phase and the fourth phase of the four-phase output clock.
8. The four-phase clock buffer of claim 6 , wherein a drain of the first P-channel MOS transistor is coupled to a drain of the first N-channel MOS transistor, a drain of the second P-channel MOS transistor is coupled to a drain of the second N-channel MOS transistor, a drain of the third P-channel MOS transistor is coupled to a drain of the third N-channel MOS transistor, and a drain of the fourth P-channel MOS transistor is coupled to a drain of the fourth N-channel MOS transistor.
9. The four-phase clock buffer of claim 8 , wherein the first phase of the four-phase input clock is sent to a gate of the first P-channel metal oxide semiconductor transistor, the second phase of the four-phase input clock is sent to a gate of the second P-channel metal oxide semiconductor transistor, the third phase of the four-phase input clock is sent to a gate of the third P-channel metal oxide semiconductor transistor, and the fourth phase of the four-phase input clock is sent to a gate of the fourth P-channel metal oxide semiconductor transistor.
10. A two-stage four-phase clock buffer, comprising a first stage and a second stage connected in series, wherein: The first stage includes four P-channel metal oxide semiconductor transistors and four N-channel metal oxide semiconductor transistors, the four P-channel metal oxide semiconductor transistors of the first stage are arranged in a common source ring structure to send a first four-phase clock, and the four N-channel metal oxide semiconductor transistors of the first stage are arranged in a common source structure to control the first four-phase clock in response to a second four-phase clock, and The second stage includes four P-channel metal oxide semiconductor transistors and four N-channel metal oxide semiconductor transistors. The four N-channel metal oxide semiconductor transistors of the second stage are arranged in a common source ring structure to send a third four-phase clock. The four P-channel metal oxide semiconductor transistors of the second stage are arranged in a common source structure to control the third four-phase clock in response to the first four-phase clock.