Phase-locked loop circuit and display device

Abstract

Embodiments of the present application provide a phase-locked loop circuit and a display device. In the phase-locked loop circuit, after obtaining a temperature adjustment trigger signal, a control circuit outputs a corresponding bandwidth gating signal based on different ambient temperatures, so that a voltage-controlled oscillator corrects a target voltage frequency adjustment curve currently applied by the voltage-controlled oscillator based on different ambient temperatures, so that the target voltage frequency adjustment curve can compensate for errors caused by frequency drift. The voltage-controlled oscillator generates feedback adjustment of the control signal generation circuit based on the voltage frequency adjustment curve, so that the error between the target clock signal output by the voltage-controlled oscillator and the feedback signal generated therefrom and the reference clock signal meets the error standard of the phase-locked loop, and an accurate target clock signal is output. The problem of frequency drift caused by a single voltage frequency adjustment curve in the voltage-controlled oscillator when the ambient temperature changes in the related art is solved, and the stability of the phase-locked loop circuit is improved.

Description

Technical Field

[0001] Embodiments of this application relate to the field of LED displays, and more particularly to a phase-locked loop circuit and display device. Background Technology

[0002] The display device includes a controller, a display panel, and a backlight panel. The controller includes a timing controller, which includes a phase-locked loop circuit. After obtaining image data or video data, the controller outputs backlight driving data based on the clock signal provided by the phase-locked loop circuit to control the backlight panel to provide backlight, and outputs liquid crystal display driving data to control the display panel to display the corresponding image.

[0003] Increased temperature during use of the display device and / or increased ambient temperature can cause frequency drift in the phase-locked loop circuit, affecting the timing accuracy of the timing controller's output data and thus the accuracy of the displayed image.

[0004] Improving the stability of the output clock signal of a phase-locked loop circuit has become a key research focus. Summary of the Invention

[0005] This application provides a phase-locked loop circuit and a display device to solve the above-mentioned technical problems.

[0006] In a first aspect, embodiments of this application provide a phase-locked loop circuit, including:

[0007] Voltage-controlled oscillator, outputting the target clock signal;

[0008] The control signal generation circuit is electrically connected to the reference clock generation circuit and the voltage-controlled oscillator. The control signal generation circuit obtains the reference clock signal and the feedback signal, and outputs the control voltage signal. The feedback signal is a signal generated based on the target clock signal.

[0009] The control circuit is electrically connected to the regulation signal generation circuit. The control circuit obtains the regulation voltage signal and, after obtaining the temperature adjustment trigger signal, outputs a target bandwidth gating signal based on the ambient temperature and the regulation voltage signal.

[0010] The voltage-controlled oscillator is electrically connected to the modulation signal generation circuit and the control circuit. The voltage-controlled oscillator obtains the target bandwidth gating signal and the modulation voltage signal, and corrects the target voltage frequency adjustment curve applied by the voltage-controlled oscillator based on the target bandwidth gating signal.

[0011] The frequency of the target clock signal is adjusted based on the control voltage signal and the target voltage frequency adjustment curve.

[0012] In the above technical solution, in the phase-locked loop circuit, after the control circuit receives the temperature adjustment trigger signal, it outputs a corresponding bandwidth gating signal based on different ambient temperatures. This allows the voltage-controlled oscillator (VCO) to correct the target voltage-frequency regulation curve of the current application based on different ambient temperatures, so that the target voltage-frequency regulation curve can compensate for the error caused by frequency drift. Based on the voltage-frequency regulation curve, the VCO, combined with the feedback adjustment of the control signal generation circuit, ensures that the error between the feedback signal generated corresponding to the target clock signal and the reference clock signal meets the error standard of the phase-locked loop, thus outputting an accurate target clock signal. This solves the problem of frequency drift caused by changes in ambient temperature in the single voltage-frequency regulation curve within the VCO in related technologies, improving the stability of the phase-locked loop circuit.

[0013] Optionally, the voltage-controlled oscillator includes multiple voltage-frequency adjustment curves, and the multiple voltage-frequency adjustment curves correspond to multiple bandwidth gating signals;

[0014] The voltage-controlled oscillator selects the voltage-frequency adjustment curve corresponding to the target bandwidth gating signal from among the multiple voltage-frequency adjustment curves, and uses it as the target voltage-frequency adjustment curve.

[0015] In the above technical solution, by setting multiple voltage frequency adjustment curves in the voltage-controlled oscillator, the accuracy of the correspondence between the frequency of the control voltage signal and the target clock signal based on temperature drift setting under different ambient temperatures can be ensured, thereby ensuring the accuracy of the correction of the target voltage adjustment curve during the operation of the phase-locked loop circuit, so as to improve the accuracy of the target clock signal output by the phase-locked loop circuit.

[0016] Optionally, the control signal generation circuit includes:

[0017] The frequency and phase detector is electrically connected to the reference clock generation circuit and the voltage-controlled oscillator. The frequency and phase detector obtains the reference clock signal and the feedback signal, and outputs the error signal of the reference clock signal and the feedback signal.

[0018] A charge pump is electrically connected to the frequency and phase detector. The charge pump receives the error signal and outputs a first voltage signal.

[0019] The signal conditioning circuit is electrically connected to the charge pump, the control circuit, and the voltage-controlled oscillator. The signal conditioning circuit outputs the regulating voltage signal based on the first voltage signal.

[0020] Optionally, among the plurality of voltage frequency adjustment curves, two adjacent voltage frequency adjustment curves include a first voltage frequency adjustment curve and a second voltage frequency adjustment curve.

[0021] For the same control voltage signal, the first frequency of the control voltage signal in the first voltage frequency adjustment curve is greater than the second frequency of the control voltage signal in the second voltage frequency adjustment curve;

[0022] The minimum frequency of the first voltage frequency adjustment curve is greater than or equal to the maximum frequency of the second voltage frequency adjustment curve.

[0023] In the above technical solution, when the frequency value of the same control voltage signal determined in the first voltage frequency adjustment curve is greater than the frequency value determined in the second voltage frequency adjustment curve, the minimum frequency of the first voltage frequency adjustment curve is greater than the maximum frequency of the second voltage frequency adjustment curve, thus ensuring the continuity of frequency changes between the two curves and ensuring the accuracy of phase-locked loop frequency adjustment.

[0024] Optionally, the first regulating voltage signal corresponds to a third frequency in the first voltage frequency adjustment curve;

[0025] The second control voltage signal corresponds to the third frequency in the second voltage frequency adjustment curve;

[0026] The third frequency is greater than or equal to the minimum frequency of the first voltage frequency adjustment curve;

[0027] The third frequency is less than or equal to the maximum frequency of the second voltage frequency adjustment curve;

[0028] Each of the voltage frequency adjustment curves is correspondingly set with a first temperature threshold and a second temperature threshold;

[0029] After receiving the temperature adjustment trigger signal, when the voltage-controlled oscillator applies the second voltage frequency adjustment curve, and the ambient temperature is greater than or equal to the first temperature threshold corresponding to the second voltage frequency adjustment curve, and the control voltage signal is greater than or equal to the second control voltage signal, the control circuit outputs a first target bandwidth gating signal to enable the voltage-controlled oscillator to apply the first voltage frequency adjustment curve.

[0030] When the voltage-controlled oscillator applies the first voltage-frequency adjustment curve, and the ambient temperature is less than the second temperature threshold corresponding to the first voltage-frequency adjustment curve, and the control voltage signal is less than the first control voltage signal, a second target bandwidth gating signal is output so that the voltage-controlled oscillator applies the second voltage-frequency adjustment curve.

[0031] In the above technical solution, after receiving the temperature adjustment trigger signal, the control circuit determines that the voltage frequency adjustment curve has over-temperature drift when the ambient temperature is greater than or equal to the first temperature threshold corresponding to the voltage frequency adjustment curve currently used by the voltage-controlled oscillator, and the control voltage signal is greater than or equal to the second control voltage signal. It then selects an adjacent voltage frequency adjustment curve with a uniformly increasing frequency value as the current voltage frequency adjustment curve to ensure the voltage-controlled oscillator outputs a larger frequency to meet the frequency output requirements. Conversely, when the ambient temperature is less than the second temperature threshold corresponding to the voltage frequency adjustment curve currently used by the voltage-controlled oscillator, and the control voltage signal is less than the first control voltage signal, it determines that the voltage frequency adjustment curve has over-temperature drift. It then selects an adjacent voltage frequency adjustment curve with a uniformly decreasing frequency value as the current voltage frequency adjustment curve to ensure the voltage-controlled oscillator outputs a smaller frequency to meet the frequency output requirements and ensure the accuracy of the output frequency.

[0032] Optionally, if the temperature adjustment trigger signal is not obtained after the phase-locked loop circuit is started, the control circuit outputs a third target bandwidth gating signal based on the regulation voltage signal;

[0033] The voltage-controlled oscillator determines the corresponding third voltage frequency adjustment curve based on the third target bandwidth gating signal;

[0034] The voltage-controlled oscillator adjusts the frequency of the target clock signal based on the third voltage-frequency adjustment curve and the control voltage signal, so as to lock the phase-locked loop circuit.

[0035] When the phase-locked loop circuit is locked, the phase of the feedback signal generated based on the target clock signal is the same as the phase of the reference clock signal, and the frequency of the feedback signal generated based on the target clock signal is the same as the frequency of the reference clock signal.

[0036] In the above technical solution, after the phase-locked loop circuit starts, if no temperature adjustment trigger signal is obtained, the control circuit controls the voltage-controlled oscillator to select the third voltage frequency adjustment curve based on the adjustment voltage signal. The target clock signal output based on the third voltage frequency adjustment curve is fed back to the frequency and phase detector. This feedback signal can achieve the same target as the reference clock signal, so that the phase-locked loop circuit can quickly lock without considering the influence of ambient temperature factors, thereby improving the adjustment efficiency of the phase-locked loop circuit.

[0037] Optionally, the control circuit outputs the plurality of bandwidth gating signals one by one in a preset order until the phase-locked loop circuit locks;

[0038] The preset order includes either an order in which the value of the bandwidth gating signal increases or an order in which the value of the bandwidth gating signal decreases.

[0039] Optionally, the control circuit includes:

[0040] The temperature sensor, upon receiving the temperature adjustment trigger signal, outputs an ambient temperature signal.

[0041] A voltage sampler is electrically connected to the signal conditioning circuit and the voltage-controlled oscillator. The voltage sampler samples the regulating voltage signal and outputs a control voltage signal. The regulating voltage signal is an analog electrical signal, and the control voltage signal is a digital electrical signal.

[0042] The logic controller is electrically connected to the temperature sensor and the voltage sampler. When the ambient temperature signal is not obtained, the logic controller obtains the control voltage signal and outputs bandwidth gating signals in a preset order until the target bandwidth gating signal is output.

[0043] After obtaining the ambient temperature signal, the logic controller adjusts the target bandwidth gating control signal based on the ambient temperature signal and the control voltage signal.

[0044] Optionally, the phase-locked loop circuit further includes:

[0045] The frequency divider is electrically connected between the frequency and phase detector and the voltage-controlled oscillator. The frequency divider obtains the target clock signal, divides the target clock signal, and outputs the feedback signal.

[0046] In the above technical solution, the frequency divider can increase the frequency range of clock signals that the phase-locked loop circuit can process.

[0047] Optionally, the signal conditioning circuit includes:

[0048] A low-pass filter is electrically connected to the charge pump. The low-pass filter obtains the first voltage signal, filters out the high-frequency components of the first voltage signal, and outputs a second voltage signal.

[0049] The regulating voltage signal is a signal determined based on the second voltage signal.

[0050] In the above technical solution, the low-pass filter can filter out high-frequency noise, smooth control signals, and adjust the loop response time.

[0051] Optionally, the signal conditioning circuit further includes a frequency adjustment module electrically connected between the low-pass filter and the voltage-controlled oscillator;

[0052] When the absolute value of the frequency difference between the feedback signal and the reference clock signal is greater than a preset frequency threshold, the frequency adjustment module outputs a coarse adjustment voltage signal.

[0053] When the absolute value of the frequency difference between the feedback signal and the reference clock signal is less than or equal to the preset frequency threshold, a fine adjustment voltage signal is output.

[0054] The control voltage signal includes either the coarse control voltage signal or the fine control voltage signal.

[0055] In the above technical solution, when the error between the feedback signal and the reference clock signal is large, the frequency adjustment module outputs a coarse adjustment voltage signal to improve the frequency adjustment speed of the voltage-controlled oscillator; after the error between the feedback signal and the reference clock signal is reduced, the frequency adjustment module outputs a fine adjustment voltage signal to ensure the frequency adjustment accuracy of the voltage-controlled oscillator.

[0056] Optionally, the coarse adjustment voltage signal is a preset voltage signal;

[0057] The fine adjustment voltage signal is the second voltage signal.

[0058] Optionally, the frequency adjustment module includes a first controllable switching device and a second controllable switching device;

[0059] The first terminal of the first controllable switching device is electrically connected to the low-pass filter, the second terminal of the first controllable switching device is electrically connected to the voltage-controlled oscillator, the control terminal of the first controllable switching device is electrically connected to the logic controller, and the logic controller is electrically connected to the frequency and phase detector.

[0060] When the absolute value of the frequency difference between the feedback signal and the reference clock signal is greater than the preset frequency threshold, the logic controller outputs a first turn-on control signal and a second turn-off control signal.

[0061] When the absolute value of the frequency difference between the feedback signal and the reference clock signal is less than or equal to the preset frequency threshold, the logic controller outputs a first shutdown control signal and a second turn-on control signal.

[0062] The first controllable switching device turns on when it receives the first turn-on control signal, so as to output the second voltage signal;

[0063] The first controllable switching device turns off when it receives the first turn-off control signal;

[0064] The first terminal of the second controllable switch is electrically connected to the power supply circuit, and the second terminal of the second controllable switch is electrically connected to the voltage-controlled oscillator. The second controllable switch is turned on when it receives the second conduction control signal and outputs the preset voltage signal provided by the power supply circuit.

[0065] The second controllable switching device is turned off when it receives the second turn-off control signal.

[0066] Secondly, this application provides a display device, including a controller, a display panel, and a backlight panel, wherein the controller is electrically connected to the display panel and the backlight panel;

[0067] The controller includes a timing controller, which includes a phase-locked loop circuit as described in any of the claims of the first aspect.

[0068] Optionally, the timing controller outputs a frame header, driving data, and a frame tail sequentially in each frame display cycle, wherein the driving data includes backlight driving data or display driving data.

[0069] The phase-locked loop circuit switches the voltage-frequency regulation curve applied by the voltage-controlled oscillator at the beginning or end of the frame.

[0070] The phase-locked loop (PLL) circuit and display device provided in this application embodiment, in which the control circuit, after receiving the temperature adjustment trigger signal, outputs a corresponding bandwidth gating signal based on different ambient temperatures, so that the voltage-controlled oscillator (VCO) can correct the target voltage-frequency adjustment curve of the VCO based on different ambient temperatures, so that the target voltage-frequency adjustment curve can compensate for the error caused by frequency drift. Based on the voltage-frequency adjustment curve, the VCO, combined with the feedback adjustment of the control signal generation circuit, ensures that the error between the feedback signal generated corresponding to the output target clock signal and the reference clock signal meets the error standard of the PLL, and outputs an accurate target clock signal. This solves the problem of frequency drift caused by the single voltage-frequency adjustment curve in the VCO when the ambient temperature changes in related technologies, and improves the stability of the PLL circuit. Attached Figure Description

[0071] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0072] Figure 1 This is a schematic diagram of the structure of a display device provided in accordance with an exemplary embodiment of this application;

[0073] Figure 2 This is a circuit structure diagram of a conventional phase-locked loop circuit provided in accordance with an exemplary embodiment of this application;

[0074] Figure 3 This is a schematic diagram of the structure of a phase-locked loop circuit provided in an exemplary embodiment of this application;

[0075] Figure 4 This is a schematic diagram of a voltage frequency adjustment curve provided according to an exemplary embodiment of this application;

[0076] Figure 5This is a schematic diagram of the structure of a phase-locked loop circuit provided in another exemplary embodiment of this application;

[0077] Figure 6 This is a schematic diagram of the structure of a phase-locked loop circuit provided in another exemplary embodiment of this application;

[0078] Figure 7 This is a schematic diagram of the phase-locked loop circuit provided in this application according to another exemplary embodiment.

[0079] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0080] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0081] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0082] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0083] A display device is a device that can output images or videos; that is, a device that generates corresponding images based on input image data or video data. A schematic diagram of a display device can be found here. Figure 1As shown, it includes a controller, a display panel 40 and a backlight panel 10. The controller is electrically connected to the display panel 40 and the backlight panel 10. The backlight panel 10 is placed overlapping the display panel 40 and is located on the side of the display surface away from the display panel 40.

[0084] In some embodiments, the controller includes a master controller 30, a timing controller 50, and a dimming controller 20;

[0085] In some embodiments, the circuit connections of the display device are as follows: Figure 1 As shown, the main controller 20 is electrically connected to the timing controller 50, the timing controller 50 is electrically connected to the display panel 40, the timing controller 50 is electrically connected to the dimming controller 20, and the dimming controller 20 is electrically connected to the backlight panel 10.

[0086] After the main controller 30 obtains image data or video data, it outputs liquid crystal display data to the timing controller 50. The timing controller 50 outputs liquid crystal display driving data based on the liquid crystal display data to control the deflection of liquid crystal molecules in the display panel 40.

[0087] After obtaining image data or video data, the main controller 30 outputs backlight brightness data to the timing controller 50. The timing controller 50 outputs backlight control data to the dimming controller 20 based on the backlight brightness data, so that the dimming controller 20 outputs backlight driving data based on the backlight control data, driving the backlight panel 10 to emit light, and the backlight is projected onto the display panel 10 to display the corresponding image.

[0088] Since the LCD driving data and backlight control data output by the timing controller 50 are digital electrical signals transmitted based on a serial protocol, it is necessary to adjust the transmission speed of the data electrical signals based on the clock signal, and also to adjust the consistency of the display process of the display panel 40 and the light emission process of the backlight panel 10 based on the clock signal.

[0089] In some embodiments, the timing controller 50 includes a phase-locked loop circuit 501, which provides a clock signal.

[0090] Figure 2 This is a circuit structure diagram of a conventional phase-locked loop circuit provided in this application according to an exemplary embodiment, such as... Figure 2As shown, the circuit includes a control signal generation circuit 500 and a voltage-controlled oscillator (VCO) 505. The input terminal of the control signal generation circuit 500 is electrically connected to the output terminal of the VCO 505, and the output terminal of the control signal generation circuit 500 is electrically connected to the input terminal of the VCO 505. During the operation of the phase-locked loop (PLL) circuit, the control signal generation circuit 500 obtains the target clock signal output by the VCO 505, compares it with the obtained reference clock signal, and outputs a control voltage signal to adjust the amplitude and frequency of the signal output by the VCO 505, so that the phase and frequency of the clock signal output by the VCO 505 are synchronized with the reference clock signal.

[0091] In some embodiments, the control signal generation circuit 500 includes a frequency and phase detector 502, a charge pump 503, and a low-pass filter 504.

[0092] The input terminal of the frequency and phase detector 502 is electrically connected to the voltage-controlled oscillator 505, the input terminal of the charge pump 503 is electrically connected to the output terminal of the frequency and phase detector 502, the input terminal of the low-pass filter 504 is electrically connected to the output terminal of the charge pump 503, and the output terminal of the low-pass filter 504 is electrically connected to the input terminal of the voltage-controlled oscillator 505.

[0093] During the operation of the phase-locked loop circuit, the frequency and phase detector 502 obtains the clock signal output by the voltage-controlled oscillator 505, compares it with the obtained reference clock signal, and outputs an error signal so that the charge pump 503 and the low-pass filter 504 output the control signal after filtering out high-frequency signals, noise and other signals, thereby controlling the phase and frequency synchronization of the clock signal output by the voltage-controlled oscillator 505 and the reference clock signal.

[0094] Increased temperature during use of the display device and / or increased ambient temperature can cause frequency drift in the phase-locked loop circuit. More specifically, the voltage-controlled oscillator 505 contains a voltage-frequency correspondence. After the temperature rises, the frequency output based on the same control signal decreases compared to the frequency before the temperature rise, causing the output frequency to be inconsistent with the frequency of the reference clock signal. This inconsistency cannot be corrected by negative feedback adjustment of the clock signal, resulting in inaccurate frequency of the output clock signal. This affects the timing accuracy of the timing controller's output data, thereby affecting the accuracy of the displayed image.

[0095] Improving the stability of the output clock signal of a phase-locked loop circuit has become a key research focus.

[0096] To address the aforementioned problems, this application provides a phase-locked loop (PLL) circuit and a display device. The technical concept of this application is as follows: In the PLL circuit, after receiving a temperature adjustment trigger signal, the control circuit outputs a corresponding bandwidth gating signal based on different ambient temperatures. This allows the voltage-controlled oscillator (VCO) to correct the target voltage-frequency adjustment curve of its current application based on different ambient temperatures. This ensures that the target voltage-frequency adjustment curve can compensate for errors caused by frequency drift. Based on the voltage-frequency adjustment curve, the VCO, combined with feedback adjustment from the control signal generation circuit, ensures that the error between the generated feedback signal and the reference clock signal corresponding to its output target clock signal meets the error standard of the PLL, thus outputting an accurate target clock signal. This solves the problem of frequency drift caused by changes in ambient temperature within a single voltage-frequency adjustment curve within the VCO in related technologies, improving the stability of the PLL circuit.

[0097] The circuit structure of the phase-locked loop provided in this application will be explained below. Figure 3 This is a schematic diagram of the phase-locked loop circuit provided in an exemplary embodiment of this application, as shown below. Figure 3 As shown, the phase-locked loop circuit provided in this application embodiment includes: a voltage-controlled oscillator 505, a control signal generation circuit 500, a control circuit 507, and a voltage-controlled oscillator 505.

[0098] The voltage-controlled oscillator 505 is provided with an output terminal, and the voltage-controlled oscillator 505 outputs the target clock signal from its output terminal;

[0099] The control signal generation circuit 500 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the control signal generation circuit 500 is electrically connected or coupled to the reference signal generation circuit. The second input terminal of the control signal generation circuit 500 is electrically connected to the output terminal of the voltage-controlled oscillator 505. The output terminal of the control signal generation circuit 500 is electrically connected to the input terminal of the voltage-controlled oscillator 505. The control signal generation circuit 500 obtains a reference clock signal and a feedback signal, and outputs a control voltage signal, wherein the feedback signal is a signal generated based on the target clock signal.

[0100] In this embodiment, the reference clock generation circuit is the Clock and Data Recovery (CDR) module in the timing controller 50. The CDR module recovers the clock and data signals from the received SOC signal output by the master controller 30, and the recovered clock signal is used as the reference clock signal. In some embodiments, the reference clock generation circuit includes a crystal oscillator.

[0101] The regulating voltage signal is an electrical signal determined based on the error between the reference clock signal and the feedback signal, used to regulate at least one characteristic of the frequency and phase of the output signal of the voltage-controlled oscillator 505.

[0102] The control circuit 507 and the regulation signal generation circuit 500 are electrically connected. The control circuit 507 obtains the regulation voltage signal. After obtaining the temperature regulation trigger signal, it outputs the target bandwidth gating signal based on the ambient temperature and the regulation voltage signal.

[0103] In one embodiment, when the ambient temperature increases, the value of the regulation voltage signal obtained by the control circuit 507 increases; when the ambient temperature decreases, the value of the regulation voltage signal obtained by the control circuit 507 decreases.

[0104] The input terminal of the voltage-controlled oscillator 505 is electrically connected to the modulation signal generation circuit 500, and the control terminal of the voltage-controlled oscillator 505 is electrically connected to the control circuit 507. The voltage-controlled oscillator 505 corrects the target voltage frequency adjustment curve of the voltage-controlled oscillator application based on the target bandwidth gating signal, and adjusts the frequency of the target clock signal based on the modulation voltage signal and the target voltage frequency adjustment curve.

[0105] In the above technical solution, in the phase-locked loop circuit, after the control circuit receives the temperature adjustment trigger signal, it outputs a corresponding bandwidth gating signal based on different ambient temperatures. This allows the voltage-controlled oscillator (VCO) to correct the target voltage-frequency regulation curve of the current application based on different ambient temperatures, so that the target voltage-frequency regulation curve can compensate for the error caused by frequency drift. Based on the voltage-frequency regulation curve, the VCO, combined with the feedback adjustment of the control signal generation circuit, ensures that the error between the feedback signal generated corresponding to the target clock signal and the reference clock signal meets the error standard of the phase-locked loop, thus outputting an accurate target clock signal. This solves the problem of frequency drift caused by changes in ambient temperature in the single voltage-frequency regulation curve within the VCO in related technologies, improving the stability of the phase-locked loop circuit.

[0106] In some embodiments, the voltage-controlled oscillator 505 includes multiple voltage-frequency adjustment curves, and the multiple voltage-frequency adjustment curves correspond to multiple bandwidth gating signals. The voltage-controlled oscillator 505 obtains a target bandwidth gating signal and a control voltage signal, and determines the corresponding target voltage-frequency adjustment curve based on the target bandwidth gating signal.

[0107] In the above technical solution, by setting multiple voltage frequency adjustment curves in the voltage-controlled oscillator, the accuracy of the correspondence between the frequency of the control voltage signal and the target clock signal based on temperature drift setting under different ambient temperatures can be ensured, thereby ensuring the accuracy of the correction of the target voltage adjustment curve during the operation of the phase-locked loop circuit, so as to improve the accuracy of the target clock signal output by the phase-locked loop circuit.

[0108] Continue to refer to Figure 3 In some embodiments of the circuit structure shown, the control signal generation circuit 500 includes a frequency and phase detector 502, a charge pump 503, and a signal conditioning circuit 506.

[0109] The frequency and phase detector 502 has a first input terminal and a second input terminal. The first input terminal of the frequency and phase detector 502 is electrically connected or coupled to the reference clock generation circuit, and the second input terminal of the frequency and phase detector 502 is electrically connected to the output terminal of the voltage-controlled oscillator 505.

[0110] The frequency and phase detector 502 obtains a reference clock signal from its first input terminal and a feedback signal from its second input terminal, and outputs an error signal between the reference clock signal and the feedback signal; the feedback signal is a signal generated based on the target clock signal.

[0111] In some embodiments, the error signal includes at least one of a phase error signal and a frequency error signal.

[0112] In some embodiments, the frequency and phase detector 502 and the voltage-controlled oscillator 505 are electrically connected, the phase of the feedback signal is the same as the phase of the target clock signal, and the frequency of the feedback signal is the same as the frequency of the target clock signal.

[0113] In some embodiments, the frequency and phase detector 502 and the voltage-controlled oscillator 505 are coupled together and electrically connected to a signal processing circuit. The signal processing circuit obtains the target clock signal and generates a feedback signal. The frequency of the feedback signal is determined based on the target clock signal and a preset frequency processing rule, and the phase of the feedback signal is determined based on the target clock signal and a preset phase processing rule.

[0114] In some embodiments, the frequency of the feedback signal is a sub-clock signal within a preset frequency range in the target clock signal;

[0115] In some embodiments, the phase of the feedback signal is the same as the phase of the target clock signal;

[0116] In some embodiments, there is a preset phase difference between the phase of the feedback signal and the phase of the target clock signal.

[0117] The input terminal of the charge pump 503 is electrically connected to the output terminal of the frequency and phase detector 502. The charge pump 503 obtains an error signal and outputs a first voltage signal. The first voltage signal is the initial electrical signal that regulates the frequency of the clock signal output by the voltage-controlled oscillator 505.

[0118] In some embodiments, the first voltage signal and the error signal correspond, and the larger the absolute value of the error signal, the larger the absolute value of the first voltage signal.

[0119] The input terminal of the signal conditioning circuit 506 is electrically connected to the output terminal of the charge pump 503. The signal conditioning circuit 506 obtains a first voltage signal and outputs a control voltage signal; wherein, the control voltage signal is a control signal generated based on the first voltage signal.

[0120] The voltage-controlled oscillator 505 is better at controlling the frequency of the target clock signal based on the control voltage signal than the voltage-controlled oscillator 505 is better at controlling the frequency of the target clock signal based on the first voltage signal.

[0121] The following section further explains the relationship between the multiple voltage-frequency adjustment curves in a voltage-controlled oscillator (VCO), as well as the control circuit and the frequency regulation process of the VCO based on these curves.

[0122] A schematic diagram showing the setting of multiple voltage frequency adjustment curves in a voltage-controlled oscillator 505 is shown below. Figure 4 As shown.

[0123] If the control circuit 507 can provide an n-bit digital strobe signal, then the number of bandwidth strobe signals is 2. n .

[0124] Correspondingly, the number of voltage frequency adjustment curves set in the voltage-controlled oscillator 505 is less than or equal to the number of bandwidth gating signals.

[0125] exist Figure 4 In the schematic diagram shown, the voltage-controlled oscillator 505 has 2 voltage-frequency adjustment curves. n When n is 6, the correspondence between the bandwidth gating signal and the corresponding voltage-frequency adjustment curve (VF curve) is shown in Table 1.

[0126] Table 1

[0127]

[0128] The voltage range of the control voltage signal corresponding to multiple voltage-frequency adjustment curves is the same. For the same control voltage signal, different voltage-frequency adjustment curves determine different frequencies based on the control voltage signal.

[0129] In some embodiments, reference Figure 4 In the schematic diagram shown, for the same control voltage signal, the larger the value of the bandwidth gating signal corresponding to the voltage frequency adjustment curve, the larger the frequency value determined by the control voltage signal in the voltage frequency adjustment curve.

[0130] In other embodiments, for the same control voltage signal, the smaller the value of the bandwidth gating signal corresponding to the voltage frequency adjustment curve, the smaller the frequency value determined by the control voltage signal in the voltage frequency adjustment curve.

[0131] In some embodiments, the trend of the change in the value of the bandwidth gating signal corresponding to the voltage-frequency adjustment curve follows a preset rule as does the trend of the change in the frequency value determined by the same control voltage signal in the voltage-frequency adjustment curve.

[0132] In some embodiments, among multiple voltage frequency adjustment curves, two adjacent voltage frequency adjustment curves include a first voltage frequency adjustment curve and a second voltage frequency adjustment curve. For the same control voltage signal, the first frequency corresponding to the control voltage signal in the first voltage frequency adjustment curve is greater than the second frequency corresponding to the control voltage signal in the second voltage frequency adjustment curve.

[0133] The minimum frequency of the first voltage frequency adjustment curve is greater than or equal to the maximum frequency of the second voltage frequency adjustment curve.

[0134] For example, in the adjacent first voltage frequency adjustment curve VF(1) and second voltage frequency adjustment curve VF(0), for the same control voltage signal, the frequency value determined on VF(1) is always greater than the frequency value determined on VF(0). The minimum frequency value of VF(1) (the value of the minimum control voltage signal VL on VF(1)) is less than or equal to the maximum frequency value of VF(0) (the value of the maximum control voltage signal VH on VF(0)).

[0135] In the above technical solution, when the frequency value of the same control voltage signal determined in the first voltage frequency adjustment curve is greater than the frequency value determined in the second voltage frequency adjustment curve, the minimum frequency of the first voltage frequency adjustment curve is greater than the maximum frequency of the second voltage frequency adjustment curve, thus ensuring the continuity of frequency changes between the two curves and ensuring the accuracy of phase-locked loop frequency adjustment.

[0136] In some embodiments, the first control voltage signal corresponds to the third frequency in the first voltage frequency adjustment curve;

[0137] The second control voltage signal corresponds to the third frequency in the second voltage frequency adjustment curve.

[0138] The third frequency is greater than or equal to the minimum frequency of the first voltage frequency adjustment curve;

[0139] The third frequency is less than or equal to the maximum frequency of the second voltage frequency adjustment curve.

[0140] Continue to refer to Figure 4 The curves shown indicate that the frequency of the control voltage signal V1 determined in the second voltage frequency adjustment curve VF(0) is equal to the frequency of the control voltage signal V2 determined in the first voltage frequency adjustment curve VF(1). This frequency is the third frequency, which is less than or equal to the maximum frequency of the maximum control voltage signal VH determined in the second voltage frequency adjustment curve VF(0), and greater than or equal to the minimum frequency of the minimum control voltage signal VL determined in the first voltage frequency adjustment curve VF(1).

[0141] In some embodiments, the voltage frequency adjustment curves are parallel.

[0142] In some embodiments, the voltage value and frequency of the regulating voltage signal are linearly related in the voltage-frequency regulation curve.

[0143] In some embodiments, V1 = VL + a × (VHVL); V2 = VL + b × (VHVL).

[0144] In some embodiments, a+b=1;

[0145] In some embodiments, V1 can be set to VL + 0.9 × (VHVL), and V2 can be set to VL + 0.1 × (VHVL).

[0146] In some embodiments, each voltage frequency adjustment curve is set with a first temperature threshold and a second temperature threshold.

[0147] After receiving the temperature adjustment trigger signal, when the voltage-controlled oscillator 505 applies the second voltage frequency adjustment curve, and the ambient temperature is greater than or equal to the first temperature threshold corresponding to the second voltage frequency adjustment curve, and the control voltage signal is greater than or equal to the second control voltage signal, the control circuit 507 outputs a first target bandwidth gating signal to enable the voltage-controlled oscillator 505 to apply the first voltage frequency adjustment curve.

[0148] Otherwise, when the voltage-controlled oscillator 505 applies the second voltage frequency adjustment curve and the ambient temperature is less than the first temperature threshold corresponding to the second voltage frequency adjustment curve, the voltage-controlled oscillator 505 continues to apply the second voltage frequency adjustment curve, and the control voltage signal exceeding the second control voltage signal still determines the corresponding frequency in the second voltage frequency adjustment curve.

[0149] Alternatively, when the voltage-controlled oscillator 505 applies the second voltage frequency adjustment curve and the control voltage signal is less than the second control voltage signal, the voltage-controlled oscillator 505 continues to apply the second voltage frequency adjustment curve; no curve change will occur when the ambient temperature is greater than or equal to the first temperature threshold corresponding to the second voltage frequency adjustment curve.

[0150] When the voltage-controlled oscillator 505 applies the first voltage-frequency adjustment curve, and the ambient temperature is less than the second temperature threshold corresponding to the first voltage-frequency adjustment curve, and the control voltage signal is less than the first control voltage signal, it outputs a second target bandwidth gating signal so that the voltage-controlled oscillator 505 applies the second voltage-frequency adjustment curve.

[0151] Otherwise, when the voltage-controlled oscillator 505 applies the first voltage frequency adjustment curve and the ambient temperature is greater than or equal to the second temperature threshold corresponding to the second voltage frequency adjustment curve, the voltage-controlled oscillator 505 continues to apply the first voltage frequency adjustment curve, and the control voltage signal lower than the first control voltage signal still determines the corresponding frequency in the first voltage frequency adjustment curve.

[0152] Alternatively, when the voltage-controlled oscillator 505 applies the first voltage-frequency adjustment curve and the control voltage signal is greater than or equal to the first control voltage signal, the voltage-controlled oscillator 505 maintains the application of the first voltage-frequency adjustment curve; no curve change will occur when the ambient temperature is less than the second temperature threshold corresponding to the first voltage-frequency adjustment curve.

[0153] For example: The relationship between the frequency change and the bandwidth gating signal change in the voltage-frequency adjustment curve is a positive correlation as shown in Figure 4 When the ambient temperature rises, when the ambient temperature ≥ the first temperature threshold corresponding to VF(i), it is judged whether the control voltage signal Vctrol ≥ the V1(i) value of VF(i). When the control voltage signal Vctrol ≥ V1(i), the bandwidth gating signal output by the control circuit 507 is incremented by 1, and the voltage-frequency adjustment curve applied in the voltage-controlled oscillator 505 changes from the curve VF(i) to the curve VF(i + 1);

[0154] When the control voltage signal Vctrol < V1(i), the bandwidth gating signal output by the control circuit 507 remains unchanged, and the voltage-controlled oscillator 505 continues to maintain the curve VF(i).

[0155] When the ambient temperature rise < the first temperature threshold, the bandwidth gating signal output by the control circuit 507 remains unchanged, and the voltage-controlled oscillator 505 continues to maintain the curve VF(i).

[0156] When the ambient temperature drops, when the ambient temperature ≤ the second temperature threshold corresponding to VF(i), it is judged whether the control voltage signal Vctrol ≤ the V2(i) value of VF(i). When the control voltage signal Vctrol ≤ V2(i), the bandwidth gating signal output by the control circuit 507 is decremented by 1, and the voltage-frequency adjustment curve applied in the voltage-controlled oscillator 505 changes from the curve VF(i) to the curve VF(i - 1);

[0157] When the control voltage signal Vctrol > V2(i), the bandwidth gating signal output by the control circuit 507 remains unchanged, and the control circuit 507 continues to maintain the curve VF(i).

[0158] When the ambient temperature > the second temperature threshold, the bandwidth gating signal output by the control circuit 507 remains unchanged, and the control circuit 507 continues to maintain the curve VF(i).

[0159] In the above technical solution, after receiving the temperature adjustment trigger signal, the control circuit determines that the voltage frequency adjustment curve has over-temperature drift when the ambient temperature is greater than or equal to the first temperature threshold corresponding to the voltage frequency adjustment curve currently used by the voltage-controlled oscillator, and the control voltage signal is greater than or equal to the second control voltage signal. It then selects an adjacent voltage frequency adjustment curve with a uniformly increasing frequency value as the current voltage frequency adjustment curve to ensure the voltage-controlled oscillator outputs a larger frequency to meet the frequency output requirements. Conversely, when the ambient temperature is less than the second temperature threshold corresponding to the voltage frequency adjustment curve currently used by the voltage-controlled oscillator, and the control voltage signal is less than the first control voltage signal, it determines that the voltage frequency adjustment curve has over-temperature drift. It then selects an adjacent voltage frequency adjustment curve with a uniformly decreasing frequency value as the current voltage frequency adjustment curve to ensure the voltage-controlled oscillator outputs a smaller frequency to meet the frequency output requirements and ensure the accuracy of the output frequency.

[0160] In some embodiments, after the phase-locked loop circuit is started, if no temperature adjustment trigger signal is obtained, the control circuit 507 outputs a third target bandwidth gating signal based on the regulation voltage signal.

[0161] In some embodiments, if the phase-locked loop circuit is located in the display device, the phase-locked loop circuit will start when the display device is started. If the control circuit 507 does not receive the temperature adjustment trigger signal, the control circuit 507 will only output the third target bandwidth gating signal based on the regulation voltage signal.

[0162] The voltage-controlled oscillator 505 determines the corresponding third voltage frequency adjustment curve based on the third target bandwidth gating signal;

[0163] The voltage-controlled oscillator 505 adjusts the frequency of the target clock signal based on the third voltage-frequency adjustment curve and the control voltage signal to lock the phase-locked loop circuit.

[0164] When the phase-locked loop circuit is locked, the phase of the feedback signal generated based on the target clock signal is the same as the phase of the reference clock signal, and the frequency of the feedback signal generated based on the target clock signal is the same as the frequency of the reference clock signal.

[0165] After the phase-locked loop circuit is locked, the control circuit 507 obtains a temperature adjustment trigger signal, so that the phase-locked loop circuit can perform corresponding regulation based on the frequency regulation method performed after obtaining the temperature adjustment trigger signal in the aforementioned embodiment.

[0166] In some embodiments, the voltage-controlled oscillator 505 does not output a lock signal when the phase-locked loop circuit is not locked; the voltage-controlled oscillator 505 outputs a lock signal after the phase-locked loop circuit is locked. This lock signal can be used as a temperature adjustment trigger signal.

[0167] In the above technical solution, after the phase-locked loop circuit starts, if no temperature adjustment trigger signal is obtained, the control circuit controls the voltage-controlled oscillator to select the third voltage frequency adjustment curve based on the adjustment voltage signal. The target clock signal output based on the third voltage frequency adjustment curve is fed back to the frequency and phase detector. This feedback signal can achieve the same target as the reference clock signal, so that the phase-locked loop circuit can quickly lock without considering the influence of ambient temperature factors, thereby improving the adjustment efficiency of the phase-locked loop circuit.

[0168] In some embodiments, the control circuit 507 outputs multiple bandwidth gating signals one by one in a preset order until the phase-locked loop circuit locks;

[0169] The preset sequence includes either an increasing or decreasing order of the bandwidth gating signal values.

[0170] In some embodiments, the control circuit 507 is provided with a frequency direction selection module, which is used to set the preset order, wherein the preset order is adjustable.

[0171] In some embodiments, when the preset order of the frequency direction selection module is the order of increasing values, after the display device is started, the control circuit 507 of the voltage-controlled oscillator 505 outputs an n-bit bandwidth strobe signal starting from 0 based on the preset order of the frequency direction selection module. Then, the voltage frequency adjustment curve of the voltage-controlled oscillator 505 changes successively according to VF(0), VF(1), VF(2), VF(3)... until the phase-locked loop circuit is locked. When the phase-locked loop circuit is locked, the voltage-controlled oscillator 505 determines the third voltage frequency adjustment curve.

[0172] In some embodiments, the third voltage frequency adjustment curve is 2 from small to large. n The first voltage-frequency adjustment curve is the curve that corresponds to the target frequency of the target clock signal, which is the reference frequency set by the reference clock signal.

[0173] For example, if the frequency and phase detector 502 and the voltage-controlled oscillator 505 are electrically connected or coupled, and the phase-locked loop circuit is locked, the frequency of the feedback signal generated based on the reference clock signal is the same as the frequency of the target clock signal, and the phase of the reference clock signal is the same as the phase of the feedback signal. Therefore, the third voltage-frequency adjustment curve is the curve with the smallest corresponding bandwidth gating signal among the multiple voltage-frequency adjustment curves that can realize the frequency of the reference clock signal.

[0174] In other embodiments, when the preset order set by the frequency direction selection module is a decreasing numerical order, after the display device is started, the control circuit 507, based on the preset order set by the frequency direction selection module, selects the voltage-controlled oscillator 505 from (2... n-1) Starting by sequentially decreasing the output n-bit bandwidth gating signal, the voltage-controlled oscillator 505's voltage-frequency regulation curve follows VF(2 n -1), VF(2) n -2), VF(2) n -3), VF(2) n -4)……The changes are made one by one until the phase-locked loop circuit is locked. When the phase-locked loop circuit is locked, the voltage-controlled oscillator 505 determines the third voltage frequency adjustment curve.

[0175] In some embodiments, the third voltage frequency adjustment curve is a 2 from large to small. n The first voltage-frequency adjustment curve is the curve that corresponds to the target frequency of the target clock signal, which is the reference frequency set by the reference clock signal.

[0176] For example, if the frequency and phase detector 502 and the voltage-controlled oscillator 505 are electrically connected or coupled, and the phase-locked loop circuit is locked, the frequency of the feedback signal generated based on the reference clock signal is the same as the frequency of the target clock signal, and the phase of the reference clock signal is the same as the phase of the feedback signal. Therefore, the third voltage frequency adjustment curve is the curve with the largest bandwidth gating signal among the multiple voltage frequency adjustment curves that can achieve the frequency of the reference clock signal.

[0177] In some embodiments, the timing controller outputs a frame header, driving data and a frame tail sequentially in each frame display cycle, and the driving data includes backlight driving data or display driving data.

[0178] Voltage-frequency regulation curves of phase-locked loop circuits used in switching voltage-controlled oscillators at the beginning or end of frames.

[0179] In some embodiments, reference Figure 5 The circuit structure shown includes a control circuit 507, which includes a temperature sensor 5071. After receiving a temperature adjustment trigger signal, the temperature sensor 5071 outputs an ambient temperature signal.

[0180] Temperature sensor 5071 either does not work or works but does not output an ambient temperature signal when it does not receive a temperature adjustment trigger signal.

[0181] In some embodiments, the control circuit 507 includes a voltage sampler 5072 and a logic controller 5073. The input terminal of the voltage sampler 5072 is electrically connected to the output terminal of the signal conditioning circuit 506 and the input terminal of the voltage-controlled oscillator 505. The output terminal of the voltage sampler 5072 is electrically connected to the input terminal of the logic controller 5073. The voltage sampler 5072 samples the regulating voltage signal and outputs a control voltage signal; wherein, the regulating voltage signal is an analog electrical signal and the control voltage signal is a digital electrical signal.

[0182] In some embodiments, the voltage sampling circuit 5072 includes an analog-to-digital converter circuit for converting the sampled analog electrical signal (regulating voltage signal) into a digital electrical signal to meet the input requirements of the logic controller 5073.

[0183] In some embodiments, the voltage sampling circuit 5072 further includes a voltage divider circuit. The input terminal of the voltage divider circuit is electrically connected to the output terminal of the signal conditioning circuit 506, and the output terminal of the voltage divider circuit is electrically connected to the input terminal of the analog-to-digital converter circuit. The voltage divider circuit divides the voltage value of the control voltage signal, and the divided electrical signal is used as the sampled voltage value to meet the input range of the analog-to-digital converter circuit.

[0184] The input terminal of the logic controller 5073 is also electrically connected to the temperature sensor 5071. When the ambient temperature signal is not obtained, the logic controller 5073 obtains the control voltage signal and outputs the bandwidth gating signal in a preset order until the target bandwidth gating signal is output. This process is the same as the process of determining the third voltage frequency adjustment curve based on the frequency direction selection module in the previous embodiment, and will not be described again here.

[0185] After obtaining the ambient temperature signal, the logic controller 5073 adjusts the target bandwidth gating control signal based on the ambient temperature signal and the control voltage signal. This process is the same as that in the previous embodiment, after the control circuit 507 obtains the temperature trigger signal, it outputs the target bandwidth gating signal based on the ambient temperature and the aforementioned control voltage signal, and will not be described again here.

[0186] In some embodiments, reference Figure 6 The circuit structure shown includes a phase-locked loop circuit that also includes a frequency divider 508.

[0187] The input terminal of frequency divider 508 is electrically connected to the output terminal of voltage-controlled oscillator 505, and the output terminal of frequency divider 508 is electrically connected to the second input terminal of frequency and phase detector 502. Frequency divider 508 obtains the target clock signal, divides the target clock signal, and outputs a feedback signal.

[0188] In some embodiments, the frequency of the feedback signal output by the frequency divider 508 is less than the frequency of the target clock signal.

[0189] In the above technical solution, the frequency divider 508 can increase the frequency range of clock signals that the phase-locked loop circuit can process.

[0190] In some embodiments, the signal conditioning circuit 506 includes a low-pass filter 504, the input terminal of the low-pass filter 504 and the output terminal of the charge pump 503 are electrically connected, the low-pass filter 504 obtains a first voltage signal, filters out the high-frequency components of the first voltage signal, and outputs a second voltage signal.

[0191] The regulating voltage signal is a signal determined based on the second voltage signal.

[0192] In the above technical solution, the low-pass filter can filter out high-frequency noise, smooth control signals, and adjust the loop response time.

[0193] In some embodiments, the output terminal of the low-pass filter 504 serves as the output terminal of the signal conditioning circuit 506, and the voltage signal is adjusted to be the second voltage signal.

[0194] In some embodiments, reference Figure 7 The circuit structure shown includes a signal conditioning circuit 506 that further includes a frequency adjustment module 509. The first terminal of the frequency adjustment module 509 is electrically connected to the output terminal of the low-pass filter 504, and the second terminal of the frequency adjustment module 509 is electrically connected to the input terminal of the voltage-controlled oscillator 505.

[0195] When the absolute value of the frequency difference between the feedback signal and the reference clock signal is greater than a preset frequency threshold, the frequency adjustment module 509 outputs a coarse adjustment voltage signal.

[0196] When the absolute value of the frequency difference between the feedback signal and the reference clock signal is less than or equal to a preset frequency threshold, a fine adjustment voltage signal is output.

[0197] The voltage control signal includes a coarse adjustment voltage signal or a fine adjustment voltage signal.

[0198] In the above technical solution, when the error between the feedback signal and the reference clock signal is large, the frequency adjustment module outputs a coarse adjustment voltage signal to improve the frequency adjustment speed of the voltage-controlled oscillator; after the error between the feedback signal and the reference clock signal is reduced, the frequency adjustment module outputs a fine adjustment voltage signal to ensure the frequency adjustment accuracy of the voltage-controlled oscillator.

[0199] In some embodiments, the coarse adjustment voltage signal is a preset voltage signal;

[0200] The fine adjustment voltage signal is the second voltage signal.

[0201] In some embodiments, the frequency adjustment module 509 includes a first controllable switching device S1 and a second controllable switching device S2;

[0202] The first terminal of the first controllable switching device S1 is electrically connected to the output terminal of the low-pass filter 504, the second terminal of the first controllable switching device S1 is electrically connected to the input terminal of the voltage-controlled oscillator 505, the control terminal of the first controllable switching device S1 is electrically connected to the logic controller 5073, and the logic controller 5073 is electrically connected to the first and second input terminals of the frequency and phase detector 502.

[0203] When the absolute value of the frequency difference between the feedback signal and the reference clock signal is greater than a preset frequency threshold, the logic controller 5073 outputs a first turn-on control signal and a second turn-off control signal.

[0204] When the absolute value of the frequency difference between the feedback signal and the reference clock signal is less than or equal to a preset frequency threshold, the logic controller 5073 outputs a first shutdown control signal and a second turn-on control signal.

[0205] The first controllable switching device S1 turns on when it receives the first conduction control signal, so as to output the second voltage signal;

[0206] The first controllable switching device S1 is turned off when it receives the first turn-off control signal;

[0207] The first terminal of the second controllable switch S2 is electrically connected to the power supply circuit Vref, and the second terminal of the second controllable switch S2 is electrically connected to the voltage-controlled oscillator 505. The second controllable switch S2 is turned on when it receives the second turn-on control signal and outputs the preset voltage signal provided by the power supply circuit Vref.

[0208] The second controllable switching device S2 is turned off when it receives the second turn-off control signal.

[0209] This application also provides a display device, the circuit structure of which is as follows: Figure 1 As shown, it includes a controller, a display panel 40, and a backlight panel 10, and the controller is electrically connected to the display panel 40 and the backlight panel 10.

[0210] In some embodiments, the controller includes a master controller 30 and a timing controller 50, wherein the timing controller 50 includes the phase-locked loop circuit 501 in the foregoing embodiments.

[0211] In some embodiments, the timing controller 50 sequentially outputs a frame header, driving data and a frame tail in each frame display cycle, and the driving data includes backlight driving data or display driving data.

[0212] The voltage-frequency regulation curve of the phase-locked loop circuit 501 in the application of switching voltage-controlled oscillators at the beginning or end of the frame.

[0213] In the above technical solution, the phase-locked loop circuit switches the voltage-frequency adjustment curve of the voltage-controlled oscillator at the beginning or end of the frame, thus avoiding data loss or abnormality caused by changes in the voltage-frequency adjustment curve during data transmission.

[0214] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0215] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A phase-locked loop circuit, characterized by comprising: The application relates to a phase-locked loop circuit, comprising: a voltage-controlled oscillator outputting a target clock signal, wherein the voltage-controlled oscillator comprises a plurality of voltage-frequency adjustment curves, in adjacent two voltage-frequency adjustment curves, for the same control voltage signal, the corresponding frequency in a first voltage-frequency adjustment curve is greater than the corresponding frequency in a second voltage-frequency adjustment curve, and the minimum frequency of the first voltage-frequency adjustment curve is greater than or equal to the maximum frequency of the second voltage-frequency adjustment curve; a control signal generation circuit electrically connected with a reference clock generation circuit and the voltage-controlled oscillator, the control signal generation circuit obtains a reference clock signal and a feedback signal, and outputs a control voltage signal; the feedback signal is a signal generated based on the target clock signal; a control circuit electrically connected with the control signal generation circuit, the control circuit comprises a temperature sensor and a voltage sampler, after obtaining a temperature control trigger signal, the temperature sensor collects an ambient temperature and outputs a temperature signal, the voltage sampler samples the control voltage signal and outputs a digital voltage signal, and the control circuit outputs a target bandwidth gating signal based on the combination logic of the temperature signal and the digital voltage signal, wherein only when the ambient temperature exceeds the temperature threshold corresponding to the current curve and the control voltage signal exceeds the corresponding voltage threshold, the adjacent voltage-frequency adjustment curve is switched to; the voltage-controlled oscillator and the control signal generation circuit and the control circuit are electrically connected, the voltage-controlled oscillator obtains the target bandwidth gating signal and the control voltage signal, and corrects the target voltage-frequency adjustment curve applied by the voltage-controlled oscillator based on the target bandwidth gating signal; the frequency of the target clock signal is adjusted based on the control voltage signal and the target voltage-frequency adjustment curve; the phase-locked loop circuit is used for a timing controller of a display device, the timing controller sequentially outputs a frame head, driving data and a frame tail in each frame display period, and the phase-locked loop circuit switches the target voltage-frequency adjustment curve applied by the voltage-controlled oscillator at the frame head or the frame tail. The first control voltage signal corresponds to a third frequency in the first voltage frequency adjustment curve; the second control voltage signal corresponds to the third frequency in the second voltage frequency adjustment curve; the third frequency is greater than or equal to the minimum frequency of the first voltage frequency adjustment curve; the third frequency is less than or equal to the maximum frequency of the second voltage frequency adjustment curve; each of the voltage frequency adjustment curves corresponds to a first temperature threshold and a second temperature threshold; after the temperature control trigger signal is obtained, when the voltage controlled oscillator applies the second voltage frequency adjustment curve and the ambient temperature is greater than or equal to the first temperature threshold corresponding to the second voltage frequency adjustment curve and the control voltage signal is greater than or equal to the second control voltage signal, the control circuit outputs a first target bandwidth selection signal to make the voltage controlled oscillator apply the first voltage frequency adjustment curve; when the voltage controlled oscillator applies the first voltage frequency adjustment curve and the ambient temperature is less than the second temperature threshold corresponding to the first voltage frequency adjustment curve and the control voltage signal is less than the first control voltage signal, the control circuit outputs a second target bandwidth selection signal to make the voltage controlled oscillator apply the second voltage frequency adjustment curve; in each of the voltage frequency adjustment curves, the voltage value and the frequency of the corresponding control voltage signal are in a linear relationship.

2. The phase-locked loop circuit of claim 1, wherein, The plurality of voltage frequency adjustment curves and the plurality of bandwidth selection signals correspond to each other; The voltage controlled oscillator selects, from the plurality of voltage frequency adjustment curves, a voltage frequency adjustment curve corresponding to the target bandwidth selection signal as the target voltage frequency adjustment curve.

3. The phase-locked loop circuit of claim 2, wherein, The control signal generation circuit comprises: A phase frequency detector, which is electrically connected to the reference clock generation circuit and the voltage controlled oscillator, obtains the reference clock signal and the feedback signal, and outputs an error signal of the reference clock signal and the feedback signal; A charge pump, which is electrically connected to the phase frequency detector, obtains the error signal, and outputs a first voltage signal; A signal conditioning circuit, which is electrically connected to the charge pump, the control circuit, and the voltage controlled oscillator, outputs the control voltage signal based on the first voltage signal.

4. The phase-locked loop circuit of claim 3, wherein, After the phase-locked loop circuit is started and the temperature control trigger signal is not obtained, the control circuit outputs a third target bandwidth selection signal based on the control voltage signal; The voltage controlled oscillator determines a third voltage frequency adjustment curve corresponding to the third target bandwidth selection signal; The voltage controlled oscillator adjusts the frequency of the target clock signal based on the third voltage frequency adjustment curve and the control voltage signal, so that the phase-locked loop circuit is locked. When the phase-locked loop circuit is locked, the phase of the feedback signal generated based on the target clock signal is the same as the phase of the reference clock signal, and the frequency of the feedback signal generated based on the target clock signal is the same as the frequency of the reference clock signal.

5. The phase-locked loop circuit of claim 4, wherein, The control circuit outputs the plurality of bandwidth selection signals in a preset order one by one until the phase-locked loop circuit is locked. The preset order comprises an order of increasing values of the bandwidth selection signals or an order of decreasing values of the bandwidth selection signals.

6. The phase-locked loop circuit of claim 4, wherein, The temperature sensor outputs an ambient temperature signal after obtaining the temperature adjustment trigger signal; The voltage sampler is electrically connected with the signal conditioning circuit and the voltage controlled oscillator; The control circuit further comprises a logic controller which is electrically connected with the temperature sensor and the voltage sampler, and obtains a control voltage signal when the ambient temperature signal is not obtained, and outputs the bandwidth selection signals according to a preset order until the target bandwidth selection signal is outputted; The logic controller adjusts the target bandwidth selection control signal based on the ambient temperature signal and the control voltage signal after obtaining the ambient temperature signal.

7. The phase-locked loop circuit of claim 3, wherein, The phase-locked loop circuit further comprises: A frequency divider which is electrically connected between the frequency discriminator and phase discriminator and the voltage controlled oscillator, obtains the target clock signal, divides the target clock signal, and outputs the feedback signal.

8. The phase-locked loop circuit of claim 3, wherein, The signal conditioning circuit comprises: A low-pass filter which is electrically connected with the charge pump, obtains the first voltage signal, filters high-frequency components of the first voltage signal, and outputs a second voltage signal; The control voltage signal is a signal determined based on the second voltage signal.

9. The phase-locked loop circuit of claim 8, wherein, The signal conditioning circuit further comprises a frequency adjustment module which is electrically connected between the low-pass filter and the voltage controlled oscillator; The frequency adjustment module outputs a coarse adjustment voltage signal when an absolute value of a frequency difference between the feedback signal and the reference clock signal is greater than a preset frequency threshold value; The frequency adjustment module outputs a fine adjustment voltage signal when the absolute value of the frequency difference between the feedback signal and the reference clock signal is less than or equal to the preset frequency threshold value; The control voltage signal comprises the coarse adjustment voltage signal or the fine adjustment voltage signal.

10. The phase-locked loop circuit of claim 9, wherein The coarse adjustment voltage signal is a preset voltage signal; The fine adjustment voltage signal is the second voltage signal.

11. The phase-locked loop circuit of claim 9, wherein, The frequency adjustment module comprises a first controllable switching device and a second controllable switching device; A first end of the first controllable switching device is electrically connected with the low-pass filter, a second end of the first controllable switching device is electrically connected with the voltage controlled oscillator, a control end of the first controllable switching device is electrically connected with a logic controller, and the logic controller is electrically connected with the frequency discriminator; The logic controller outputs a first conduction control signal and a second turn-off control signal when the absolute value of the frequency difference between the feedback signal and the reference clock signal is greater than the preset frequency threshold value; The logic controller outputs a first turn-off control signal and a second conduction control signal when the absolute value of the frequency difference between the feedback signal and the reference clock signal is less than or equal to the preset frequency threshold value; The first controllable switching device is turned on to output the second voltage signal when the first conduction control signal is obtained; The first controllable switching device is turned off when the first turn-off control signal is obtained. The first end of the second controllable switching device is electrically connected with the power supply circuit, the second end of the second controllable switching device is electrically connected with the voltage-controlled oscillator, and the second controllable switching device is turned on when the second turn-on control signal is obtained, and outputs a preset voltage signal provided by the power supply circuit; The second controllable switching device is turned off when the second turn-off control signal is obtained.

12. A display device comprising: The display panel, the backlight plate, and the controller are electrically connected. The controller comprises a timing controller, and the timing controller comprises the phase-locked loop circuit according to any one of claims 1 to 11.

13. The display device of claim 12, wherein, The timing controller sequentially outputs a frame header, driving data, and a frame trailer in each frame display period, and the driving data comprises backlight driving data or display driving data. The phase-locked loop circuit switches the voltage frequency adjustment curve applied by the voltage-controlled oscillator at the frame header or the frame trailer.

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