Multi-channel analog pulse amplitude sampling circuit

Abstract

The invention discloses a multichannel analog pulse amplitude sampling circuit which comprises an analog circuit, a signal sampling circuit and a digital circuit, and multiple signal processing circuits in the analog circuit share one signal sampling circuit and one digital circuit. Each signal processing circuit comprises a pre-amplifier, a pole-zero cancellation circuit, a filtering shaping circuit and a signal triggering and extracting circuit. Wherein the signal triggering and extracting circuit is composed of a peak holding circuit, a proportional amplifying circuit and a voltage comparator, signal peak acquisition is completed, and signals before and after acquisition are compared, so that signal amplitude and triggering signals are obtained. The trigger signal of each channel instructs the digital circuit to control the ADC to sample its signal amplitude. The multi-channel analog pulse amplitude sampling circuit is powered by a single power supply, and DC offset and a signal base line are adjusted by using a DAC, so that the voltage utilization range of signal amplification is expanded. The power consumption and the cost are reduced by reducing the number of operational amplifiers used in the analog circuit.

Description

Technical Field

[0001] The invention belongs to the field of nuclear signal detection and processing, and in particular relates to a multi-channel analog pulse amplitude sampling circuit. Background Art

[0002] In the current context of globalization, nuclear technology has been widely used in many key fields such as energy, industry, agriculture, and medical care, greatly promoting social and economic development. Nuclear technology is inseparable from energy spectrum measurement. Nuclear energy spectrum measurement technology is mainly used to measure and analyze the energy distribution of particles emitted by nuclear radiation sources, so as to obtain information about the types, abundance, reaction mechanisms, and material composition of radioactive nuclides. The acquisition of energy spectrum is usually achieved by statistically analyzing the histogram of pulse amplitude. Pulse amplitude refers to the height of the pulse signal, which is usually proportional to the energy of the incident particle or ray. The multi-channel pulse amplitude analyzer is an instrument used to measure the amplitude distribution of pulse signals and is an important component of the nuclear energy spectrum measurement system.

[0003] Multi-channel pulse amplitude analyzers are generally divided into analog multi-channel pulse amplitude analyzers and digital multi-channel pulse amplitude analyzers. The main difference between them lies in the way the signal is processed. Digital multi-channel pulse amplitude analyzers convert the received analog signals into digital form for processing. They usually have higher accuracy and flexibility, and are convenient for data storage and analysis, but they often have high power consumption and complex circuits. Analog multi-channel pulse amplitude analyzers directly process analog signals. Although their accuracy is relatively low, they usually have simple circuit structures, fast response speeds, low power consumption and costs, and are difficult to replace in systems with a large number of channels.

[0004] Multi-channel analog pulse amplitude analyzers usually include a preamplifier, a filter shaping circuit, a peak holding circuit, etc. The operational amplifier in the existing multi-channel analog pulse amplitude sampling circuit generally uses a dual power supply to enable the signal to be amplified in both the positive and negative half cycles, but the dual power supply will increase power consumption and may require more space to accommodate additional power components and wiring. At the same time, in the peak holding circuit, a trigger signal needs to be generated by a fast shaping circuit and transmitted to a microcontroller or FPGA. The microcontroller or FPGA compares the output signal of the fast shaping circuit with the set detection threshold. If a signal higher than the set threshold is detected, the peak holder is controlled to discharge after a delay, thereby resetting. Under this circuit design, the entire circuit requires too many chips, and the circuit design is more complicated, resulting in increased circuit power consumption and cost. Summary of the invention

[0005] The present invention aims to solve the technical problems existing in the background technology, and aims to provide a multi-channel analog pulse amplitude sampling circuit. Compared with the existing multi-channel analog pulse amplitude analyzer, it has a simpler circuit structure, lower power consumption and lower cost; the circuit includes an analog circuit, a signal sampling circuit and a digital circuit. The signal processing circuit in the analog circuit processes N signals (N≥1) through N signal processing circuits, and each signal processing circuit is composed of a preamplifier, a pole-zero phase cancellation circuit, a filter shaping circuit, and a signal triggering and extraction circuit. Each signal triggering and extraction circuit is composed of a peak holding circuit, a proportional amplification circuit and a voltage comparator. When a pulse signal arrives, a trigger is generated by comparing the signals before and after the peak holding circuit. No additional signal processing circuit is required. After receiving the trigger signal, the FPGA or MCU outputs a reset signal after a delay to control the peak holding circuit to discharge, thereby resetting. The signal sampling circuit is composed of a multi-channel analog switch and an ADC. N signal processing circuits share a signal sampling circuit and a digital circuit. The ADC required for the signal sampling circuit is reduced by time-sharing sampling. The digital circuit is composed of FPGA or MCU and DAC. The DAC is used to adjust the DC offset and signal baseline of the operational amplifier in the signal processing circuit to maximize the voltage range of signal amplification.

[0006] In order to solve the technical problem, the technical solution of the present invention is:

[0007] A multi-channel analog pulse amplitude sampling circuit, the circuit comprising: an analog circuit, a signal sampling circuit and a digital circuit; the analog circuit interacts with the digital circuit, the signal processing circuit signal is connected to the signal sampling circuit, the signal sampling circuit signal is connected to the digital circuit, and the digital circuit is connected to a host computer;

[0008] The analog circuit includes N signal processing circuits, N≥1, all including: a preamplifier, a pole-zero cancellation circuit, a filter shaping circuit, a signal trigger and extraction circuit; the signal trigger and extraction circuits all include a peak holding circuit, a proportional amplifier circuit and a voltage comparator; the digital circuit includes: an FPGA or an MCU, a DAC, and the DC offset and signal baseline of the operational amplifier in the signal processing circuit are adjusted by the DAC; when a pulse signal arrives, a trigger is generated by comparing the signals before and after the peak holding circuit, and after receiving the trigger signal, the FPGA or MCU outputs a signal after a delay to control the peak holding circuit to discharge, thereby resetting; the signal sampling circuit includes a multi-channel analog switch and an ADC, and the N signal processing circuits share a signal sampling circuit and a digital circuit.

[0009] Furthermore, the preamplifier is connected to an external signal, the input end of the pole-zero cancellation circuit is connected to the output end of the preamplifier, the output end of the pole-zero cancellation circuit is connected to the input end of the filter shaping circuit, the output end of the filter shaping circuit is connected to the signal triggering and extraction circuit, and the signal triggering and extraction circuit outputs.

[0010] Furthermore, the signal output from the filter shaping circuit enters the peak holding circuit. At this stage, the amplitude of the signal is maintained until the FPGA or MCU controls its discharge; the maintained signal then flows into the proportional amplifier circuit to further amplify the signal; wherein, the two input terminals of the voltage comparator are connected to the signal: the negative input terminal is connected to the input of the peak holding circuit; the positive input terminal is connected to the output of the proportional amplifier circuit; the peak holding circuit is connected to a switch, and the other end of the switch is grounded. When the FPGA or MCU receives a trigger signal, the switch is controlled to be turned on, that is, grounded, to complete the discharge and reset of the peak holding circuit; or each peak holding circuit output terminal is grounded through a field effect tube. When the FPGA or MCU receives a trigger signal, a high level is output to the gate of the field effect tube, so that the peak holding circuit is discharged and reset through the field effect tube.

[0011] Furthermore, when the nuclear pulse signal arrives, it specifically includes: first arriving at the negative input terminal of the voltage comparator after the filter shaping circuit, and then arriving at the positive input terminal of the voltage comparator after the proportional amplifier circuit, generating a region where the filter shaping signal is higher than the peak hold shaping signal. At this time, the voltage comparator outputs a negative signal for triggering, that is, a trigger signal. After the FPGA or MCU detects the trigger signal, it delays the peak hold shaping signal to maintain it for a period of time, and then delays the output of a reset signal to control the peak hold circuit to discharge and reset its state; when the peak hold shaping signal is discharged, a second filter shaping signal will be generated in a region where the peak hold shaping signal is higher than the peak hold shaping signal, and the voltage comparator will output a negative signal again, that is, the acquisition end mark signal, indicating that the signal acquisition is over.

[0012] Further, the digital circuit includes: a first DAC, a second DAC and a third DAC; one end of the first DAC is connected to the FPGA or MCU, and the other end is connected to the preamplifier, one end of the second DAC is connected to the FPGA or MCU, and the other end is connected to the filter shaping circuit, and one end of the third DAC is connected to the FPGA or MCU, and the other end is connected to the proportional amplifier circuit;

[0013] The first DAC is used to adjust the DC offset of the preamplifier, the second DAC is used to adjust the signal baseline in the filter shaping circuit, and the third DAC is used to adjust the trigger threshold of the proportional amplifier circuit.

[0014] Furthermore, the multi-channel analog switch inputs the signal amplitude sent by the signal processing circuit and the control signal sent by the FPGA or MCU, and the ADC samples the signals of the channels of the multi-channel analog switch and sends them to the digital circuit after analog-to-digital conversion.

[0015] Furthermore, when the FPGA or MCU receives a trigger signal from a certain channel, it controls the multi-channel analog switch to connect the channel where the signal is located, so that the ADC samples the signal of the channel; when the ADC is sampling the signal of a certain channel, if other channels also detect the trigger signal, the FPGA or MCU will extend the peak hold time of other channels and wait for the ADC to sample one after another. When the ADC completes sampling the signal of a certain channel, the FPGA or MCU controls the peak hold circuit of this channel to discharge and reset; when multiple channels generate trigger signals at the same time, the FPGA or MCU controls the multi-channel analog switch to enable the ADC to sample the signal in order from the smallest number of channels to the largest number of channels.

[0016] Compared with the prior art, the advantages of the present invention are:

[0017] A new minimalist circuit structure is proposed. A signal triggering and extraction circuit is composed of a peak holding circuit, a proportional amplifier circuit and a voltage comparator. The trigger is generated by comparing the signals before and after the peak holding circuit. No additional signal processing circuit is required, which greatly simplifies the circuit structure and reduces power consumption and cost.

[0018] The DAC is used to adjust the DC offset and signal baseline of the op amp in the signal processing circuit to maximize the voltage range of the signal amplification, avoiding signal distortion when the op amp is powered by a single power supply. The op amps in the circuit are all powered by a single power supply, which simplifies the circuit structure and reduces power consumption and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 , a framework diagram of a complete circuit in an embodiment of the present invention;

[0020] Figure 2 , a circuit diagram of a signal processing circuit in an embodiment of the present invention;

[0021] Figure 3 , input signal and output signal waveform diagram of the voltage comparator of the signal triggering and extraction circuit in the embodiment of the present invention. DETAILED DESCRIPTION

[0022] The specific implementation mode of the present invention is described below in conjunction with embodiments:

[0023] It should be noted that the structures, proportions, sizes, etc. shown in this specification are only used to match the contents disclosed in the specification so that people familiar with this technology can understand and read them, and are not used to limit the conditions under which the present invention can be implemented. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0024] At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" cited in this specification are only for the convenience of description and are not used to limit the scope of implementation of the present invention. Changes or adjustments to their relative relationships should be regarded as the scope of implementation of the present invention without substantially changing the technical content.

[0025] Embodiment 1:

[0026] Figure 1 This is a complete framework diagram of a multi-channel analog pulse amplitude sampling circuit, which consists of N signal processing circuits (N≥1), multi-channel analog switches, ADC, DAC, FPGA or MCU, and PC. The signal amplitude of each signal processing circuit is sampled by the ADC after passing through the multi-channel analog switch, and the ADC is sent to the FPGA or MCU after sampling, and the FPGA or MCU is sent to the PC through the serial port. In this process, the FPGA or MCU also controls the multi-channel analog switch to select the route, sends a reset signal to the peak holding circuit in each channel, controls the DAC to input the DC offset to the preamplifier, adjusts the signal baseline in the Gaussian filter circuit, and adjusts the trigger threshold of the proportional amplifier circuit.

[0027] like Figure 2 As shown in FIG. 1 , it is a circuit diagram of a signal processing circuit, which is composed of a preamplifier, a pole-zero phase cancellation circuit, a filter shaping circuit, and a signal triggering and extraction circuit. The first-stage preamplifier can also be used as a same-phase or reverse amplifier circuit by selecting different connection modes as needed, and it can be input with a DC offset through a DAC.

[0028] The preamplifier signal obtained after the signal passes through the preamplifier has a long attenuation time.

[0029] The attenuation time of the pole-zero cancellation signal obtained after the preamplifier signal passes through the pole-zero cancellation circuit becomes shorter.

[0030] After the pole-zero cancellation signal passes through the filtering and shaping circuit, the noise in the signal is effectively removed, making the signal smooth.

[0031] The signal baseline of the filter shaping circuit can be adjusted by DAC. The signal triggering and extraction circuit consists of a peak holding circuit, a proportional amplifier circuit and a voltage comparator. After the signal passes through the peak holding circuit and maintains the peak value for a period of time, the FPGA or MCU controls its discharge. The proportional amplifier circuit can adjust the trigger threshold through the DAC, and after amplifying the peak holding signal, the signal sampling circuit can better collect the amplitude of the signal. The two input ends of the voltage comparator are respectively connected before the peak holding circuit and after the proportional adjustment circuit. Whenever the nuclear pulse signal comes, the voltage comparator will generate a signal to the FPGA or MCU. After a delay, the FPGA or MCU outputs a signal to control the peak holder to discharge, thereby resetting. The signal amplitude output by the signal triggering and extraction circuit is then input to the ADC for sampling via a multi-channel analog switch.

[0032] The position where the input terminal of the voltage comparator used in this example is connected is only for illustration of the nature of the example, that is, the position where the voltage comparator used to generate the trigger signal is connected is not limited to that shown in the schematic diagram. The connection mode and number of the ADC and DAC used are also only for illustration of the nature of the example, that is, the connection mode and number of the ADC used for sampling and the DAC for adjusting the DC offset, signal baseline and trigger threshold are not limited to those shown in the schematic diagram, and the staff in this field can make appropriate adjustments according to actual needs.

[0033] like Figure 3 As shown in the figure, it is a waveform diagram of the input and output of the voltage comparator. The filter shaping signal is the negative input terminal signal, and the peak hold shaping signal is the positive input terminal signal. When there is no nuclear pulse signal, the negative terminal voltage is slightly higher than the positive terminal voltage. When the nuclear pulse signal arrives, it first reaches the negative input terminal of the voltage comparator after the filter shaping circuit, and then reaches the positive input terminal of the voltage comparator after the proportional amplifier circuit, resulting in a region where the filter shaping signal is higher than the peak hold shaping signal. At this time, the voltage comparator outputs a negative signal for triggering, that is, a trigger signal. After the FPGA or MCU detects this signal, it delays and keeps the peak hold shaping signal for a period of time before controlling the peak hold circuit to discharge; when the peak hold shaping signal is discharged, a second region where the filter shaping signal is higher than the peak hold shaping signal will be generated, and the voltage comparator will output a negative signal, that is, a collection end mark signal, indicating that the signal collection is over.

[0034] The waveform diagram of the voltage comparator in this example is merely an illustrative description, that is, the waveform diagram may vary depending on the different connection positions of the voltage comparator.

[0035] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in this field without departing from the purpose of the present invention.

[0036] Many other changes and modifications may be made without departing from the concept and scope of the present invention.It should be understood that the present invention is not limited to the specific embodiments, and the scope of the present invention is defined by the appended claims.

Claims

1. A multi-channel analog pulse amplitude sampling circuit, characterized in that: The circuit includes: an analog circuit, a signal sampling circuit and a digital circuit; the analog circuit interacts with the digital circuit, the signal processing circuit signal is connected to the signal sampling circuit, the signal sampling circuit signal is connected to the digital circuit, and the digital circuit is connected to the host computer; The analog circuit includes N signal processing circuits, N≥1, all including: a preamplifier, a pole-zero cancellation circuit, a filter shaping circuit, a signal trigger and extraction circuit; the signal trigger and extraction circuits all include a peak holding circuit, a proportional amplifier circuit and a voltage comparator; the digital circuit includes: an FPGA or an MCU, a DAC, and the DC offset and signal baseline of the operational amplifier in the signal processing circuit are adjusted by the DAC; when a pulse signal arrives, a trigger is generated by comparing the signals before and after the peak holding circuit, and after receiving the trigger signal, the FPGA or MCU outputs a signal after a delay to control the peak holding circuit to discharge, thereby resetting; the signal sampling circuit includes a multi-channel analog switch and an ADC, and the N signal processing circuits share a signal sampling circuit and a digital circuit.

2. A multi-channel analog pulse amplitude sampling circuit according to claim 1, characterized in that: The preamplifier is connected to an external signal, the input end of the pole-zero cancellation circuit is connected to the output end of the preamplifier, the output end of the pole-zero cancellation circuit is connected to the input end of the filter shaping circuit, the output end of the filter shaping circuit is connected to the signal triggering and extraction circuit, and the signal triggering and extraction circuit outputs.

3. A multi-channel analog pulse amplitude sampling circuit according to claim 1, characterized in that: The signal output from the filter shaping circuit enters the peak holding circuit. At this stage, the amplitude of the signal is maintained until the FPGA or MCU controls its discharge; the maintained signal then flows into the proportional amplifier circuit to further amplify the signal; wherein, the two input terminals of the voltage comparator are connected to the signal: the negative input terminal is connected to the input of the peak holding circuit; the positive input terminal is connected to the output of the proportional amplifier circuit; the peak holding circuit is connected to a switch, and the other end of the switch is grounded. When the FPGA or MCU receives a trigger signal, the switch is controlled to be turned on, that is, grounded, to complete the discharge and reset of the peak holding circuit; or each peak holding circuit output terminal is grounded through a field effect tube. When the FPGA or MCU receives a trigger signal, a high level is output to the gate of the field effect tube, so that the peak holding circuit is discharged and reset through the field effect tube.

4. The multi-channel analog pulse amplitude sampling circuit according to claim 1, characterized in that: When the nuclear pulse signal arrives, it specifically includes: first arriving at the negative input terminal of the voltage comparator after the filter shaping circuit, and then arriving at the positive input terminal of the voltage comparator after the proportional amplifier circuit, generating a region where the filter shaping signal is higher than the peak hold shaping signal. At this time, the voltage comparator outputs a negative signal for triggering, that is, a trigger signal. After the FPGA or MCU detects the trigger signal, it delays the peak hold shaping signal to maintain it for a period of time, and then delays the output of a reset signal to control the peak hold circuit to discharge and reset its state; when the peak hold shaping signal is discharged, a second filter shaping signal will be generated in a region where the peak hold shaping signal is higher than the peak hold shaping signal, and the voltage comparator will output a negative signal again, that is, the acquisition end mark signal, indicating that the signal acquisition is over.

5. The multi-channel analog pulse amplitude sampling circuit according to claim 3, characterized in that: The digital circuit comprises: a first DAC, a second DAC and a third DAC; one end of the first DAC is connected to the FPGA or MCU, and the other end is connected to the preamplifier; one end of the second DAC is connected to the FPGA or MCU, and the other end is connected to the filter shaping circuit; one end of the third DAC is connected to the FPGA or MCU, and the other end is connected to the proportional amplification circuit; The first DAC is used to adjust the DC offset of the preamplifier, the second DAC is used to adjust the signal baseline in the filter shaping circuit, and the third DAC is used to adjust the trigger threshold of the proportional amplifier circuit.

6. The multi-channel analog pulse amplitude sampling circuit according to claim 1, characterized in that: The multi-channel analog switch inputs the signal amplitude sent by the signal processing circuit and the control signal sent by the FPGA or MCU. The ADC samples the signals of the channels of the multi-channel analog switch and sends them to the digital circuit after analog-to-digital conversion.

7. The multi-channel analog pulse amplitude sampling circuit according to claim 1, characterized in that: When the FPGA or MCU receives a trigger signal from a certain channel, it controls the multi-channel analog switch to connect the channel where the signal is located, so that the ADC samples the signal of the channel; When the ADC is sampling a channel signal, if other channels also detect trigger signals, the FPGA or MCU will extend the peak hold time of other channels and wait for the ADC to sample one after another. When the ADC completes sampling a channel signal, the FPGA or MCU controls the peak hold circuit of this channel to discharge and reset; when multiple channels generate trigger signals at the same time, the FPGA or MCU controls the multi-channel analog switch to enable the ADC to sample signals in order from the smallest number of channels to the largest number of channels.

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