Clock synchronization system and method, switch and storage medium
By designing a clock synchronization system, using a clock server and a multi-stage PTP switch, time synchronization between subsystems supported by the PTP and NTP protocol is realized, solving the problem of time out-of-synchronization and improving timing accuracy.
Patent Information
- Application Number
- CN202411909086.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-24
- Publication Date
- 2025-02-25
AI Technical Summary
In the control system, the subsystems supported by the PTP and NTP clock synchronization protocols are not consistent with the synchronization accuracy and time reference source, resulting in time out of synchronization.
Design a clock synchronization system to realize time synchronization between subsystems supported by the PTP and NTP protocol through a clock server and a multi-stage PTP switch. The PTP switch contains a hardware clock module, supports PTP and NTP protocol modules, and performs time synchronization through hardware timestamps.
Time synchronization between subsystems supported by PTP and NTP protocol is realized, which improves the timing accuracy of subsystems supported by NTP protocol, and avoids the problem of inconsistent time reference sources.
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Figure CN119519880A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of clock synchronization technology, and in particular to a clock synchronization system, method, switch and storage medium. Background Art
[0002] In some control systems, multiple control subsystems may be included, and among these control subsystems, some control subsystems only support PTP clock synchronization protocol (Precision Time Protocol, precision clock synchronization protocol standard for network measurement and control systems), while other control subsystems only support NTP clock synchronization protocol (Network Time Protocol, a protocol for synchronizing device clocks in computer networks). In the prior art, the PTP clock synchronization protocol uses an independent PTP hardware clock and its synchronization accuracy is at the sub-microsecond level, while the NTP clock synchronization protocol uses a system clock and its synchronization accuracy is usually at the 100ms level, which will lead to the problem of time asynchrony between various control subsystems in the same control system. Summary of the invention
[0003] In view of this, the embodiments of the present application provide a clock synchronization system, method, switch and storage medium, which can realize time synchronization between a subsystem supporting the PTP clock synchronization protocol and a subsystem supporting the NTP clock synchronization protocol and improve the time synchronization accuracy of the subsystem supporting the NTP clock synchronization protocol.
[0004] In a first aspect, an embodiment of the present application provides a clock synchronization system, comprising: a clock server, a plurality of PTP switches connected in sequence, and a subsystem connected to each level of the PTP switch; wherein the subsystem connected to the PTP switch comprises a first subsystem supporting a PTP clock synchronization protocol and a second subsystem supporting an NTP clock synchronization protocol;
[0005] The clock server is used to publish timing information to at least one PTP switch connected to the clock server;
[0006] The PTP switch includes a hardware clock module, which is used to receive the timing information of the clock server or the adjacent upper-level PTP switch, and synchronize the timing information to the hardware clock module;
[0007] The PTP switch is further used to provide time to the connected first subsystem and / or the second subsystem based on the timing information of the hardware clock module.
[0008] In some embodiments, the PTP switch further includes a PTP protocol module and an NTP protocol module;
[0009] The PTP switch obtains hardware timestamp information from the hardware clock module through the PTP protocol module based on the PTP clock synchronization protocol, and publishes the timing information to the adjacent next-level PTP switch and / or the corresponding first subsystem; wherein the timing information includes the hardware timestamp information;
[0010] The PTP switch obtains the hardware timestamp information from the hardware clock module through the NTP protocol module based on the NTP clock synchronization protocol, and publishes the timing information to the corresponding second subsystem; wherein the timing information includes the hardware timestamp information.
[0011] In some embodiments, the clock server includes at least one first master port; the PTP switch includes at least one first slave port and at least one second master port; the first subsystem includes at least one second slave port; the second subsystem includes at least one third slave port;
[0012] The clock server publishes the timing information to the PTP switch connected to the clock server through the first master port;
[0013] The PTP switch receives the timing information of the clock server or the PTP switch of the adjacent upper level through the first slave port;
[0014] The PTP switch publishes the timing information to the adjacent next-level PTP switch through the second master port;
[0015] The PTP switch publishes the timing information to the first subsystem and / or the second subsystem through the second master port;
[0016] The first subsystem receives the timing information issued by the PTP switch through the second slave port;
[0017] The second subsystem receives the timing information published by the PTP switch through the second slave port.
[0018] In some embodiments, the first subsystem and the second subsystem are train control subsystems.
[0019] In a second aspect, an embodiment of the present application provides a clock synchronization method, which is applied to a PTP switch of the above-mentioned clock synchronization system, including:
[0020] Receive the timing information from the clock server or the PTP switch of the adjacent upper level in real time, and synchronize the timing information to the hardware clock module;
[0021] When timing the adjacent next-level PTP switch and subsystem connected to the current PTP switch, timing information is sent to the adjacent next-level PTP switch and the first subsystem in real time, so that the clocks of the adjacent next-level PTP switch and the first subsystem are synchronized with the clock of the current PTP switch; wherein the timing information includes hardware timestamp information;
[0022] When providing time to a second subsystem connected to the current PTP switch, in response to a clock synchronization request message of the second subsystem, after obtaining the hardware timestamp information from the hardware clock module based on the NTP clock synchronization protocol, the timing information is published to the second subsystem so that the second subsystem performs clock synchronization according to the timing information.
[0023] In some embodiments, it also includes: when starting the PTP switch, establishing a connection between the hardware clock module and the PTP protocol module, and a connection between the hardware clock module and the NTP protocol module, so that when the timing information is released through the PTP protocol module and the NTP protocol module, the hardware timestamp information can be obtained from the hardware clock module.
[0024] In some embodiments, in response to the clock synchronization request message of the second subsystem, after obtaining the hardware timestamp information from the hardware clock module based on the NTP clock synchronization protocol, issuing timing information to the second subsystem so that the second subsystem performs clock synchronization according to the timing information includes:
[0025] receiving the clock synchronization request message sent by the second subsystem, and generating a second timestamp; wherein the clock synchronization request message carries the first timestamp of the second subsystem;
[0026] Sending a clock synchronization response message carrying the first timestamp, the second timestamp, and the third timestamp to the second subsystem, so that the second subsystem determines the time difference according to the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp received in the clock synchronization response message, and performs clock calibration according to the time difference;
[0027] Among them, the second timestamp is the hardware timestamp information obtained from the hardware clock module when the PTP switch receives the clock synchronization request message; the third timestamp is the hardware timestamp information obtained from the hardware clock module when the clock synchronization response message is sent to the second subsystem.
[0028] In some embodiments, the formula for determining the time difference is: offset = (T2-T1) + (T3-T4)] / 2.
[0029] Among them, the offset is the time difference between the second subsystem and the PTP switch; T1 is the first timestamp; T2 is the second timestamp; T3 is the third timestamp; T4 is the fourth timestamp.
[0030] In a third aspect, an embodiment of the present application provides a PTP switch, the PTP switch comprising a processor and a memory, the memory storing a computer program, and the processor being used to execute the computer program to implement the above-mentioned clock synchronization method.
[0031] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program, which implements the above-mentioned clock synchronization method when executed on a processor.
[0032] The embodiments of the present application have the following beneficial effects: all PTP switch clock sources in the present application are clock sources provided by the clock server. In addition, since the PTP switch includes a hardware clock module, time synchronization is performed based on the timestamp provided by the hardware clock module for the subsystem supporting the PTP protocol and the subsystem supporting the NTP protocol, that is, the subsystem supporting the PTP protocol and the subsystem supporting the NTP protocol use the same PTP hardware clock source, thereby avoiding the problem of inconsistent time reference sources caused by the PTP protocol using an independent PTP hardware clock and the NTP protocol using an independent system clock in the prior art; further, in the present application, when time calibration is performed on the subsystem supporting the NTP clock synchronization protocol, hardware timestamps are used for calibration, thereby improving the time synchronization accuracy of the subsystem supporting the NTP clock synchronization protocol. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0034] Figure 1 A schematic diagram of clock synchronization of a train control system is shown;
[0035] Figure 2 A schematic diagram of the structure of a clock synchronization system according to an embodiment of the present application is shown;
[0036] Figure 3 A first flow chart of a clock synchronization method according to an embodiment of the present application is shown;
[0037] Figure 4 A second flow chart of the clock synchronization method according to an embodiment of the present application is shown;
[0038] Figure 5 A schematic diagram of the clock synchronization principle of the second subsystem in an embodiment of the present application is shown. DETAILED DESCRIPTION
[0039] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.
[0040] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0041] Hereinafter, the terms "including", "having" and their cognates that can be used in various embodiments of the present application are intended only to indicate specific features, numbers, steps, operations, elements, components or a combination of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or a combination of the foregoing items or increasing the possibility of one or more features, numbers, steps, operations, elements, components or a combination of the foregoing items. In addition, the terms "first", "second", "third" and the like are only used to distinguish descriptions and cannot be understood as indicating or implying relative importance.
[0042] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.
[0043] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.
[0044] In some control systems, there may be multiple control subsystems, and among these control subsystems, some control subsystems only support the PTP clock synchronization protocol, while others only support the NTP clock synchronization protocol. Figure 1The train control system shown in the figure has different clock synchronization protocols supported by its subsystems ( Figure 1 The train control subsystem marked with NTP protocol supports the NTP clock synchronization protocol, and the train control subsystem marked with PTP protocol supports the NTP clock synchronization protocol. Figure 1 The port marked with M is the master port, and the port marked with S is the slave port), which will cause the problem of inconsistent time between the subsystems. In order to synchronize the time between the subsystems and meet the time accuracy requirements of all subsystems, in this embodiment, the time synchronization between the subsystems is achieved by making each subsystem have the same time reference source.
[0045] The NTP clock synchronization protocol uses the system clock and its synchronization accuracy is usually at the 100ms level; while the PTP clock synchronization protocol uses an independent PTP hardware clock and its synchronization accuracy is at the sub-microsecond level.
[0046] Among them, PTP (Precision Time Protocol) is defined by the IEEE 1588 standard and is a time synchronization protocol that can be used for high-precision time synchronization and frequency synchronization between devices. PTP uses bidirectional timestamps to accurately measure the round-trip time of data packets by exchanging synchronization and follow-up messages between master and slave clocks. In this process, the advanced hardware timestamp unit can directly mark the time when the data packet enters and leaves the network port, greatly reducing the uncertainty introduced by the operating system and ensuring the accuracy of time measurement.
[0047] The clock synchronization system is described below in conjunction with some specific embodiments.
[0048] Figure 2 A structural schematic diagram of a clock synchronization system of an embodiment of the present application is shown. Exemplarily, the clock synchronization system includes: a clock server 100, multiple stages of PTP switches 200 connected in sequence, and a subsystem connected to each stage of the PTP switch 200; wherein the subsystem connected to the PTP switch 200 includes a first subsystem 300 supporting the PTP clock synchronization protocol and a second subsystem 400 supporting the NTP clock synchronization protocol.
[0049] Among them, the first subsystem 300 and the second subsystem 400 can be train control subsystems; such as automatic train protection system (ATP), automatic train control system (ATC), automatic train operation system (ATO), automatic train supervision system (ATS), data communication system (DCS), onboard computer system (Onboard Computer System), passenger information system (PIS) and power management system (Power Management System), etc.
[0050] The clock server 100 and the PTP switch 200 communicate with each other through the PTP clock synchronization protocol, and two adjacent PTP switches 200 communicate with each other through the PTP clock synchronization protocol.
[0051] It should be noted that the following description is that if the timing information is released through the PTP clock synchronization protocol, it is PTP timing information, and if the timing information is released through the NTP clock synchronization protocol, it is NTP timing information.
[0052] The clock server 100 is used to publish timing information to at least one PTP switch 200 connected to the clock server 100 .
[0053] The clock server 100 runs a high-precision stable clock source and outputs clock information from the master port to the PTP switch 200 connected thereto through the PTP protocol. It can be understood that the time of the entire system is determined based on the clock source in the clock server 100.
[0054] The clock server 100 can be connected to only one PTP switch 200, or it can be connected to multiple PTP switches 200. If the clock server 100 is connected to only one PTP switch 200, the clock server 100 only needs to publish timing information to the connected PTP switch 200; if the clock server 100 is connected to multiple PTP switches 200, the clock server 100 can simultaneously publish timing information to multiple PTP switches 200 connected thereto through different main ports. Although, if the timing information received by each PTP switch 200 is sent from the clock server 100, the time in each PTP switch 200 will be more accurate, but usually, in order to avoid the difficulty of wiring, only one PTP switch 200 is connected through the clock server 100, and time synchronization is performed to other PTP switches 200 through this one PTP switch 200.
[0055] The PTP switch 200 includes a hardware clock module, which is used to receive timing information from the clock server 100 or the adjacent upper-level PTP switch 200, and synchronize the timing information to the hardware clock module.
[0056] It can be understood that the PTP switch 200 supports a high-precision stable PTP hardware clock, that is, it has a built-in high-precision hardware timestamp unit, which can directly mark the hardware timestamp when the data packet enters and exits the network port. The accuracy of this hardware timestamp is much higher than the timestamp of the system clock. Therefore, this embodiment can significantly improve the accuracy of clock synchronization.
[0057] The PTP switch 200 includes at least one first slave port and at least one second master port. The PTP switch 200 receives timing information from the clock server 100 or an adjacent upper-level PTP switch 200 through the first slave port.
[0058] It can be understood that in this embodiment, the master port is used to publish timing information, and the slave port is used to receive timing information. The PTP switch 200 connected to the clock server 100 receives the timing information published by the clock server 100 through its first slave port, and synchronizes to the hardware clock module of the current PTP switch 200 through the timing information, so that the time of the PTP switch 200 is synchronized with the time of the clock server 100.
[0059] Since each PTP switch 200 may be connected to a next-level PTP switch 200, the PTP switch 200 can publish timing information to the next-level PTP switch 200 through its own second master port, and the published timing information is provided by its own hardware clock module. Figure 2Both sides of the PTP switch 200 connected to the clock server 100 are connected to other PTP switches 200. In this way, the previous-level PTP switch 200 publishes timing information to the next-level PTP switch 200, and after the next-level PTP switch 200 receives the timing information, it synchronizes the timing information to its own hardware clock module. In this way, the time of all PTP switches 200 can be synchronized, and the synchronized time is the time of the high-precision clock source provided by the clock server 100.
[0060] The PTP switch 200 is also used to provide time to the connected first subsystem 300 and / or second subsystem 400 based on the timing information of the hardware clock module.
[0061] The first subsystem 300 includes at least one second slave port; the second subsystem 400 includes at least one third slave port. The PTP switch 200 publishes timing information to the first subsystem 300 and / or the second subsystem 400 through the second master port; the first subsystem 300 receives the timing information published by the PTP switch 200 through the second slave port; the second subsystem 400 receives the timing information published by the PTP switch 200 through the second slave port.
[0062] It can be understood that each subsystem includes at least one slave port for receiving timing information issued by the PTP switch 200 connected to the subsystem, so as to synchronize the time of the subsystem with the time of the PTP switch 200. The same PTP switch 200 can be connected to multiple subsystems. Among the multiple subsystems connected to the same PTP switch 200, all can be subsystems that only support the PTP clock synchronization protocol, all can be subsystems that only support the NTP clock synchronization protocol, and can also include both subsystems that support the PTP clock synchronization protocol and subsystems that support the NTP clock synchronization protocol.
[0063] In addition, the PTP switch 200 also includes a PTP protocol module and an NTP protocol module; the PTP protocol module is used to support the release of timing information of subsystems that only support the PTP clock synchronization protocol, and the NTP protocol module is used to support the release of timing information of subsystems that only support the NTP clock synchronization protocol. The PTP switch 200 obtains hardware timestamp information from the hardware clock module through the PTP protocol module based on the PTP clock synchronization protocol, and releases the timing information to the adjacent next-level PTP switch 200 and / or the corresponding first subsystem 300; the PTP switch 200 obtains hardware timestamp information from the hardware clock module through the NTP protocol module based on the NTP clock synchronization protocol, and releases the timing information to the corresponding second subsystem 400. Among them, the timing information includes hardware timestamp information; the timing information includes hardware timestamp information.
[0064] It can be understood that no matter it is the PTP switch 200, the subsystem supporting the PTP clock synchronization protocol, or the subsystem supporting the NTP clock synchronization protocol, the timing information obtained all comes from the same PTP hardware clock source, so the problem of inconsistent time reference source can be avoided. In addition, when performing time synchronization, the hardware timestamp is used, which further improves the accuracy of clock synchronization.
[0065] Figure 3 A schematic flow chart of a clock synchronization method according to an embodiment of the present application is shown. Exemplarily, the clock synchronization method is applied to a PTP switch in the above-mentioned clock synchronization system, and the method includes:
[0066] Step S100, receiving the timing information of the clock server or the adjacent upper-level PTP switch in real time, and synchronizing the timing information to the hardware clock module.
[0067] If the PTP switch is connected to the clock server, it directly obtains the timing information from the clock server, that is, the clock server publishes the timing information to the PTP switch connected to it through the PTP clock synchronization protocol. After the PTP switch receives the timing information published by the PTP switch, it synchronizes the timing information to the hardware clock module, thereby achieving time synchronization with the clock server. If the PTP switch is not connected to the clock server, but is connected to the upper-level PTP switch, the upper-level PTP switch obtains the hardware timestamp information from its own hardware clock module through the PTP clock synchronization protocol, and places the hardware timestamp information into the timing information for publication. After receiving the timing information, it synchronizes the timing information to its own hardware clock module, thereby achieving time synchronization with the upper-level PTP switch.
[0068] In some implementations, when the PTP switch is started, a connection between the hardware clock module and the PTP protocol module, and a connection between the hardware clock module and the NTP protocol module are established, so that when the timing information is released through the PTP protocol module and the NTP protocol module, the hardware timestamp information can be obtained from the hardware clock module.
[0069] When timing is provided to the adjacent next-level PTP switch and subsystem connected to the current PTP switch, step S200 is executed to send a timing information message to the adjacent next-level PTP switch and the first subsystem in real time, so that the clocks of the adjacent next-level PTP switch and the first subsystem are synchronized with the clock of the current PTP switch.
[0070] For the first subsystem and PTP switch supporting the PTP clock synchronization protocol, when performing clock synchronization, the current PTP switch will send a timing information message to the adjacent next-level PTP switch and the first subsystem in real time, and the timing information message includes hardware timestamp information. After the next-level PTP switch and the first subsystem receive the timing information, they adjust their own time according to the timing information, thereby synchronizing the clocks of the adjacent next-level PTP switch and the first subsystem with the clock of the current PTP switch.
[0071] When timing is provided to the second subsystem connected to the current PTP switch, step S300 is executed. In response to the clock synchronization request message of the second subsystem, after obtaining the hardware timestamp information from the hardware clock module based on the NTP clock synchronization protocol, the timing information is issued to the second subsystem so that the second subsystem performs clock synchronization according to the timing information.
[0072] For the second subsystem that supports the NTP clock synchronization protocol, the PTP switch cannot directly publish timing information to the second subsystem. The second subsystem needs to send a clock synchronization request message to the PTP switch before it can publish timing information to the second subsystem.
[0073] For example, Figure 4 As shown, step S300 includes:
[0074] Step S410: receiving a clock synchronization request message sent by the second subsystem, and generating a second timestamp.
[0075] In this step, the second subsystem sends a clock synchronization request message to the PTP switch at the first moment, and the clock synchronization request message carries the first timestamp of the second subsystem at the first moment. After the PTP switch receives the clock synchronization request message, the hardware clock module generates a second timestamp of the PTP hardware clock. It can be understood that the second timestamp is the hardware timestamp obtained from the hardware clock module when the PTP switch receives the clock synchronization request message.
[0076] Step S420, send a clock synchronization response message carrying a first timestamp, a second timestamp and a third timestamp to the second subsystem, so that the second subsystem determines the time difference according to the first timestamp, the second timestamp, the third timestamp and the fourth timestamp received in the clock synchronization response message, and performs clock calibration according to the time difference.
[0077] After the second timestamp is generated in step S410, the PTP switch will send a clock synchronization response message to the second subsystem. When sending the clock synchronization response message, a departure timestamp, i.e., a third timestamp, will be obtained from the hardware clock module. Then, the clock synchronization response message includes the first timestamp, the second timestamp, and the third timestamp. When the second subsystem receives the clock synchronization response message, there will be a fourth timestamp of receiving the clock synchronization response message. At this time, the second subsystem obtains the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp. Then, the time difference between the second subsystem and the PTP switch can be calculated based on the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp.
[0078] The specific process of calculating the time difference is as follows: first determine the time Delay of the clock synchronization response message from the second subsystem to the PTP switch, then Delay-[(T4-T1)-(T3-T2)] / 2 is based on the time of the fourth timestamp. When the clock synchronization response message sent by the PTP switch is received by the second subsystem, the time of the PTP switch is already T3+Delay, then the time difference Offset can be calculated by the following formula: T4+Offset=T3+Delay, that is, offset=(T2-T1)+(T3-T4)] / 2 ◎ in, offset For the second subsystem PTP Time difference between switches; T1 is the first timestamp; T2 is the second timestamp; T3 is the third timestamp; T4 is the fourth timestamp.
[0079] The timestamps generated during the sending and receiving of the clock synchronization request message and the clock synchronization response message in the above steps S410 and S420 are as follows: Figure 5 shown.
[0080] If software timestamps are used when calculating offsets, due to delays in software scheduling and hardware processing, the second timestamp is sometimes late when it is received and the third timestamp is sometimes early when it is sent. Therefore, when calculating offsets, the calculation result will have large jitters, so the accuracy will also be poor. However, in this embodiment, when calculating offsets, both the second timestamp and the third timestamp use hardware timestamps, which avoids interference caused by factors such as software scheduling and hardware delays, solves the impact of the second timestamp and the third timestamp on the calculation of offsets, and thus improves the accuracy of offsets, thereby improving the accuracy of time synchronization between the second subsystem and the PTP switch.
[0081] In the present application, since the clock server used runs a high-precision stable clock source, it can provide a high-precision stable clock source to the PTP switch connected thereto, and other PTP switches are all synchronized with the PTP switch connected to the clock server through the PTP protocol, so all PTP switch clock sources are the same. In addition, since the PTP switch includes a hardware clock module, for the subsystem supporting the PTP protocol and the subsystem supporting the NTP protocol, time synchronization is performed based on the timestamp provided by the hardware clock module, that is, the subsystem supporting the PTP protocol and the subsystem supporting the NTP protocol use the same PTP hardware clock source, thus avoiding the problem of inconsistent time reference sources caused by the PTP protocol using an independent PTP hardware clock and the NTP protocol using an independent system clock in the prior art. Furthermore, in the present application, when calibrating the time of the subsystem supporting the NTP clock synchronization protocol, the hardware timestamp is used for calibration, thereby improving the time synchronization accuracy of the subsystem supporting the NTP clock synchronization protocol.
[0082] It can be understood that the device of this embodiment corresponds to the clock synchronization method of the above embodiment, and the options in the above embodiment are also applicable to this embodiment, so they will not be described repeatedly here.
[0083] The present application also provides a PTP switch. Exemplarily, the PTP switch includes a processor and a memory, wherein the memory stores a computer program, and the processor runs the computer program to enable the PTP switch to execute the functions of each module in the above-mentioned clock synchronization method or the above-mentioned clock synchronization device.
[0084] Among them, the processor can be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a central processing unit (CPU), a graphics processing unit (GPU) and a network processor (NP), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or at least one of other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc., which can implement or execute the disclosed methods, steps and logic block diagrams in the embodiments of the present application.
[0085] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc. The memory is used to store a computer program, and the processor may execute the computer program accordingly after receiving an execution instruction.
[0086] The present application also provides a computer-readable storage medium for storing the computer program used in the above-mentioned PTP switch. For example, the computer-readable storage medium may include but is not limited to: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other media that can store program codes.
[0087] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow diagram, and the combination of boxes in the structure diagram and / or the flow diagram, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.
[0088] In addition, the functional modules or units in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
[0089] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application.
[0090] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.
Claims
1. A clock synchronization system, characterized in that: include: A clock server, a multi-stage PTP switch connected in sequence, and a subsystem connected to each stage of the PTP switch; wherein the subsystem connected to the PTP switch includes a first subsystem supporting the PTP clock synchronization protocol and a second subsystem supporting the NTP clock synchronization protocol; The clock server is used to publish timing information to at least one PTP switch connected to the clock server; The PTP switch includes a hardware clock module, which is used to receive the timing information of the clock server or the adjacent upper-level PTP switch, and synchronize the timing information to the hardware clock module; The PTP switch is further used to provide time to the connected first subsystem and / or the second subsystem based on the timing information of the hardware clock module.
2. The clock synchronization system according to claim 1, characterized in that: The PTP switch also includes a PTP protocol module and an NTP protocol module; The PTP switch obtains hardware timestamp information from the hardware clock module through the PTP protocol module based on the PTP clock synchronization protocol, and publishes the timing information to the adjacent next-level PTP switch and / or the corresponding first subsystem; The PTP switch obtains the hardware timestamp information from the hardware clock module through the NTP protocol module based on the NTP clock synchronization protocol, and publishes the timing information to the corresponding second subsystem; Wherein, the timing information includes the hardware timestamp information.
3. The clock synchronization system according to claim 1, characterized in that: The clock server includes at least one first master port; the PTP switch includes at least one first slave port and at least one second master port; the first subsystem includes at least one second slave port; the second subsystem includes at least one third slave port; The clock server publishes the timing information to the PTP switch connected to the clock server through the first master port; The PTP switch receives the timing information of the clock server or the PTP switch of the adjacent upper level through the first slave port; The PTP switch publishes the timing information to the adjacent next-level PTP switch through the second master port; The PTP switch publishes the timing information to the first subsystem and / or the second subsystem through the second master port; The first subsystem receives the timing information issued by the PTP switch through the second slave port; The second subsystem receives the timing information published by the PTP switch through the second slave port.
4. The clock synchronization system according to claim 1, characterized in that: The first subsystem and the second subsystem are train control subsystems.
5. A clock synchronization method, characterized in that: A PTP switch applied to a clock synchronization system according to any one of claims 1 to 4, comprising: Receive the timing information from the clock server or the PTP switch of the adjacent upper level in real time, and synchronize the timing information to the hardware clock module; When timing the adjacent next-level PTP switch and subsystem connected to the current PTP switch, timing information is sent to the adjacent next-level PTP switch and the first subsystem in real time, so that the clocks of the adjacent next-level PTP switch and the first subsystem are synchronized with the clock of the current PTP switch; wherein the timing information includes hardware timestamp information; When providing time to a second subsystem connected to the current PTP switch, in response to a clock synchronization request message of the second subsystem, after obtaining the hardware timestamp information from the hardware clock module based on the NTP clock synchronization protocol, the timing information is published to the second subsystem so that the second subsystem performs clock synchronization according to the timing information.
6. The clock synchronization method according to claim 5, characterized in that: Also includes: When the PTP switch is started, a connection between the hardware clock module and the PTP protocol module, and a connection between the hardware clock module and the NTP protocol module are established, so that when the timing information is released through the PTP protocol module and the NTP protocol module, the hardware timestamp information can be obtained from the hardware clock module.
7. The clock synchronization method according to claim 5, characterized in that: The method of responding to the clock synchronization request message of the second subsystem, obtaining the hardware timestamp information from the hardware clock module based on the NTP clock synchronization protocol, and issuing timing information to the second subsystem so that the second subsystem performs clock synchronization according to the timing information includes: receiving the clock synchronization request message sent by the second subsystem, and generating a second timestamp; wherein the clock synchronization request message carries the first timestamp of the second subsystem; Sending a clock synchronization response message carrying the first timestamp, the second timestamp, and the third timestamp to the second subsystem, so that the second subsystem determines the time difference according to the first timestamp, the second timestamp, the third timestamp, and the fourth timestamp received in the clock synchronization response message, and performs clock calibration according to the time difference; Among them, the second timestamp is the hardware timestamp information obtained from the hardware clock module when the PTP switch receives the clock synchronization request message; the third timestamp is the hardware timestamp information obtained from the hardware clock module when the clock synchronization response message is sent to the second subsystem.
8. The clock synchronization method according to claim 7, characterized in that: The formula for determining the time difference is: offset = [(T2-T1) + (T3-T4)] / 2; Among them, the offset is the time difference between the second subsystem and the PTP switch; T1 is the first timestamp; T2 is the second timestamp; T3 is the third timestamp; T4 is the fourth timestamp.
9. A PTP switch, characterized in that: The PTP switch comprises a processor and a memory, wherein the memory stores a computer program, and the processor is configured to execute the computer program to implement the clock synchronization method according to any one of claims 5 to 8.
10. A computer-readable storage medium, characterized in that: The device stores a computer program, which, when executed on a processor, implements the clock synchronization method according to any one of claims 5 to 8.