Signal receiving device and clock data recovery circuit and method thereof

Abstract

The invention discloses a signal receiving device, a clock data recovery circuit and a clock data recovery method. The clock data recovery circuit comprises a sampling circuit which performs burst mode oversampling on an input analog data signal according to a sampling time sequence in a burst mode to generate an oversampling result. The selection circuit judges two adjacent oversampling results with opposite logic states in the burst mode, selects a plurality of data edge sampling results and a plurality of data center sampling results which are staggered from the oversampling results and have the same period as the input analog data signal, and outputs the selected data edge sampling results and the selected data center sampling results as a plurality of output sampling results. The phase detection circuit performs phase detection according to the output sampling result to generate a phase locking direction. The phase adjusting circuit adjusts the sampling time sequence of the sampling circuit according to the phase locking direction so as to lock the input analog data signal.

Description

Technical Field

[0001] The present invention relates to clock data recovery technology, and in particular to a signal receiving device and a clock data recovery circuit and method thereof. Background Art

[0002] In high-speed communication systems, clock and data recovery (CDR) circuits are often used to ensure that the transmitted data signals can be read correctly. In some technologies, the clock and data recovery circuit samples at a slower speed to determine the edge and center of the data, and gradually adjusts the sampling timing to lock the input analog data signal.

[0003] However, in applications such as passive optical networks, signal receiving devices operating as optical link terminals often switch quickly to receive signals from different optical network terminals. When the clock data recovery operates at a slower speed, it will not be able to quickly lock the data signal, resulting in incorrect signal reception. Summary of the invention

[0004] In view of the problems in the prior art, one object of the present invention is to provide a signal receiving device and a clock data recovery circuit and method thereof to improve the prior art.

[0005] One object of the present invention is to provide a clock and data recovery (CDR) circuit, comprising: a sampling circuit, a selection circuit, a phase detection circuit and a phase adjustment circuit. The sampling circuit is configured to perform burst mode oversampling on an input analog data signal according to a sampling timing in a burst mode to generate a plurality of oversampling results. The selection circuit is configured to determine two adjacent oversampling results with opposite logic states in the burst mode, and select a plurality of data edge sampling results and a plurality of data center sampling results that are interlaced with each other and have the same period as the input analog data signal from the oversampling results to output as a plurality of output sampling results. The phase detection circuit is configured to perform phase detection according to the output sampling results to generate a phase locking direction. The phase adjustment circuit is configured to adjust the sampling timing of the sampling circuit according to the phase locking direction to lock the input analog data signal.

[0006] The present invention further includes a clock data recovery method, comprising: a sampling circuit performs oversampling on an input analog data signal according to a sampling timing in a burst mode to generate a plurality of oversampling results; a selection circuit determines two adjacent oversampling results having opposite logic states in the burst mode, and selects a plurality of data edge sampling results and a plurality of data center sampling results that are interlaced with each other and have the same period as the input analog data signal from the oversampling results to output as a plurality of output sampling results; a phase detection circuit performs phase detection according to the output sampling results to generate a phase locking direction; and a phase adjustment circuit adjusts the sampling timing of the sampling circuit according to the phase locking direction to lock the input analog data signal.

[0007] The present invention further includes a signal receiving device, comprising: an equalizer circuit, a clock data recovery circuit and a digital processing circuit. The equalizer circuit is configured to receive an external signal for equalization to generate an input analog data signal. The clock data recovery circuit comprises: a sampling circuit, a selection circuit, a phase detection circuit and a phase adjustment circuit. The sampling circuit is configured to perform burst mode oversampling on the input analog data signal according to the sampling timing in the burst mode to generate multiple oversampling results. The selection circuit is configured to judge two adjacent oversampling results with opposite logic states in the burst mode, and select multiple data edge sampling results and multiple data center sampling results that are interlaced with each other and have the same period as the input analog data signal from the oversampling results to output as multiple output sampling results. The phase detection circuit is configured to perform phase detection according to the output sampling results to generate a phase locking direction. The phase adjustment circuit is configured to adjust the sampling timing of the sampling circuit according to the phase locking direction to lock the input analog data signal. The digital processing circuit is configured to receive the output digital data signal from the selection circuit for processing.

[0008] The features, implementation and efficacy of the present invention are described in detail below with reference to the accompanying drawings as preferred embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A block diagram showing a signal receiving device according to an embodiment of the present invention; Figure 2 A block diagram showing a clock data recovery circuit in one embodiment of the present invention; Figure 3 A schematic diagram showing a sampling circuit performing burst mode oversampling on an input analog data signal according to a sampling timing in one embodiment of the present invention; Figure 4 A schematic diagram showing a sampling circuit performing normal mode sampling on an input analog data signal according to a sampling timing in an embodiment of the present invention; and Figure 5 A flowchart of a clock data recovery method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0010] One of the purposes of the present invention is to provide a signal receiving device and a clock data recovery circuit and method thereof, wherein a sampling circuit performs burst mode oversampling in a burst mode to generate an oversampling result, and a selection circuit quickly determines the data edge and data center to generate a phase lock direction by a phase detection circuit, and then a phase adjustment circuit adjusts the sampling timing of the sampling circuit according to the phase lock direction to achieve a fast locking effect.

[0011] Please refer to Figure 1 . Figure 1 The block diagram of a signal receiving device 100 according to an embodiment of the present invention is shown. The signal receiving device 100 comprises an equalizer circuit 110 , a clock data recovery circuit 120 and a digital processing circuit 130 .

[0012] The equalizer circuit 110 is configured to receive an external signal EXS for equalization to generate an input analog data signal IDS. In one embodiment, the equalizer circuit 110 may include, for example, but not limited to, an analog equalizer, a decision feedback equalizer (DFE), or a combination thereof to perform corresponding equalization processing on the external signal EXS.

[0013] The clock data recovery circuit 120 is configured to perform clock data recovery on the input analog data signal IDS to generate an output digital data signal ODS. The digital processing circuit 130 is configured to receive the output digital data signal ODS for processing.

[0014] In one embodiment, the signal receiving device 100 can be applied to the technology of a passive optical network (PON) and operated as an optical line terminal (OLT) in the passive optical network. The optical line terminal may switch connections with multiple different optical network terminals (ONT) as light sources in a short period of time to receive different data signals. When the clock data recovery circuit 120 of the signal receiving device 100 cannot quickly lock the frequency and phase of the received signal, the speed of the clock data recovery will not be fast enough to correctly receive the data.

[0015] Please refer to Figure 2 . Figure 2A block diagram of a clock data recovery circuit 120 is shown in one embodiment of the present invention. In one embodiment, the clock data recovery circuit 120 can selectively operate in a burst mode and a normal mode, and provide a fast locking mechanism in the burst mode. The following paragraphs will first describe the structure of the clock data recovery circuit 120 and the operation in the burst mode.

[0016] The clock data recovery circuit 120 includes a sampling circuit 200 , a selection circuit 210 , a phase detection circuit 220 , a low pass filter 230 and a phase adjustment circuit 240 .

[0017] The sampling circuit 200 is configured to perform burst mode oversampling on the input analog data signal IDS according to a sampling timing in the burst mode to generate a plurality of oversampling results OSR, wherein each piece of data of the input analog data signal IDS corresponds to a number of 2 N The oversampling result OSR is obtained, and N is a positive integer greater than 1.

[0018] Please also refer to Figure 3 . Figure 3 A schematic diagram showing an embodiment of the present invention, in which the sampling circuit 200 performs burst mode oversampling on the input analog data signal IDS according to the sampling timing.

[0019] like Figure 3 As shown, the input analog data signal IDS includes multiple data, and the data DA is exemplarily indicated. 0 -DA 2 In this embodiment, the burst mode oversampling performed by the sampling circuit 200 will make each data DA 0 -DA 2 The corresponding number of oversampling results OSR is 8 (N=3), and each oversampling result OSR has a corresponding logic state. It should be noted that the above number is only an example. In practice, the burst mode oversampling performed by the sampling circuit 200 can correspond to each data DA 0 -DA 2 Generates other 2 N And N is greater than 1.

[0020] More specifically, the data DA 0 The corresponding sampling timings T00-T07 are sampled to generate oversampling results OSR whose logic states are all high (1). 1 The corresponding sampling timing T10-T17 is sampled to generate an oversampling result OSR whose logic state is all low (0). 2 The corresponding sampling timings T20-T27 are sampled to generate over-sampling results OSR whose logic states are all high (1).

[0021] The sampling circuit 200 can be based on Figure 2 The input analog data signal IDS is sampled at the sampling timing of the sampling clock CKS generated by the phase adjustment circuit 230. In one embodiment, the sampling clock CKS may be generated by the sampling circuit 200 according to an external reference clock signal CKR.

[0022] In one embodiment, the sampling clock CKS may be a single high-frequency clock signal having a frequency higher than the input analog data signal IDS, so that the sampling circuit 200 performs burst mode oversampling according to the sampling timing of the high-frequency clock signal. The sampling timing of the high-frequency clock signal may correspond to the timing of multiple edges (positive edge and / or negative edge) in a data.

[0023] In another embodiment, the sampling clock CKS may be a multi-phase clock signal whose frequency is not higher than the input analog data signal IDS, so that the sampling circuit 200 performs burst mode oversampling according to the sampling timing of the multi-phase clock signal. The sampling timing of the multi-phase clock signal includes the timing of the clock signals of different phases corresponding to multiple edges (positive edge and / or negative edge) in a data.

[0024] Figure 2 The selection circuit 210 is configured to judge two adjacent over-sampling results OSR having opposite logic states in the burst mode, and select a plurality of data edge sampling results and a plurality of data center sampling results that are staggered with each other and have the same period as the input analog data signal IDS from the over-sampling results OSR to output as a plurality of output sampling results OSS.

[0025] In one embodiment, the selection circuit 210 first determines that one of the two adjacent oversampling results with opposite logic states is a data edge, and then selects a data edge sampling result and a data center sampling result according to the data edge, so that one of the selected data edge sampling results corresponds to the data edge.

[0026] For example, Figure 3 The oversampling results OSR corresponding to the sampling timing T07 and the sampling timing T10 are high and low, respectively. Figure 2 The selection circuit 210 may set the latter of two adjacent over-sampling results OSR having opposite logic states, ie, the over-sampling result OSR corresponding to the sampling timing T10 , as the data edge.

[0027] The selection circuit 210 selects the oversampling result OSR corresponding to the sampling timing T10 and T20 as the data edge sampling results E0 and E1. One of the data edge sampling results E0 and E1 (data edge sampling result E0) corresponds to the data edge, and the period length between the data edge sampling results E0 and E1 is the same as the period length of the input analog data signal. It should be noted that Figure 3 Only exemplary indication to data DA 2 , however, the selection circuit 210 may correspond to the data DA 2 The oversampling result OSR generated by the subsequent data undergoes the same selection.

[0028] The selection circuit 210 further selects the oversampling results OSR corresponding to the sampling timings T14 and T24 as the data center sampling results D0 and D1. The data center sampling results D0 and D1 are interlaced with the data edge sampling results E0 and E1. In more detail, the data center sampling result D0 is equidistant from the data edge sampling results E0 and E1, while the data center sampling result D1 is equidistant from the data edge sampling result E1 and the next data edge sampling result. The data center sampling results D0 and D1 are thus interlaced with the data edge sampling results E0 and E1. It should be noted that Figure 3 Only exemplary indication to data DA 2 , however, the selection circuit 210 may correspond to the data DA 2 The oversampling result OSR generated by the subsequent data undergoes the same selection.

[0029] It should be noted that, according to the different positions of two adjacent over-sampling results OSR with opposite logic states, the data edge set by the selection circuit 210 will also be different.

[0030] For example, when the two oversampling results OSR corresponding to the sampling timings T10 and T11 have opposite logic states, the selection circuit 210 may set the oversampling result OSR corresponding to the sampling timings T11 as the data edge, and sequentially select the oversampling results OSR corresponding to the sampling timings T11, T15, and T21 as the data edge sampling result E0, the data center sampling result D0, and the data edge sampling result E1. When the two oversampling results OSR corresponding to the sampling timings T13 and T14 have opposite logic states, the selection circuit 210 may set the oversampling result OSR corresponding to the sampling timings T14 as the data edge, and sequentially select the oversampling results OSR corresponding to the sampling timings T14, T20, and T24 as the data edge sampling result E0, the data center sampling result D0, and the data edge sampling result E1. And so on.

[0031] also, Figure 2The selection circuit 210 can also selectively select the former of two adjacent oversampling results OSR having opposite logic states, for example Figure 3 The oversampling result OSR corresponding to the sampling timing T07 is set as the data edge, and the data edge sampling result and the data center sampling result are selected accordingly. No further details are given here.

[0032] Through the above selection method, Figure 2 The selection circuit 210 can generate an output sampling result OSS including a data edge sampling result E0, a data center sampling result D0, a data edge sampling result E1 and a data center sampling result D1 in sequence. On the other hand, the selection circuit 210 can output the selected data center sampling results D0 and D1 as an output digital data signal ODS. Figure 1 The digital processing circuit is configured to receive the output digital data signal ODS from the selection circuit 210 for processing.

[0033] The phase detection circuit 220 is configured to perform phase detection according to the output sampling result OSS to generate a phase locking direction UD.

[0034] In one embodiment, the phase detection circuit 220 performs phase detection according to the logic state relationship between three consecutive output sampling results OSS. For example, the phase detection circuit 220 can perform phase detection according to the logic state relationship between the data edge sampling result E0, the data center sampling result D0, and the data edge sampling result E1, and generate a phase lock direction UD according to the phase detection result.

[0035] Please refer to Table 1. Table 1 shows the corresponding relationship between the output sampling result OSS and the phase locking direction UD in one embodiment of the present invention. In this embodiment, the logical state relationship of the data edge sampling result E0, the data center sampling result D0, and the data edge sampling result E1 is used as an example for explanation. The phase locking direction UD is represented by a value of 1 for the forward direction and a value of -1 for the backward direction.

[0036] Table 1

[0037] As shown in Table 1, when the logic state relationship of the data edge sampling result E0, the data center sampling result D0, and the data edge sampling result E1 is low, low, high, and represented as (001) or high, high, low, and represented as (110), the phase detection result is "lag". That is, the sampling timing of the sampling circuit 200 sampling the input analog data signal IDS lags behind the input analog data signal IDS. At this time, the phase detection circuit 220 will generate a phase lock direction UD with a value of 1 corresponding to the "forward direction".

[0038] When the logic state relationship of the data edge sampling result E0, the data center sampling result D0, and the data edge sampling result E1 is low, high, high, and represented as (011) or high, low, low, and represented as (100), the phase detection result is "leading". That is, the sampling timing of the sampling circuit 200 sampling the input analog data signal IDS is ahead of the input analog data signal IDS. At this time, the phase detection circuit 220 will generate a phase lock direction UD with a value of -1 corresponding to the "backward direction".

[0039] When the logic state relationship of the data edge sampling result E0, the data center sampling result D0, and the data edge sampling result E1 are all low states and represented as (000) or all high states and represented as (111), the phase detection circuit 220 will not be able to determine the phase relationship and generate a value of 0 that does not correspond to any direction of the phase lock direction UD.

[0040] In addition, since at least two consecutive data edge sampling results E0, data center sampling results D0, and data edge sampling results E1 correspond to the same data sampling, the combination of low state, high state, low state represented by (010) or high state, low state, high state represented by (101) should not appear in practice.

[0041] Corresponds to Figure 3 In the embodiment, since the logic state relationship among the data edge sampling result E0, the data center sampling result D0, and the data edge sampling result E1 is low state, high state, and high state and is represented as (011), the phase detection circuit 220 will generate a phase locking direction UD with a value of 1 corresponding to the "forward direction".

[0042] It should be noted that the above embodiment is described by performing phase detection based on three consecutive output sampling results OSS, namely, data edge sampling result E0, data center sampling result D0, and data edge sampling result E1. In other embodiments, the phase detection circuit 220 can also perform phase detection based on the logical state relationship between the data center sampling result D0, data edge sampling result E1, and data center sampling result D1, or perform phase detection based on a larger number of logical state relationships. The present invention is not limited thereto.

[0043] The low pass filter 230 is configured to filter the phase lock direction UD. The phase adjustment circuit 240 is configured to adjust the sampling timing of the sampling circuit 200 according to the filtered phase lock direction UD to lock the input analog data signal IDS. In more detail, according to the filtered phase lock direction UD, the phase adjustment circuit 240 adjusts the sampling timing of the sampling circuit 200 by adjusting the timing of the sampling clock CKS.

[0044] It should be noted that the clock data recovery circuit 120 may selectively include the low-pass filter 230 , or may operate by directly allowing the phase adjustment circuit 240 to receive the phase locking direction UD generated by the phase detection circuit 220 without the low-pass filter 230 .

[0045] In one embodiment, the input analog data signal IDS is determined to be locked when the probability of the phase locking direction UD being the forward direction and the backward direction is substantially equal. It should be noted that the term "substantially" means that the probability of the forward direction and the backward direction can have a reasonable range of difference, and does not have to be completely equal.

[0046] For example, the phase adjustment circuit 240 may count the number of times the phase locking direction UD appears in the forward direction with a value of 1 and in the backward direction with a value of −1. When the statistical result shows that the number of times the forward direction and the backward direction appear is only slightly different and are substantially equal, the phase adjustment circuit 240 may determine that the probability of the forward direction and the backward direction appearing is substantially equal, and further determine that the input analog data signal IDS has been locked.

[0047] In one embodiment, when it is determined that the input analog data signal IDS is locked or it is determined that it is not necessary to operate in the burst mode based on other factors, the clock data recovery circuit 120 can operate in the normal mode. Figure 2 as well as Figure 3 , the operation of normal mode is explained.

[0048] In one embodiment, the sampling circuit 200 continues to perform burst mode oversampling on the input analog data signal IDS in the normal mode. The selection circuit 210 selects the data edge sampling result and the data center center sampling result to output as the output sampling result OSS according to one of the oversampling results OSR in the normal mode. In more detail, the selection circuit 210 can arbitrarily set one of the oversampling results OSR as the data edge to select the data edge sampling result and the data center center sampling result to output as the output sampling result OSS in the manner described in the previous embodiment.

[0049] Preferably, when the clock data recovery circuit 120 switches from the burst mode to the normal mode, the selection made in the burst mode can be continued. For example, when the selection circuit 210 selects the oversampling result OSR corresponding to the sampling timing T10, T14, T20, T24 to be output as the output sampling result OSS before the burst mode ends, the same selection can be made in the normal mode.

[0050] However, the clock data recovery circuit 120 can also perform a more random selection in the normal mode. For example, the selection circuit 210 can be arbitrarily set Figure 3The oversampling result OSR corresponding to the sampling timing T03 is used as the data edge, and the oversampling results OSR corresponding to the sampling timings T03, T07, and T13 are further selected according to the aforementioned selection method as the data edge sampling result E0, the data center sampling result D0, and the data edge sampling result E1, and are output as the output sampling result OSS.

[0051] In another embodiment, the sampling circuit 200 performs normal mode sampling on the input analog data signal IDS in the normal mode to generate a plurality of normal sampling results NSR, wherein each data of the input analog data signal IDS corresponds to a number of normal sampling results NSR of 2. In more detail, the sampling circuit 200 may perform normal mode sampling according to other clock signals with a lower frequency or fewer phases to generate the normal sampling results NSR.

[0052] Please refer to Figure 4 . Figure 4 A schematic diagram showing an embodiment of the present invention, in which the sampling circuit 200 performs normal mode sampling on the input analog data signal IDS according to the sampling timing.

[0053] Similar to Figure 3 The input analog data signal IDS includes multiple data and the data DA is exemplarily indicated. 0 -DA 2 .exist Figure 4 In the embodiment of the present invention, the normal mode sampling performed by the sampling circuit 200 will make each data DA 0 -DA 2 The corresponding number of normal sampling results NSR is 2, and each normal sampling result NSR has a corresponding logic state.

[0054] More specifically, the data DA 0 The corresponding sampling timing T00-T01 is sampled to generate a normal sampling result NSR in which the logic state is high (1). 1 The corresponding sampling timing T10-T11 is sampled to generate a normal sampling result NSR in which the logic state is low (0). 2 The corresponding sampling timing T20-T21 is sampled to generate a normal sampling result NSR in which the logic states are all high (1).

[0055] The selection circuit 210 determines two adjacent normal sampling results NSR having opposite logic states in the normal mode, and selects a data edge sampling result and a data center sampling result from the normal sampling results NSR to output as the output sampling result OSS. In more detail, the selection circuit 210 first determines that one of the two adjacent normal sampling results NSR having opposite logic states is a data edge, and then selects the data edge sampling result and the data center sampling result according to the data edge, so that one of the selected data edge sampling results corresponds to the data edge.

[0056] For example, for two adjacent normal sampling results NSR having opposite logic states corresponding to the sampling timings T01 and T10, the selection circuit 210 can set the latter as the data edge, and select the normal sampling results NSR corresponding to the sampling timings T01 and T11 as the data edge sampling results E0 and E1 according to the selection method in the previous embodiment, and select the normal sampling results NSR corresponding to the sampling timings T10 and T20 as the data center sampling results D0 and D1, and output them as the output sampling results OSS.

[0057] In any of the above normal mode implementations, the phase detection circuit 220 , the low pass filter 230 and the phase adjustment circuit 240 can all operate according to the same operation mechanism as the burst mode after the selection circuit 210 outputs the output sampling result OSS, which will not be described in detail here.

[0058] In some technologies, the clock data recovery circuit must determine the data edge and data center at a relatively slow speed and gradually adjust the sampling timing to lock the input analog data signal. However, in applications such as passive optical networks, signal receiving devices operating as optical link terminals often switch quickly to receive signals from different optical network terminals. When the clock data recovery operates at a relatively slow speed, it will not be able to quickly lock the data signal, resulting in incorrect signal reception.

[0059] The clock data recovery circuit of the present invention can generate an oversampling result by burst mode oversampling performed by the sampling circuit in burst mode, and the selection circuit can quickly determine the edge and data center of the data to generate a phase lock direction by the phase detection circuit, and then the phase adjustment circuit can adjust the sampling timing of the sampling circuit according to the phase lock direction to achieve the effect of fast locking. In one embodiment, the clock data recovery circuit of the present invention can lock the input analog data signal within nanosecond (NS) level time to correctly receive data.

[0060] Please refer to Figure 5 . Figure 5 A flowchart of a clock data recovery method 500 with a fast locking mechanism is shown in one embodiment of the present invention.

[0061] In addition to the aforementioned apparatus, the present invention further discloses a clock data recovery method 500, which is applied to, for example, but not limited to Figure 2 In the clock data recovery circuit 120. One implementation of the clock data recovery method 500 is as follows: Figure 5 As shown, the following steps are included.

[0062] In step S510, the sampling circuit 200 performs oversampling on the input analog data signal IDS according to the sampling timing in the burst mode to generate an oversampling result OSR, wherein each data entry of the input analog data signal IDS corresponds to a number of 2 N The oversampling result OSR is obtained, and N is a positive integer greater than 1.

[0063] In step S520, the selection circuit 210 determines two adjacent over-sampling results OSR having opposite logic states in the burst mode, and selects a plurality of data edge sampling results and a plurality of data center sampling results that are staggered with each other and have the same period as the input analog data signal IDS from the over-sampling results OSR to output as a plurality of output sampling results OSS.

[0064] In step S530 , the phase detection circuit 220 performs phase detection according to the output sampling result OSS to generate a phase locking direction UD.

[0065] In step S540 , the phase adjustment circuit 240 adjusts the sampling timing of the sampling circuit 200 according to the phase locking direction UD to lock the input analog data signal IDS.

[0066] It should be noted that the above implementation is only an example. In other embodiments, those skilled in the art may make changes without departing from the spirit of the present invention.

[0067] In summary, the signal receiving device and the clock data recovery circuit and method of the present invention generate oversampling results by burst mode oversampling performed by the sampling circuit in burst mode, and the selection circuit quickly determines the data edge and data center to generate a phase lock direction by the phase detection circuit, and then the phase adjustment circuit adjusts the sampling timing of the sampling circuit according to the phase lock direction to achieve a fast locking effect.

[0068] Although the embodiments of the present case are described above, these embodiments are not intended to limit the present case. A technician with ordinary knowledge in the technical field may make changes to the technical features of the present case based on the explicit or implicit content of the present case. All these changes may fall within the scope of patent protection sought in the present case. In other words, the scope of patent protection in the present case shall be based on what is defined in the claims of this specification.

Explanation of symbols

[0069] 100: signal receiving device 110:Equalizer circuit 120: Clock data recovery circuit 130: Digital processing circuit 200: Sampling circuit 210: Select Circuit 220: Phase detection circuit 230: Low pass filter 240: Phase adjustment circuit 500: Clock data recovery method S510~S540: Steps CKR: reference clock signal CKS: sampling clock DA 0 -DA 2 :data D0, D1: Data center sampling results E0, E1: Data edge sampling results EXS: External Signal IDS: Input analog data signal NSR: Normal sampling result ODS: Output digital data signal OSR: Oversampling Result OSS: Output sampling results T00-T07, T10-T17, T20-T27: Sampling timing UD: Phase lock direction

Claims

1. A clock data recovery circuit, characterized in that: Include: A sampling circuit configured to perform a burst mode oversampling on an input analog data signal according to a sampling timing in a burst mode to generate a plurality of oversampling results; a selection circuit configured to determine two adjacent oversampling results having opposite logic states in the burst mode, and accordingly select a plurality of data edge sampling results and a plurality of data center sampling results that are interleaved with each other and have the same period as the input analog data signal from the oversampling results to output as a plurality of output sampling results; a phase detection circuit configured to perform phase detection according to the output sampling result to generate a phase locking direction; and A phase adjustment circuit is configured to adjust the sampling timing of the sampling circuit according to the phase locking direction to lock the input analog data signal.

2. The clock data recovery circuit according to claim 1, characterized in that: The selection circuit determines that one of the two adjacent oversampling results having opposite logic states is a A data edge is selected, and the data edge sampling result and the data center sampling result are selected according to the data edge, so that one of the selected data edge sampling results corresponds to the data edge.

3. The clock data recovery circuit according to claim 1, characterized in that: The phase detection circuit performs phase detection according to a logic state relationship between three consecutive output sampling results. Detection.

4. The clock data recovery circuit according to claim 1, characterized in that: The selection circuit selects the data edge sampling result and the data center sampling result from the oversampling results according to one of the oversampling results in a normal mode and outputs them as the output sampling result.

5. The clock data recovery circuit according to claim 1, characterized in that: The sampling circuit performs a normal mode sampling on the input analog data signal in a normal mode to generate a plurality of normal sampling results, wherein each piece of data of the input analog data signal corresponds to 2 normal sampling results; and The selection circuit determines two adjacent normal sampling results with opposite logic states in the normal mode, and accordingly selects the data edge sampling result and the data center sampling result from the normal sampling results to output as the output sampling result.

6. The clock data recovery circuit according to claim 1, characterized in that: The selection circuit outputs the data center sampling result as an output digital data signal.

7. The clock data recovery circuit according to claim 1, characterized in that: The sampling circuit samples the data according to a high-frequency clock signal with a higher frequency than the input analog data signal. The burst mode oversampling is performed, or the burst mode oversampling is performed according to the sampling timing of the multi-phase clock signal whose frequency is not higher than that of the input analog data signal.

8. The clock data recovery circuit according to claim 1, characterized in that: The input analog data signal is a forward direction and an output signal is a backward direction in the phase locking direction. When the current probabilities are substantially equal, it is determined to be locked.

9. A clock data recovery method, characterized in that: Include: A sampling circuit performs burst mode oversampling on an input analog data signal according to a sampling timing in a burst mode to generate a plurality of oversampling results; A selection circuit determines two adjacent oversampling results having opposite logic states in the burst mode, and accordingly selects a plurality of data edge sampling results and a plurality of data center sampling results that are interlaced with each other and have the same period as the input analog data signal from the oversampling results to output as a plurality of output sampling results; A phase detection circuit performs phase detection according to the output sampling result to generate a phase locking direction; and A phase adjustment circuit adjusts the sampling timing of the sampling circuit according to the phase locking direction to lock the input analog data signal.

10. A signal receiving device, characterized in that: Include: an equalizer circuit configured to receive an external signal for equalization to generate an input analog data signal; A clock data recovery circuit, comprising: a sampling circuit configured to perform burst mode oversampling on the input analog data signal according to a sampling timing in a burst mode to generate a plurality of oversampling results; a selection circuit configured to determine two adjacent oversampling results having opposite logic states in the burst mode, and accordingly select a plurality of data edge sampling results and a plurality of data center sampling results that are interleaved with each other and have the same period as the input analog data signal from the oversampling results to output as a plurality of output sampling results; a phase detection circuit configured to perform phase detection according to the output sampling result to generate a phase locking direction; and a phase adjustment circuit configured to adjust the sampling timing of the sampling circuit according to the phase locking direction to lock the input analog data signal; and A digital processing circuit is configured to receive an output digital data signal from the selection circuit for processing.

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