Self-adaptive single-wire parallel and cascade communication method and self-adaptive single-wire parallel and cascade communication system

Abstract

The invention relates to a self-adaptive single-line parallel and cascade communication method and system, the system comprises a system framework, the system framework comprises a host and a plurality of LED chips, and the communication method comprises the following steps: changing a host output signal from 0 to 1 into a starting point of a single Bit, and when 1 / 2 of the time length of the data Bit is reached, locking whether the data is 0 or 1; if the data on the signal line at the 1 / 2 position of the time is 0, the Bit data is 0, otherwise, the Bit data is 1; after the 1Bit data is sent, sending the 1Bit data until the data is sent; decoding the data of each bit in the LED chip according to 1 / 2 of the data time length to obtain all data sent by the host; the problem of complex host debugging in the existing single-line cascade mode can be well solved, and the data output frequency does not need to be continuously adjusted to adapt to the decoding frequency of the chip, so that the communication efficiency can be remarkably improved.

Description

Technical Field

[0001] The invention relates to the technical field of LED display communication, and more specifically to an adaptive single-line parallel and cascade communication method and system. Background Art

[0002] In today's society, electronic information has become inseparable from human beings. The electronic products we come into contact with every day will communicate electronically, and all electronic communications are an important part of electronic products. The internal components of electronic products must communicate to coordinate work, and they will also communicate with other electronic products to cooperate with work. Before communication, both parties need to agree on a communication protocol to ensure normal communication between the two parties. There are many types of existing communication protocols, including wired and wireless; short-distance, medium-distance, and long-distance; low-speed, medium-speed, and high-speed. Each protocol has certain characteristic application scenarios. A relatively suitable protocol is defined according to the scenario, and many factors such as hardware cost and assembly must also be considered.

[0003] Single-line communication transmission is becoming more and more popular, especially in LED display communication. Currently, the most common method is single-line cascade, such as Figure 1 The host first sends data to the SI of chip 1, and the data received by chip 1 is decoded and intercepted and then forwarded to the next chip 2 through SO. Similarly, each chip decodes, intercepts and forwards the data. Figure 2 shown.

[0004] The above-mentioned techniques have the following problems:

[0005] Due to the use of single-line cascade technology, each chip not only receives and decodes data but also forwards data. In addition, the chip can be easily damaged if data cannot be transmitted. Once a chip in the middle is damaged, subsequent chips will not be able to receive data, and subsequent chips will not work properly.

[0006] The chip itself has a certain timing deviation when decoding data, and this deviation is caused by the chip. In this way, each chip will have a certain deviation. The accumulation of this deviation to a certain extent will cause decoding errors in subsequent chips.

[0007] This cascade technology can only decode, intercept and forward data, making communication transmission extremely simple and unable to control other functions inside the chip.

[0008] This cascade technology simply transmits data to subsequent chips, without any mechanism to detect whether the cascaded chips receive and decode the data correctly.

[0009] Single-line data transmission uses a fixed frequency for decoding, which requires the data sent by the host to conform to the decoding frequency of the chip. In addition, the decoding frequency inside the chip deviates with the voltage and temperature, and the frequency of each chip also deviates. This brings a huge workload when debugging the solution, and it may even be impossible to adjust the entire control solution and system.

[0010] In the above single-line cascade transmission technology, the host debugging is complicated, and the data output frequency needs to be constantly adjusted to adapt to the decoding frequency of the chip; the host data can only be output to the chip, and the chip cannot transmit the data back to the host; any chip damage in the middle will cause the subsequent chip to be unable to receive data; or the chip decoding error in the middle will cause the subsequent chip to receive wrong data. In order to solve the above problems, an adaptive single-line parallel and cascade communication method and system are urgently needed. Summary of the invention

[0011] The technical problem to be solved by the present invention is to provide an adaptive single-line parallel and cascade communication method and an adaptive single-line parallel and cascade communication system in view of the above-mentioned defects of the prior art.

[0012] The technical solution adopted by the present invention to solve its technical problem is:

[0013] A communication method for adaptive single-line parallel and cascade connection is constructed, wherein the system architecture includes a host and a plurality of LED chips, the host is provided with a first signal output port, a second signal output port and a signal receiving port, and the LED chip is provided with a parallel input port PI, a serial input port SI and a signal output port SO; the plurality of LED chips are connected in series in sequence, the first signal output port is connected to the SI port of the frontmost LED chip, the signal receiving port is connected to the SO port of the rearmost LED chip; the second signal output port is connected to the PI port of each LED chip;

[0014] The communication method between the host and the LED chip is:

[0015] The host output signal changes from 0 to 1 as the starting point of a single bit. When it waits for 1 / 2 of the data bit time length, it locks whether the data is 0 or 1.

[0016] If the data on the signal line is 0 at 1 / 2 of the time, the bit data is 0, otherwise the bit data is 1;

[0017] When 1 bit of data is sent, the next 1 bit of data is sent immediately until all data is sent.

[0018] The LED chip decodes each bit of data in 1 / 2 of the data time length to obtain all the data sent by the host.

[0019] When the data is sent, the host outputs a 0 level until the next set of data is sent.

[0020] The adaptive single-line parallel and cascade communication method of the present invention, wherein the LED chip is provided with a high-speed clock; the method further comprises the steps of:

[0021] The host adds 2n ​​empty data to learn the data frequency before sending valid data, where n is an integer greater than 0;

[0022] The LED chip uses a high-speed clock to count the number of clocks of 2n empty data, and the number of clocks divided by 2n is the number of clocks of a single bit, Tbit;

[0023] The data after the null data is decoded with the time point data of Tbit / 2. When the input signal at this time point is 0, the bit is decoded to 0, otherwise it is 1.

[0024] During the waiting period, the host sends a signal to output 0 level. When the internal 0 level counter of the LED chip is greater than the 2n Bits time width, the next set of data will restart frequency learning.

[0025] In the adaptive single-line parallel and cascade communication method of the present invention, the data format sent by the host is defined as follows:

[0026] Frequency learning + instruction name + execution parameters;

[0027] The command name includes one or more of: address burning command, internal register writing command, display data writing command, internal register reading command and input switching command.

[0028] The adaptive single-line parallel and cascade communication method of the present invention, wherein the host communicates with the LED chip in a parallel mode;

[0029] Before the LED chip enters normal data reception, a unique address is burned into each LED chip in cascade mode.

[0030] The adaptive single-line parallel and cascade communication method of the present invention, wherein, before the LED chip enters the normal data reception mode, a unique address is burned into each LED chip in the cascade mode using the following method:

[0031] The host's PI signal outputs a high level, and after 1 millisecond, all chips enter the cascade mode, and the data input switches to the SI port;

[0032] The host sends an address burning command with the address following 0. At this time, the LED chip enters the address burning waiting mode, and the SO ports of all LED chips temporarily shut down the output;

[0033] The host sends an address burning command followed by an address of 1. After receiving the command and address, the first LED chip starts burning and writes the address into the internal storage location of the chip.

[0034] After the burning is completed, the first LED chip opens the SO port and outputs the data input from the SI port from the SO port;

[0035] The host sends an address burning command with the address 2 at the end. The first LED chip outputs the data inputted from the SI port from the SO port. The SI port of the second LED chip receives the WR_ADDR command with an address not equal to 0 and writes the received address into the internal storage location of the chip.

[0036] And so on, until the Nth LED chip writes address N into the internal storage location of the chip;

[0037] After the LED chip is powered on, a power-on reset is generated inside the chip. After a period of time after the reset is completed, the internal storage address is automatically loaded inside the LED chip. After the address loading is completed, the entire cascade system enters normal operation.

[0038] The adaptive single-line parallel and cascade communication method of the present invention further comprises:

[0039] If in an existing cascade system, it is found that an LED chip in the middle is damaged and needs to be replaced, the address of the chip needs to be re-burned after replacement;

[0040] When the address inside the LED chip has been programmed, the LED chip will not start programming.

[0041] The adaptive single-line parallel and cascade communication method of the present invention, wherein the write internal register instruction format includes: write internal register instruction + LED chip address + register address + register parameter;

[0042] The method for writing an internal register includes the following steps: the host configures the internal function register parameters of the LED chip according to the application requirements; when the chip address sent by the host is 0, a global configuration is performed, and the parameters of the register addresses corresponding to all LED chips will be rewritten;

[0043] The read internal register format includes: read internal register instruction + chip address + register address + read register parameter;

[0044] The method for reading the internal register includes the following steps: the host reads the internal function parameters and results of the LED chip according to the application requirements.

[0045] The adaptive single-line parallel and cascade communication method of the present invention, wherein the write display data format includes: write display data instruction + first data address + data 1 + data 2 + ... + data n;

[0046] The method for writing display data includes the following steps: when the LED chip receives the instruction, the first data address is loaded into the address counter inside the LED chip, and the LED chip whose address is equal to the first data address saves data 1; when the data is received, the internal address count of the LED chip is automatically increased by 1, and at this time, the chip whose internal address count is equal to the LED chip address saves data 2, and the internal address count of the LED chip is automatically increased by 1 again, and so on, each LED chip saves the data when the address matches, so that each LED chip will save the data specified by the host; when the LED chip address sent by the host is 0, it will be a global configuration, and all LED chips will save data 1.

[0047] The adaptive single-line parallel and cascade communication method of the present invention further comprises the step of switching the input port of the LED chip:

[0048] After the LED chip is powered on, the default PI port is the signal input port;

[0049] When the data input port of the LED chip needs to be switched to the SI port, the PI port signal is set to 1 and the time is greater than 1mS. When the PI high level 1mS monitoring counter inside the LED chip is full, the LED chip will automatically select SI as the data input port.

[0050] When you need to switch the data input port of the LED chip to the PI port, input the SI_EXT instruction at the SI port.

[0051] A system for adaptive single-line parallel and cascade communication, using the adaptive single-line parallel and cascade communication method as described above, wherein the system includes the system architecture;

[0052] The LED chip also includes an MX device, a decoding clock, a command control module, a data control module and an address burning storage module;

[0053] The MX device is used to select the signal input to the SI port and the PI port;

[0054] The decoding clock is used to decode the signal selected by the input MX device, and send it to the instruction control module or the data control module according to the decoded data type, and forward the serial data through the SO port;

[0055] The address burning storage module is used to store the address sent by the instruction control module.

[0056] The beneficial effects of the present invention are:

[0057] 1. Chip cascading: the host can access and control each chip in cascade or parallel mode without any additional devices, which greatly reduces the number of peripheral devices;

[0058] 2. The system wiring is simple, and the processing and assembly are convenient;

[0059] 3. The system adopts cascade and parallel coexistence, which significantly improves data transmission and makes the system easy to maintain;

[0060] 4. The timing of the host control chip is simple, which is convenient for host program development;

[0061] 5. All signal lines are digital lines, and the system is not easily interfered with. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work:

[0063] Figure 1 It is a schematic diagram of the existing single-line cascade system architecture;

[0064] Figure 2 It is a schematic diagram of existing single-line cascade data transmission;

[0065] Figure 3 It is a schematic diagram of the system architecture of the adaptive single-line parallel and cascade communication method of a preferred embodiment of the present invention;

[0066] Figure 4 It is a schematic diagram of parallel and cascade switching of an adaptive single-line parallel and cascade communication method of a preferred embodiment of the present invention;

[0067] Figure 5 It is a data communication sampling timing diagram of the adaptive single-line parallel and cascade communication method of the preferred embodiment of the present invention;

[0068] Figure 6 It is a frequency learning timing diagram of the adaptive single-line parallel and cascade communication method of a preferred embodiment of the present invention;

[0069] Figure 7 It is a schematic diagram of the data structure of each instruction of the adaptive single-line parallel and cascade communication method of the preferred embodiment of the present invention;

[0070] Figure 8 It is a timing diagram of chip address writing instruction of the adaptive single-line parallel and cascade communication method of the preferred embodiment of the present invention;

[0071] Fig. 9 It is a reset schematic diagram of the adaptive single-line parallel and cascade communication method of a preferred embodiment of the present invention;

[0072] Fig.10 The timing diagram of the parallel system chip receiving data is a preferred embodiment of the present invention.

[0073] Fig.11 The adaptive single-line parallel and cascade communication method of the preferred embodiment of the present invention is a timing diagram of the cascade system chip receiving data

[0074] Fig.12 The adaptive single-line parallel and cascade communication method of the preferred embodiment of the present invention is a timing diagram of the chip internal address burning control

[0075] Fig.13 The system control timing diagram of the adaptive single-line parallel and cascade communication method of the preferred embodiment of the present invention is

[0076] Fig.14 It is a system principle block diagram of the adaptive single-line parallel and cascade connection of the preferred embodiment of the present invention. DETAILED DESCRIPTION

[0077] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the following will be described clearly and completely in combination with the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are partial embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0078] The adaptive single-line parallel and cascade communication method of the preferred embodiment of the present invention is as follows: Figure 3 See also Figure 4-Figure 13 , including a system architecture, the system architecture includes a host and a plurality of LED chips, the host is provided with a first signal output port, a second signal output port and a signal receiving port, the LED chip is provided with a parallel input port PI, a serial input port SI and a signal output port SO; the plurality of LED chips are connected in series in sequence, the first signal output port is connected to the SI port of the frontmost LED chip, the signal receiving port is connected to the SO port of the rearmost LED chip; the second signal output port is connected to the PI port of each LED chip;

[0079] like Figure 5 As shown, the host and LED chip communicate using the following method:

[0080] The host output signal changes from 0 to 1 as the starting point of a single bit. When it waits for 1 / 2 of the data bit time length, it locks whether the data is 0 or 1.

[0081] If the data on the signal line is 0 at 1 / 2 of the time, the bit data is 0, otherwise the bit data is 1;

[0082] When 1 bit of data is sent, the next 1 bit of data is sent immediately until all data is sent.

[0083] The LED chip decodes each bit of data in 1 / 2 of the data time length to obtain all the data sent by the host.

[0084] When the data is sent, the host outputs 0 level until the next set of data is sent;

[0085] By applying the above-mentioned method, it is possible to ensure the parallel operation of cascading and parallel connection, and at the same time, it is possible to better cope with the complex host debugging problem existing in the existing single-line cascading method. It is no longer necessary to continuously adjust the data output frequency to adapt to the decoding frequency of the chip, so that the communication efficiency can be significantly improved.

[0086] Furthermore, due to the loss and deformation of data on the signal line, in order to enable the chip to decode correctly and stably, the data time length is relatively reasonable at a ratio of 1 / 4 and 3 / 4, and of course it should be appropriately adjusted according to the requirements of the application system.

[0087] Since the chip samples data after waiting for 1 / 2 bit time after the rising edge of the data, the period of the internal sampling clock must be agreed upon during chip design so that sampling can be performed at 1 / 2 of the data time length. However, the clock inside the chip deviates as the application link changes (temperature, voltage, etc.), and there are differences between chips during manufacturing. When multiple chips are cascaded, all chips must be taken into account for normal decoding. This requires a data frequency adaptation mechanism inside the chip.

[0088] In order to realize the chip's adaptive host sending different data width signals, a high-speed clock is designed inside the chip. The clock frequency is at least 8 times the single-bit frequency of the serial data. The host adds several empty data (generally an integer multiple of 2 for the convenience of design) before sending valid data to learn the data frequency.

[0089] like Figure 6As shown, for ease of understanding, we first assume that 4 bits of data are sent before valid data to learn the data frequency, starting from the first rising edge and ending with the fifth rising edge; these four bits of data can be any number (the rising edge of each data is consistent); the chip uses a high-speed clock to count the number of clocks for these four data, and the number of clocks divided by 4 is the number of clocks for a single bit, Tbit. Subsequent data will be decoded with the data at the time point of Tbit / 2. When the input signal is 0 at this time point, the bit is decoded to 0, otherwise it is 1.

[0090] Of course, there is a certain waiting time between each set of data. During the waiting period, the host sends a signal to output 0 level. When the internal 0 level counter of the chip is greater than the 4-bit time width, the next set of data will restart the frequency learning, so empty data for frequency learning must be added before each set of data.

[0091] From the above technical solutions, we can solve the problem of host data transmission frequency, but the chip cascade (such as Figure 1 If one chip in the middle is damaged, the subsequent chips will not work properly. A parallel mechanism is required, such as Fig.14 As shown;

[0092] In order to prevent the damage of the middle chip and cause the subsequent cascaded chips to not work properly, the chips are mainly used in parallel mode (PI is the data input port). In order for each chip to receive data correctly, each chip must have an independent address. However, the PI ports of all chips are connected in parallel. Before the chip address is assigned, it is impossible to distinguish which data is to be received from the port. Therefore, before the chip enters normal data reception, a unique address must be burned into each chip, so the address burning must be performed in the cascade mode.

[0093] In order to make the host and chip as well as the cascade and parallel systems work properly, the data format sent by the host needs to be defined as follows.

[0094] Command name Instruction Description WR_ADDR Address burning (only valid in cascade mode) WR_REG Write internal register WR_DATA Write display data RD_REG Read internal registers (valid only in cascade mode) SI_EXT Switch SI port back to PI port

[0095] like Figure 7 As shown, each instruction is preceded by frequency learning, followed by the instruction code, and then followed by different parameters.

[0096] Address burning: Fig.14 In the parallel and cascade systems shown, the initial address of the chip is 0, and the host must write an independent address to each chip. First, the host's PI signal outputs a high level, and after 1 millisecond, all chips enter the cascade mode, and the data input switches to SI. Figure 8As shown, the host sends a WR_ADDR instruction followed by an address of 0. At this time, all chips enter the address burning waiting mode, and the SO of all chips temporarily close the output. Next, the host sends a WR_ADDR instruction followed by an address of 1. After receiving the instruction and address, the first chip enters the burning process and writes the address into the chip's internal storage location (not lost when power is off). After the burning is completed, the chip opens SO and outputs the data input by SI from SO. Similarly, the host then sends a WR_ADDR instruction followed by an address of 2. The first chip directly outputs the data input by SI from SO. The SI of the second chip receives a WR_ADDR instruction whose address is not 0, and writes the received address into the chip's internal storage location. And so on, until the Nth chip writes address N into the chip's internal storage location. At this point, all chips in the entire cascade system have their addresses written, and the chips can receive other instructions and data. The entire chip address burning process is as follows. Fig.12 shown.

[0097] Since the internal storage of the chip is not lost when power is off, Fig. 9 As shown, after the chip is powered on, a power-on reset (POR) is generated inside the chip. After a period of time after the reset is completed, the internal storage address is automatically loaded inside the chip. After the address is loaded, the entire cascade system enters normal operation.

[0098] If in an existing cascade system, a chip in the middle is found to be damaged and needs to be replaced, the address of the chip needs to be re-programmed after replacement. The programming method and timing are the same as above. When the address inside the chip has been programmed (the address automatically loaded at power-on is not 0), the chip will not start programming, but the control timing is the same. In this way, only the chip that has not been programmed will be programmed, and the addresses of other chips remain unchanged.

[0099] Write internal registers: Figure 7 The command shown is composed of (WR_REG command + chip address + register address + register parameter); the host configures the chip internal function register parameters according to the application needs. When the chip address sent by the host is 0, it will be a global configuration, and the parameters of the register address corresponding to all chips will be rewritten.

[0100] Write display data: Figure 7 As shown in the figure, the command consists of (WR_DATA command + first data address + data 1 + data 2 + ... + data n); Fig.10 (parallel mode) and Fig.11(Cascade mode) As shown, the chip receives the instruction, and then loads the first data address into the address counter inside the chip. The chip with the same address as the first address saves data 1. When the data is received, the chip's internal address count automatically increases by 1. At this time, the chip with the same internal address count as the chip address saves data 2. The chip's internal address count automatically increases by 1 again, and so on. Each chip saves the data when the address matches, so that each chip will save the data specified by the host. When the chip address sent by the host is 0, it will be a global configuration, and all chips will save data 1.

[0101] Read internal registers: Figure 7 The command shown is composed of (RD_REG command + chip address + register address + read register parameter); the host reads the internal function parameters and results of the chip according to the needs of the application. In this way, the host can detect the status and results of each chip in real time.

[0102] Switch SI port back to PI port: Figure 7 As shown in the figure, this instruction switches back to the PI port in the cascade mode (SI is the data input port). Of course, if the chip data access port is changed from PI to SI, it is only necessary to pull the PI signal line high for 1ms.

[0103] From the above schemes and instructions, the entire system is started and controlled as follows Fig.13 shown.

[0104] A system for adaptive single-line parallel and cascade communication, using the adaptive single-line parallel and cascade communication method as described above, such as Fig.14 See also Figure 3 ,The system includes system architecture;

[0105] The LED chip also includes an MX device, a decoding clock, a command control module, a data control module and an address burning storage module;

[0106] MX device, used to select the input signal of SI port and PI port;

[0107] Decoding clock, used to decode the signal selected by the input MX device, and send it to the instruction control module or data control module according to the decoded data type, and forward the serial data through the SO port;

[0108] The address burning storage module is used to store the address sent by the instruction control module.

[0109] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. An adaptive single-line parallel and cascade communication method, characterized in that: The system comprises a host and a plurality of LED chips, wherein the host is provided with a first signal output port, a second signal output port and a signal receiving port, and the LED chip is provided with a parallel input port PI, a serial input port SI and a signal output port SO; the plurality of LED chips are connected in series in sequence, the first signal output port is connected to the SI port of the frontmost LED chip, the signal receiving port is connected to the SO port of the rearmost LED chip; the second signal output port is connected to the PI port of each LED chip; The communication method between the host and the LED chip is: The host output signal changes from 0 to 1 as the starting point of a single bit. When it waits for 1 / 2 of the data bit time length, it locks the data to see whether it is 0 or 1. If the data on the signal line is 0 at 1 / 2 of the time, the bit data is 0, otherwise the bit data is 1; When 1 bit of data is sent, the next 1 bit of data is sent immediately until all data are sent. The LED chip decodes each bit of data in 1 / 2 of the data time length to obtain all the data sent by the host. When the data is sent, the host outputs a 0 level until the next set of data is sent.

2. The adaptive single-line parallel and cascade communication method according to claim 1, characterized in that: The LED chip is provided with a high-speed clock; the method further comprises the steps of: The host adds 2n ​​empty data to learn the data frequency before sending valid data, where n is an integer greater than 0; The LED chip uses a high-speed clock to count the number of clocks of 2n empty data, and the number of clocks divided by 2n is the number of clocks of a single bit, Tbit; The data after the null data is decoded with the time point data of Tbit / 2. When the input signal at this time point is 0, the bit is decoded to 0, otherwise it is 1. During the waiting period, the host sends a signal to output 0 level. When the internal 0 level counter of the LED chip is greater than the 2n Bits time width, the next set of data will restart frequency learning.

3. The adaptive single-line parallel and cascade communication method according to claim 2, characterized in that: The format of data sent to the host is defined as follows: Frequency learning + instruction name + execution parameters; The command name includes one or more of: address burning command, internal register writing command, display data writing command, internal register reading command and input switching command.

4. The adaptive single-line parallel and cascade communication method according to claim 2, characterized in that: The host communicates with the LED chip in parallel mode; Before the LED chip enters normal data reception, a unique address is burned into each LED chip in cascade mode.

5. The adaptive single-line parallel and cascade communication method according to claim 4, characterized in that: Before the LED chip enters the normal data receiving mode, a unique address is burned into each LED chip in the cascade mode using the following method: The host's PI signal outputs a high level, and after 1 millisecond all chips enter the cascade mode, and the data input switches to the SI port; The host sends an address burning command with the address following 0. At this time, the LED chip enters the address burning waiting mode, and the SO ports of all LED chips temporarily shut down the output; The host sends an address burning command followed by an address of 1. After receiving the command and address, the first LED chip starts burning and writes the address into the internal storage location of the chip. After the burning is completed, the first LED chip opens the SO port and outputs the data input from the SI port from the SO port; The host sends an address burning command with the address 2 at the end. The first LED chip outputs the data inputted from the SI port from the SO port. The SI port of the second LED chip receives the WR_ADDR command with an address not equal to 0 and writes the received address into the internal storage location of the chip. And so on, until the Nth LED chip writes address N into the internal storage location of the chip; After the LED chip is powered on, a power-on reset is generated inside the chip. After a period of time after the reset is completed, the internal storage address is automatically loaded inside the LED chip. After the address loading is completed, the entire cascade system enters normal operation.

6. The adaptive single-line parallel and cascade communication method according to claim 5, characterized in that: The method further comprises: If in an existing cascade system, it is found that an LED chip in the middle is damaged and needs to be replaced, the address of the chip needs to be re-burned after replacement; When the address inside the LED chip has been programmed, the LED chip will not start programming.

7. The adaptive single-line parallel and cascade communication method according to claim 3, characterized in that: The command format of writing internal register includes: writing internal register command + LED chip address + register address + register parameter; The method for writing an internal register includes the following steps: the host configures the internal function register parameters of the LED chip according to the application requirements; when the chip address sent by the host is 0, a global configuration is performed, and the parameters of the register addresses corresponding to all LED chips will be rewritten; The read internal register format includes: read internal register instruction + chip address + register address + read register parameter; The method for reading the internal register includes the following steps: the host reads the internal function parameters and results of the LED chip according to the application requirements.

8. The adaptive single-line parallel and cascade communication method according to claim 3, characterized in that: The write display data format includes: write display data instruction + first data address + data 1 + data 2 + ... + data n; The method for writing display data includes the following steps: when the LED chip receives the instruction, the first data address is loaded into the address counter inside the LED chip, and the LED chip whose address is equal to the first data address saves data 1; when the data is received, the internal address count of the LED chip is automatically increased by 1, and at this time, the chip whose internal address count is equal to the LED chip address saves data 2, and the internal address count of the LED chip is automatically increased by 1 again, and so on, each LED chip saves the data when the address matches, so that each LED chip will save the data specified by the host; when the LED chip address sent by the host is 0, it will be a global configuration, and all LED chips will save data 1.

9. The adaptive single-line parallel and cascade communication method according to claim 1, characterized in that: The method further comprises the step of switching the input port of the LED chip: After the LED chip is powered on, the default PI port is the signal input port; When the data input port of the LED chip needs to be switched to the SI port, the PI port signal is set to 1 and the time is greater than 1mS. When the PI high level 1mS monitoring counter inside the LED chip is full, the LED chip will automatically select SI as the data input port. When you need to switch the data input port of the LED chip to the PI port, input the SI_EXT instruction at the SI port.

10. A system for adaptive single-line parallel and cascade communication, using the adaptive single-line parallel and cascade communication method according to any one of claims 1 to 9, characterized in that: The system includes the system architecture; The LED chip also includes an MX device, a decoding clock, a command control module, a data control module and an address burning storage module; The MX device is used to select the signal input to the SI port and the PI port; The decoding clock is used to decode the signal selected by the input MX device, and send it to the instruction control module or the data control module according to the decoded data type, and forward the serial data through the SO port; The address burning storage module is used to store the address sent by the instruction control module.

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