Single-sided copper embedded asymmetric structure double-sided circuit board and preparation method thereof

Abstract

The present application relates to the technical field of circuit board preparation, and specifically discloses a double-sided circuit board with a single-sided copper-embedded asymmetric structure and a preparation method thereof, which forms a structure with one side copper-clad and the other side rough substrate by single-sided etching of a double-sided copper-clad core board, and uses a gong plate process to accurately process the copper-embedded area, ensuring that the gap between the copper block and the FR4 gong vacancy is well matched, thereby avoiding the glue overflow phenomenon and ensuring the flatness of the surface. At the same time, the introduction of PI film in the lamination process and the rational use of prepregs not only enhance the bonding force between the copper block and the core board, but also prevent the resin from contaminating the surface copper foil, ensuring a high-quality yield rate. In addition, the use of a copper core board effectively prevents the quality problem of wrinkles in thin copper foil during conventional lamination.

Description

Technical Field

[0001] The present application relates to the technical field of circuit board preparation, and more specifically, to a double-sided circuit board with a single-sided copper-embedded asymmetric structure and a preparation method thereof. Background Art

[0002] In the electronics manufacturing industry, with the increasing complexity of electronic product functions and the continuous improvement of integration, the demand for circuit boards has gradually shifted from simple single-layer structures to multi-layer structures. In particular, double-sided circuit boards have attracted much attention because they can provide higher wiring density and better electrical performance. For some special applications, such as electronic products with high power, high current carrying and high heat dissipation requirements, the traditional practice is to use 2 ounces or thicker copper foil to manufacture circuit boards to meet their requirements for current carrying capacity and heat dissipation performance. However, in some cases, due to the mismatch between the designed line width and the required copper thickness, or due to cost considerations, it becomes infeasible to directly use thick copper foil.

[0003] In response to these problems, the industry generally adopts the method of partially embedding copper blocks or copper bars to replace the design of thick copper foil on the whole surface. This method can enhance the conductivity and heat dissipation efficiency of specific areas in a targeted manner without affecting the overall layout, thereby achieving the purpose of large current transmission and efficient heat dissipation. However, the current conventional embedded copper block / copper bar process still has many control difficulties, such as overflow glue problem, surface unevenness, pressure loss problem and insufficient bonding force. Specifically, during the lamination process, the resin may overflow from the embedded part, affecting the flatness of the circuit board surface. Even if there is no obvious overflow glue phenomenon, the embedded copper block may cause local surface unevenness, which poses a challenge to subsequent processes (such as welding). In addition, if the pressure distribution is uneven during lamination, it may cause poor fixation of the embedded part, thereby affecting the reliability of the product. In addition, if the bonding strength between the embedded part and the substrate is not enough, there may be a risk of delamination or falling off after long-term use, which greatly limits the scope of application of this process.

[0004] Therefore, an optimized preparation scheme for a double-sided circuit board with a single-sided copper-embedded asymmetric structure is desired. Summary of the invention

[0005] The present application provides a double-sided circuit board with a single-sided copper-embedded asymmetric structure and a preparation method thereof, which forms a structure with one side copper-clad and the other side rough substrate by single-sided etching of a double-sided copper-clad core board, and uses a gong plate process to accurately process the copper-embedded area, ensuring that the gap between the copper block and the FR4 gong vacancy is well matched, thereby avoiding the glue overflow phenomenon and ensuring the flatness of the surface. At the same time, the introduction of PI film in the lamination process and the rational use of prepregs not only enhance the bonding force between the copper block and the core board, but also prevent the resin from contaminating the surface copper foil, ensuring a high-quality yield rate. In addition, the use of a copper core board effectively prevents the quality problem of thin copper foil wrinkles during conventional lamination.

[0006] In a first aspect, a method for preparing a double-sided circuit board with a single-sided copper-embedded asymmetric structure is provided, comprising:

[0007] Performing single-side etching on a core board with copper clad on both sides to obtain an etched core board, wherein one side of the etched core board is copper clad and the other side of the etched core board is a rough substrate;

[0008] Drilling a reference hole on the etched core board, and processing the copper-embedded area of ​​the etched core board using a gong plate process to obtain a gong plate-processed core board;

[0009] Prepare copper blocks;

[0010] Browning and drying the gong plate treated core plate and the copper block to obtain a browned core plate and a browned copper block;

[0011] Using a PI film, laminating the browned core board and the browned copper block to obtain a circuit board substrate;

[0012] The circuit board substrate is post-processed to obtain a double-sided circuit board with a single-sided copper-embedded asymmetric structure.

[0013] In a second aspect, a double-sided circuit board with a single-sided copper-embedded asymmetric structure is provided, wherein the double-sided circuit board with a single-sided copper-embedded asymmetric structure is prepared by the preparation method of the double-sided circuit board with a single-sided copper-embedded asymmetric structure as described in the first aspect.

[0014] The present application provides a double-sided circuit board with a single-sided copper-embedded asymmetric structure and a preparation method thereof, which forms a structure with one side copper-clad and the other side rough substrate by single-sided etching of the double-sided copper-clad core board, and uses the gong plate process to accurately process the copper-embedded area, ensuring that the gap between the copper block and the FR4 gong vacancy is well matched, thereby avoiding the overflow of glue and ensuring the flatness of the surface. At the same time, the introduction of PI film in the lamination process and the rational use of prepregs not only enhance the bonding force between the copper block and the core board, but also prevent the resin from contaminating the surface copper foil, ensuring a high-quality yield rate. In addition, the use of a copper core board effectively prevents the quality problem of thin copper foil wrinkles during conventional lamination. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments of the present application are briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present application, and are not intended to limit the present application.

[0016] Figure 1 This is a schematic flow chart of a double-sided circuit board with a single-sided copper embedded asymmetric structure and a preparation method thereof according to an embodiment of the present application.

[0017] Figure 2 This is a schematic flow chart of step S5 in a double-sided circuit board with asymmetric structure and a single-sided copper embedding according to an embodiment of the present application and a method for preparing the same.

[0018] Figure 3 This is a schematic flow chart of step S6 in a double-sided circuit board with asymmetric structure and a single-sided copper embedding according to an embodiment of the present application and a method for preparing the same.

[0019] Figure 4 It is a schematic flow chart of step S64 in the single-sided copper embedded asymmetric structure double-sided circuit board and the preparation method thereof according to the embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work also fall within the scope of protection of the present application.

[0021] In view of the above technical problems, in the technical solution of the present application, a method for preparing a double-sided circuit board with a single-sided copper embedded asymmetric structure is proposed, such as Figure 1 As shown, the preparation method of the single-sided copper-embedded asymmetric structure double-sided circuit board is characterized in that it includes: S1, single-sided etching of the double-sided copper-clad core board to obtain an etched core board, wherein one side of the etched core board is copper-clad and the other side of the etched core board is a rough substrate; S2, drilling reference holes on the etched core board, and using a gong plate process to treat the copper-embedded area of ​​the etched core board to obtain a gong plate-treated core board; S3, preparing copper blocks; S4, browning and drying the gong plate-treated core board and the copper block to obtain a browned core board and a browned copper block; S5, using a PI film, laminating the browned core board and the browned copper block to obtain a circuit board substrate; S6, post-treating the circuit board substrate to obtain a single-sided copper-embedded asymmetric structure double-sided circuit board. In the above-mentioned method for preparing a double-sided circuit board with a single-sided copper-embedded asymmetric structure, a structure with one side copper-clad and the other side rough substrate is formed by single-sided etching of the double-sided copper-clad core board, and the copper-embedded area is accurately processed by the gong plate process, ensuring that the gap between the copper block and the FR4 gong vacancy is well matched, thereby avoiding the overflow of glue and ensuring the flatness of the surface. At the same time, the introduction of PI film in the lamination process and the rational use of prepregs not only enhance the bonding force between the copper block and the core board, but also prevent the resin from contaminating the surface copper foil, ensuring a high-quality yield rate. In addition, the use of a copper core board effectively prevents the quality problem of wrinkles in thin copper foil during conventional lamination.

[0022] Exemplarily, in step S1, a core board with double-sided copper cladding is single-sidedly etched to obtain an etched core board, wherein one side of the etched core board is copper clad and the other side of the etched core board is a rough substrate. It should be understood that by single-sidedly etching the core board with double-sided copper cladding to obtain an etched core board with one side copper clad and the other side being a rough substrate, it is ensured that the circuit board can meet specific design requirements and technical performance in subsequent processing and use. Specifically, by processing in this way, a rough surface can be formed on the other side while maintaining a complete copper layer on one side of the circuit board, which helps to enhance the bonding force with the embedded copper block or copper bar, and prevents the resin from overflowing and contaminating the circuit layer, thereby improving the quality and reliability of the finished product.

[0023] Specifically, the process of single-sided etching includes: first, a core board covered with copper foil on both sides is selected as the starting material. Next, according to the design requirements, a resist (such as photoresist) is applied to the side where the copper layer does not need to be retained, and the area where the copper layer needs to be removed is defined through processes such as exposure and development. Then, the treated core board is placed in an etching solution, which will dissolve the copper layer not protected by the resist, but will not affect the side covered with the resist and the underlying substrate. After an appropriate period of etching, the core board is removed and the residual etching solution and resist are cleaned off. At this time, one side of the core board still retains a complete copper layer, while the other side forms a rough surface caused by the etching process. This single-sided etching method not only limits the location of the copper layer, but also creates an environment that is conducive to subsequent process operations (such as copper embedding). The roughened substrate surface increases the contact area with the prepreg and other materials, improves the bonding strength, and reduces the risk of delamination due to differences in thermal expansion coefficients. At the same time, such a structure also avoids the problem of resin overflowing from the embedded part during the lamination process, ensures the flatness of the circuit board surface, and provides better conditions for subsequent processes such as welding.

[0024] Exemplarily, in step S2, a reference hole is drilled on the etched core board, and the copper-embedded area of ​​the etched core board is processed using a gong plate process to obtain a gong plate-processed core board. It should be understood that drilling the reference hole provides a reference point for the entire manufacturing process, making the alignment between the layers more accurate, thereby ensuring the stacking accuracy of the multilayer circuit board. At the same time, the gong plate process is used to process the copper-embedded area, which can accurately remove the substrate material at the position where the copper block needs to be embedded, forming a small gap match that matches the size of the copper block, which is not only convenient for placing the copper block, but also can ensure that the resin of the semi-cured sheet is filled on the sides of the copper block, and the bottom semi-cured sheet resin is fully in contact, which is conducive to improving the bonding strength of the two materials, avoiding glue overflow, and ensuring surface flatness.

[0025] In the specific operation, after the single-sided etching step is completed, several reference holes are first determined and drilled on the etched core board. These reference holes play a vital role in the entire circuit board production process. They serve as the positioning basis for subsequent processes such as pattern transfer and drilling, ensuring that all processing operations can be accurately performed according to design requirements. Next, the specific area where the copper block is planned to be embedded is finely processed using the gong plate process (i.e., using a milling cutter or other cutting tool through a CNC machine tool). This process accurately controls the degree of substrate material removal according to pre-set parameters to ensure that the gong space is slightly larger than the copper block size by 0.05-0.075mm, which is convenient for the installation of the copper block and ensures that there is appropriate space between the two for the prepreg to fill and achieve a good bonding effect. After such treatment, the final result is a gong plate-treated core board that is ready to accept the copper block embedding and has high precision and good surface quality.

[0026] In one embodiment, in step S3, preparing the copper block includes: cutting the copper plate to obtain the copper block. The process of preparing the copper block, especially obtaining the required copper block by cutting the copper plate, is to ensure that the copper block embedded in the circuit board can accurately meet the design specifications and size requirements. Doing so not only ensures a good fit between the copper block and the pre-hollowed FR4 substrate, but also improves the bonding force between the copper block and the core board, thereby enhancing the electrical performance and mechanical strength of the circuit board. At the same time, the precisely prepared copper block helps to avoid problems such as overflowing glue and uneven surface during the lamination process, ensuring the high quality and flatness of the final product.

[0027] Specifically, preparing copper blocks includes: first, determining the key dimensions of the required copper blocks, such as shape, size, and thickness, based on the design drawings of the circuit board. Then, using high-precision cutting tools such as laser cutting machines, stamping equipment, or computer-controlled milling machines (CNC), individual copper blocks are cut out from the larger copper plate according to these size requirements. In order to ensure the smoothness and dimensional accuracy of the cutting edges, a highly automated cutting technology is usually used, which can not only improve production efficiency, but also reduce the adverse effects of human errors. In addition, the needs of subsequent processing may also be considered during the cutting process, such as reserving a certain margin for grinding or adjusting the size. Once the cutting is completed, the resulting copper block can be further browned and dried to enhance its bonding performance with the prepreg and other materials, preparing for the next lamination and lamination step.

[0028] Exemplarily, in step S4, the core board after the gong plate treatment and the copper block are browned and dried to obtain the browned core board and the browned copper block. It should be understood that browning is a surface treatment process that generates a uniform and rough oxide layer on the copper surface through chemical reaction. This oxide layer not only increases the friction coefficient of the copper surface, but also provides more microscopic contact points, thereby greatly improving the bonding strength between copper and prepreg (such as epoxy resin) or other copper-clad materials. At the same time, the surface after browning has good heat resistance and moisture resistance, which helps to prevent delamination or degumming during high-temperature pressing, and ensures the stability and reliability of the circuit board in long-term use.

[0029] In the specific operation, after the gong plate treatment is completed and the copper block is prepared, the two will be placed together in the browning treatment equipment. In this process, a specific browning solution needs to be prepared first. The solution usually contains sulfuric acid, hydrogen peroxide and other additives. These ingredients work together on the copper surface to promote the oxidation reaction. The core plate and copper block after the gong plate treatment are immersed in this solution for a period of time, so that a layer of brown oxide film is evenly generated on the copper surface. In order to ensure the consistency and uniformity of the treatment effect, the whole process needs to strictly control parameters such as temperature, time and solution concentration. After the browning treatment, the next step is drying. The purpose of drying is to remove the residual moisture in the treatment process to prevent the steam generated by heating during the subsequent pressing from affecting the quality of the finished product. Usually a hot air circulation oven or other types of drying equipment is used for drying to ensure that all treated surfaces are completely dry. The final result is a browning core plate and a browning copper block.

[0030] In one embodiment, Figure 2 As shown, in step S5, the PI film is used to laminate the browned core board and the browned copper block to obtain a circuit board substrate, including: S51, attaching a polyimide film to the copper foil surface of the browned core board; S52, placing the browned copper block on the polyimide film, the browned copper block corresponding to the copper embedded area; S53, placing a semi-cured sheet on the browned copper block; S54, covering a layer of copper foil on the semi-cured sheet; S55, placing a steel plate on the copper foil to obtain a laminated structure, wherein the steel plate serves as a support for the lamination process; S56, laminating the laminated structure to obtain the circuit board substrate.

[0031] Specifically, the lamination process starts with attaching a layer of polyimide film to the copper foil surface of the core board after browning treatment. This film not only provides good thermal stability and mechanical strength, but also plays an isolating role, ensuring that the resin in the prepreg will not contaminate the surface copper foil of the core board during lamination. Even if there is a small amount of overflow, it can be easily removed by subsequent sanding. Next, the copper block after browning treatment is precisely placed on this layer of polyimide film so that it corresponds to the copper embedding area that has been pre-empted. The small gap between the copper block and the empty space is designed so that the space between the two can be fully filled with the resin in the prepreg, thereby enhancing the bonding effect between the copper block and the core board. Then, a prepreg with an appropriate amount of glue is placed on top of the copper block. These prepregs will melt and fill the gap between the copper block and the core board during the lamination process to form a solid connection. Subsequently, a new layer of copper foil is covered on the prepreg, which will become the copper cladding layer on the other side of the circuit board, providing a basis for subsequent circuit wiring. In order to ensure that the entire laminate structure remains flat and is not affected by external pressure during the lamination process, a steel plate is placed on the top layer as a support. This steel plate plays a key role in the entire lamination process. It evenly distributes the applied pressure and ensures that the layers of materials fit tightly without offset or deformation. After completing the above steps, the entire laminate structure enters the lamination stage. In this process, the high temperature and high pressure environment causes the resin in the prepreg to completely melt and tightly bond with the upper and lower layers of material. After the lamination is completed, it is cooled and formed, and the final result is a circuit board substrate made of multiple layers of materials firmly bonded together. The embedded copper block forms a whole with the surrounding materials, which not only ensures the needs of large current transmission and efficient heat dissipation, but also maintains the flatness and aesthetics of the circuit board surface.

[0032] In one embodiment, in step S6, the circuit board substrate is post-processed to obtain a double-sided circuit board with a single-sided copper-embedded asymmetric structure, including: drilling, copper deposition, full-board electroplating, pattern transfer, copper-tin plating, film stripping etching, tin stripping, automatic optical inspection, solder mask text printing, lead-free tin spraying, molding, surface cleaning, testing, appearance inspection and reliability testing of the circuit board substrate.

[0033] The post-processing process of the circuit board substrate starts with drilling, which is to prepare for the subsequent installation of components and electrical connections by accurately drilling holes on the circuit board; followed by the copper deposition process, which deposits a thin layer of copper inside the drilled hole wall to ensure good conductivity between the holes. Then the whole board is electroplated to increase the thickness of the hole wall and surface copper layer, and improve the current carrying capacity and durability of the circuit board. In order to define the circuit pattern, the next step is the graphic transfer step, which uses photolithography technology to transfer the pre-designed circuit diagram to the circuit board and plate a layer of copper-tin alloy in the designated area. This step is crucial to form a precise circuit path. After the copper-tin plating is completed, the film needs to be stripped and etched to remove the unnecessary metal layer, leaving only the circuit pattern formed according to the design; then the tin is stripped to further accurately define the circuit pattern. Automatic optical inspection (AOI) is a quality control method introduced at this stage. It uses high-precision camera scanning and comparison with design data to identify possible defects or deviations to ensure that each circuit board meets high quality standards. In order to protect the circuit and prevent short circuits, solder mask ink is printed on the surface of the circuit board and identification text is added, which not only plays a protective role but also facilitates identification. The lead-free tin-spraying process is to spray a layer of tin on the surface of the circuit board to enhance the solderability and corrosion resistance during welding. The molding process cuts or trims the circuit board according to the size and shape requirements of the final product to meet the assembly requirements. Surface cleaning is to remove residual flux and other contaminants in the production process to ensure the cleanliness of the circuit board. Finally, the testing process includes electrical performance testing and reliability testing to verify whether the function of the circuit board is normal and whether it can work stably under various environmental conditions. Appearance inspection is a comprehensive inspection of the finished product by manual or machine vision system to ensure that there are no obvious physical defects.

[0034] The above-prepared single-sided copper-embedded asymmetric double-sided circuit board has the following advantages: 1. There is a small gap between the copper block and the FR4 gong vacancy, which is convenient for placing and removing the copper block. At the same time, it can ensure that the resin of the semi-cured sheet is filled on the sides of the copper block. In addition, the resin of the semi-cured sheet on the bottom is fully in contact, which is conducive to improving the bonding strength of the two materials. 2. The cutting of the copper block is equivalent to the core board, and the outer surface steel plate is used as the reference surface. 2-3 semi-cured sheets are used in the middle during pressing. When the copper block is slightly thinner or thicker than the core board, the semi-cured sheet in the middle has enough buffer space to ensure that the surface of the copper block is completely flush with the surface of the first and second core boards. 3. A 0.025-0.05MM PI film is attached to the outer surface of the core board, which can ensure that the resin of the semi-cured sheet is filled along the gap between the core board and the copper block during pressing without contaminating the surface copper foil of the core board. Even if there is, it is very little and can be easily removed by normal sanding. 4. The use of a copper core board will not cause quality problems caused by wrinkles of conventional pressed thin copper foil. 5. Although the copper block has an asymmetric structure, which is not conducive to warping control, the thickness of the core board is more than 5 times that of the prepreg, which can overcome the influence of its structure and ensure that it meets the requirements of SMT and the deformation degree is within 0.75%. 6. Using double-sided materials to etch one side is conducive to improving the bonding strength of the materials.

[0035] In particular, in the preparation process, automatic optical inspection is a key technology, which is an indispensable part of ensuring product quality. It can accurately identify and locate possible subtle defects in the circuit board, such as short circuit, open circuit or poor solder joints, etc., to ensure that each circuit board shipped meets strict design standards, further improving the quality reliability and market competitiveness of the product. Specifically, in the process of automatic optical inspection, the technical concept of the present application is to obtain a circuit board surface scan image by scanning the surface of the circuit board with a camera, and input this scan image and the circuit board surface design image into an image processing and recognition algorithm based on artificial intelligence and deep learning for analysis, so as to capture the surface state detection features and surface state design features of the circuit board, and use the difference encoding semantics between the state features of the two to perform circuit board defect detection. In this way, optical inspection can be automatically performed based on the semantic comparison and difference information between the surface state of the circuit board actually produced and the surface state of the circuit board on the design drawing to identify the defects of the circuit board, providing support for improving the preparation quality of circuit board products.

[0036] In one embodiment, Figure 3As shown, the automatic optical inspection includes: S61, using a camera to scan the surface of the circuit board to obtain a circuit board surface scan image; S62, extracting a circuit board surface design image from a background database; S63, respectively performing circuit board surface state feature extraction on the circuit board surface scan image and the circuit board surface design image to obtain a circuit board surface state image semantic coding feature map and a circuit board surface state design image semantic coding feature map; S64, performing feature selection based on importance measurement on the circuit board surface state image semantic coding feature map and the circuit board surface state design image semantic coding feature map to obtain a sparse circuit board surface state image semantic coding feature map and a sparse circuit board surface state design image semantic coding feature map; S65, calculating the position difference between the sparse circuit board surface state image semantic coding feature map and the sparse circuit board surface state design image semantic coding feature map to obtain a circuit board surface real-design state difference coding feature map; S66, inputting the circuit board surface real-design state difference coding feature map into a detection module based on a classifier to obtain a detection result, and the detection result is used to indicate whether the circuit board has a defect.

[0037] Exemplarily, in step S61, a camera is used to scan the surface of the circuit board to obtain a scanned image of the circuit board surface. It should be understood that the use of a camera to scan the surface of the circuit board to obtain a scanned image of the circuit board surface is to achieve high-precision automatic optical inspection (AOI) to ensure that each circuit board meets strict design standards and quality requirements. In this way, subtle defects that may exist in the circuit board, such as short circuits, open circuits, or poor solder joints, can be accurately identified and located, thereby ensuring the reliability and market competitiveness of the product. Camera scanning can not only capture tiny defects that are difficult to detect with the naked eye, but also sense the overall state of the circuit board, providing detailed data support for subsequent defect analysis and quality control.

[0038] In one embodiment, the circuit board to be tested is first placed on a professional testing device equipped with a high-resolution camera. The camera is usually mounted on a movable platform and can move accurately in the X-axis and Y-axis directions to cover the entire circuit board surface. When scanning begins, the camera scans the circuit board line by line along a preset path, while collecting image information of every detail. In order to ensure image quality and detection accuracy, a light source of a specific wavelength is used to illuminate the surface of the circuit board during the scanning process to reduce interference from reflected light and highlight the contrast between different materials. In addition, the camera is connected to a background database, which stores standard images of the corresponding circuit board design. These standard images are used as reference benchmarks for subsequent image processing and comparison analysis. After the scan is completed, the resulting scanned image of the circuit board surface is immediately transmitted to a computer system for processing.

[0039] Exemplarily, in step S62, the circuit board surface design image is extracted from the background database. It should be understood that the circuit board surface design image is extracted from the background database to provide an accurate reference benchmark in the automatic optical inspection (AOI) process, so that the circuit board surface image actually scanned can be accurately compared with the design standard. This process ensures that each circuit board produced strictly follows the original design intent, thereby ensuring the electrical performance, reliability and consistency of the product. By comparing the actually manufactured circuit board with the original design image, any possible manufacturing defects or deviations, such as short circuits, open circuits, poor solder joints, etc., can be quickly identified, thereby improving product quality and production efficiency.

[0040] In one embodiment, when the camera completes scanning the surface of the circuit board and obtains a real-time image, the system will immediately retrieve the design image of the corresponding model circuit board from the background database. This background database is a digital warehouse that centrally stores all circuit board design information, including key parameters such as detailed layout, size, routing path, etc. of each circuit board. In order to ensure that the correct design image is extracted, the system usually relies on information such as pre-entered product identifiers or batch numbers to locate specific design files. Once the design image to be extracted is determined, the system will access the database server through a high-speed network connection and download the relevant data to the local computer environment for immediate analysis.

[0041] Exemplarily, in step S63, the circuit board surface state feature extraction is performed on the circuit board surface scan image and the circuit board surface design image respectively to obtain the circuit board surface state image semantic coding feature map and the circuit board surface state design image semantic coding feature map. It should be understood that, considering that both the circuit board surface scan image and the circuit board surface design image contain local detail semantics and global overall semantics, the image semantics of the two can reflect the state characteristics of different aspects of the circuit board, which are of great significance to the state detection and defect identification of the circuit board. Therefore, in order to be able to discover tiny defects in the circuit board that are difficult to detect with the naked eye, it is also possible to perceive the overall state of the circuit board, providing more comprehensive and accurate data support for subsequent circuit board defect detection.

[0042] In one embodiment, the circuit board surface state feature extraction is performed on the circuit board surface scan image and the circuit board surface design image respectively to obtain the circuit board surface state image semantic coding feature map and the circuit board surface state design image semantic coding feature map, including: inputting the circuit board surface scan image and the circuit board surface design image into a circuit board surface state feature extractor based on a dynamic convolutional labeling model to obtain the circuit board surface state image semantic coding feature map and the circuit board surface state design image semantic coding feature map. In particular, the circuit board surface state feature extractor based on the dynamic convolutional labeling model is a combination of a convolutional neural network (CNN) and a Transformer model. Its main idea is to divide the image into multiple local blocks, and use CNN to process and feature analyze each local image block. Finally, the feature maps of these local blocks are spliced ​​together, and global processing and long-distance dependency association encoding are performed through the Transformer model. In this way, the local detailed states of the circuit board in the circuit board surface scan image and the circuit board surface design image can be captured respectively, and the overall semantics between these local detailed states can also be understood, thereby improving the accuracy and comprehensiveness of the actual detection and design circuit board state feature extraction, and providing support for subsequent difference feature extraction and circuit board defect detection.

[0043] Exemplarily, in step S64, feature selection based on importance measurement is performed on the semantic coding feature map of the circuit board surface state image and the semantic coding feature map of the circuit board surface state design image to obtain a sparse circuit board surface state image semantic coding feature map and a sparse circuit board surface state design image semantic coding feature map. It should be understood that the circuit board surface state image semantic coding feature map and the circuit board surface state design image semantic coding feature map respectively contain semantic features of the actual detection circuit board surface state and semantic features of the design circuit board surface state related to the circuit board, and these two features may contain a large amount of redundant information or noise, which are not conducive to accurately identifying the difference between the actual state and the design state of the circuit board. At the same time, in the circuit board surface state image semantic coding feature map and the circuit board surface state design image semantic coding feature map, not all extracted circuit board surface state features have the same contribution to the final defect detection task, and some features may be highly correlated or less important. Therefore, in order to more effectively identify, quantify and highlight the differences between the actual production and design of circuit boards, while ensuring that these differences are accurately captured for subsequent defect analysis and quality control, in the technical solution of the present application, the circuit board surface state image semantic coding feature map and the circuit board surface state design image semantic coding feature map are further subjected to feature selection based on importance metrics to obtain sparse circuit board surface state image semantic coding feature maps and sparse circuit board surface state design image semantic coding feature maps. Through the feature selection process based on importance metrics, the feature representation in the deep learning model can be optimized by evaluating the interaction between the local surface state features actually detected by the circuit board and the designed local surface state features and their neighboring features, respectively, so as to achieve effective compression and sparseness of the original circuit board surface state image semantic coding feature map and the circuit board surface state design image semantic coding feature map.

[0044] In one embodiment, Figure 4As shown, feature selection based on importance measurement is performed on the semantic coding feature map of the circuit board surface state image and the semantic coding feature map of the circuit board surface state design image to obtain a sparse circuit board surface state image semantic coding feature map and a sparse circuit board surface state design image semantic coding feature map, including: S641, feature decomposition is performed on the circuit board surface state image semantic coding feature map to obtain a set of circuit board surface state image semantic coding local feature vectors; S642, each circuit board surface state image semantic coding local feature vector in the set of circuit board surface state image semantic coding local feature vectors is input into an importance measurement module to obtain a set of circuit board surface state image semantic coding local feature importance score values; S643, based on the set of circuit board surface state image semantic coding local feature importance score values, feature selection and feature shape reshaping are performed on the set of circuit board surface state image semantic coding local feature vectors to obtain the sparse circuit board surface state image semantic coding feature map.

[0045] In one embodiment, in step S641, feature decomposition is performed on the semantic coding feature map of the circuit board surface state image to obtain a set of semantic coding local feature vectors of the circuit board surface state image, including: feature decoupling and feature flattening are performed on the semantic coding feature map of the circuit board surface state image to obtain a set of semantic coding local feature vectors of the circuit board surface state image. Specifically, the process can be expressed by a formula as follows:

[0046]

[0047]

[0048] in, is the semantic coding feature map of the circuit board surface state image, is a feature decoupling operation, They represent the first, second, and third features in the set of semantic coding feature matrices of the circuit board surface state image. and The semantic encoding feature matrix of the circuit board surface state image, To flatten the features, They represent the first, second, and third features in the set of semantically encoded local feature vectors of the circuit board surface state image. and The local feature vector of the semantic encoding of the circuit board surface state image.

[0049] Exemplarily, in step S642, each circuit board surface state image semantically encoded local feature vector in the set of circuit board surface state image semantically encoded local feature vectors is input into an importance measurement module to obtain a set of circuit board surface state image semantically encoded local feature importance score values. Specifically, the process can be expressed by the formula:

[0050]

[0051] in, and They are The corresponding weight matrix and bias vector, is matrix multiplication, is the modulation vector, for The corresponding circuit board surface state image semantically encodes the local feature importance score value.

[0052] It should be understood that the process of inputting each vector in the set of local feature vectors of the semantic encoding of the circuit board surface state image into the importance measurement module to obtain a set of score values ​​for the importance of each local feature is intended to accurately locate and quantify which local features are most critical for identifying circuit board defects. In the automatic optical inspection (AOI) scenario, this step greatly enhances the understanding and analysis capabilities of the circuit board surface state and ensures the accuracy and reliability of defect detection. Through this process, the degree of influence of each local feature vector on the final detection result can be evaluated. The importance measurement module assigns a score value to each local feature based on the pre-trained model or algorithm, considering the relationship between local features and their consistency with the global structure. These score values ​​reflect the importance of the local feature in describing the actual state of the circuit board, that is, how much it contributes to determining whether there is a defect and what type of defect it is. For example, on a complex multi-layer circuit board, some areas may contain dense circuit layouts or tiny solder joints, while other areas may be relatively simple blank areas. Through importance measurement, those features that are critical to ensuring electrical connections, such as the quality of solder joints, the continuity and width of lines, etc., can be identified and given higher scores. Conversely, features that have less impact on the overall functionality may receive lower score values. This weight distribution helps in the subsequent feature selection step, allowing the system to remove redundant or irrelevant data while retaining the most critical information, thereby optimizing the use of computing resources.

[0053] In one embodiment, in step S643, based on the set of importance score values ​​of the semantically encoded local features of the circuit board surface state image, feature selection and feature shape reshaping are performed on the set of semantically encoded local feature vectors of the circuit board surface state image to obtain the sparse circuit board surface state image semantic encoding feature map, including: based on the set of importance score values ​​of the semantically encoded local features of the circuit board surface state image, the set of semantically encoded local feature vectors of the circuit board surface state image is arranged in descending order to obtain a descending sequence of the semantically encoded local feature vectors of the circuit board surface state image. Specifically, the process can be expressed by the formula:

[0054]

[0055] in, Indicates descending sort operation. They represent the first, second, and third features in the descending sequence of the semantically encoded local feature vectors of the circuit board surface state image. and The local feature vector of the semantic encoding of the circuit board surface state image.

[0056] Based on the neighborhood features of each circuit board surface state image semantically encoded local feature vector in the descending sequence of the circuit board surface state image semantically encoded local feature vector, the feature neighborhood activity of each circuit board surface state image semantically encoded local feature vector is calculated to obtain a sequence of feature neighborhood activity. Specifically, the process can be expressed by the formula:

[0057]

[0058] in, is the first in the descending sequence of the semantically encoded local feature vector of the circuit board surface state image The first local feature vector of the semantic encoding of the circuit board surface state image Position feature values, For the said The number of eigenvalues ​​in the semantically encoded local feature vector of the circuit board surface state image, For the said Neighborhood feature factors of the local feature vectors of the semantic encoding of the circuit board surface state images, It is Neighborhood feature factors of the local feature vectors of the semantic encoding of the circuit board surface state images, It is the The feature neighborhood activity of the local feature vector of the semantic encoding of the circuit board surface state image.

[0059] Based on the sequence of the feature neighborhood activity, feature selection is performed on the descending sequence of the semantically encoded local feature vectors of the circuit board surface state image to obtain a descending sequence of the semantically encoded local feature vectors of the circuit board surface state image after selection. Specifically, the process can be expressed by the formula:

[0060]

[0061]

[0062] in, is a predetermined threshold, is the feature selection process, is the first, second, and third in the descending sequence of the semantically encoded local feature vector of the circuit board surface state image after selection. and The local feature vector of the semantic encoding of the circuit board surface state image after selection.

[0063] The descending sequence of the selected circuit board surface state image semantic coding local feature vectors is reshaped to obtain the sparse circuit board surface state image semantic coding feature map. Specifically, the process can be expressed as follows:

[0064]

[0065] in, It is the characteristic shape reshaping process, The process of performing feature selection based on importance measurement on the semantic coding feature map of the circuit board surface state design image to obtain the sparse circuit board surface state design image semantic coding feature map can refer to the data processing process of the semantic coding feature map of the circuit board surface state image.

[0066] It should be understood that, first, by sorting the local feature vectors in descending order according to their importance scores, the system can quickly identify which features are most critical to describing the actual state of the circuit board. This sorting not only helps focus on the most important information, but also provides an ordered data structure for subsequent processing. High-scoring features usually correspond to key areas that directly affect the function of the circuit board, such as solder joint quality, line continuity, etc.; while low-scoring features may be redundant or insignificant data. Therefore, descending order enables the system to prioritize the most important features in subsequent steps while reducing the impact of unnecessary information. Next, based on the sorted feature vector sequence, the system analyzes the relationship between each feature vector and its surrounding neighborhood features to calculate the feature neighborhood activity. This process aims to evaluate the relative importance of each local feature in the global context. For example, if a seemingly ordinary solder joint is located at a location that connects multiple key components, its neighborhood activity will be high, indicating that it plays a vital role in the function of the entire circuit board. In this way, the system can capture complex patterns and potential associations that cannot be reflected by a single feature, thereby gaining a more comprehensive understanding of the state of the circuit board. Subsequently, based on the sequence of feature neighborhood activity, the system will perform feature selection on the original descending sequence to obtain a new descending sequence. The core of this step is to remove redundant information that is important in itself but highly correlated with neighboring features, and only retain those features that truly have unique contributions. Such a feature selection method can not only improve the generalization ability of the model, but also enhance the understanding of the intrinsic structure of the circuit board surface state, promote deeper learning and better adaptability. Finally, the descending sequence after feature selection is reshaped to form a sparse semantic encoding feature map of the circuit board surface state image. This sparse processing means that only the features that best reflect the actual state of the circuit board are retained, which greatly reduces the amount of data while maintaining the validity and integrity of the information.

[0067] In summary, taking the sparse circuit board surface state image semantic coding feature map obtained by performing feature selection based on importance measurement on the semantic coding feature map of the circuit board surface state image as an example, through the feature selection processing based on importance measurement, the input circuit board surface state image semantic coding feature map can be effectively compressed and optimized through multi-level analysis of the circuit board surface state features, which not only improves the efficiency of feature extraction, but also enhances the understanding of the intrinsic structure of the circuit board surface state, and promotes deeper learning of circuit board surface state semantics and better generalization ability. Compared with traditional feature selection algorithms, feature selection processing based on importance measurement can identify and remove those features that are important in the local features of the circuit board surface state but highly correlated with its neighbors, thereby effectively reducing redundant information and improving model efficiency. At the same time, by comprehensively considering the relationship between the local features of the circuit board surface state and its neighborhood, it can better capture the complex patterns in the data and the interaction between local features. In addition, since the feature selection processing method based on importance measurement can emphasize the relationship between features rather than simply relying on the importance of individual features, the selected features can often better reflect the true characteristics of the circuit board surface state semantics, thereby improving the transparency and interpretability of the model decision, and facilitating understanding the impact of each local feature of the circuit board surface state on the final feature representation and subsequent defect detection tasks, thereby improving the interpretability and credibility of the model.

[0068] Exemplarily, in step S65, the positional difference between the semantic coding feature map of the sparse circuit board surface state image and the semantic coding feature map of the sparse circuit board surface state design image is calculated to obtain the circuit board surface real-design state difference coding feature map. It should be understood that by calculating the difference semantics between the circuit board surface real state features and the design state features after sparseness and feature selection optimization, the extent of these differences can be quantified. For example, some subtle changes may be normal fluctuations within the allowable tolerance range, while other larger differences may indicate serious manufacturing defects. Quantifying the difference helps to distinguish between acceptable variations and unacceptable defects. In addition, by calculating the difference between each corresponding position between the two circuit board surface state features, the specific position where the circuit board in actual production deviates from the design standard can be accurately located. These deviations may include inconsistencies in line width, shape, position, etc., which are potential quality problems and provide a basis for subsequent defect detection and quality control.

[0069] Exemplarily, in step S66, the circuit board surface real-design state difference coding feature map is input into the detection module based on the classifier to obtain the detection result, and the detection result is used to indicate whether the circuit board has defects. In other words, the difference coding features between the real state and the design state of the circuit board surface are used for classification processing to detect circuit board defects. In this way, optical detection can be automatically performed based on the semantic comparison and difference information between the surface state of the circuit board actually produced and the surface state of the circuit board on the design drawing to identify the defects of the circuit board, providing support for improving the preparation quality of circuit board products.

[0070] In one embodiment, after the difference between the actual state and the designed state of the circuit board surface is encoded into feature maps, these feature maps are input into a pre-trained neural network. The last layer of the network uses the softmax function as the activation function, which is responsible for converting the numerical value output by the previous layer into the probability distribution of these two categories. In this way, the softmax classifier can give the probability value corresponding to each possible category (i.e., whether there is a defect), thereby determining the most likely classification result. In a specific embodiment, if the processed feature map shows that some areas are abnormal, the softmax classifier may give the following prediction results: the probability of "defects" is 0.9, and the probability of "no defects" is 0.1. This indicates that the circuit board is likely to be defective because the probability of the "defects" category is significantly higher than that of the other category.

[0071] In summary, the double-sided circuit board with asymmetric structure of single-sided copper embedding according to the embodiment of the present application and its preparation method are explained, which forms a structure with one side copper-clad and the other side rough substrate by single-sided etching of the double-sided copper-clad core board, and uses the gong plate process to accurately process the copper-embedded area, ensuring that the gap between the copper block and the FR4 gong vacancy is well matched, thereby avoiding the overflow of glue and ensuring the flatness of the surface. At the same time, the introduction of PI film in the lamination process and the rational use of prepreg not only enhance the bonding force between the copper block and the core board, but also prevent the resin from contaminating the surface copper foil, ensuring a high-quality yield rate. In addition, the use of a copper core board effectively prevents the quality problem of wrinkles of thin copper foil during conventional lamination.

[0072] Specifically, a double-sided circuit board with a single-sided copper embedded asymmetric structure is also provided, and the double-sided circuit board with a single-sided copper embedded asymmetric structure is prepared by the aforementioned preparation method of the double-sided circuit board with a single-sided copper embedded asymmetric structure.

[0073] The basic principle of the present invention is described above in conjunction with specific embodiments. However, it should be pointed out that the advantages, strengths, effects, etc. mentioned in the present invention are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. must be possessed by each embodiment of the present invention. In addition, the specific details of the above embodiments are only for the purpose of illustration and facilitation of understanding, rather than limitation, and the above details do not limit the present invention to being implemented by adopting the above specific details.

[0074] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments. In the several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the module division is only a logical function division, and there may be other division methods in actual implementation. The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0075] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0076] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference to a figure in a claim should not be considered as limiting the claim to which it relates.

[0077] In addition, it is obvious that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units stated in the device claim can also be implemented by one unit through software or hardware.

[0078] Finally, it should be noted that the above description has been given for the purpose of illustration and description. In addition, the above embodiments are only used to illustrate the technical solution of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for preparing a double-sided circuit board with a single-sided copper-embedded asymmetric structure, characterized in that: include: Performing single-side etching on a core board with copper clad on both sides to obtain an etched core board, wherein one side of the etched core board is copper clad and the other side of the etched core board is a rough substrate; Drilling a reference hole on the etched core board, and processing the copper-embedded area of ​​the etched core board using a gong plate process to obtain a gong plate-processed core board; Prepare copper blocks; Browning and drying the gong plate treated core plate and the copper block to obtain a browned core plate and a browned copper block; Using a PI film, laminating the browned core board and the browned copper block to obtain a circuit board substrate; Post-processing the circuit board substrate to obtain a double-sided circuit board with a single-sided copper-embedded asymmetric structure; The post-processing of the circuit board substrate to obtain a double-sided circuit board with a single-sided copper-embedded asymmetric structure includes: performing automatic optical inspection on the circuit board substrate; Wherein, the automatic optical detection comprises: Scanning the surface of the circuit board using a camera to obtain a circuit board surface scan image; Extracting circuit board surface design images from the background database; Extracting circuit board surface state features from the circuit board surface scan image and the circuit board surface design image respectively to obtain a circuit board surface state image semantic coding feature map and a circuit board surface state design image semantic coding feature map; Importance measurement-based feature selection is performed on the semantic coding feature map of the circuit board surface state image and the semantic coding feature map of the circuit board surface state design image to obtain a sparse circuit board surface state image semantic coding feature map and a sparse circuit board surface state design image semantic coding feature map, including: feature decomposition is performed on the circuit board surface state image semantic coding feature map to obtain a set of circuit board surface state image semantic coding local feature vectors; each circuit board surface state image semantic coding local feature vector in the set of circuit board surface state image semantic coding local feature vectors is input into an importance measurement module to obtain a set of circuit board surface state image semantic coding local feature importance score values; based on the set of circuit board surface state image semantic coding local feature importance score values, feature selection and feature shape reshaping are performed on the set of circuit board surface state image semantic coding local feature vectors to obtain the sparse circuit board surface state image semantic coding feature map; Calculating the positional difference between the sparse circuit board surface state image semantic coding feature map and the sparse circuit board surface state design image semantic coding feature map to obtain a circuit board surface real-design state difference coding feature map; The circuit board surface actual-design state difference encoding feature map is input into a classifier-based detection module to obtain a detection result, and the detection result is used to indicate whether the circuit board has a defect.

2. The method for preparing a double-sided circuit board with asymmetric structure and single-sided copper embedding according to claim 1, characterized in that: The method comprises: preparing a copper block, comprising: cutting a copper plate to obtain the copper block.

3. The method for preparing a double-sided circuit board with asymmetric structure and single-sided copper embedding according to claim 1, characterized in that: Using a PI film, laminating the browned core board and the browned copper block to obtain a circuit board substrate, comprising: A polyimide film is attached to the copper foil surface of the core board after the browning treatment; Placing the browned copper block on the polyimide film, wherein the browned copper block corresponds to the copper embedded area; placing a prepreg on the copper block after the browning treatment; Covering the prepreg with a layer of copper foil; placing a steel plate on the copper foil to obtain a laminated structure, wherein the steel plate serves as a support for the lamination process; The laminated structure is subjected to a lamination process to obtain the circuit board substrate.

4. The method for preparing a double-sided circuit board with asymmetric structure and single-sided copper embedding according to claim 3, characterized in that: The circuit board substrate is post-processed to obtain a double-sided circuit board with a single-sided copper-embedded asymmetric structure, and also includes: drilling, copper deposition, full-board electroplating, pattern transfer, copper-tin plating, film stripping etching, tin stripping, solder mask text printing, lead-free tin spraying, molding, surface cleaning, testing, appearance inspection and reliability testing of the circuit board substrate.

5. The method for preparing a double-sided circuit board with asymmetric structure and single-sided copper embedding according to claim 1, characterized in that: The circuit board surface state feature extraction is performed on the circuit board surface scan image and the circuit board surface design image respectively to obtain a circuit board surface state image semantic coding feature map and a circuit board surface state design image semantic coding feature map, including: inputting the circuit board surface scan image and the circuit board surface design image into a circuit board surface state feature extractor based on a dynamic convolutional labeling model to obtain the circuit board surface state image semantic coding feature map and the circuit board surface state design image semantic coding feature map.

6. The method for preparing a double-sided circuit board with asymmetric structure and single-sided copper embedding according to claim 5, characterized in that: The circuit board surface state image semantic coding feature map is feature decomposed to obtain a set of circuit board surface state image semantic coding local feature vectors, including: feature decoupling and feature flattening of the circuit board surface state image semantic coding feature map to obtain a set of circuit board surface state image semantic coding local feature vectors.

7. The method for preparing a double-sided circuit board with asymmetric structure and single-sided copper embedding according to claim 6, characterized in that: Based on the set of importance score values ​​of the semantically encoded local features of the circuit board surface state image, feature selection and feature shape reshaping are performed on the set of semantically encoded local feature vectors of the circuit board surface state image to obtain the sparse circuit board surface state image semantically encoded feature map, including: Based on the set of importance score values ​​of the semantically encoded local features of the circuit board surface state image, the set of semantically encoded local feature vectors of the circuit board surface state image is arranged in descending order to obtain a descending sequence of the semantically encoded local feature vectors of the circuit board surface state image; Based on the neighborhood features of each circuit board surface state image semantically encoded local feature vector in the descending sequence of the circuit board surface state image semantically encoded local feature vector, the feature neighborhood activity of each circuit board surface state image semantically encoded local feature vector is calculated to obtain a sequence of feature neighborhood activity; Based on the sequence of the feature neighborhood activity, feature selection is performed on the descending sequence of the semantically encoded local feature vectors of the circuit board surface state image to obtain a descending sequence of the semantically encoded local feature vectors of the circuit board surface state image after selection; The descending sequence of the selected circuit board surface state image semantic coding local feature vectors is reshaped to obtain the sparse circuit board surface state image semantic coding feature map.

8. A double-sided circuit board with a single-sided copper embedding and asymmetric structure, characterized in that: The single-sided copper-embedded asymmetric structure double-sided circuit board is manufactured by the method for manufacturing a single-sided copper-embedded asymmetric structure double-sided circuit board as described in any one of claims 1-7.

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