Methods for fabricating active regions of semiconductor devices

Abstract

This disclosure provides a method for fabricating a semiconductor device. The method includes: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming a plurality of islands on the second mask layers; forming an opening pattern defining layer on the islands to define a plurality of second openings; removing the islands to form a plurality of third openings; forming a shearing pattern by removing the second mask layers that overlap with the second and third openings along the third third direction, wherein the third third direction is orthogonal to the first and second directions; patterning the first mask layers by the shearing pattern; and patterning the substrate to define an active region. The opening pattern defining layer is formed using an atomic layer deposition process.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 2023115575462, filed on November 21, 2023, entitled “Method for fabricating an active region of a semiconductor element”. Application No. 2023115575462 claims priority and benefits of U.S. Patent Application No. 18 / 238,015, filed on August 25, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to a method for fabricating a semiconductor device. More particularly, it relates to a method for fabricating the active region of a semiconductor device. Background Technology

[0003] With the rapid development of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advancements in IC materials and design have resulted in many generations of ICs, each generation of circuits being smaller and more complex than the previous one.

[0004] Dynamic Random Access Memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Generally, DRAM is arranged in a square array with one capacitor and one transistor per cell. It is already 4F. 2 DRAM cells utilize vertical transistors, where F represents the minimum feature width or critical dimension (CD) of the lithography. However, recently, with the continuous shrinking of word line pitch, DRAM manufacturers have faced significant challenges in reducing the area of ​​memory cells.

[0005] The above description of "prior art" is merely to provide background information and does not constitute an admission that the above description of "prior art" reveals the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming a plurality of islands on the second mask layers; forming an opening pattern defining layer on the islands to define a plurality of first openings; removing the islands to form a plurality of second openings; forming a shearing pattern by removing the second mask layers that overlap with the first and second openings along a third direction perpendicular to the first and second directions; patterning the first mask layers using the shearing pattern; and patterning the substrate to define an active region.

[0007] Another aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming an aperture pattern defining layer on the second mask layers to define a plurality of apertures, which overlaps with the second mask layers along a third direction substantially perpendicular to the first and second directions; forming a first aperture modification layer to modify the size of the apertures; patterning the second mask layers by removing the second mask layers overlapping the apertures to form a shear pattern; patterning the first mask layers to form an active region defining pattern; and patterning the substrate to define an active region by the active region defining pattern.

[0008] Embodiments of this disclosure provide a method for fabricating a semiconductor device. In this embodiment, an aperture modification layer can be formed to reduce the size of the opening whose aperture is defined by a lithography process. Due to equipment limitations, the aperture defined by the lithography process cannot be reduced to a desired size; therefore, an aperture modification layer can be formed to reduce the size of the opening. In this way, the semiconductor device can have a smaller pitch active region, which is beneficial for forming more devices per unit area.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims when considered in conjunction with the drawings, wherein similar reference numerals represent similar elements in the overall drawings, and:

[0011] Figure 1A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0012] Figure 1B According to some embodiments of this disclosure, along Figure 1A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0013] Figure 1C According to some embodiments of this disclosure, along Figure 1A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0014] Figure 2A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0015] Figure 2B According to some embodiments of this disclosure, along Figure 2A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0016] Figure 2C According to some embodiments of this disclosure, along Figure 2A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0017] Figure 3A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0018] Figure 3B According to some embodiments of this disclosure, along Figure 3A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0019] Figure 3C According to some embodiments of this disclosure, along Figure 3A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0020] Figure 4A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0021] Figure 4B According to some embodiments of this disclosure, along Figure 4A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0022] Figure 4C According to some embodiments of this disclosure, along Figure 4A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0023] Figure 5A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0024] Figure 5B According to some embodiments of this disclosure, along Figure 5A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0025] Figure 5C According to some embodiments of this disclosure, along Figure 5A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0026] Figure 6A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0027] Figure 6B According to some embodiments of this disclosure, along Figure 6A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0028] Figure 6C According to some embodiments of this disclosure, along Figure 6A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0029] Figure 7A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0030] Figure 7B According to some embodiments of this disclosure, along Figure 7A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0031] Figure 7C According to some embodiments of this disclosure, along Figure 7A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0032] Figure 8A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0033] Figure 8B According to some embodiments of this disclosure, along Figure 8A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0034] Figure 8C According to some embodiments of this disclosure, along Figure 8A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0035] Figure 9A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0036] Figure 9B According to some embodiments of this disclosure, along Figure 9A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0037] Figure 9C According to some embodiments of this disclosure, along Figure 9A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0038] Figure 10A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0039] Figure 10B According to some embodiments of this disclosure, along Figure 10A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0040] Figure 10C According to some embodiments of this disclosure, along Figure 10A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0041] Figure 11A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0042] Figure 11B According to some embodiments of this disclosure, along Figure 11A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0043] Figure 11C According to some embodiments of this disclosure, along Figure 11A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0044] Figure 12A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0045] Figure 12B According to some embodiments of this disclosure, along Figure 12A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0046] Figure 12C According to some embodiments of this disclosure, along Figure 12A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0047] Figure 13A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0048] Figure 13B According to some embodiments of this disclosure, along Figure 13A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0049] Figure 13C According to some embodiments of this disclosure, along Figure 13A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0050] Figure 14A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0051] Figure 14B According to some embodiments of this disclosure, along Figure 14A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0052] Figure 14C According to some embodiments of this disclosure, along Figure 14A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0053] Figure 15A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0054] Figure 15B According to some embodiments of this disclosure, along Figure 15A The cross-sectional view of the semiconductor device shown is drawn along line A-A'.

[0055] Figure 15C According to some embodiments of this disclosure, along Figure 15A The cross-sectional view of the semiconductor device shown is drawn along line B-B'.

[0056] Figure 16A According to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0057] Figure 16B According to some embodiments of this disclosure, along Figure 16A The cross-sectional view of the semiconductor device shown is drawn along line C-C'.

[0058] Figure 17AAccording to some embodiments of this disclosure, one or more stages of an example method for preparing a semiconductor element are shown.

[0059] Figure 17B According to some embodiments of this disclosure, along Figure 17A The cross-sectional view of the semiconductor device shown is drawn along line C-C'.

[0060] Figure 18A and Figure 18B A flowchart of a method for fabricating a semiconductor device is shown according to some embodiments of this disclosure.

[0061] The reference numerals in the attached figures are explained as follows:

[0062] 100: Semiconductor components

[0063] 102: Substrate

[0064] 102a: Active Region

[0065] 102r: Groove

[0066] 106: Mask layer

[0067] 106a: Active Region Definition Pattern

[0068] 108: Bottom Layer

[0069] 112: Dielectric layer

[0070] 112a: Mask layer

[0071] 112b: Cutout Pattern

[0072] 114: Dielectric layer

[0073] 116: Dielectric layer

[0074] 118: Photosensitive layer

[0075] 120: Pitch Definition Layer

[0076] 122: Bottom Layer

[0077] 124: Dielectric layer

[0078] 126: Dielectric layer

[0079] 128: Dielectric layer

[0080] 130: Photosensitive layer

[0081] 132: Island

[0082] 134: Opening Pattern Definition Layer

[0083] 140: Aperture Modification Layer

[0084] 150: Aperture Modification Layer

[0085] 200: Method

[0086] 202: Operation

[0087] 204: Operation

[0088] 206: Operation

[0089] 208: Operation

[0090] 210: Operation

[0091] 212: Operation

[0092] 214: Operation

[0093] 216: Operation

[0094] 218: Operation

[0095] 220: Operation

[0096] 222: Operation

[0097] 224: Operation

[0098] A-A': line

[0099] B-B': Line

[0100] C-C': Line

[0101] G1: Gap

[0102] G2: Gap

[0103] G3: Gap

[0104] G4: Gap

[0105] O1: Opening

[0106] O2: Opening

[0107] O1': Opening

[0108] O2': Open

[0109] O3: Opening

[0110] O4: Opening

[0111] P1: Pitch

[0112] P2: Pitch

[0113] P3: Pitch Detailed Implementation

[0114] The embodiments or examples of this disclosure shown in the drawings are described below using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the embodiments, and any further application of the principles set forth herein, are to be regarded as normal occurrences by those skilled in the art related to this disclosure. Reference numerals may be repeated in all embodiments, but this does not necessarily mean that a component of one embodiment is applicable to another embodiment, even if they use the same reference numerals.

[0115] It should be understood that when a component is referred to as "connected to" or "coupled to" another component, the initial component may be directly connected to or coupled to another component or other intermediate component.

[0116] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or parts, these elements, components, regions, layers, or parts are not limited to these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the conceptual teachings of this disclosure, the first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part.

[0117] The terms used herein are for the purpose of describing particular example embodiments only and are not intended to limit the concepts of this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” also include the plural forms. It should be further understood that the terms “comprises” and “comprising” as used in this specification indicate the presence of said components, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more components, integers, steps, operations, elements, components, or combinations thereof.

[0118] It should be noted that the term "approximately" used in this disclosure to modify the amount of ingredients, components, or reactants refers to quantitative variations that may occur, for example, through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to negligence or errors in measurement procedures, or differences in the manufacture, source, or purity of the ingredients used in the production of the composition or the implementation of the method. On one hand, the term "approximately" means within 10% of the reported value. On the other hand, the term "approximately" means within 5% of the reported value. Also, on another hand, the term "approximately" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0119] Figures 1A to 17AVarious stages of an example method for fabricating a semiconductor device are shown according to some embodiments of this disclosure; Figures 1B to 15B Show along Figures 1A to 15A A cross-sectional view of the semiconductor device shown, drawn along line A-A'. Figures 1C to 15C Show along Figures 1A to 15A A cross-sectional view of the semiconductor device shown, drawn along line B-B'. Figure 16B and Figure 17B Show along Figure 16A and Figure 17A The diagram shows a cross-sectional view of the semiconductor element drawn along line C-C'. It should be noted that some elements have been omitted for simplicity.

[0120] Reference Figure 1A , Figure 1B ,and Figure 1C A substrate 102 may be provided. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate 102 may include elemental semiconductors, including single-crystal, polycrystalline, or amorphous forms of silicon or germanium; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP; any other suitable materials; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a SiGe alloy having a gradient Ge feature, wherein the Si and Ge composition changes from one ratio at one location of the gradient SiGe feature to another ratio at another location of the gradient SiGe feature. In another embodiment, the SiGe alloy is formed on a silicon substrate. In some embodiments, another material in contact with the SiGe alloy may cause the SiGe alloy to be mechanically strained. In some embodiments, substrate 102 may have a multilayer structure, or substrate 102 may include a multilayer compound semiconductor structure.

[0121] Multiple mask layers 106 can be formed on the substrate 102. Each mask layer 106 can extend along a direction not parallel to the X and Y directions. The mask layer 106 can be configured to define an active region of the substrate 102. A portion of the substrate 102 can be exposed by the mask layer 106. The mask layer 106 may include silicon oxycarbide, silicon carbide, silicon oxide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The fabrication techniques for the mask layer 106 may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or other suitable processes.

[0122] Reference Figure 2A , Figure 2B ,and Figure 2C A substrate 108 can be formed on top of the mask layer 106. The substrate 108 can fill the openings defined by the mask layer 106. The substrate 108 may include a dielectric material, such as a polymer or other suitable material. For example, the fabrication technique of the substrate 108 may include spin coating or other suitable processes.

[0123] A dielectric layer 112 may be formed on the substrate 108. The dielectric layer 112 may be configured to form a mask, thereby defining an active region definition pattern, which will be described later. The dielectric layer 112 may include silicon oxide, silicon carbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The fabrication techniques for the dielectric layer 112 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0124] A dielectric layer 114 can be formed on the dielectric layer 112. The dielectric layer 114 can be configured to serve as a mask to define the pattern of the dielectric layer 112. In some embodiments, the dielectric layer 114 may include a carbon-containing material, such as amorphous carbon or other suitable materials. The fabrication techniques for the dielectric layer 114 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0125] A dielectric layer 116 can be formed on the dielectric layer 114. The dielectric layer 116 can be used as a dielectric anti-reflection coating (DARC). The dielectric layer 116 may include silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, or suitable materials. The fabrication techniques for the dielectric layer 116 may include CVD, ALD, PVD, LPCVD, PECVD, spin coating, or other suitable processes.

[0126] A photosensitive layer 118 (or a photoresist pattern) can be formed on the dielectric layer 116. The photosensitive layer 118 can extend along the Y direction. The photosensitive layer 118 may include photoresist or other suitable materials.

[0127] Reference Figure 3A , Figure 3B ,and Figure 3C A pitch definition layer 120 can be formed on the dielectric layer 116 and the side surface (not noted) of the photosensitive layer 118. Each segment of the pitch definition layer 120 can extend along the Y direction. The pitch definition layer 120 can include silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, or suitable materials. The fabrication techniques for the pitch definition layer 120 can include CVD, ALD, PVD, LPCVD, PECVD, spin coating, or other suitable processes.

[0128] A portion of the dielectric layer 116 may be exposed by the photosensitive layer 118 and the pitch definition layer 120. This portion of the dielectric layer 116 may not perpendicularly overlap with the photosensitive layer 118 and the pitch definition layer 120 along the Z-direction. In some embodiments, the photosensitive layer 118 may be removed after the pitch definition layer 120 has been formed.

[0129] Reference Figure 4A , Figure 4B ,and Figure 4C The dielectric layer 112 can be patterned to form a mask layer 112a. Portions of the dielectric layer 112 that do not overlap with the pitch definition layer 120 can be removed. Next, the dielectric layers 114, 116, and 120 can be removed. In some embodiments, the fabrication technique for the mask layer 112a may include a self-aligning double patterning (SADP) process.

[0130] In some embodiments, the extension direction of mask layer 112a and the extension direction of mask layer 106 can be defined by an angle θ in a top view. In some embodiments, the angle θ can range from about 20° to about 35°, such as 20°, 22°, 24°, 26°, 28°, 30°, 33°, or 35°.

[0131] In some embodiments, the width of the mask layer 112a may be defined by the pitch definition layer 120. In some embodiments, the pitch P1 of the mask layer 112a may be defined by the pitch definition layer 120. In some embodiments, the width of the pitch definition layer 120 may be controlled to determine the thickness of the mask layer 112a.

[0132] Reference Figure 5A , Figure 5B ,and Figure 5C A substrate 122 can be formed on top of the substrate 108. The substrate 122 can fill the openings defined by the mask layer 112a. The substrate 122 can include a dielectric material, such as a polymer or other suitable material. For example, the fabrication technique of the substrate 122 can include spin coating or other suitable processes.

[0133] A dielectric layer 124 can be formed on the substrate 122. The dielectric layer 124 may include silicon oxide, silicon oxycarbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The fabrication technology of the dielectric layer 124 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0134] A dielectric layer 126 can be formed on the dielectric layer 124. The dielectric layer 126 can be configured to serve as a mask to define the pattern of the dielectric layer 124. In some embodiments, the dielectric layer 126 may include a carbon-containing material, such as amorphous carbon. The fabrication techniques for the dielectric layer 126 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0135] A dielectric layer 128 can be formed on the dielectric layer 126. The dielectric layer 128 can be used as a dielectric antireflective coating (DARC). The dielectric layer 128 may include silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, or suitable materials. The fabrication techniques for the dielectric layer 128 may include CVD, ALD, PVD, LPCVD, PECVD, spin coating, or other suitable processes.

[0136] Reference Figure 6A , Figure 6B ,and Figure 6C A photosensitive layer 130 (or photoresist pattern) can be formed on the dielectric layer 128. The photosensitive layer 130 can define a plurality of openings O1. The openings O1 can expose a portion of the dielectric layer 128. The photosensitive layer 130 may include photoresist or other suitable materials. The openings O1 may include a circular outline, an elliptical outline, or other suitable outline. In some embodiments, the pitch of the openings O1 may be twice the pitch of the mask layer 112a along the X direction.

[0137] Reference Figure 7A , Figure 7B ,and Figure 7C Multiple islands 132 can be formed within the openings O1 of the photosensitive layer 130. In some embodiments, the islands 132 may include silicon oxide, silicon carbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The fabrication techniques for the islands 132 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes.

[0138] In some embodiments, a dielectric material may be deposited to cover the photosensitive layer 130, and then a polishing process (e.g., chemical mechanical polishing (CMP)) may be performed to remove the upper portion of the dielectric material until the photosensitive layer 130 is exposed, after which the photosensitive layer 130 may be removed. In some embodiments, the island 132 may include a circular profile, an elliptical profile, or other suitable profile. In some embodiments, the pitch of the island 132 may be twice the pitch of the mask layer 112a.

[0139] Reference Figure 8A , Figure 8B ,and Figure 8C An opening pattern definition layer 134 can be formed. In some embodiments, the opening pattern definition layer 134 can be formed on the side surface (not noted) of the island 132. In some embodiments, the opening pattern definition layer 134 may include silicon nitride, silicon oxycarbide, silicon carbide, silicon oxide, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The fabrication techniques for the opening pattern definition layer 134 may include ALD, CVD, PVD, LPCVD, PECVD, or other suitable processes.

[0140] The opening pattern definition layer 134 can define multiple openings O2. In some embodiments, the outline of opening O2 may differ from the outline of opening O1. Although Figure 8A The opening O2 is shown to have an irregular or rhomboid profile. The opening O2 may have other profiles, such as a circular or elliptical profile, configured according to the deposition rate, temperature, or other process conditions to form the opening pattern definition layer 134. In some embodiments, the opening pattern definition layer 134 may include two or more materials formed in different stages to modify or control the profile of the opening pattern definition layer 134.

[0141] Reference Figure 9A , Figure 9B ,and Figure 9CIsland 132 can be removed. Opening O1 can be defined by opening pattern definition layer 134. In some embodiments, openings O1 and O2 can be configured alternately. One of the openings O1 can be surrounded or adjacent to four openings O2. In some embodiments, the size (e.g., area or aperture) of opening O1 can be substantially the same as the size of opening O2.

[0142] In some embodiments, the pitch P2 of opening O1 can be substantially the same as the pitch P3 of opening O2 along the X direction. In some embodiments, the pitch P2 of opening O1 can be twice the pitch P1 of mask layer 112a along the X direction, such as... Figure 4A As shown. In some embodiments, the pitch P3 of the opening O2 can be twice the pitch P1 of the mask layer 112a along the X direction, such as... Figure 4A As shown.

[0143] Reference Figure 10A , Figure 10B ,and Figure 10C An aperture modification layer 140 can be formed. In some embodiments, the aperture modification layer 140 can be formed on the side surface of the opening pattern definition layer 134. In some embodiments, the aperture modification layer 140 can be configured to define and control or modify the dimensions of openings O1 and O2, thereby defining openings O1' and O2' corresponding to openings O1 and O2. In some embodiments, the size (e.g., area or aperture) of opening O1' can be smaller than the size of opening O1. In some embodiments, the size (e.g., area or aperture) of opening O2' can be smaller than the size of opening O2. The contour of opening O2' can be modified or controlled by the aperture modification layer 140.

[0144] In some embodiments, the pore size modification layer 140 may include silicon oxide, silicon carbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The fabrication techniques for the pore size modification layer 140 may include CVD, ALD, PVD, LPCVD, PECVD, or other suitable processes. The formation of the pore size modification layer 140 may be optional. In other embodiments, the formation of the pore size modification layer 140 may be omitted.

[0145] Reference Figure 11A , Figure 11B ,and Figure 11CAn etching process, such as dry etching or reactive ion etching (RIE), can be performed. The aperture pattern definition layer 134 and the aperture modification layer 140 can jointly serve as a hard mask, and portions of the mask layer 112a, the bottom layer 122, the dielectric layer 124, the dielectric layer 126, and the dielectric layer 128 can be partially etched. In some embodiments, the mask layer 112a exposed by the opening O1' (or opening O1) can be removed. In some embodiments, the mask layer 112a exposed by the opening O2' (or opening O2) can be removed. As a result, a shear pattern 112b can be defined.

[0146] Reference Figure 12A , Figure 12B ,and Figure 12C The bottom layer 122, dielectric layer 124, dielectric layer 126, dielectric layer 128, aperture pattern definition layer 134, and aperture modification layer 140 can be removed to expose the shear pattern 112b. For example... Figure 12A As shown, each segment of the shear pattern 112b can extend along the Y direction. From a top view, the side surface of the shear pattern 112b can have a concave profile. The shear pattern 112b can define gaps G1 and G2 corresponding to the positions of openings O1 and O2, respectively. In some embodiments, each segment of the shear pattern 112b can vertically overlap with two mask layers 106. In some embodiments, the length of one of the gaps G1 and G2 along the Y direction can be greater than the length of one of the mask layers 106 along the Y direction. In some embodiments, the dimensions of the gaps G1 and G2 can be determined by the aperture modification layer 140.

[0147] Reference Figure 13A , Figure 13B ,and Figure 13C An aperture modification layer 150 can be formed to define openings O3 and O4. In some embodiments, the aperture modification layer 150 can be formed on the side surface of the shear pattern 112b. In some embodiments, the aperture modification layer 150 may include silicon oxide, silicon carbide, silicon carbide, silicon nitride, silicon carbonitride, silicon oxynitride, aluminum oxide, aluminum oxynitride, or other suitable materials. The fabrication techniques for the aperture modification layer 150 may include ALD, CVD, PVD, LPCVD, PECVD, or other suitable processes.

[0148] In some embodiments, the aperture modification layer 150 can be configured to define, modify, and / or control the dimensions of openings O3 and O4 to more precisely define the active region of substrate 102. The positions of openings O3 and O4 can correspond to the positions of openings O1 and O2, respectively. In some embodiments, opening O3 can have a circular outline, an elliptical outline, or other suitable outline. In some embodiments, opening O4 can have a circular outline, an elliptical outline, or other suitable outline. In some embodiments, the size (e.g., area or aperture) of opening O3 can be smaller than the size of opening O1. In some embodiments, the size (e.g., area or aperture) of opening O4 can be smaller than the size of opening O2. In some embodiments, the aperture modification layer 150 can include two or more materials formed through different stages or process conditions.

[0149] Reference Figure 14A , Figure 14B ,and Figure 14C An etching process, such as dry etching or RIE, can be performed to etch a portion of the mask layer 106, the base layer 108, and the aperture modification layer 150. The mask layer 106 can be patterned. In some embodiments, the cut pattern 112b and the aperture modification layer 150 can be used as hard masks to define the pattern of the etched mask layer 106. The mask layer 106 exposed by the cut pattern 112b and the aperture modification layer 150 can be removed.

[0150] Reference Figure 15A , Figure 15B ,and Figure 15C The bottom layer 108 can be removed. The shear pattern 112b can be removed. The aperture modification layer 150 can be removed. The active region definition pattern 106a can be defined. The active region definition pattern 106a can be configured to define the pattern of the active region of the substrate 102.

[0151] Each segment of the active region definition pattern 106a may extend along a direction not parallel to the X and Y directions. In some embodiments, the active region definition pattern 106a may define gaps G3 and G4. The positions of gaps G3 and G4 may correspond to the positions of gaps G1 and G2, respectively. In some embodiments, the size (e.g., length or width) of gap G3 may be smaller than the size of gap G1. In some embodiments, the size (e.g., length or width) of gap G4 may be smaller than the size of gap G2.

[0152] Reference Figure 16A and Figure 16BThe substrate 102 can be patterned to define an active region 102a. The substrate 102 exposed by the active region defining pattern 106a can be etched to form a recess 102r from the upper surface of the substrate 102. In some embodiments, each segment of the active region 102a may have a circular profile, an elliptical profile, or other suitable profile. In some embodiments, each segment of the active region 102a may have a long axis substantially parallel to the mask layer 106, such as... Figure 1A As shown.

[0153] Reference Figure 17A and Figure 17B The active region definition pattern 106a can be removed. The active region 102a of the substrate 102 can be exposed. As a result, a semiconductor device 100 can be generated.

[0154] In some embodiments, semiconductor element 100 may be configured to form a memory element. The memory element may include, for example, a dynamic random access memory (DRAM) element, a one-time programming (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. In some embodiments, DRAM may include, for example, transistors, capacitors, and other components. During a read operation, a word line (WL) may be asserted, thereby turning on a transistor. The turned-on transistor allows a sense amplifier to read the voltage across a capacitor via a bit line (BL). During a write operation, data to be written can be provided on the BL when the WL is asserted.

[0155] For example, the recess 102r can be filled with an insulating material to separate each segment of the active region 102a. Word lines, capacitors, and / or other components can be formed on the active region 102a to create a memory element.

[0156] It should be noted that due to the topography of the structure, the etching rate is not uniform, so the outline of the etched object may not follow the outline of the mask layer.

[0157] Figure 18A and Figure 18B A flowchart of a method 200 for preparing a semiconductor device is shown according to some embodiments of this disclosure.

[0158] Reference Figure 18A Method 200 may begin with operation 202, providing a substrate. A plurality of first mask layers are formed on the substrate.

[0159] Method 200 can continue to operation 204, forming a first dielectric layer on the first mask layers. A photoresist pattern is formed on the first dielectric layer.

[0160] Method 200 can continue to operation 206, forming a pitch definition layer on the side surface of the photoresist pattern.

[0161] Method 200 can proceed to operation 208, patterning the first dielectric layer to form a plurality of second mask layers. The first and second mask layers can define an angle ranging from about 20° to about 35°.

[0162] Method 200 may continue to operation 210, forming a second dielectric layer on the second mask layers. A photosensitive layer is formed on the second dielectric layer. The photosensitive layer defines a plurality of first openings overlapping the second mask layers.

[0163] Method 200 can proceed to operation 212, where multiple islands can be formed within the first openings. The photosensitive layer can then be removed.

[0164] Reference Figure 18B Method 200 can proceed to operation 214, which can form an opening pattern definition layer to define a plurality of second openings. The outlines of the second openings may differ from the outlines of the first openings. The second openings and the first openings may be configured alternately.

[0165] Method 200 can proceed to operation 216, where a first aperture modification layer can be formed to reduce the size of the first openings and the second openings. The contours of the first openings and the second openings can be modified. The formation of the first aperture modification layer can be selective.

[0166] Method 200 can proceed to operation 218, which can pattern the second mask layers to form a shear pattern. The shear pattern defines a plurality of gaps that overlap perpendicularly with the first mask layers.

[0167] Method 200 can proceed to operation 220, which can form a second aperture modification layer to form a plurality of third openings and a plurality of fourth openings. The positions of the third openings can correspond to the first openings. The positions of the fourth openings can correspond to the second openings. The size of the third openings can be smaller than the size of the first opening. The size of the fourth openings can be smaller than the size of the second opening.

[0168] Method 200 can proceed to operation 222, whereby the first mask layers can be patterned to form an active region definition pattern.

[0169] Method 200 can proceed to operation 224, where the substrate can be patterned to define an active region. As a result, a semiconductor device can be produced.

[0170] Method 200 is merely an example and is not intended to limit this disclosure beyond what is expressly recited in the claims. Additional operations may be provided before, during, or after each operation of method 200, and some of these operations may be replaced, removed, or reordered for additional embodiments of the method. In some embodiments, method 200 may include... Figure 18A and Figure 18B Further operations not depicted herein. In some embodiments, method 200 may include... Figure 18A and Figure 18B One or more operations described in the document.

[0171] One aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming a plurality of islands on the second mask layers; forming an opening pattern defining layer on the islands to define a plurality of first openings; removing the islands to form a plurality of second openings; forming a shearing pattern by removing the second mask layers that overlap with the first and second openings along a third direction perpendicular to the first and second directions; patterning the first mask layers using the shearing pattern; and patterning the substrate to define an active region.

[0172] Another aspect of this disclosure provides a method for fabricating a semiconductor device. The method includes: providing a substrate; forming a plurality of first mask layers on the substrate, wherein each of the first mask layers extends along a first direction; forming a plurality of second mask layers on the substrate, wherein each of the second mask layers extends along a second direction different from the first direction; forming an aperture pattern defining layer on the second mask layers to define a plurality of apertures, which overlaps with the second mask layers along a third direction substantially perpendicular to the first and second directions; forming a first aperture modification layer to modify the size of the apertures; patterning the second mask layers by removing the second mask layers overlapping the apertures to form a shear pattern; patterning the first mask layers to form an active region defining pattern; and patterning the substrate to define an active region by the active region defining pattern.

[0173] Embodiments of this disclosure provide a method for fabricating a semiconductor device. In this embodiment, an aperture modification layer can be formed to reduce the size of the opening whose aperture is defined by a lithography process. Due to equipment limitations, the aperture defined by the lithography process cannot be reduced to a desired size; therefore, an aperture modification layer can be formed to reduce the size of the opening. In this way, the semiconductor device can have a smaller pitch active region, which is beneficial for forming more devices per unit area.

[0174] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0175] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A method for fabricating a semiconductor device, comprising: Provide a substrate; A plurality of first mask layers are formed on the substrate, wherein each of the plurality of first mask layers extends along a first direction; A plurality of second mask layers are formed on the plurality of first mask layers, wherein each of the plurality of second mask layers extends along a second direction different from the first direction; Multiple islands are formed on the multiple second mask layers; An opening pattern is formed to define the gaps between the multiple islands to define multiple first openings; Remove these multiple islands to create multiple second openings; A shearing pattern is formed by removing the plurality of second mask layers that overlap with the plurality of first openings and the plurality of second openings along a third direction, wherein the third direction is orthogonal to the first direction and the second direction; The multiple first mask layers are patterned using this cutout pattern; Remove the first mask layer to form multiple third openings; as well as The substrate is patterned using the multiple third openings to define an active region. The opening pattern definition layer is formed using an atomic layer deposition process.

2. The method for fabricating a semiconductor element as claimed in claim 1, wherein an angle defined by the first direction and the second direction ranges from 20° to 35°.

3. The method for fabricating a semiconductor device as described in claim 1, further comprising: A first aperture modification layer is formed in the gap between the opening pattern definition layer to define the plurality of third openings, which overlap with the plurality of first mask layers along the third direction.

4. The method for fabricating a semiconductor device as claimed in claim 3, wherein patterning the plurality of first mask layers includes removing the plurality of first mask layers that overlap with the plurality of third openings along the third direction.

5. The method for fabricating a semiconductor device as described in claim 3, wherein the fabrication technique for the first aperture modification layer includes an atomic layer deposition process.

6. The method for fabricating a semiconductor element as claimed in claim 3, wherein the first aperture modification layer comprises an oxide, a nitride, an oxynitride, or a combination thereof.

7. The method for preparing a semiconductor device as described in claim 1, further comprising: A second aperture modification layer is formed in the gap between the plurality of islands to modify the size of the plurality of first openings and the plurality of second openings.

8. The method for fabricating a semiconductor element as claimed in claim 1, wherein the plurality of second openings are alternately arranged with the plurality of first openings.

9. The method for fabricating a semiconductor element as claimed in claim 1, wherein the pitch of the plurality of second openings is substantially equal to the pitch of the plurality of first openings.

10. The method for fabricating a semiconductor device as claimed in claim 1, wherein forming the plurality of second mask layers comprises: A dielectric layer is formed on the plurality of first mask layers; A photoresist pattern is formed on the dielectric layer; A pitch definition layer is formed on the photoresist pattern; as well as The dielectric layer is patterned by removing the dielectric layer that does not overlap with the photoresist pattern and the pitch definition layer along the third direction.

11. The method for fabricating a semiconductor device as claimed in claim 10, wherein a pitch of the plurality of second mask layers is defined by the pitch defining layer.

12. A method for fabricating a semiconductor device, comprising: Provide a substrate; A plurality of first mask layers are formed on the substrate, wherein each of the plurality of first mask layers extends along a first direction; A plurality of second mask layers are formed on the plurality of first mask layers, wherein each of the plurality of second mask layers extends along a second direction different from the first direction; An opening pattern definition layer is formed on the plurality of second mask layers to define a plurality of first openings, which overlaps with the plurality of second mask layers along a third direction, the third direction being substantially perpendicular to the first direction and the second direction; The plurality of second mask layers are patterned by removing the plurality of second mask layers that overlap with the plurality of first openings to form a cut pattern; The plurality of first mask layers are patterned using the cutting pattern, and the plurality of first mask layers are removed to form an active region definition pattern; as well as The substrate is patterned using the active region definition pattern to define an active region.

13. The method for fabricating a semiconductor device as described in claim 12, further comprising: A first aperture modification layer is formed to modify the size of the plurality of first openings.

14. The method for fabricating a semiconductor device as claimed in claim 13, wherein the first aperture modification layer comprises an oxide, a nitride, an oxynitride, or a combination thereof.

15. The method of fabricating a semiconductor element as claimed in claim 12, wherein an angle defined by the first direction and the second direction ranges from 20° to 35°.

16. The method for fabricating a semiconductor device as described in claim 12, further comprising: A second aperture modification layer is formed in the gap between the shearing patterns to define a plurality of second openings, which overlap with the plurality of first mask layers along the third direction.

17. The method of fabricating a semiconductor device as claimed in claim 16, wherein patterning the plurality of first mask layers includes removing the first mask layers that overlap with the plurality of second openings along the third direction.

18. The method for fabricating a semiconductor device as claimed in claim 16, wherein the fabrication technique for the second aperture modification layer includes an atomic layer deposition process.

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