Memory device and forming method thereof

Abstract

The embodiment of the invention discloses a memory device and a forming method thereof. A memory device includes a memory array including a plurality of memory cells arranged on a plurality of rows, the rows respectively including a plurality of word lines, a first set of memory cells coupled to even digital lines, and a second set of memory cells coupled to odd digital lines. An even number line is disposed in a first layer of a plurality of metallization layers formed vertically over a substrate, where the even number line extends along a first lateral direction and includes a first stitched portion extending along a second lateral direction perpendicular to the first lateral direction. The odd number line is disposed in a second layer of the plurality of metallization layers, where the odd number line extends along the first lateral direction and includes a second stitched portion extending in a second lateral direction.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. As integrated circuits continue to shrink, more and more devices are integrated into a single chip. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a plurality of first memory cells, each of the plurality of first memory cells comprising a corresponding first transistor and a corresponding first storage element, the first transistor being formed along a main surface of a substrate and arranged along a first lateral direction, the first storage element being formed in a first metallization layer among a plurality of metallization layers vertically arranged above the main surface; a plurality of second memory cells, each of the plurality of second memory cells comprising a corresponding second transistor and a corresponding second storage element, the second transistor being formed along a main surface of the substrate and arranged along a first lateral direction, the second storage element being formed in a second metallization layer among the plurality of metallization layers, wherein the second transistor of the second memory cell is arranged along a direction perpendicular to the first lateral direction relative to the first transistor of the first memory cell. a first metal track, operably configured as a first word line of a plurality of first memory cells and extending along the first lateral direction, disposed in a third metallization layer among the plurality of metallization layers, and including a first stitching portion extending away from the first metal track in the second lateral direction, wherein the first stitching portion is configured to connect the first word line to a corresponding gate structure of a first transistor of the first memory cell; and a second metal track, operably configured as a second word line of a plurality of second memory cells and extending along the first lateral direction, disposed in a fourth metallization layer among the plurality of metallization layers, and including a second stitching portion extending away from the second metal track in the second lateral direction, wherein the second stitching portion is configured to connect the second word line to a corresponding gate structure of a second transistor of the second memory cell.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a memory array comprising a plurality of memory cells arranged on a plurality of rows, the rows comprising a plurality of word lines, a first group of memory cells coupled to even word lines in the word lines, and a second group of memory cells coupled to odd word lines in the word lines; wherein the even word lines are arranged in a first metallization layer among a plurality of metallization layers vertically formed above a substrate, wherein the even word lines extend along a first lateral direction, and wherein the even word lines include a first longitudinal portion extending in the first lateral direction and a first stitching portion extending in a second lateral direction perpendicular to the first lateral direction to allow connection to a gate structure of a first transistor of the first group of memory cells; and wherein the odd word lines are arranged in a second metallization layer among a plurality of metallization layers, wherein the odd word lines extend along the first lateral direction, and wherein the odd word lines include a second longitudinal portion extending in the first lateral direction and a second stitching portion extending in the second lateral direction to allow connection to a gate structure of a second transistor of the second group of memory cells.

[0005] According to another aspect of an embodiment of the present application, a method for forming a memory device is provided, comprising: forming a first group of transistors and a second group of transistors along a main surface of a substrate, wherein the first group of transistors are aligned along a first lateral direction, and the second group of transistors are aligned along the first lateral direction, and the first group of transistors and the second group of transistors are arranged relative to each other along a second lateral direction perpendicular to the first lateral direction; forming a first metal track in a first metallization layer among a plurality of metallization layers vertically arranged above the main surface, wherein the first metal track includes a first longitudinal portion extending along the first lateral direction and a first stitching portion extending along the second lateral direction, and the first stitching portion is coupled to a gate structure of the first group of transistors; forming a second metal track in a second metal layer among the plurality of metallization layers, wherein the second metal track includes a second longitudinal portion extending along the first lateral direction and a second stitching portion extending along the second lateral direction, and the second stitching portion is coupled to a gate structure of the second group of transistors; forming a first group of storage elements in a third metallization layer among the plurality of metallization layers, wherein the first group of storage elements are respectively coupled to the first group of transistors; and forming a second group of storage elements in the third metallization layer, wherein the second group of storage elements are respectively coupled to the second group of transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1An example block diagram of a memory device including a memory array having a plurality of memory cells is shown in accordance with some embodiments.

[0008] Figure 2 According to some embodiments Figure 1 An example schematic diagram of a memory cell.

[0009] Figure 3 According to some embodiments Figure 1 An example schematic diagram of a portion of a memory array of FIG.

[0010] Figure 4 shows a device configured to form a Figure 1 An example layout of a portion of a memory array.

[0011] Figure 5 shows a device configured to form a Figure 1 Another example layout of a portion of a memory array of FIG.

[0012] Figure 6 According to some embodiments Figure 1 A first example schematic diagram of a portion of a memory array.

[0013] Figure 7 shows a device configured to form a Figure 6 An example layout of multiple metal tracks is shown.

[0014] Figure 8 According to some embodiments, at least Figure 7 A cross-sectional view of a semiconductor structure formed by a layout.

[0015] Fig. 9 According to some embodiments Figure 1 A second example schematic diagram of a portion of a memory array.

[0016] Fig.10 shows a device configured to form a Fig. 9 An example layout of multiple metal tracks is shown.

[0017] Fig.11 According to some embodiments, at least Fig.10 A cross-sectional view of a semiconductor structure formed by a layout.

[0018] Fig.12 According to some embodiments, at least Figure 4 A cross-sectional view of a semiconductor structure formed by a layout.

[0019] Fig.13According to some embodiments, at least Figure 4 A cross-sectional view of a semiconductor structure formed by a layout.

[0020] Fig.14 An example flow chart of a method for manufacturing a memory device according to some embodiments is shown. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0023] Highly integrated semiconductor circuits often include onboard data storage. Such data storage can take the form of volatile or non-volatile memory cells, for example, where one or more arrays of capacitive or resistive memory cells are provided. In an example of a capacitive memory cell, a one-transistor-capacitor (1T1C) memory cell is used, each memory cell having an access transistor and a capacitor; in an example of a resistive memory cell, a one-transistor-resistor (1T1R) memory cell is used, each memory cell having an access transistor and a resistor. In a 1T1C or 1T1R embodiment, the access transistor has a first source / drain terminal connected to one of the terminals of the capacitor or resistor, and a second source / drain terminal connected to a source or select line (SL). The data stored in such a memory cell is usually stored in a capacitor or resistor (sometimes referred to as a storage element). Data is usually accessed by outputting the data to a sense amplifier via a bit line (BL) connected to the other terminal of the capacitor or resistor. When the access transistor is activated, the data is usually output via a word line (WL) connected to the gate or control terminal of the access transistor.

[0024] Such access lines (WL, SL, BL, etc.) are typically formed as metal tracks that span one or more metallization layers disposed on the main (e.g., front side) surface of the substrate. In addition, in order to realize a large array of memory cells of a memory device, each storage element of the memory cell is formed in one of the metallization layers or between adjacent metallization layers. As the technology nodes become increasingly advanced, the size and pitch of these metal tracks are correspondingly reduced, which causes the access lines to present an increasing resistance. In this regard, some access lines (e.g., WL) are pushed to a metallization layer higher than the location where the storage elements are formed. Therefore, some storage elements can be requisitioned or repurposed as through-hole structures to electrically couple the WL to the gate terminal below the access transistor. Compared with other through-hole structures formed of pure metal materials, these repurposed storage elements typically have higher resistance and / or higher defect rates. Therefore, some memory cells may not work as originally designed. Therefore, existing memory devices are not completely satisfactory in some aspects.

[0025] The present disclosure provides various embodiments of a memory device, which includes a memory array having a plurality of memory cells, each of which may include at least one switch (e.g., implemented as a transistor) and a storage element (e.g., implemented as a capacitor or a resistor). In some embodiments, the memory cell may be a non-volatile memory cell. However, it should be understood that in some other embodiments, the memory cell may be a volatile memory cell while still within the scope of the present disclosure. Unlike existing memory devices, the SL of the currently disclosed memory device is formed in the bottommost metallization layer. This "repositioning" of the SL allows the formation of WLs on two adjacent metallization layers, each of which is vertically located below the location where the storage element is formed. Specifically, the even-numbered WLs are formed in the first metallization layer, and the odd-numbered WLs are formed as the second metallization layer, wherein any one of the first metallization layer or the second metallization layer is vertically lower than the storage element. Therefore, each WL can be electrically coupled to the transistor below without using a respective storage element that can be implemented as a metal-insulator-metal (MIM) structure. In addition, in order to achieve electrical connection between the WL and the transistor, each WL may include one or more stitching portions. The term "stitching portion" as used herein refers to a portion of a structure that protrudes from a longitudinal portion of the structure and extends in a direction perpendicular to the longitudinal portion. Such a stitching portion may sometimes be referred to as an extension or protruding portion. For example, the stitching portion of the even-numbered WL and the stitching portion of the odd-numbered WL may extend in opposite directions. By arranging the even-numbered and odd-numbered WLs in different metallization layers, respectively, the density of the memory cells can be significantly increased, for example, by a factor of two. In other words, even if the pitch between laterally adjacent WLs is reduced, the density of the memory cells of the disclosed memory device can still be improved.

[0026] Figure 1 1 is a block diagram of a memory device 100 according to various embodiments. As shown, the memory device 100 includes a memory array 102, a WL driver circuit 104, a BL driver circuit 106, an input / output (I / O) circuit 108, and a control logic circuit 110. Figure 1 Although not shown in FIG. 1 , the components of the memory device 100 may be operably coupled to each other and to the control logic circuit 112. Figure 1 In the illustrated embodiment, for the purpose of clarity, each component is shown as a separate block, but in some other embodiments, Figure 1 Some or all of the components shown in can be integrated together.For example, memory array 102 can include embedded I / O circuits 108.

[0027] The memory array 102 is a hardware component that stores data. In one aspect, the memory array 102 is implemented as a semiconductor memory device. The memory array 102 includes a plurality of memory cells / bits (or other storage units) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R M , each row extending in a first direction, and a plurality of columns C1, C2, C3 . . . C N , each column extends in the second direction. Each row / column may include one or more conductive structures. For example, each column may include at least one bit line (BL) and at least one source line or select line (SL), and each row may include at least one word line (WL). In some embodiments, each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and may be operated according to a voltage or current signal conducted by a BL / SL disposed in the column and a WL disposed in the row.

[0028] According to various embodiments of the present disclosure, each memory cell 103 is implemented to include a storage element and an access transistor, wherein the storage elements are coupled in series with each other. The storage element may be a resistor or a capacitor. The configuration of a resistor and an access transistor coupled in series is sometimes referred to as 1T1R, and the configuration of a capacitor and an access transistor coupled in series is sometimes referred to as 1T1C. The access transistor may be coupled to a corresponding WL (e.g., selected by the corresponding WL). The access transistor may be turned on / off to enable / disable access (e.g., programming, reading) to the corresponding memory cell. For example, after being selected, the access transistor of the selected memory cell is turned on to generate a programming or reading path that conducts through its resistor / capacitor and itself. The following will refer to Figure 2 A detailed description of the 1T1R and 1T1C configurations is discussed.

[0029] The WL driver circuit 104 is a hardware component that can receive a row address of the memory array 102 and assert the WL associated with the row address. The BL driver circuit 106 is a hardware component that can receive a column address of the memory array 102 and assert the BL associated with the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each memory cell 103 asserted by the WL driver circuit 104 and the BL driver circuit 106. The control logic circuit 110 is a hardware component that can control the coupled components (e.g., 102 to 108).

[0030] Figure 2 Memory cell 103 ( Figure 1). As shown, the memory cell 103 includes a storage element 202 and an access transistor 204 coupled in series with each other. In some embodiments, the storage element 202 may include a resistor (e.g., a 1T1R configuration) or a capacitor (e.g., a 1T1C configuration). However, it should be understood that the memory cell 103 may use any of a variety of other memory cell configurations including at least one access transistor, such as a multi-transistor-resistor (multi-T1R) configuration, a multi-transistor-capacitor (multi-T1C) configuration, etc., while still within the scope of the present disclosure.

[0031] In an example of a 1T1R configuration, the storage element 202 may be formed between two adjacent metallization layers of a plurality of metallization layers disposed vertically above the main surface of the substrate, and the access transistor 204 may be formed along the main surface of the substrate. For example, the storage element 202 may include a bottom electrode and a top electrode separated by a resistance switching layer. In some embodiments, the bottom and top electrodes may each include a through-hole structure or a wire. The bottom electrode and the top electrode may include titanium, tantalum, titanium nitride, tantalum nitride, or one or more layers of other metal composite films. The resistance switching layer may include a transition metal oxide including a combination of one or more layers of hafnium oxide, aluminum oxide, tantalum oxide, or other composite materials, such as hafnium aluminum oxide. In some other embodiments, the resistance switching layer may include one or more layers of carbon-based materials, such as a carbon nanotube material resistance switching layer.

[0032] In an example of a 1T1C configuration, the storage element 202 may be similarly formed between two adjacent metallization layers disposed vertically above the main surface of the substrate, and the access transistor 204 may be formed along the main surface of the substrate. For example, the storage element 202 may include a bottom electrode and a top electrode separated by a capacitor insulator layer. In some embodiments, the bottom electrode and the top electrode may each include a through-hole structure or a wire. The bottom electrode and the top electrode may include titanium, tantalum, titanium nitride, tantalum nitride, or one or more layers of other metal composite films. The capacitor insulator layer may include a dielectric material, which may be or include zirconium oxide, aluminum oxide, hafnium oxide, silicon oxide, some other suitable dielectric, or any combination thereof. In some embodiments, the capacitor insulator layer is or includes a metal oxide, and / or, is or includes a high-k dielectric material. For example, a high-k dielectric material may be a dielectric material having a dielectric constant greater than about 10 or some other suitable value. In some other embodiments, the capacitor insulator layer may include a ferroelectric insulating layer, such as doped hafnium oxide, strontium bismuth tantalate, lead zirconate titanate, or a combination thereof. Doped hafnium oxide may, for example, be doped with zirconium, silicon, yttrium, aluminum, gadolinium, lanthanum, strontium, some other suitable element, or any combination of the above.

[0033] In general, components formed along the major surface (e.g., access transistor 204) are sometimes referred to as part of the front-end-of-line (FEOL) process / network, while metallization layers and components formed in the metallization layers (e.g., storage element 202) are sometimes referred to as part of the back-end-of-line (BEOL) process / network. Metallization layers may sometimes be referred to as M0 layers (optional), M1 layers, M2 layers, etc., where the M0 layer (if formed) or the M1 layer is the bottom-most metallization. Such BEOL components may include various conductor (e.g., metallization or metal) tracks disposed in each metallization layer, and various conductor (e.g., metallization or metal) via structures vertically inserted between adjacent metallization layers. Conductor tracks may be referred to as M0 tracks, M1 tracks, M2 tracks, etc., depending on the metallization layer to which they belong, while via structures may be referred to as V0, V1, V2, etc., based on the metallization layer to which they are connected. In addition, (e.g., conductor) components may be formed vertically between the FEOL network and the BEOL network, and these components are sometimes referred to as part of the middle-of-line (MEOL) process / network. These MEOL components may include various conductors (e.g., metal or metal structures) that electrically connect at least one FEOL component to a corresponding BEOL component. These MEOL components are sometimes referred to as MD, MP, VG, or VD. For example, MD may electrically couple the source / drain terminals of a transistor to an upper BEOL component via VD or V0; MP may electrically couple the gate terminal of a transistor to a BEOL component via V0; VG may electrically couple the gate terminal of a transistor to a BEOL component.

[0034] Figure 3 Memory array 102 ( Figure 1 ). For example, Figure 3 The illustrated memory array 102 includes memory cells 103A, 103B, 103C, 103D, 103E, 103F, 103G, and 103H. For purposes of illustration, Figure 3 The schematic diagram has been simplified, so it should be understood that Figure 3 The memory array 102 shown in part in FIG. 1 may include any of a variety of other components while remaining within the scope of the present disclosure.

[0035] In some embodiments, memory cells 103A to 103D may form a first subset of memory cells of memory array 102 arranged along a first row, and memory cells 103E to 103H may form a second subset of memory cells of memory array 102 arranged along a second row. The first row may include or otherwise correspond to a first WL, WL[0] (e.g., an even WL represented as WL[2N]), and the second row may include or otherwise correspond to a second WL, WL[1] (e.g., an odd WL represented as WL[2N+1]), where N is an integer equal to or greater than 0. In addition, the first subset of memory cells 103A to 103D may be arranged along a plurality of columns, respectively, and the second subset of memory cells 103E to 103H may be arranged along the same columns, respectively. Each column may include or otherwise correspond to a corresponding BL and a corresponding SL.

[0036] In various embodiments of the present disclosure, the first subset of memory cells 103A to 103H may have their respective source terminals of access transistors coupled to each other through one or more MEOL components (e.g., MD), which are further coupled to one or more SLs formed as first BEOL components (e.g., M1 tracks). Similarly, the second subset of memory cells 103I to 103P may have their respective source terminals of access transistors coupled to each other through one or more MEOL components (e.g., MD), which are further coupled to one or more SLs. In addition, the first WL WL[0] connected to the gate terminals of the first subset of memory cells 103A to 103D may be formed as a second BEOL component (e.g., M2 track) disposed one layer above the M1 track (SL); the second WL WL[1] connected to the gate terminals of the second subset of memory cells 103E to 103H may be formed as a third BEOL component (e.g., M3 track) disposed one layer above the M2 track (first WL[0]). The storage elements of the memory cells 103A to 103P may be formed over the first and second WLs (eg, between the M4 and M5 layers), with the BL formed as one or more fourth BEOL components (eg, M6 tracks) further disposed over the storage elements. Figure 8 and Fig.11 Details of the arrangement of memory cells 103A to 103P are discussed further.

[0037] According to various embodiments, Figure 4 A first layout 400 is shown that is configured to form a plurality of memory cells (eg, 103A-103H), Figure 5A second layout 500 is shown that is configured to form a plurality of BEOL components (e.g., WL[0] and WL[1]) that are operably coupled to a memory cell. Layouts 400 and 500 may vertically overlap each other, and further, layout 500 may correspond to a portion of (e.g., be vertically disposed above) layout 400. Layouts 400 and 500 have been simplified for purposes of illustration, and therefore, it should be understood that layouts 400, 500 may each have any of a variety of other components while still being within the scope of the present disclosure.

[0038] First reference Figure 4 , layout 400 includes patterns 402, 404, 406, and 408, each configured to form an active region (hereinafter referred to as "active region 402", "active region 404", "active region 406", and "active region 408", respectively); and patterns 410, 412, 414, 416, and 418, each configured to form a gate structure (hereinafter referred to as "gate structure 410", "gate structure 412", "gate structure 414", "gate structure 416", and "gate structure 418", respectively). In some embodiments, active regions 402 to 408 may each extend along a first lateral direction (e.g., X direction), and gate structures 410 to 418 may each extend along a different second lateral direction (e.g., Y direction). The first lateral direction is perpendicular to the second lateral direction.

[0039] In some embodiments, each of the active regions 402 to 408 is formed by a fin structure or a stacked structure protruding from a main (e.g., front side) surface of the substrate. For example, the fin structure may extend continuously from the substrate. The portion of the fin structure covered by the gate structure is retained, while the other portion of the fin structure is replaced by a number of epitaxial structures. The remainder of the fin structure may be configured as a channel of a corresponding transistor, the epitaxial structure coupled to both sides (or ends) of the remainder of the fin structure may be configured as a source / drain structure (or terminal) of the transistor, and a portion of the gate structure covering (e.g., crossing) the remainder of the fin structure may be configured as a gate structure (or terminal) of the transistor. For another example, the stack may include a plurality of semiconductor nanostructures (e.g., nanosheets) extending along a first lateral direction and separated vertically from each other. The portion of the semiconductor structure covered by the gate structure in the stack is retained, while the other portion is replaced by a number of epitaxial structures. The remainder of the semiconductor structure can be configured as a channel of a corresponding transistor, the epitaxial structure coupled to both sides (or ends) of the remainder of the semiconductor structure can be configured as a source / drain structure (or terminal) of the transistor, and a portion of the gate structure covering (e.g., crossing) the remainder of the semiconductor structure can be configured as a gate structure (or terminal) of the transistor.

[0040] For example, in Figure 4, the access transistors of memory cells 103A to 103D may be formed by active regions 402 to 408 and gate structure 410; and the access transistors of memory cells 103E to 103H may be formed by active regions 402 to 408 and gate structure 412. Thus, gate structure 410 may correspond to (e.g., be electrically coupled to) a portion of a first WL WL[0] or otherwise be a portion of the first WL, and gate structure 412 may correspond to (e.g., be electrically coupled to) a portion of a second WL WL[1] or otherwise be a portion of the second WL WL[1]. In addition, layout 400 may be used to form access transistors of memory cells 103I, 103J, 103K, and 103L (which may be formed from active regions 402 to 408 and gate structure 416), and access transistors of memory cells 103M, 103N, 103O, and 103P (which may be formed from active regions 402 to 408 and gate structure 418). In some embodiments, gate structure 414 interposed between gate structures 412 and 416 may be configured as a dummy gate structure (e.g., not as part of an active transistor).

[0041] Layout 400 also includes patterns 420, 422, 424, 426, 428, and 430, each of which is configured to form a MEOL component, such as an MD (hereinafter referred to as "MD 420", "MD 422", "MD 424", "MD 426", "MD 428", and "MD 430", respectively). In some embodiments, each of MD 420, 424, 426, and 430 may be cut into a plurality of portions (sometimes referred to as cut MD 420, cut MD 424, cut MD 426, cut MD 430) by one or more cut metal structures formed by pattern 431. Each of these cut metal structures (CMD) may pass through one or more of MD 420, 424, 426, and 430. On the other hand, MD 422 and 428 may remain uncut (sometimes referred to as uncut MD 422 and 428), i.e., continuously extend through a plurality of active structures along the Y direction. Therefore, the uncut MD can be electrically coupled to the source / drain terminals of a plurality of corresponding transistors, and the cut MD can be electrically coupled to the drain / source terminal of a single corresponding transistor.

[0042] exist Figure 4In the example, uncut MD 422 is coupled to the source / drain terminals of the access transistors of memory cells 103A to 103H (e.g., shorting the source terminals of the access transistors in memory cells 103A to 103H); uncut MD 428 is coupled to the source / drain terminals of the access transistors of memory cells 103I to 103P (e.g., shorting the source terminals of the access transistors of memory cells 103I to 103P); one of the cut MDs 420 is coupled to the source / drain terminals of the access transistor of memory cell 103A; another cut MD 420 is coupled to the source / drain terminals of the access transistor of memory cell 103B; and so on.

[0043] The layout 400 also includes a plurality of patterns 432 and a plurality of patterns 434, each of which is configured to form a BEOL component in the M1 layer, such as an M1 island (hereinafter referred to as "M1 island 432"), and each of which is configured to form another BEOL component in the M1 layer, such as an M1 track (hereinafter referred to as "M1 track 434"). In some embodiments, the M1 island 432 is configured to be connected to (e.g., electrically coupled to) a corresponding one of the cut MDs, such as the cut MD 420, the cut MD 424, the cut MD 426, the cut MD 430, etc., through a corresponding via structure. Therefore, the M1 island 432 may not extend beyond one cut / uncut MD. The M1 track 434 extending across multiple MDs in the X direction is configured to be electrically coupled to one or more uncut MDs, such as 422 and 428.

[0044] In various embodiments, the M1 rails 434 may be configured as a plurality of SLs, respectively. Thus, one of the source / drain terminals of the access transistors of the memory cells 103A to 103P (formed based on the layout 400) may be short-circuited to each other by the M1 rails 434 (SL) and the uncut MDs 422 and 428 below. For example, in Figure 4 , the source terminals of the access transistors of the memory cells 103A to 103H may be coupled to each other through the uncut MD 422, and the source terminals of the access transistors of the memory cells 103I to 103P may be coupled to each other through the uncut MD 428. In addition, the two uncut MDs 422 and 428 may be coupled to each other through the M1 track 434.

[0045] Next reference Figure 5, layout 500 may cover a portion of layout 400 (e.g., including a portion of patterns / structures forming memory cells 103A-103B, 103E-103F, 103I-103J, and 103M-103N), and include: patterns 510 and 515, each configured to form a BEOL component in the M3 layer, such as an M3 track (hereinafter referred to as "M3 track 510" and "M3 track 515", respectively), and patterns 520 and 525, each configured to form a BEOL component in the M2 layer (e.g., an M2 track (hereinafter referred to as "M2 track 530" and "M2 track 535", respectively). In some embodiments, the M3 tracks 510-515 and the M2 tracks 520-525 each extend in the Y direction. In addition, each of the M3 tracks 510-515 and the M2 tracks 520-525 includes a longitudinal portion extending in the Y direction and a stitching portion protruding away from the longitudinal portion in the X direction.

[0046] For example, in Figure 5 , M3 track 510 includes longitudinal portion 510A and stitching portion 510B; M2 track 520 includes longitudinal portion 520A and stitching portion 520B; M3 track 515 includes longitudinal portion 515A and stitching portion 515B; M2 track 525 includes longitudinal portion 525A and stitching portion 525B. Longitudinal portion 510A and longitudinal portion 520A may overlap each other vertically, while stitching portion 510B and stitching portion 520B may protrude in opposite directions. Similarly, longitudinal portion 515A and longitudinal portion 525A may overlap each other vertically, while stitching portion 515B and stitching portion 525B may protrude in opposite directions.

[0047] In some embodiments, the M3 rail 510 can be operable to function as a first WLWL[0] connected to the gate terminals of the access transistors of the memory cells 103A-103B and 103C-103D (not shown); the M2 rail 520 can be operable to function as a second WLWL[1] connected to the gate terminals of the access transistors of the memory cells 103E-103F and 103G-103H (not shown). Similarly, the M3 rail 515 can be operable to function as a third WLWL[2] connected to the gate terminals of the access transistors of the memory cells 103I-103J and 103K-103L (not shown); the M2 rail 525 can be operable to function as a fourth WLWL[3] connected to the gate terminals of the access transistors of the memory cells 103M-103N and 103O-103P (not shown). According to the present disclosure, WL[0] and WL[2] are referred to as even WLs, and WL[1] and WL[3] are referred to as odd WLs.

[0048] Since adjacent even WLs and odd WLs (e.g., WL[0] and WL[1]) are formed in their own metallization layers, the arrangement of the WLs will not be limited by the relatively tight spacing (pitch) in the underlying metallization layers and can be formed in these underlying metallization layers (e.g., M2 layer, M3 layer). In other words, the pitch of the WLs in any of these metallization layers can be increased by a factor of two. Advantageously, more space can be freed up between these metallization layers to arrange other connections, thereby significantly increasing the density of corresponding memory cells in a particular area.

[0049] In some embodiments, WL[0] (e.g., a portion of which is implemented as an M3 track 510) can be coupled to the gate terminals of the access transistors of the memory cells 103A-103D via its stitching portion 510B, and WL[1] (e.g., a portion of which is implemented as an M2 track 520) can be coupled to the gate terminals of the access transistors of the memory cells 103E-103H via its stitching portion 520B. For example, WL[0] (or M3 track 510) can be coupled to the gate terminals of the corresponding memory cells 103A-103D via the stitching portion 510B, one V2, one M2 track, one V1, one M1 track or island, one V0, and one MP, and WL[1] (or M2 track 520) can be coupled to the gate terminals of the corresponding memory cells 103E-103H via the stitching portion 520B, another V1, another M1 track or island, another V0, and another MP. This can be done in Figure 8 and Fig.11 can be better understood in the cross-sectional view.

[0050] Figure 6 Memory array 102 ( Figure 1 ). For example, Figure 6 The memory array 102 shown in FIG. 1 includes gate terminals of access transistors 204 of a plurality of memory cells 103, which are coupled to each other through the same WL (e.g., along the same row). The gate terminals of these access transistors may be embodied as a single gate structure 610, which may be Figure 6 For illustration purposes, Figure 6 The schematic diagram has been simplified, so it should be understood that Figure 6 The memory array 102 shown in part in FIG. 1 may include any of a variety of other components while remaining within the scope of the present disclosure.

[0051] In some embodiments, Figure 6 The schematic diagram is based on Figure 3 Schematic diagram and Figure 4-Figure 5 Therefore, the gate terminals of the respective access transistors of the memory cells 103 (at Figure 6 The M2 / M3 rail 620 is a metal rail 630 disposed in a vertically higher metallization layer (e.g., an M7 layer). The additional metal rail 630, for example, implemented as an M7 rail (hereinafter referred to as "M7 rail 630"), is coupled to the M2 / M3 rail 620 in parallel through a plurality of repurposed storage elements 640. In some embodiments, these storage elements 640 may be disposed between the M4 layer and the M5 layer, with any one of the storage elements 640 disposed vertically above the M2 / M3 rail 620. The M7 rail 630 typically has a larger size (e.g., a wider width) than the M2 / M3 rail 620 and therefore has a lower resistance. By this arrangement, the total resistance of the WL (embodied as at least one M2 / M3 track coupled in parallel with one M7 track) can be significantly reduced.

[0052] Figure 7 An example layout 700 is shown, in accordance with some embodiments, which is configured to form a plurality of M7 tracks 630, each track 630 coupled to a respective one of the WLs formed as M2 / M3 tracks. Layout 700 can be used with layouts (such as layout 400 ( Figure 4 )) overlap vertically. Therefore, Figure 7 4 shows some patterns of layout 400 for reference. As shown, layout 700 includes patterns 710, 715, 720, and 725, each configured to form an M7 track (hereinafter referred to as "M7 track 710", "M7 track 715", "M7 track 720", and "M7 track 725", respectively). M7 tracks 710 to 725 each extend along the Y direction and can be laterally offset away from corresponding (e.g., lower) M2 and M3 tracks configured as WL, or aligned with the M2 and M3 tracks.

[0053] Figure 8 4 shows a cross-sectional view of a semiconductor structure 800 according to some embodiments, which may be based on the layout 400 ( Figure 4 ), layout 500( Figure 5 ) and layout 700( Figure 7 ) together. For example, Figure 8 The cross-section of the Figure 5 and Figure 7 ), line XX passes through the stitching portion of the M2 and M3 tracks of the WL used for multiple memory cells.

[0054] As shown, gate structures 410, 412, 416, and 418, which are respectively operable to serve as a portion of WL[0], WL[1], WL[2], and WL[3], are formed along the major surface of the substrate. WL[0] to WL[3] can each be operably shared by a corresponding number of memory cells 103 (e.g., 64 memory cells arranged along a particular row of the memory array). A plurality of metallization layers, such as from the M1 layer to the M7 layer, are formed on the gate structures 410 to 418.

[0055] According to some embodiments of the present disclosure, one of the M2 tracks 520 has a stitching portion 520B electrically coupled to the gate structure 412 (WL[1]) through a corresponding V1, a corresponding M1, a corresponding V0, and a corresponding MP; and the other M2 track 525 has a stitching portion 525B electrically coupled to the gate structure 418 (WL[3]) through a corresponding V1, a corresponding M1, a corresponding V0, and a corresponding MP. Similarly, one of the M3 tracks 510 has a stitching portion 510B electrically connected to the gate structure 410 (WL[0]) through a corresponding V2, a corresponding M2, a corresponding V1, a corresponding M1, a corresponding V0, and a corresponding MP; and the other M3 track 515 has a stitching portion 515B electrically coupled to the gate structure 416 (WL[2]) through a corresponding V2, a corresponding M2, a corresponding V1, a corresponding M1, a corresponding V0, and a corresponding MP. In some embodiments, the above-mentioned M1 coupled to the corresponding gate structure may not be used as any of the SLs. In some embodiments, the M2 rail 520 and the M3 rail 510 may have their respective longitudinal portions vertically aligned with each other (eg, Figure 8 The longitudinal portions of the M2 track 525 and the M3 track 515 can be vertically aligned with each other (as shown in the dashed line in FIG. 1 ); Figure 8 ).

[0056] In addition, M3 track 510 (part of WL[0]) can be coupled to M7 track 710; M2 track 520 (part of WL[1]) can be coupled to M7 track 715; M3 track 515 (part of WL[2]) can be coupled to M7 track 720; M2 track 525 (part of WL[3]) can be coupled to M7 track 725. M7 tracks 710, 715, 720 and 725 can thus be part of WL[0], WL[1], WL[2] and WL[3], respectively. As shown, M2 tracks 520-525 and M3 tracks 510-515 can each be coupled to a corresponding M7 track using their stitched portions (e.g., the stitched portions are vertically aligned with the corresponding M7 tracks). However, other arrangements are also contemplated.

[0057] In some embodiments of the present disclosure, the M2 tracks 520-525 and the M3 tracks 510-515 can each be coupled to a corresponding M7 track via a storage element 810 interposed between the M4 layer and the M5 layer. The storage element 810, which can be formed as a MIM structure as described above, can be requisitioned or repurposed as a via structure to electrically couple the M7 track to the underlying M2 or M3 track. It should be noted that the corresponding storage element of the memory cell 103 (driven by WL[0] to WL[3]) can also be formed between the M4 layer and the M5 layer, but laterally offset from the requisitioned storage element 810. For example, a non-requisitioned storage element that is still used to store data can be roughly aligned with the source / drain terminals of the corresponding access transistor formed along the main surface of the substrate.

[0058] Fig. 9 Memory array 102 ( Figure 1 ). For example, Fig. 9 The illustrated memory array 102 includes gate terminals of access transistors 204 of a plurality of memory cells 103, which are coupled to each other via the same WL (e.g., along the same row). The gate terminals of these access transistors may be embodied as a single gate structure 910, which may be Fig. 9 For illustration purposes, Fig. 9 The schematic diagram has been simplified, so it should be understood that Fig. 9 The memory array 102 shown in part in FIG. 1 may include any of a variety of other components while remaining within the scope of the present disclosure.

[0059] In some embodiments, Fig. 9 The schematic diagram is based on Figure 3 Schematic diagram and Figure 4-Figure 5 Therefore, the gate terminal of the corresponding access transistor of the memory cell 103 (at Fig. 9 The M2 / M3 track 920 (implemented as a gate structure 910) is coupled to each other through a WL 920, which is formed as an M2 track or an M3 track (hereinafter referred to as "M2 / M3 track 920"), depending on whether WL is an odd number or an even number. The M2 / M3 track 920 can be operably coupled to a WL driver (e.g., 104) via a metal track 930 disposed in a vertically higher metallization layer (e.g., an M7 layer). An additional metal track 930, for example implemented as an M7 track (hereinafter referred to as "M7 track 930"), can be configured to carry a WL enable signal to activate the M2 / M3 track 920 (WL). For example, as long as the WL enable signal (WL_ENB) is pulled down, the WL signal carried on the M2 / M3 track 920 can be pulled up, and vice versa. Therefore, with Figure 6Unlike the schematic diagram of FIG. 1 , the M7 track 930 may not be coupled to the M2 / M3 track 620 through any storage element interposed between the M4 layer and the M5 layer. Given the lower resistance of the M7 track 930 operatively coupled to the proximal and distal ends of the M2 / M3 track 920, the transition period of the WL signal may be significantly reduced (e.g., reduced by at least about 7%). With such an arrangement, the read / write speed of the memory cell may be significantly improved.

[0060] Fig.10 1 shows an example layout 1000 configured to form a plurality of M7 tracks 930, each track 930 being coupled to the proximal and distal ends of a corresponding one of the WLs formed as M2 / M3 tracks via a proximal WL driver and a distal WL driver, respectively. Layout 1000 may be used in conjunction with (e.g., the following) layouts (such as layout 400 ( Figure 4 )) overlap vertically. Therefore, Fig.10 4 shows some patterns of layout 400 for reference. As shown, layout 1000 includes patterns 1010, 1015, 1020, and 1025, each configured to form an M7 track (hereinafter referred to as "M7 track 1010", "M7 track 1015", "M7 track 1020", and "M7 track 1025", respectively). M7 tracks 1010 to 1025 each extend along the Y direction and can be laterally away from or aligned with corresponding (e.g., lower) M2 and M3 tracks configured as WL.

[0061] Fig.11 4 shows a cross-sectional view of a semiconductor structure 1100 according to some embodiments, which may be based on a layout 400 ( Figure 4 ), layout 500( Figure 5 ) and layout 1000( Fig.10 ) together. For example, Fig.11 The cross-section of the Figure 5 and Fig.10 ), line XX passes through the stitching portion of the M2 and M3 tracks of the WL used for multiple memory cells.

[0062] As shown, gate structures 410, 412, 416, and 418, which are respectively operable to serve as a portion of WL[0], WL[1], WL[2], and WL[3], are formed along the major surface of the substrate. WL[0] to WL[3] can each be operably shared by a corresponding number of memory cells 103 (e.g., 64 memory cells arranged along a particular row of the memory array). A plurality of metallization layers, such as M1 to M7 layers, are formed on the gate structures 410 to 418.

[0063] According to some embodiments of the present disclosure, one of the M2 tracks 520 has a stitching portion 520B electrically coupled to the gate structure 412 (WL[1]) through a corresponding V1, a corresponding M1, a corresponding V0, and a corresponding MP; and the other M2 track 525 has a stitching portion 525B electrically coupled to the gate structure 418 (WL[3]) through a corresponding V1, a corresponding M1, a corresponding V0, and a corresponding MP. Similarly, one of the M3 tracks 510 has a stitching portion 510B electrically connected to the gate structure 410 (WL[0]) through a corresponding V2, a corresponding M2, a corresponding V1, a corresponding M1, a corresponding V0, and a corresponding MP; and the other M3 track 515 has a stitching portion 515B electrically coupled to the gate structure 416 (WL[2]) through a corresponding V2, a corresponding M2, a corresponding V1, a corresponding M1, a corresponding V0, and a corresponding MP. In some embodiments, the above-mentioned M1 coupled to the corresponding gate structure may not be used as any of the SLs. In some embodiments, the M2 rail 520 and the M3 rail 510 may have their respective longitudinal portions vertically aligned with each other (eg, Fig.11 The longitudinal portions of the M2 track 525 and the M3 track 515 can be vertically aligned with each other (as shown in the dashed line in FIG. 1 ); Fig.11 ).

[0064] In addition, the M3 track 510 (a portion of WL[0]) can be connected to the M7 track 1010 via a corresponding WL driver (not shown) formed along the main surface; the M2 track 520 (a portion of WL[1]) can be coupled to the M7 track 1015 via a corresponding WL driver (not shown) formed along the main surface; the M3 track 515 (a portion of WL[2]) can be coupled to the M7 track 1020 via a corresponding WL driver (not shown) formed along the main surface; and the M2 track 525 (a portion of WL[3]) can be coupled to the M7 track 1025 via a corresponding WL driver (not shown) formed along the main surface. As shown, the M2 tracks 520-525 and the M3 tracks 510-515 can each have a stitching portion that is vertically aligned with the corresponding M7 track, but other arrangements are also contemplated.

[0065] In some embodiments of the present disclosure, each of the M2 tracks 520-525 and the M3 tracks 510-515 may not be coupled to the corresponding M7 track through a storage element (e.g., 1110) interposed between the M4 layer and the M5 layer. In other words, the storage element 1110, which may be formed as a MIM structure as described above, may not be requisitioned or repurposed as a through-hole structure to electrically couple the M7 track to the underlying M2 or M3 track. For example, in Fig.11 In, with Figure 8Compared to the semiconductor structure 800 shown, there may be no via structures (e.g., V3 and V5) above the top electrode and below the bottom electrode of the storage element 1110. Such storage elements 1110 may be disposed above stitching portions 510B-525B, respectively. It should be noted that the corresponding storage elements of the memory cell 103 (driven by WL[0] to WL[3]) may also be formed between the M4 layer and the M5 layer, but laterally offset from the storage element 1110 shown.

[0066] Fig.12 and Fig.13 4 and 500 ( Figure 4-Figure 5 ) is a cross-sectional view of the semiconductor structures 1200 and 1300 formed together. For example, Figure 12-13 The cross-section of the Figure 4 ), the line YY extends along the M2 and M3 tracks of WL used as multiple memory cells.

[0067] exist Fig.12 , semiconductor structure 1200 includes a plurality of source terminals (e.g., epitaxial structures) of access transistors of memory cells 103A to 103H formed in active regions 402, 404, 406, and 408, respectively. Above the source terminals, MD 422 is formed to couple to these source / drain terminals. Above MD 422, semiconductor structure 1200 includes a plurality of M1 tracks coupled to MD 422 through a plurality of V0s. In some embodiments, the M1 tracks are operable to function as SLs together with the MDs to short-circuit the source terminals of the access transistors of memory cells 103A to 103H. In addition, above the M1 tracks, semiconductor structure 1200 includes at least one M2 track operable to function as a WL of memory cells 103A-103D and at least one M3 track operable to function as a WL of memory cells 103E-103H. In some embodiments, Fig.12 The M1 track, M2 track, and M3 track shown in the cross-sectional view of FIG. 4 may be formed based on the patterns 434 , 520 , and 510 of the layouts 400 - 500 , respectively.

[0068] exist Fig.13, semiconductor structure 1300 includes a plurality of source terminals (e.g., epitaxial structures) of access transistors of memory cells 103A-103H formed in active regions 402, 404, 406, and 408, respectively. Above the source terminals, MD 422 is formed to couple to these source / drain terminals. Above MD 422, semiconductor structure 1300 includes a plurality of M0 tracks coupled to MD 422 through a plurality of VDs. In some embodiments, the M0 tracks are operable to function as SLs together with the MDs to short-circuit the source terminals of the access transistors of memory cells 103A-103H. In addition, above the M0 tracks, semiconductor structure 1300 includes at least one M1 track operable to function as a WL of memory cells 103A-103D and at least one M3 track operable to function as a WL of memory cells 103E-103H. In some embodiments, Fig.13 The M0 track, M1 track, and M3 track shown in the cross-sectional view of FIG. 4 may be formed based on the patterns 434 , 520 , and 510 of the layouts 400 - 500 , respectively.

[0069] Fig.14 A flowchart of an example method 1400 for forming at least a portion of a memory array according to one or more embodiments of the present disclosure is shown. For example, method 1400 can be performed to form a semiconductor (e.g., memory) device according to layouts 400, 500, 700, and / or 1000. In some embodiments, method 1400 includes operations to manufacture a plurality of memory cells, each memory cell including an access transistor and a storage element. The source terminals of the access transistors are coupled to each other via an M1 track or an M0 track (operably used as one SL), and their gate terminals are coupled to an M2 track and an M3 track or an M1 track and an M3 track (operably used as two WLs, respectively). The storage element can be formed vertically above these WLs. It should be noted that method 1400 is merely an example and is not intended to limit the present disclosure. Therefore, it will be understood that in Figure 1 Additional operations may be provided before, during, and after method 1400. And some other operations may only be briefly described here.

[0070] According to various embodiments, method 1400 begins with operation 1402, in which a plurality of access transistors are formed along a main surface of a substrate. The access transistors may be configured according to Figure 4 Patterns 402-408 and 410-412 are formed which form a portion of a memory array, for example, access transistors for eight memory cells (103A to 103H) arranged across two rows and four columns.

[0071] The substrate includes a semiconductor material substrate, such as silicon. Alternatively, the substrate may include other elemental semiconductor materials, such as germanium. The substrate may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, and gallium indium phosphide. In one embodiment, the substrate includes an epitaxial layer. For example, the substrate may have an epitaxial layer covering the bulk semiconductor. In addition, the substrate may include a semiconductor on insulator (SOI) structure. For example, the substrate may include a buried oxide (BOX) layer formed by a process such as separation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0072] The access transistors may each be formed as any of a planar transistor, a fin transistor, a full-ring gate (GAA) transistor, and the like. In the example of a GAA transistor, a plurality of stacks may be defined on the substrate according to patterns 402-408. Each stack includes a series of alternating first and second nanostructures. The first nanostructure may include a SiGe sacrificial nanostructure, and the second nanostructure may include a Si channel nanostructure. Such a stack may sometimes be referred to as a superlattice. In a non-limiting example, the SiGe sacrificial nanostructure may be SiGe 25%. The symbol "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge. It should be understood that the percentage of Ge in each SiGe sacrificial nanostructure may be any value between 0 and 100 (excluding 0 and 100) while still within the scope of the present disclosure. In some other embodiments, the second nanostructure may include a first semiconductor material other than Si, and the first nanostructure may include a second semiconductor material other than SiGe, as long as the first and second semiconductors have different etching characteristics (e.g., etching rates), respectively.

[0073] After forming the stack, a plurality of dummy gate structures can be formed according to patterns 410-412. The dummy gate structure is formed by depositing amorphous silicon (a-Si) on the stack. Other materials suitable for forming dummy gates (e.g., polysilicon) can be used while still within the scope of the present disclosure. The a-Si is then flattened to a desired level. A hard mask is deposited on the flattened a-Si and patterned. The hard mask can be formed of a nitride or oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form a dummy gate structure.

[0074] After forming the dummy gate structure, a gate spacer may be formed to extend along the sidewall of each dummy gate structure. The gate spacer may be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of these materials) followed by directional etching (e.g., RIE). Next, an internal spacer may be formed by replacing the end of each SiGe sacrificial nanostructure with a dielectric material. Next, a plurality of epitaxial structures are formed using an epitaxial layer growth process on the exposed end of the Si nanostructure. In-situ doping (ISD) may be applied to form a doped epitaxial structure that is operable as a source / drain terminal of an access transistor. Next, the dummy gate structure and the remaining SiGe sacrificial nanostructure are replaced with a corresponding active gate structure. Thus, active gate structures 410 and 412 may each surround each Si nanostructure formed based on active regions 402 to 408. In some embodiments, active gate structure 410 may be operable to function as part of the WL of a first subset of memory cells 103A-103D and active gate structure 412 may be operable to function as part of the WL of a second subset of memory cells 103E-103H.

[0075] According to various embodiments, the method 1400 continues to operation 1404 in which a MEOL structure is formed to couple source terminals or drain terminals of the access transistors to each other. For example, the MEOL structure may be a MD 422 extending between the active gate structures 410 and 412 .

[0076] MD 422 may be formed of a metal material. The metal material may be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front side interconnect structure may be formed by covering the front side of the substrate with the above metal materials, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating, or a combination thereof.

[0077] According to various embodiments, the method 1400 continues to operation 1406, where a plurality of first BEOL structures disposed in the first metallization layer are formed to couple to the MEOL structure. For example, the first BEOL structure may be an M1 track 434. The M1 track 434 may pass through a plurality of MEOL structures similar to the MD 422. In some embodiments, the M1 track 434 and the electrically coupled MD 422 may be operable to serve as SLs for the memory cells 103A-103H.

[0078] The M1 track 434 may be formed of a metal material. The metal material may be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front side interconnect structure may be formed by covering the front side of the substrate with the above metal materials, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating, or a combination thereof.

[0079] According to various embodiments, the method 1400 continues to operation 1408, where a second BEOL structure disposed in the second metallization layer is formed to couple to the gate terminals of the first subset of access transistors. For example, the second BEOL structure can be an M2 track 520 including a longitudinal portion and a stitching portion. In some embodiments, the M2 track 520 is operable to serve as another portion of the WL of the second subset of memory cells 103E-103H. For example, the stitching portion of the M2 track 520 can be used to electrically connect to the active gate structure 412.

[0080] The M2 track 520 can be formed of a metal material. The metal material can be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front side interconnect structure can be formed by covering the front side of the substrate with the above metal materials, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating or a combination thereof.

[0081] According to various embodiments, the method 1400 continues to operation 1410, where a third BEOL structure disposed in the third metallization layer is formed to couple to gate terminals of the second subset of access transistors. For example, the third BEOL structure can be an M3 track 510 that also includes a longitudinal portion and a stitching portion. However, the stitching portion of the M2 track 520 and the stitching portion of the M3 track 510 can point in opposite directions. In some embodiments, the M3 track 510 is operable to serve as another portion of the WL of the first subset of memory cells 103A-103D. For example, the stitching portion of the M3 track 520 can be used to electrically connect to the active gate structure 410.

[0082] The M3 track 510 can be formed of a metal material. The metal material can be selected from aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and combinations thereof. Other metal materials are also within the scope of the present disclosure. The front side interconnect structure can be formed by covering the front side of the substrate with the above metal materials, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating or a combination thereof.

[0083] According to various embodiments, method 1400 continues to operation 1412, where a plurality of storage elements are formed between a fourth metallization layer and a fifth metallization layer vertically disposed above the second BEOL structure and the third BEOL structure. For example, the storage elements can be formed between the M4 layer and the M5 layer. In some embodiments, the storage elements can be formed based on a MIM configuration, for example, with an insulator layer vertically interposed between a bottom electrode and a top electrode. The storage elements are electrically coupled in series to access transistors formed along a major surface of the substrate, thereby forming memory cells 103A-103H. For example, each storage element can be vertically aligned with at least one component (e.g., a source or drain terminal) of a corresponding access transistor.

[0084] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a plurality of first memory cells, each of the plurality of first memory cells includes a corresponding first transistor and a corresponding first storage element, the first transistor is formed along the main surface of the substrate and arranged along the first lateral direction, and the first storage element is formed in a first metallization layer of a plurality of metallization layers vertically arranged above the main surface. The memory device includes a plurality of second memory cells, each of the plurality of second memory cells includes a corresponding second transistor and a corresponding second storage element, the second transistor is formed along the main surface of the substrate and arranged along the first lateral direction, and the second storage element is formed in a second metallization layer of a plurality of metallization layers, wherein the second transistor of the second memory cell is arranged along a second lateral direction perpendicular to the first lateral direction relative to the first transistor of the first memory cell. The memory device includes a first metal track, which is operably configured as a first word line of the plurality of first memory cells and extends along the first lateral direction, is arranged in a third metallization layer of the plurality of metallization layers, and includes a first stitching portion extending away from the first metal track in the second lateral direction, wherein the first stitching portion is configured to connect the first word line to the corresponding gate structure of the first transistor of the first memory cell. The memory device includes a second metal track operably configured as a second word line of a plurality of second memory cells and extending along a first lateral direction, disposed in a fourth metallization layer among the plurality of metallization layers, and including a second stitching portion extending away from the second metal track in a second lateral direction, wherein the second stitching portion is configured to connect the second word line to a corresponding gate structure of a second transistor of the second memory cell.

[0085] In some embodiments, the first metallization layer and the second metallization layer are located at the same level.

[0086] In some embodiments, the third metallization layer and the fourth metallization layer are located at different levels and are vertically lower than the first metallization layer and the second metallization layer, respectively.

[0087] In some embodiments, the first metal track and the second metal track are vertically aligned with each other.

[0088] In some embodiments, the first stitched portion and the second stitched portion extend away from each other.

[0089] In some embodiments, the memory device further includes: a plurality of third memory cells, each of the plurality of third memory cells includes a corresponding third transistor and a corresponding third storage element, the third transistor is formed along the main surface of the substrate and arranged along the first lateral direction, and the third storage element is formed in a fifth metallization layer among the plurality of metallization layers; a plurality of fourth memory cells, each of the plurality of fourth memory cells includes a corresponding fourth transistor and a corresponding fourth storage element, the fourth transistor is formed along the main surface of the substrate and arranged along the first lateral direction, and the fourth storage element is formed in a sixth metallization layer among the plurality of metallization layers, wherein the fourth transistor of the fourth memory cell is arranged along the second lateral direction relative to the third transistor of the third memory cell; A third metal track, operably configured as a third word line for a plurality of third memory cells and extending along the first lateral direction, is disposed in a third metallization layer and includes a third stitching portion extending away from the third metal track in a second lateral direction, wherein the third stitching portion is configured to connect the third word line to a corresponding gate structure of a third transistor of the third memory cell; and a fourth metal track, operably configured as a fourth word line for a plurality of fourth memory cells and extending along the first lateral direction, is disposed in a fourth metallization layer and includes a fourth stitching portion extending away from the fourth metal track in the second lateral direction, wherein the fourth stitching portion is configured to connect the fourth word line to a corresponding gate structure of a fourth transistor of the fourth memory cell.

[0090] In some embodiments, the first metallization layer, the second metallization layer, the fifth metallization layer, and the sixth metallization layer are located at the same level.

[0091] In some embodiments, the first word line and the third word line are each configured as an even word line, and the second word line and the fourth word line are each configured as an odd word line.

[0092] In some embodiments, the third metal track and the fourth metal track are vertically aligned with each other.

[0093] In some embodiments, the third stitched portion and the fourth stitched portion extend away from each other.

[0094] In some embodiments, the first storage element of the first memory cell and the second storage element of the second memory cell each include a resistor or a capacitor.

[0095] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory array, the memory array includes a plurality of memory cells arranged on a plurality of rows, the rows include a plurality of word lines, a first group of memory cells are coupled to even word lines in the word lines, and a second group of memory cells are coupled to odd word lines in the word lines. The even word lines are arranged in a first metallization layer among a plurality of metallization layers vertically formed above a substrate, wherein the even word lines extend along a first lateral direction, and wherein the even word lines include a first longitudinal portion extending in the first lateral direction and a first stitching portion extending in a second lateral direction perpendicular to the first lateral direction to allow connection to a gate structure of a first transistor of the first group of memory cells. The odd word lines are arranged in a second metallization layer among a plurality of metallization layers, wherein the odd word lines extend along the first lateral direction, and wherein the odd word lines include a second longitudinal portion extending in the first lateral direction and a second stitching portion extending in the second lateral direction to allow connection to a gate structure of a second transistor of the second group of memory cells.

[0096] In some embodiments, the first longitudinal portion and the second longitudinal portion are perpendicularly aligned with each other, and the first stitched portion and the second stitched portion extend away from each other.

[0097] In some embodiments, the first transistors are aligned with respect to each other along a first lateral direction, and the second transistors are aligned with respect to each other along the first lateral direction.

[0098] In some embodiments, the first transistor and the second transistor are arranged along a second lateral direction relative to each other.

[0099] In some embodiments, the plurality of memory cells include a plurality of storage elements, and the plurality of storage elements are disposed in a third metallization layer of the plurality of metallization layers.

[0100] In some embodiments, the third metallization layer is vertically disposed on any one of the first metallization layer or the second metallization layer.

[0101] In some embodiments, each of the plurality of storage elements comprises a resistor or a capacitor.

[0102] In another aspect of the present disclosure, a method for forming a memory device is disclosed. The method includes: forming a first group of transistors and a second group of transistors along a main surface of a substrate, wherein the first group of transistors are aligned along a first lateral direction, and the second group of transistors are aligned along the first lateral direction, and the first group of transistors and the second group of transistors are arranged relative to each other along a second lateral direction perpendicular to the first lateral direction. The method includes: forming a first metal track in a first metallization layer of a plurality of metallization layers vertically arranged above the main surface, wherein the first metal track includes a first longitudinal portion extending along the first lateral direction and a first stitching portion extending along the second lateral direction, and the first stitching portion is coupled to a gate structure of the first group of transistors. The method includes: forming a second metal track in a second metal layer of a plurality of metallization layers, wherein the second metal track includes a second longitudinal portion extending along the first lateral direction and a second stitching portion extending along the second lateral direction, and the second stitching portion is coupled to a gate structure of the second group of transistors. The method includes: forming a first group of storage elements in a third metallization layer of a plurality of metallization layers, wherein the first group of storage elements are respectively coupled to the first group of transistors. The method includes forming a second group of storage elements in a third metallization layer, wherein the second group of storage elements are respectively coupled to the second group of transistors.

[0103] In some embodiments, the third metallization layer is vertically formed on any one of the first metallization layer or the second metallization layer.

[0104] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary depending on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a 10-30% range (e.g., +10%, ±20%, or ±30% of a value).

[0105] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, comprising: a plurality of first memory cells, each of the plurality of first memory cells comprising a corresponding first transistor and a corresponding first storage element, the first transistor being formed along a major surface of the substrate and arranged along a first lateral direction, the first storage element being formed in a first metallization layer of a plurality of metallization layers disposed vertically above the major surface; a plurality of second memory cells, each of the plurality of second memory cells comprising a corresponding second transistor and a corresponding second storage element, the second transistor being formed along the main surface of the substrate and arranged along the first lateral direction, the second storage element being formed in a second metallization layer of the plurality of metallization layers, wherein the second transistor of the second memory cell is arranged along a second lateral direction perpendicular to the first lateral direction relative to the first transistor of the first memory cell; a first metal track operably configured as a first word line of the plurality of first memory cells and extending along the first lateral direction, disposed in a third metallization layer of the plurality of metallization layers and comprising a first stitching portion extending away from the first metal track along the second lateral direction, wherein the first stitching portion is configured to connect the first word line to a corresponding gate structure of the first transistor of the first memory cell; and A second metal track, operably configured as a second word line of the plurality of second memory cells and extending along the first lateral direction, is disposed in a fourth metallization layer among the plurality of metallization layers and includes a second stitching portion extending away from the second metal track along the second lateral direction, wherein the second stitching portion is configured to connect the second word line to a corresponding gate structure of the second transistor of the second memory cell.

2. The memory device according to claim 1, wherein: The first metallization layer and the second metallization layer are located at the same level.

3. The memory device according to claim 1, wherein: The third metallization layer and the fourth metallization layer are respectively located at different levels and are respectively disposed vertically lower than the first metallization layer and the second metallization layer.

4. The memory device according to claim 1, wherein: The first metal track and the second metal track are vertically aligned with each other.

5. The memory device according to claim 1, wherein: The first stitched portion and the second stitched portion extend away from each other.

6. The memory device according to claim 1, further comprising: a plurality of third memory cells, each of the plurality of third memory cells comprising a corresponding third transistor and a corresponding third storage element, the third transistor being formed along the main surface of the substrate and arranged along the first lateral direction, the third storage element being formed in a fifth metallization layer of the plurality of metallization layers; a plurality of fourth memory cells, each of the plurality of fourth memory cells comprising a corresponding fourth transistor and a corresponding fourth storage element, the fourth transistor being formed along the main surface of the substrate and arranged along the first lateral direction, the fourth storage element being formed in a sixth metallization layer of the plurality of metallization layers, wherein the fourth transistor of the fourth memory cell is arranged along the second lateral direction relative to the third transistor of the third memory cell; a third metal track operably configured as a third word line for the plurality of third memory cells and extending along the first lateral direction, disposed in the third metallization layer and comprising a third stitching portion extending away from the third metal track along the second lateral direction, wherein the third stitching portion is configured to connect the third word line to a respective gate structure of the third transistor of the third memory cell; and A fourth metal track, operably configured as a fourth word line of the plurality of fourth memory cells and extending along the first lateral direction, is disposed in the fourth metallization layer and includes a fourth stitching portion extending away from the fourth metal track along the second lateral direction, wherein the fourth stitching portion is configured to connect the fourth word line to a corresponding gate structure of the fourth transistor of the fourth memory cell.

7. The memory device according to claim 6, wherein: The first metallization layer, the second metallization layer, the fifth metallization layer, and the sixth metallization layer are located at the same level.

8. A memory device comprising: A memory array comprising a plurality of memory cells arranged in a plurality of rows, the rows comprising a plurality of word lines, a first group of memory cells of the plurality of memory cells coupled to even word lines of the word lines, and a second group of memory cells coupled to odd word lines of the word lines; wherein the even word line is disposed in a first metallization layer of a plurality of metallization layers formed vertically above a substrate, wherein the even word line extends along a first lateral direction, and wherein the even word line includes a first longitudinal portion extending along the first lateral direction and a first stitching portion extending in a second lateral direction perpendicular to the first lateral direction to allow connection to a gate structure of a first transistor of the first group of memory cells; and wherein the odd word line is disposed in a second metallization layer among the plurality of metallization layers, wherein the odd word line extends along the first lateral direction, and wherein the odd word line includes a second longitudinal portion extending in the first lateral direction and a second stitching portion extending along the second lateral direction to allow connection to a gate structure of a second transistor of the second group of memory cells.

9. The memory device according to claim 8, wherein: The plurality of memory cells include a plurality of storage elements, and the plurality of storage elements are disposed in a third metallization layer among the plurality of metallization layers.

10. A method of forming a memory device, comprising: forming a first group of transistors and a second group of transistors along a major surface of a substrate, wherein the first group of transistors is aligned along a first lateral direction and the second group of transistors is aligned along the first lateral direction, and the first group of transistors and the second group of transistors are arranged relative to each other along a second lateral direction perpendicular to the first lateral direction; forming a first metal track in a first metallization layer of a plurality of metallization layers disposed vertically above the major surface, wherein the first metal track comprises a first longitudinal portion extending along the first lateral direction and a first stitching portion extending along the second lateral direction, the first stitching portion being coupled to the gate structures of the first set of transistors; forming a second metal track in a second metal layer of the plurality of metallization layers, wherein the second metal track comprises a second longitudinal portion extending along the first lateral direction and a second stitching portion extending along the second lateral direction, the second stitching portion being coupled to the gate structures of the second set of transistors; forming a first set of storage elements in a third metallization layer of the plurality of metallization layers, wherein the first set of storage elements are respectively coupled to the first set of transistors; and A second set of storage elements are formed in the third metallization layer, wherein the second set of storage elements are respectively coupled to the second set of transistors.

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