Semiconductor device structure and forming method thereof

Abstract

A semiconductor device structure includes: a first electrode overlying a substrate; a node dielectric contacting the first electrode and including a dielectric material having a dielectric constant greater than 30; and a second electrode contacting the node dielectric. A first of the first and second electrodes includes a first catalytic metal plate in direct contact with the node dielectric and having a first electronegativity not greater than an electronegativity of molybdenum. The embodiment of the invention also discloses a method for forming the semiconductor device structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor device structures and methods for forming the same. Background Art

[0002] The formation of high capacitance capacitors in semiconductor dies benefits from the formation of thin node dielectrics with high dielectric constants. However, dielectric materials that provide high dielectric constants exhibit degradation in crystal quality over a low thickness range. This is because as the thickness of the dielectric material decreases, the proportion of the dielectric material crystallizing into the desired symmetrical crystalline phase decreases. As a result, thin layers of dielectric material used as node dielectrics for capacitor structures tend to exhibit low effective dielectric constants due to poor crystallinity compared to highly crystalline bulk dielectric materials of the same material composition. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor device structure is provided, comprising: a first electrode, overlying a substrate; a node dielectric, contacting the first electrode and comprising a dielectric material having a dielectric constant greater than 30; and a second electrode, contacting the node dielectric, wherein a first of the first electrode and the second electrode comprises a first catalytic metal plate, the first catalytic metal plate is in direct contact with the node dielectric, and has a first electronegativity not greater than the electronegativity of molybdenum.

[0004] According to another aspect of an embodiment of the present application, a semiconductor device structure is provided, comprising: a first electrode, overlying a substrate; a node dielectric, contacting the first electrode and comprising a dielectric material, wherein a major volume fraction of the dielectric material is a symmetric crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure; and a second electrode, contacting the node dielectric, wherein a first of the first electrode and the second electrode comprises a first catalytic metal plate, the first catalytic metal plate is in direct contact with the node dielectric, and comprises a metal having a first electronegativity not greater than 1.50.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device structure is provided, the method comprising: forming a first metal interconnect structure in a first dielectric material layer on a substrate; forming a stack of a first electrode, a node dielectric, and a second electrode above the first dielectric material layer, wherein the first electrode is formed on a top surface of one of the first metal interconnect structures, the node dielectric comprises an amorphous phase dielectric material, and the first of the first electrode and the second electrode comprises a first catalytic metal plate, the first catalytic metal plate is in direct contact with the node dielectric, and has a first electronegativity not greater than that of molybdenum; and annealing the dielectric material so that the first catalytic metal plate induces catalytic crystallization of the amorphous phase dielectric material into a crystalline phase dielectric material having a dielectric constant greater than 30. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 1F 2 is a sequential vertical cross-sectional view of the structure of the first embodiment during the manufacturing process according to the embodiment of the present disclosure.

[0008] FIG. 2A to FIG. 2F are vertical cross-sectional views of various configurations of capacitor structures according to embodiments of the present disclosure.

[0009] FIG. 3A to FIG. 3E 2 is a sequential vertical cross-sectional view of the structure of the second embodiment during the manufacturing process according to the embodiment of the present disclosure.

[0010] Figure 4 Schematic diagram of a circuit according to the first embodiment of the present disclosure.

[0011] Figure 5 is a circuit diagram of a second embodiment of the present disclosure.

[0012] Figure 6 Examples of symmetric crystal structures of dielectric materials that may be used for node dielectrics of various embodiments of the present disclosure are shown.

[0013] Figure 7 is a line graph showing the dependence of the dielectric constant of the node dielectric as a function of thickness and crystallinity.

[0014] Figure 8 is a flow chart illustrating a sequence of processing steps for fabricating a resistive memory device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not meant to be limiting. The drawings are not drawn to scale. Elements with the same reference numerals represent the same elements and are assumed to have the same material composition and the same thickness range unless otherwise expressly indicated. Unless otherwise expressly stated, embodiments that repeat multiple instances of any of the described elements are expressly contemplated. Embodiments that omit non-essential elements are expressly contemplated, even if these embodiments are not expressly disclosed, but are known in the art.

[0016] In addition, for ease of description, spatial relative terms such as "below", "under", "lower", "above" and "upper" may be used herein to describe the relationship of an element or component to other elements or components shown in the figure. In addition to the directions shown in the drawings, spatial relative terms are intended to cover different directions of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can also be interpreted accordingly. Ordinals such as "first", "second", "third", etc. are merely adjectives and are not part of the unique name of any structural element. Therefore, elements identified with a specific ordinal number (such as "first") in the specification can be identified with a different ordinal number (such as second) or a different adjective (such as "additional", "another", etc.). For example, a limitation such as "the first of the first electrode and the second electrode includes a first catalytic metal plate" means that either of the two electrodes can include a catalytic metal plate, which is referred to as a "first catalytic metal plate" for identification purposes only.

[0017] Reducing the electrical oxide thickness (EOT) of the node dielectric may affect the device dimensions of a memory cell that uses a capacitor as a charge storage element. Many node dielectric materials that provide a high dielectric constant have a crystalline structure. Such node dielectric materials have a higher dielectric constant in the crystalline state than in the amorphous state. Simply reducing the physical thickness of such a node dielectric material results in a decrease in crystallinity, thereby reducing the dielectric constant of the node dielectric and reducing the capacitance of the capacitor. Typically, thin dielectric materials that can provide a high dielectric constant greater than 30 in the crystalline state (commonly referred to as ultra-high-k materials) are not easy to crystallize below a certain threshold thickness, which is referred to herein as the critical thickness. The critical thickness depends on the dielectric material, but is typically in the range of 3nm to 5nm.

[0018] According to one aspect of the present invention, at least one catalytic metal layer can be formed directly on a dielectric material that provides a higher dielectric constant in a crystalline phase relative to an amorphous phase. At least one catalytic metal layer includes a metal with a low electronegativity, which may be no greater than the electronegativity of molybdenum (2.16), and / or no greater than 1.80, and / or no greater than 1.50, and / or no greater than 1.20, and / or no greater than 1.00. The low electronegativity of the metal in at least one catalytic metal layer induces catalytic crystallization of the dielectric material at a lower temperature than the minimum annealing temperature required for crystallization of the dielectric material without the catalytic metal. Generally, the lower the electronegativity of the metal in at least one catalytic metal layer, the more effective the catalytic metal layer is in inducing the amorphous phase of the dielectric material to transform into a crystalline phase. Various embodiments of the present disclosure can be effectively used in back-end process (BEOL) metal-insulator-metal capacitors, which can be formed using back-end line processing steps and generally do not use any temperature above 400 degrees Celsius. Therefore, various embodiments of the present disclosure can be used to form capacitors that provide higher capacitance by engineering the crystalline state of node dielectric materials for memory devices. Various embodiments of the present disclosure are now described with reference to the following drawings.

[0019] Figures 1A to 1F 1 is a sequential vertical cross-sectional view of the structure of the first embodiment of the present disclosure during the manufacturing process. Figures 1A to 1F A single device region of a gain cell memory device is shown in FIG. 1 , but it will be appreciated that a two-dimensional array of gain cell memory devices may be formed by repeating the structure shown in the horizontal direction as a two-dimensional array.

[0020] Reference Figure 1A , the first embodiment structure includes a substrate 9, which can be a semiconductor substrate, such as a commercially available silicon wafer. A shallow trench isolation structure 720 including a dielectric material such as silicon oxide can be formed on the upper portion of the substrate 9. Suitable doped semiconductor wells, such as a p-type well and an n-type well, can be formed in each region that can be laterally surrounded by a portion of the shallow trench isolation structure 720. Field effect transistors can be formed on the top surface of the substrate 9. For example, each field effect transistor can include a source region 732, a drain region 738, a semiconductor channel 735 including a surface portion of the substrate 9 extending between the source region 732 and the drain region 738, and a gate structure 750. In some embodiments, a pair of source / drain regions 730 can be formed instead of the source region 732 and the drain region 738. The source / drain region 730 refers to a region that can be used as a source region or a drain region depending on the configuration of the electrical bias voltage applied to the field effect transistor.

[0021] Each gate structure 750 may include a gate dielectric 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source side metal semiconductor alloy region 742 may be formed on each source region 732, and a drain side metal semiconductor alloy region 748 may be formed on each drain region 738. The metal semiconductor alloy region formed on the source / drain region 730 is referred to herein as a source / drain metal semiconductor alloy region. The field effect transistor may be formed in any configuration known in the art. For example, the field effect transistor may include a planar field effect transistor, a fin field effect transistor, a full ring gate (GAA) field effect transistor, and / or any other type of field effect transistor.

[0022] The illustrated region of the first embodiment structure corresponds to the region of the gain unit memory device. In the first embodiment structure, each gain unit memory device may include a first field effect transistor (such as a write transistor WT) and a second field effect transistor (such as a read transistor RT) formed on the top surface of the substrate 9.

[0023] Reference Figure 1B , dielectric material layers and metal interconnect structures may be formed on field effect transistors (WT, RT). The dielectric material layers may include, for example, a contact-level dielectric material layer 601, a first metal line-level dielectric material layer 610, a second line and via-level dielectric material layer 620, a via-level dielectric material layer 63A, and a planar passivation dielectric layer 63B. The contact-level dielectric material layer 601, the first metal line-level dielectric material layer 610, the second line and via-level dielectric material layer 620, and the via-level dielectric layer 63A may be collectively referred to as a first dielectric material layer (601, 610, 620, 63A). Each of the contact-level dielectric material layer 601, the first metal line-level dielectric material layer 610, the second line and via-level dielectric material layer 620, and the via-level dielectric layer 63A may include an interlayer dielectric (ILD) material, such as undoped silicate glass, doped silicate glass, and / or porous or non-porous organic silicate glass. The planar passivation dielectric layer 63B includes a dielectric diffusion barrier material, such as silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or a combination thereof. The thickness of the planar passivation dielectric layer 63B can be selected to be sufficient to prevent the diffusion of the metal used to catalyze the metal layer. For example, the thickness of the planar passivation dielectric layer 63B can be in the range of 5 nm to 30 nm, but smaller or larger thicknesses can also be used.

[0024] The metal interconnect structure is formed in the first dielectric material layer (601, 610, 620, 63A) and the planar passivation dielectric layer 63B. The metal interconnect structure is referred to herein as the first metal interconnect structure (612, 618, 622, 628, 22). The first metal interconnect structure (612, 618, 622, 628, 22) may include a device contact via structure 612 formed in the contact-level dielectric material layer 601 and contacting a corresponding component of the semiconductor device on the substrate 9, a first metal line structure 618 formed in the first metal line-level dielectric material layer 610, a first metal via structure 622 formed in the lower portion of the second line and via-level dielectric material layer 620, a second metal line structure 628 formed in the upper portion of the second line and via-level dielectric material layer 620, and a bottom electrode contact via structure 22 formed through the planar passivation dielectric layer 63B and the via-level dielectric layer 63A. Each first metal interconnect structure (612, 618, 622, 628, 22) may include at least one conductive material, which may be a combination of a metal liner layer (such as a metal nitride or a metal carbide) and a metal filler material. Each metal liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof.

[0025] According to one aspect of the present disclosure, a subset of the first metal interconnect structures (612, 618, 622, 628, 22) within the region of the gain unit memory device electrically connects the source / drain region 730 of the first field effect transistor (such as the write transistor WT), the gate electrode 754 and the first electrode (32 and / or 33) of the second field effect transistor (such as the read transistor RT), and the bottom electrode contact via structure 22 (which is subsequently electrically connected to the first electrode of the capacitor). In one embodiment, the first metal interconnect structure (612, 618, 622, 628, 22) may include a connecting metal line CML that extends laterally between the first field effect transistor (such as the write transistor WT) and the second field effect transistor (such as the read transistor RT). The connecting metal line CML contacts the top surface of the first device contact via structure 612 that is electrically connected to and covers the first source / drain region 730 of the first field effect transistor, and contacts the top surface of the second device contact via structure 612 that is electrically connected to and covers the gate electrode 754 of the second field effect transistor.

[0026] In one embodiment, the first metal interconnect structure (612, 618, 622, 628, 22) may include a write word line WWL, which is a metal line used as a word line for the write transistor WT. In one embodiment, the write word line WWL may include a subset of the second metal line structure 628. In one embodiment, the first metal interconnect structure (612, 618, 622, 628, 22) may include a read word line RWL, which is a metal line used as a word line for the read transistor RT. In one embodiment, the read word line RWL may include a subset of the second metal line structure 628. Each read word line RWL may be connected to the first metal interconnect structure (612, 618, 622, 628, 22) by a conductive path (in a manner of transmitting the first word line RWL to the first metal interconnect structure) embodied as a corresponding subset of the first metal interconnect structure (612, 618, 622, 628, 22) (e.g., a device contact via structure 612, a first metal line structure 618, and a corresponding subset of the first metal via structure 622) Figure 1B The source region 732 (represented as a dotted line in FIG. 1 ) is electrically connected to the source region 732 within the corresponding row of the read transistor RT.

[0027] Reference Figure 1C , the material layer stack 30L can be deposited on the top surface of the planar passivation dielectric layer 63B. The material layer stack 30L can include from bottom to top: a bottom non-catalytic material layer 32L including a non-catalytic conductive material, a bottom catalytic metal layer 33L including a catalytic metal, a node dielectric material layer 35L, a top catalytic metal layer 37L including another catalytic metal, and a top non-catalytic material layer 38L including another non-catalytic conductive material. As used herein, a catalytic metal refers to a metal whose electronegativity is not greater than the electronegativity of platinum (i.e., 2.16). If the stable phase of the dielectric material includes a crystalline state, the catalytic metal in contact with the amorphous dielectric material can act as a catalyst during the phase transition from the amorphous state to the crystalline state. Generally, the lower the electronegativity of the catalytic metal, the more effective the catalytic metal is in inducing a phase transition.

[0028] Non-catalytic conductive materials refer to conductive materials that do not induce catalytic crystallization of dielectric metal oxides. Non-catalytic conductive materials include metals with an electronegativity greater than that of platinum, metal compounds that are chemically stable and do not include phase changes in dielectric materials, and conductive metal oxides. Exemplary metal compounds that are non-catalytic conductive materials include tungsten nitride, titanium nitride, tantalum nitride, and molybdenum nitride. Exemplary conductive metal oxides that can be used as non-catalytic conductive materials include, for example, indium tin oxide, fluorine-doped tin oxide, zinc oxide, tungsten oxide (WO3), and the like.

[0029] In one embodiment, the non-catalytic conductive material of the bottom non-catalytic material layer 32L and the top non-catalytic material layer 38L may include at least one non-radioactive metal, each of which has an electronegativity greater than that of platinum (i.e., 2.16). For example, at least one of the non-catalytic conductive materials of the bottom non-catalytic material layer 32L and the top non-catalytic material layer 38L may be independently selected from the group of elemental metals consisting of gold (Au) having an electronegativity of 2.54, tungsten (W) having an electronegativity of 2.36, platinum (Pt) having an electronegativity of 2.28, iridium (Ir) having an electronegativity of 2.20, and osmium (Os) having an electronegativity of 2.20. Alternatively or additionally, at least one of the non-catalytic conductive materials of the bottom non-catalytic material layer 32L and the top non-catalyst material layer 38L may be independently selected from conductive metal nitride materials, including tungsten nitride, titanium nitride, tantalum nitride, and molybdenum nitride.

[0030] The thickness of each of the bottom non-catalytic material layer 32L and the top non-catalytic material layer 38L can be in the range of 5 nm to 30 nm, such as 10 nm to 25 nm, although smaller or larger thicknesses can also be used. Each of the bottom non-catalytic material layer 32L and the top non-catalytic material layer 38L can be deposited by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0031] In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include non-radioactive metal materials with respective electronegativity no greater than the electronegativity of platinum. In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or may consist essentially of the corresponding elemental metal having an electronegativity no greater than that of platinum. In one embodiment, each catalytic metal of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of an alkaline earth metal, an alkali metal, a post-transition metal, a transition metal, or a metalloid, and may have an electronegativity no greater than that of platinum.

[0032] Alkali metals with an electronegativity no greater than that of platinum include lithium (Li) with an electronegativity of 0.98, sodium (Na) with an electronegativity of 0.93, potassium (K) with an electronegativity of 0.82, rubidium (Rb) with an electronegativity of 0.82, and cesium (Cs) with an electronegativity of 0.79. Alkaline earth metals with an electronegativity no greater than that of platinum include beryllium (Be) with an electronegativity of 1.57, magnesium (Mg) with an electronegativity of 1.31, calcium (Ca) with an electronegativity of 1.00, strontium (Sr) with an electronegativity of 0.95, and barium (Ba) with an electronegativity of 0.89. Late transition metals with an electronegativity no greater than that of platinum include aluminum (Al) with an electronegativity of 1.61, gallium (Ga) with an electronegativity of 1.81, indium (In) with an electronegativity of 1.78, and thallium (Tl) with an electronegativity of 1.83. Transition metals having an electronegativity no greater than that of platinum include lanthanum (La) with an electronegativity of 1.10, cerium (Ce) with an electronegativity of 1.12, praseodymium (Pr) with an electronegativity of 1.13, neodymium (Nd) with an electronegativity of 1.14, samarium (Sm) with an electronegativity of 1.17, europium (Eu) with an electronegativity of 1.15, gadolinium (Gd) with an electronegativity of 1.20, terbium (Tb) with an electronegativity of 1.20, dysprosium (Dy) with an electronegativity of 1.22, holmium (Ho) with an electronegativity of 1.23, erbium (Er) with an electronegativity of 1.24, thulium (Tm) with an electronegativity of 1.25, ytterbium (Yb) with an electronegativity of 1.10, and lutetium (Lu) with an electronegativity of 1.23. Metalloids having an electronegativity no greater than that of molybdenum include germanium (Ge) having an electronegativity of 1.81, arsenic (As) having an electronegativity of 2.05, antimony (Sb) having an electronegativity of 2.06, and tellurium (Te) having an electronegativity of 2.1.

[0033] In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include non-radioactive metal materials having respective electronegativity no greater than 1.80. In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of elemental metals having respective electronegativity no greater than 1.80. In one embodiment, each catalytic metal of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of alkaline earth metals, alkali metals, post-transition metals, or transition metals, and may have an electronegativity no greater than 1.80.

[0034] Alkali metals with an electronegativity of no more than 1.80 include lithium (Li) with an electronegativity of 0.98, sodium (Na) with an electronegativity of 0.93, potassium (K) with an electronegativity of 0.82, rubidium (Rb) with an electronegativity of 0.82, and cesium (Cs) with an electronegativity of 0.79. Alkaline earth metals with an electronegativity of no more than 1.80 include beryllium (Be) with an electronegativity of 1.57, magnesium (Mg) with an electronegativity of 1.31, calcium (Ca) with an electronegativity of 1.00, strontium (Sr) with an electronegativity of 0.95, and barium (Ba) with an electronegativity of 0.89. Late transition metals with an electronegativity of no more than 1.80 include aluminum (Al) with an electronegativity of 1.61 and indium (In) with an electronegativity of 1.78. Transition metals with an electronegativity of no more than 1.80 include lanthanum (La) with an electronegativity of 1.10, cerium (Ce) with an electronegativity of 1.12, praseodymium (Pr) with an electronegativity of 1.13, neodymium (Nd) with an electronegativity of 1.14, samarium (Sm) with an electronegativity of 1.17, europium (Eu) with an electronegativity of 1.15, gadolinium (Gd) with an electronegativity of 1.20, terbium (Tb) with an electronegativity of 1.20, dysprosium (Dy) with an electronegativity of 1.22, holmium (Ho) with an electronegativity of 1.23, erbium (Er) with an electronegativity of 1.24, thulium (Tm) with an electronegativity of 1.25, ytterbium (Yb) with an electronegativity of 1.10, and lumen (Lu) with an electronegativity of 1.23.

[0035] In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include non-radioactive metal materials having respective electronegativity no greater than 1.50. In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of elemental metals having respective electronegativity no greater than 1.50. In one embodiment, each catalytic metal of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of alkaline earth metals, alkali metals, or transition metals, and may have an electronegativity no greater than 1.50.

[0036] Alkali metals with an electronegativity of no more than 1.50 include lithium (Li) with an electronegativity of 0.98, sodium (Na) with an electronegativity of 0.93, potassium (K) with an electronegativity of 0.82, rubidium (Rb) with an electronegativity of 0.82, and cesium (Cs) with an electronegativity of 0.79. Alkaline earth metals with an electronegativity of no more than 1.50 include magnesium (Mg) with an electronegativity of 1.31, calcium (Ca) with an electronegativity of 1.00, strontium (Sr) with an electronegativity of 0.95, and barium (Ba) with an electronegativity of 0.89. Transition metals with an electronegativity of no more than 1.50 include lanthanum (La) with an electronegativity of 1.10, cerium (Ce) with an electronegativity of 1.12, praseodymium (Pr) with an electronegativity of 1.13, neodymium (Nd) with an electronegativity of 1.14, samarium (Sm) with an electronegativity of 1.17, europium (Eu) with an electronegativity of 1.15, gadolinium (Gd) with an electronegativity of 1.20, terbium (Tb) with an electronegativity of 1.20, dysprosium (Dy) with an electronegativity of 1.22, holmium (Ho) with an electronegativity of 1.23, erbium (Er) with an electronegativity of 1.24, thulium (Tm) with an electronegativity of 1.25, ytterbium (Yb) with an electronegativity of 1.10, and lumen (Lu) with an electronegativity of 1.23.

[0037] In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include non-radioactive metal materials having respective electronegativity no greater than 1.20. In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of elemental metals having respective electronegativity no greater than 1.20. In one embodiment, each catalytic metal of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of alkaline earth metals, alkali metals, or transition metals, and may have an electronegativity no greater than 1.20.

[0038] Alkali metals with an electronegativity of no more than 1.20 include lithium (Li) with an electronegativity of 0.98, sodium (Na) with an electronegativity of 0.93, potassium (K) with an electronegativity of 0.82, rubidium (Rb) with an electronegativity of 0.82, and cesium (Cs) with an electronegativity of 0.79. Alkaline earth metals with an electronegativity of no more than 1.20 include calcium (Ca) with an electronegativity of 1.00, strontium (Sr) with an electronegativity of 0.95, and barium (Ba) with an electronegativity of 0.89. Transition metals with an electronegativity of no more than 1.20 include lanthanum (La) with an electronegativity of 1.10, cerium (Ce) with an electronegativity of 1.12, praseodymium (Pr) with an electronegativity of 1.13, neodymium (Nd) with an electronegativity of 1.14, samarium (Sm) with an electronegativity of 1.17, europium (Eu) with an electronegativity of 1.15, and ytterbium (Yb) with an electronegativity of 1.10.

[0039] In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include non-radioactive metal materials having respective electronegativity no greater than 1.00. In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of elemental metals having respective electronegativity no greater than 1.00. In one embodiment, each catalytic metal of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of an alkaline earth metal or an alkali metal and may have an electronegativity no greater than 1.00.

[0040] Alkali metals with an electronegativity of no more than 1.00 include lithium (Li) with an electronegativity of 0.98, sodium (Na) with an electronegativity of 0.93, potassium (K) with an electronegativity of 0.82, rubidium (Rb) with an electronegativity of 0.82, and cesium (Cs) with an electronegativity of 0.79. Alkaline earth metals with an electronegativity of no more than 1.00 include strontium (Sr) with an electronegativity of 0.95 and barium (Ba) with an electronegativity of 0.89.

[0041] In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include non-radioactive metal materials having respective electronegativity no greater than 0.90. In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of elemental metals having respective electronegativity no greater than 0.90. In one embodiment, each catalytic metal of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of an alkaline earth metal or an alkali metal and may have an electronegativity no greater than 0.90.

[0042] Alkali metals having an electronegativity of not more than 0.90 include potassium (K) having an electronegativity of 0.82, rubidium (Rb) having an electronegativity of 0.82, and cesium (Cs) having an electronegativity of 0.79. Alkaline earth metals having an electronegativity of not more than 1.00 include barium (Ba) having an electronegativity of 0.89.

[0043] In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include non-radioactive metal materials having respective electronegativity no greater than 0.80. In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of elemental metals having respective electronegativity no greater than 0.80. In one embodiment, each catalytic metal of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may include and / or consist essentially of alkali metals having electronegativity no greater than 0.80. The alkali metal having electronegativity no greater than 0.80 is cesium (Cs) having an electronegativity of 0.79. The non-radioactive isotope of cesium is cesium 133. In one embodiment, the catalytic metals of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may consist essentially of cesium 133.

[0044] Each of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may have a thickness in the range of 2 nm to 30 nm, such as 4 nm to 15 nm, although lesser or greater thicknesses may also be used. Each of the bottom catalytic metal layer 33L and the top catalytic metal layer 37L may be deposited by physical vapor deposition, chemical vapor deposition, or atomic layer deposition.

[0045] The node dielectric material layer 35L includes a dielectric material having a crystalline phase with a dielectric constant greater than 30, and preferably has a dielectric constant greater than 35. Exemplary dielectric materials that can be used for the node dielectric material layer 35L of various embodiments of the present disclosure include perovskite oxide materials, hafnium-based oxides, zirconium-based oxides, and titanium-based oxides. Perovskite oxide materials include barium titanate (BaTiO3), strontium titanate (SrTiO3), lead zirconate titanate (PZT), barium strontium titanate (BST), lead titanate (PbTiO3), etc. The perovskite oxide material can have a dielectric constant in the range of 30 to 1000 in the crystalline phase. Hafnium-based oxides include hafnium dioxide (HfO2), hafnium oxynitride, and hafnium silicate (HfSiO4), and can have a dielectric constant in the range of 30 to 40 in the crystalline state. Zirconium-based oxides include zirconium dioxide (ZrO2), zirconium oxynitride, and zirconium silicate (ZrSiO4), and in a crystalline state may have a dielectric constant in the range of 30 to 35. Titanium-based oxides include titanium dioxide (TiO2) or titanium oxynitride, and may have a dielectric constant in the range of 80 to 150. In general, these materials provide higher dielectric constants in the crystalline phase than in the amorphous phase.

[0046] The thickness of the node dielectric material layer 35L can be in the range of 2nm to 10nm, for example, 3nm to 8nm. It should be noted that exceeding the upper limit of the thickness range of the node dielectric material layer 35L may hinder the achievement of the target capacitance value of the capacitor, while the thickness variation of the top and bottom electrodes does not significantly affect the capacitance. Node dielectric material layers 35L of smaller and larger thicknesses may also be used depending on specific application requirements. The node dielectric material layer 35L can be deposited in an amorphous phase or a partially crystalline phase using physical vapor deposition. The volume fraction of the amorphous phase dielectric material in the node dielectric material layer 35L can be in the range of 20% to 100%, and / or in the range of 50% to 95%, and / or in the range of 70% to 90%.

[0047] Reference Figure 1D , a photoresist layer 39 may be applied over the top non-catalytic material layer 38L and may be photolithographically patterned into a two-dimensional array of photoresist material portions covering corresponding areas on corresponding bottom electrode contact via structures 22. Typically, in a plan view, the area of ​​each photoresist material portion within the two-dimensional array of photoresist material portions may be in the range of 40% to 90% of the area of ​​each gain unit memory device. For example, a material layer stack 30L including a bottom non-catalytic material layer 32L, a bottom catalytic metal layer 33L, a node dielectric material layer 35L, a top catalytic metal layer 37L, and a top non-catalyst material layer 38L may be patterned into a two-dimensional array of capacitor structures 30 by performing an anisotropic etching process using the patterned photoresist material portions as an etching mask to etch unmasked portions of the layer stack.

[0048] Each capacitor structure 30 includes a first electrode (32, 33) also referred to as a bottom electrode, a node dielectric 35 as a patterned portion of a node dielectric material layer 35L, and a second electrode (37, 38) also referred to as a top electrode. The first electrode (32, 33) includes a bottom non-catalytic material plate 32 and a bottom catalytic metal plate 33. The bottom non-catalytic material plate 32 includes a patterned portion of the bottom non-catalytic material layer 32L. The bottom catalytic metal plate 33 includes a patterned portion of the bottom catalytic metal layer 33L. The node dielectric 35 includes a patterned portion of the node dielectric material layer 35L. The second electrode (37, 38) includes a top catalytic metal plate 37 and a top non-catalytic material plate 38. The top catalytic metal plate 37 is a patterned portion of the top catalytic metal layer 37L. The top non-catalytic material plate 38 is a patterned portion of the top non-catalytic material layer 38L.

[0049] Typically, a stack of first electrodes (32, 33), a node dielectric 35, and a second electrode (37, 38) can be formed above a first dielectric material layer (601, 610, 620, 63A). The first electrode (32, 33) is formed on a top surface of one of the first metal interconnect structures (612, 618, 622, 628, 22). The node dielectric 35 includes an amorphous phase dielectric material, and may also include a partially crystalline phase dielectric material having the same material composition as the amorphous phase dielectric material. The volume fraction of the amorphous phase dielectric material in the node dielectric 35 may be in the range of 20% to 100%, such as 50% to 100%, and / or 60% to 95%, but smaller or larger percentages may also be used. At least one catalytic metal plate, such as a bottom catalytic metal plate 33 and a top catalytic metal plate 37, may be in direct contact with the node dielectric 35. Each catalytic metal plate (33, 37) includes and / or is substantially composed of a metal having an electronegativity no greater than that of molybdenum. The photoresist layer 39 may then be removed, for example, by ashing.

[0050] Reference Figure 1E , a conformal passivation dielectric layer 63C may be deposited over the capacitor structure 30 and the planar passivation dielectric layer 63B. The conformal passivation dielectric layer 63C includes a dielectric diffusion barrier material, such as silicon nitride, silicon carbonitride, silicon oxycarbide, silicon oxynitride, or a combination thereof. The thickness of the conformal passivation dielectric layer 63C may be selected to be sufficient to prevent diffusion of the catalytic metal in the bottom catalytic metal plate 33 and the top catalytic metal plate 37. For example, the thickness of the conformal passivation dielectric layer 63C may be in the range of 5 nm to 30 nm, although lesser or greater thicknesses may also be used.

[0051] The conformal passivation dielectric layer 63C may contact the top surface of each second electrode (37, 38), and may contact the first electrode (32, 33), the node dielectric 35, and each sidewall of the second electrode (37, 38). The planar passivation dielectric layer 63B may contact the bottom surface of each first electrode (32, 33). The two-dimensional array of capacitor structures 30 may be encapsulated by the conformal passivation dielectric layer 63C, the planar passivation dielectric layer 63B, and the two-dimensional array of bottom electrode contact via structures 22.

[0052] Reference Figure 1F, a capacitor-level dielectric layer 63D, a fourth line and via-level dielectric material layer 640, a fifth line and via-level dielectric material layer 650, a sixth line and via-level dielectric material layer 660, and an additional dielectric material layer (not shown) may be formed on the conformal passivation dielectric layer 63C. The dielectric material layer group formed above the conformal passivation dielectric layer 63C is referred to herein as a second dielectric material layer (63D, 640, 650, 660). All dielectric material groups between the second line and via-level dielectric material layer 620 and the fourth line and via-level dielectric material layer 640 (excluding the node dielectric 35) constitute a third line and via-level dielectric material layer 630. Therefore, the third line and via-level dielectric material layer 630 may include a via-level dielectric layer 63A, a planar passivation dielectric layer 63B, a conformal passivation dielectric layer 63C, and a capacitor-level dielectric layer 63D.

[0053] A second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668) is formed in the second dielectric material layer (63D, 640, 650, 660). The second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668) may include a top electrode contact via structure 28 that contacts the top surface of the corresponding top electrode (37, 38) and passes through the capacitor-level dielectric layer 63D and the conformal passivation dielectric layer 63C, a second metal via structure 632 formed in a lower portion of the third line and via level dielectric material layer 630, a third metal line structure 638 formed in an upper portion of the third line and via level dielectric material layer 630, and a fourth line and via level dielectric material layer 640. 0, a third metal via structure 642 formed at the bottom of the fourth line and the via-level dielectric material layer 640, a fourth metal line structure 648 formed on the top of the fourth line and the via-level dielectric material layer 640, a fourth metal via structure (not shown) formed at the bottom of the fifth line and the via-level dielectric material layer 650, a fifth metal line structure 658 formed on the top of the fifth line and the via-level dielectric material layer 650, a fifth metal via structure 662 formed at the bottom of the sixth line and the via-level dielectric material layer 660, a sixth metal line structure 668 formed on the top of the sixth line and the via-level dielectric material layer 660, etc.

[0054] The second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668) may include a write bit line WBL and a read bit line RBL. Each write bit line WB may be electrically connected to the second source / drain region 730 of the write transistor WT column through a corresponding subset of the second metal interconnect structure (28, 633, 638, 642648, 658, 664, 668) and a corresponding subset of the first metal interconnect structure (612, 618, 622, 628, 22). Each read bit line RBL may be electrically connected to the drain region 738 of the read transistor RT column through a corresponding subset of the second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668) and a corresponding subset of the first metal interconnect structure (612, 618, 622, 628, 22). A set of second metal interconnect structures ( 28 , 632 , 638 , 642 , 648 , 658 , 662 , 668 ) are schematically represented as dashed lines, which serve as components of a conductive path between the read bit line RBL and the drain region 738 of the read transistor RT and are located between the third metal line structure 638 and the fifth metal line structure 658 .

[0055] In one embodiment, each top electrode (37, 38) can be electrically connected to electrical ground through a corresponding subset of second metal interconnect structures (28, 632, 638, 642, 648, 658, 662, 668), which includes a corresponding top electrode contact via structure 28. A subset of the second metal interconnect structures (28, 632, 638, 642, 648, 658, 662, 668) includes an electrically grounded interconnect structure EG.

[0056] During the formation of the second dielectric material layer (63D, 640, 650, 660) and the second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668), the node dielectric 35 in the capacitor structure 30 is subjected to thermal cycling. Processing steps, generally referred to as back-end of line (BEOL) processing steps, may be used to form the second dielectric material layer (63D, 640, 650, 660) and the second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668). The maximum temperature of the BEOL processing steps is generally no greater than 400 degrees Celsius. Therefore, the annealing effect on the crystallinity of the dielectric material in the node dielectric 35 depends on the effectiveness of the catalytic metal in the catalytic metal plate (33, 37). According to one aspect of the present disclosure, the low electronegativity of the catalytic metal in the catalytic metal plates (33, 37) provides a sufficient catalytic effect for the transformation of the amorphous phase dielectric material into the crystalline phase dielectric material in the node dielectric 35. The phase transformation of the dielectric material in the node dielectric 35 from the amorphous phase to the crystalline phase increases the dielectric constant of the node dielectric 35, thereby increasing the capacitance of each capacitor structure 30.

[0057] Typically, the dielectric material of the node dielectric 35 can be annealed so that the catalytic metal plate (33, 37) induces the amorphous phase dielectric material in the node dielectric 35 to catalytically crystallize into a crystalline phase dielectric material having a dielectric constant greater than 30, preferably greater than 35. In one embodiment, the annealing of the dielectric material of the node dielectric 35 can be achieved by a BEOL processing step for forming the second dielectric material layer (63D, 640, 650, 660) and the second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668).

[0058] In one embodiment, the crystal structure in each node dielectric 35 may include a symmetrical crystal structure that provides an enhanced dielectric constant relative to an amorphous material having the same material composition. In one embodiment, the majority volume fraction of the dielectric material in each node dielectric 35 is a symmetrical crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure. As used herein, "major volume fraction" refers to a volume fraction, i.e., a fraction measured by volume, that is at least 50%. In one embodiment, the majority volume fraction may include at least 80%, and / or at least 90%, and / or at least 95% of the entire volume of the node dielectric 35.

[0059] FIG. 2A to FIG. 2F are vertical cross-sectional views of various configurations of capacitor structures 30 according to embodiments of the present disclosure.

[0060] Reference Figure 2A , shows a first configuration of the capacitor structure 30, which can be compared with reference Figure 1C-1F The configuration of the capacitor structure described is the same.

[0061] Reference Figure 2B , shows a second configuration of the capacitor structure 30, which can be obtained by omitting the bottom catalytic metal plate 33 from the reference Figure 1C-1F and Figure 2A The first configuration of the capacitor structure 20 is derived from the description. In this embodiment, the first electrode or bottom electrode can be composed of the bottom non-catalytic material plate 32. The catalytic crystallization of the amorphous phase dielectric material in the node dielectric 35 to the crystalline phase can be achieved by the top catalytic metal plate 37.

[0062] Reference Figure 2C , shows a third configuration of the capacitor structure 30, which can be obtained by omitting the top catalytic metal plate 37 from the reference Figure 1C-1F and Figure 2A The first configuration of the capacitor structure 20 is derived from the description. In this embodiment, the second electrode or top electrode can be composed of a top non-catalytic material plate 38. The catalytic crystallization of the amorphous phase dielectric material in the node dielectric 35 to a crystalline phase can be achieved by a bottom catalytic metal plate 33.

[0063] refer to Figure 2D , shows a fourth configuration of the capacitor structure 30, which can be modified from reference 1 by omitting the bottom non-catalytic material plate 32 and the top non-catalytic material plate 38. Figure 1C-1F and Figure 2A The first configuration of the capacitor structure described is derived. In this embodiment, the first electrode or bottom electrode can be composed of a bottom catalytic metal plate 33; the second electrode or top electrode can be composed of a top catalytic metal plate 37. The catalytic crystallization of the amorphous phase dielectric material in the node dielectric 35 into a crystalline phase can be achieved by the bottom catalytic metal plate 33 and the top catalytic metal plate 37. The thickness of the bottom catalytic metal plate 33 and the thickness of the top catalytic metal plate 37 can be increased so that the thickness of the bottom electrode (composed of the bottom catalytic metal plate 33) is in the range of 15nm to 40nm, and the thickness of the top electrode (composed of the top catalytic metal plate 37) is in the range of 15nm to 40nm.

[0064] Reference Figure 2E , shows a fifth configuration of the capacitor structure 30, which can be replaced by replacing the bottom catalytic metal plate 33 with a bottom non-catalytic material plate 32. Figure 2D A fourth configuration of the capacitor structure 20 is shown. In this embodiment, the first electrode or bottom electrode is composed of a bottom non-catalytic material plate 32. Catalytic crystallization of the amorphous dielectric material in the node dielectric 35 to a crystalline phase can be achieved by a top catalytic metal plate 37.

[0065] Reference Figure 2F, shows a sixth configuration of the capacitor structure 30, which can be replaced by replacing the top catalytic metal plate 37 with a top non-catalytic material plate 38. Figure 2D A fourth configuration of the capacitor structure 30 is shown. In this embodiment, the second electrode or top electrode is composed of a top non-catalytic material plate 38. Catalytic crystallization of the amorphous dielectric material in the node dielectric 35 to a crystalline phase can be achieved by a bottom catalytic metal plate 33.

[0066] for FIG. 2A to FIG. 2F In each of the configurations shown, the dielectric material of the node dielectric 35 can be annealed so that the first catalytic metal plate (33 or 37) and the second catalytic metal plate (37 or 33) (if present) induce catalytic crystallization of the amorphous phase dielectric material into a crystalline phase dielectric material having a dielectric constant greater than 30.

[0067] Common Reference FIG. 2A to FIG. 2F , the capacitor structure 30 of various embodiments of the present disclosure may include: a first electrode (32 and / or 33) covering a substrate 9; a node dielectric 35, which contacts the first electrode (32 and / or 33) and includes a dielectric material having a dielectric constant greater than 30; and a second electrode (37 and / or 38) in contact with the node dielectric 35. The first of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a first catalytic metal plate (33 or 37) that is in direct contact with the node dielectric 35 and has a first electronegativity that is no greater than the electronegativity of molybdenum.

[0068] In one embodiment, a majority volume fraction of the dielectric material is a symmetric crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure. In one embodiment, the majority volume fraction comprises at least 80% of the entire volume of the node dielectric 35 .

[0069] In one embodiment, the second of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a second catalytic metal plate (37 or 33) and has a second electronegativity not greater than the electronegativity of platinum. In one embodiment, the second catalytic metal plate (37 or 33) is in direct contact with the node dielectric 35. In one embodiment, the first of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) also includes a first non-catalytic material plate (32 or 38) having a third electronegativity greater than the electronegativity of platinum and is separated from the node dielectric 35 by the first catalytic metal plate (33 or 37). In one embodiment, the second of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a second non-catalytic material plate (38 or 32) having a fourth electronegativity greater than the electronegativity of platinum and is separated from the node dielectric 35 by the second catalytic metal plate (37 or 33).

[0070] In one embodiment, the capacitor structure 30 of various embodiments of the present disclosure may include: a first electrode (32 and / or 33) covering a substrate 9; a node dielectric 35 contacting the first electrode (32 and / or 33) and including a dielectric material, wherein the main volume fraction of the dielectric material is a symmetrical crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure; and a second electrode (37 and / or 38) contacting the node dielectric 35. The first of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a first catalytic metal plate (33 or 37) that is in direct contact with the node dielectric 35 and includes a metal having a first electronegativity of not more than 1.50. In one embodiment, the first catalytic metal plate (33 or 37) includes an alkali metal or an alkaline earth metal. In one embodiment, the second of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a second catalytic metal plate (37 or 33) and has a second electronegativity of not more than 1.50.

[0071] In one embodiment, the planar passivation dielectric layer 63B contacts the bottom surface of the first electrode (32 and / or 33); the conformal passivation dielectric layer 63C contacts the top surface of the second electrode (37 and / or 38), and contacts the first electrode (32 and / or 33), the node dielectric 35, and the sidewalls of the second electrode. In one embodiment, a second metal interconnect structure (28, EG) may be provided that electrically connects the second electrode (37 and / or 38) and electrical ground.

[0072] FIG. 3A to FIG. 3E 2 is a sequential vertical cross-sectional view of the structure of the second embodiment of the present disclosure during the manufacturing process. FIG. 3A to FIG. 3E A single device region of a gain unit memory device is shown in FIG. 1 , but it can be understood that a two-dimensional array of gain unit memory devices can be formed by repeating the structure shown in the horizontal direction as a two-dimensional array.

[0073] Reference Figure 3A , by forming a series connection of the first read transistor RT1 and the second read transistor RT2 instead Figure 1A The read transistor RT shown in FIG. Figure 1A The second embodiment structure is derived from the first embodiment structure shown in FIG. In this embodiment, the first read transistor RT1 and the second read transistor RT2 may share a source / drain region 730, referred to herein as a common source / drain region. The first read transistor RT1 may include a drain region 738, and the second read transistor RT2 may include a source region 732.

[0074] refer to Figure 3B ,refer to Figure 1BThe described processing steps may be performed by appropriately modifying the pattern of the first metal interconnect structure (612, 618, 622, 628, 22). In one embodiment, the first metal interconnect structure (612, 618, 622, 628, 22) may include a connecting metal line CML extending laterally between a first field effect transistor (such as a write transistor WT) and a second field effect transistor (such as a second read transistor RT2). The connecting metal line CML contacts the top surface of a (first) device contact via structure 612 electrically connected to and covering a first source / drain region 730 of the first field effect transistor, and contacts the top surface of a (second) device contact via structure 612 electrically connected to and covering a gate electrode 754 of the second field effect transistor. In one embodiment, the source region 732 of the second field effect transistor (e.g., the second read transistor RT2) may be electrically grounded.

[0075] In one embodiment, the first metal interconnect structure (612, 618, 622, 628, 22) may include a write word line WWL, which is a metal line used as a word line of the write transistor WT. In one embodiment, the write word line WWL may include a subset of the second metal line structure 628. In one embodiment, the first metal interconnect structure (612, 618, 622, 628, 22) may include a read word line RWL, which is a metal line used as a word line of the first read transistor RT1. In one embodiment, the read word line RWL may include a subset of the second metal line structure 628. Each read word line RWL may be electrically connected to the gate electrode 754 of the first read transistor RT1 in the corresponding row.

[0076] Reference Figure 3C , you can execute the reference Figure 1C and Figure 1D The processing steps described above are used to form a capacitor structure 30 in each region of the gain unit memory device. Optionally, one or two layers within the capacitor structure 30 may be omitted to provide a reference Figure 2B-2F Typically, the capacitor structure 30 can be configured as described above. Figure 2A-2F Any configuration described is formed.

[0077] Reference Figure 3D , you can execute the reference Figure 1E The processing steps are described to form a conformal passivation dielectric layer 63C.

[0078] Reference Figure 3E , the wiring pattern of the second metal interconnect structure (28, 632, 638, 642, 648, 658, 662, 668) can be optionally modified to perform reference Figure 1F Describe the processing steps.

[0079] Reference Figure 4 , showing Figure 1F The schematic circuit diagram of the first embodiment structure is shown in FIG. The signal node SN corresponds to the first source / drain region 730 of the first field effect transistor (which is the write transistor WT), the gate electrode 754 of the second field effect transistor (which is the read transistor RT), and the bottom electrode (32 and / or 33) of the capacitor structure 30 through the connection metal line CML (such as Figure 1B-Figure 1F Nodes electrically connected to each other (as shown). The write bit line WBL is used to provide a bias signal representing the data bit to be encoded in the signal node SN during a write operation. The write word line WWL is used to control the switch of the write transistor WT so that the write operation can be performed only when the write transistor is turned on. Except during the read operation, the read word line RWL and the read bit line RBL can be electrically biased to keep the read transistor RT off. During the read operation, the read bit line RBL can be precharged to a read bit line bias voltage (also called a precharge bias voltage), and the read word line RWL can be electrically biased during the read operation so that if the data bit stored in the signal node SN is "1", the read transistor RT is turned on, but if the data bit stored in the information node SN is "0", it is not turned on. The stored data bit at the signal node SN can be read by determining whether the measured voltage at the read bit line RBL is higher or lower than a predetermined threshold voltage after the read transistor RT is turned on. After the read operation, the measured voltage at the read bit line RBL is lower than the predetermined threshold voltage due to the current through the read transistor RT, and the measured data bit is "1". In embodiments where the measured voltage at the read bit line RBL after the read operation is higher than a predetermined threshold voltage, the measured data bit is "0".

[0080] Reference Figure 5 , showing Figure 3E The schematic circuit diagram of the second embodiment structure is shown in FIG. The signal node SN corresponds to the first source / drain region 730 of the first field effect transistor (which is the write transistor WT), the gate electrode 754 of the second field effect transistor (which is the second read transistor RT2), and the bottom electrode (32 and / or 33) of the capacitor structure 30 through the connection metal line CML (such as Figure 3B-Figure 3ENodes electrically connected to each other (as shown). The write bit line WBL is used to provide a bias signal representing a data bit to be encoded in the signal node SN during a write operation. The write word line WWL is used to control the switch of the write transistor WT so that the write operation can be performed only when the write transistor is turned on. The source region 732 of the second read transistor RT2 is electrically grounded. Except during the read operation, the read word line RWL can be electrically biased to keep the first read transistor RT1 turned off. During the read operation, the read bit line RBL can be precharged to a read bit line bias voltage (also referred to as a precharge bias voltage), and the read word line RWL can be electrically biased to turn on the first read transistor RT1 during the read operation. If the data bit stored in the signal node SN is "1", the second read transistor RT2 is turned on, but if the data bit stored in the signal node SN is "0", the second read transistor RT2 is not turned on. The stored data bit at the signal node SN can be read by determining whether the measured voltage at the read bit line RBL after the first read transistor RT1 is turned on is higher or lower than a predetermined threshold voltage. After the read operation, in the embodiment where the voltage measured at the read bit line RBL due to the current flowing through the second read transistor RT2 is lower than the predetermined threshold voltage, the measured data bit is "1". In the embodiment where the voltage at the read bit line RBL measured after the read operation is higher than the predetermined threshold voltage, the measured data bit is "0".

[0081] Figure 6 Examples of symmetric crystal structures of dielectric materials of node dielectric 35 that can be used in various embodiments of the present disclosure are shown. In general, a symmetric crystalline phase of the dielectric material of node dielectric 35 can provide a higher dielectric constant than an amorphous phase of the dielectric material of node dielectric 35. Such symmetric crystalline phases include cubic, tetragonal, and hexagonal phases.

[0082] Reference Figure 7 , showing the dependence of the dielectric constant of the node dielectric 35 as a function of thickness and crystallinity. The white circles correspond to data points for samples that do not use any catalytic metal in the top electrode (TE) or the bottom electrode (BE). The black circles correspond to data points for samples that use at least one catalytic metal plate (33 or 37) in the top electrode and / or the bottom electrode. The thermal cycles represent typical thermal cycles in BEOL processing steps, i.e., thermal cycles with a maximum temperature of no more than 400 degrees Celsius. The critical thickness at which the crystallinity and dielectric constant of the node dielectric 35 diverge depending on whether a catalytic metal plate is present in the top electrode or the bottom electrode corresponds to a thickness in the range of 3nm to 5nm, for example 4nm. As shown, the incorporation of a catalytic metal in the top electrode (TE) or the bottom electrode (BE) results in a higher dielectric constant of the node dielectric 35 and produces higher capacitance in a low dielectric thickness range.

[0083] Reference Figure 8 , which shows a flow chart of a sequence of processing steps for fabricating various embodiment resistive memory devices.

[0084] Referring to step 810 and Figure 1A , Figure 1B , Figure 3A and Figure 3B , a first metal interconnect structure ( 612 , 618 , 622 , 628 , 22 ) formed in a first dielectric material layer ( 601 , 610 , 620 , 63A) may be formed on a substrate 9 .

[0085] Reference steps 820 and Figure 1C , Figure 2A-2F and Figure 3C A stack of a first electrode (32 and / or 33), a node dielectric 35, and a second electrode (37 and / or 38) may be formed over a first dielectric material layer (601, 610, 620, 63A). The first electrode (32 and / or 33) is formed on a top surface of one of the first metal interconnect structures (612, 618, 622, 628, 22). The node dielectric 35 includes an amorphous phase dielectric material. The first of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a first catalytic metal plate (33 or 37) that is in direct contact with the node dielectric 35 and has a first electronegativity that is no greater than the electronegativity of platinum.

[0086] Reference steps 830 and Figure 2A-2F , Figure 1D , Figure 1E , Figure 1F , Figure 3D and Figure 3E The dielectric material may be annealed so that the first catalytic metal plate (33 or 37) induces the amorphous phase dielectric material to catalytically crystallize into a crystalline phase dielectric material having a dielectric constant greater than 30.

[0087] According to one aspect of the present invention, the incorporation of a catalytic metal into the second electrode (37 and / or 38) (which may be used as a top electrode) and / or the first electrode (32 and / or 33) (which may be used as a bottom electrode) provides a higher dielectric constant for the node dielectric 35, thereby increasing the capacitance of the capacitor structure, particularly when the thickness of the node dielectric 35 is reduced. This configuration is advantageous in a planar metal-insulator-metal (MIM) capacitor, in which a planar layer of a first electrode (32 and / or 33) (which may be used as a bottom electrode), a node dielectric 35 comprising a planar dielectric layer, and a planar layer of a second electrode (37 and / or 38) (which may be used as a top electrode) are employed. Embodiments of the present disclosure may increase the capacitance of the capacitor structure without using a complex three-dimensional MIM structure, which typically requires additional mask layers and increases manufacturing costs. In addition, although particularly beneficial for planar configurations, embodiments of the present disclosure may also be applied to three-dimensional MIM capacitors, which may further improve the capacitance of such three-dimensional MIM capacitors.

[0088] With reference to all the accompanying drawings, according to various embodiments of the present disclosure, a device structure is provided, which includes: a first electrode (32 and / or 33) overlying a substrate 9; a node dielectric 35, which contacts the first electrode (32 and / or 33) and includes a dielectric material having a dielectric constant greater than 30; and a second electrode (37 and / or 38) in contact with the node dielectric 35, wherein the first of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a first catalytic metal plate (33 or 37), the first catalytic metal plate (33 or 37) is in direct contact with the node dielectric 35 and has a first electronegativity not greater than the electronegativity of molybdenum.

[0089] In one embodiment, a majority volume fraction of the dielectric material is a symmetric crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure. In one embodiment, the majority volume fraction comprises at least 80% of the entire volume of the node dielectric 35 .

[0090] In one embodiment, the second of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a second catalytic metal plate (37 or 33) and has a second electronegativity not greater than the electronegativity of platinum. In one embodiment, the second catalytic metal plate (37 or 33) is in direct contact with the node dielectric 35. In one embodiment, the first of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) also includes a first non-catalytic material plate (32 or 38) having a third electronegativity greater than the electronegativity of platinum and is spaced from the node dielectric 35 by the first catalytic metal plate (33 or 37). In one embodiment, the second of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a second non-catalytic material plate (38 or 32) having a fourth electronegativity greater than the electronegativity of platinum and is spaced from the node dielectric 35 by the second catalytic metal plate (37 or 33).

[0091] In one embodiment, the device structure includes: a first field effect transistor (such as a write transistor WT) located on the top surface of the substrate 9; a second field effect transistor (such as a read transistor RT or a second read transistor RT2) located on the top surface of the substrate 9; and a first metal interconnect structure (612, 618, 622, 628, 22) electrically connecting the source / drain region 730 of the first field effect transistor (such as the write transistor WT), the gate electrode 754 of the second field effect transistor (such as the read transistor RT or the second read transistor RT2) and the first electrode (32 and / or 33). In one embodiment, the device structure includes: a first dielectric material layer (601, 610, 620, 63A) embedded in the first metal interconnect structure (612, 618, 622, 628, 22); and a planar passivation dielectric layer 63B, which covers the first dielectric material layer (601, 610, 620, 63A) and contacts the bottom surface of the first electrode (32 and / or 33). In one embodiment, the device structure includes a conformal passivation dielectric layer 63C that contacts the top surface of the second electrode (37 and / or 38) and contacts the sidewalls of the first electrode (32 and / or 33), the node dielectric 35, and the second electrode (37 and / or 38).

[0092] According to another aspect of the present disclosure, a device structure is provided, which includes: a first electrode (32 and / or 33) overlying a substrate 9; a node dielectric 35, contacting the first electrode (32 and / or 33) and including a dielectric material, wherein the main volume fraction of the dielectric material is a symmetric crystal structure selected from a cubic crystal structure, a tetragonal crystal structure and a hexagonal crystal structure; and a second electrode (37 and / or 38) contacting the node dielectric 35, wherein the first of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a first catalytic metal plate (33 or 37), the first catalytic metal plate (33 or 37) is in direct contact with the node dielectric 35 and contains a metal having a first electronegativity not greater than 1.50.

[0093] In one embodiment, the first catalytic metal plate (33 or 37) includes an alkali metal or an alkaline earth metal. In one embodiment, the second of the first electrode (32 and / or 33) and the second electrode (37 and / or 38) includes a second catalytic metal plate (37 or 33) and has a second electronegativity not greater than 1.50. In one embodiment, the device structure includes: a planar passivation dielectric layer 63B contacting the bottom surface of the first electrode (32 and / or 33); and a conformal passivation dielectric layer 63C contacting the top surface of the second electrode (37 and / or 38) and contacting the sidewalls of the first electrode (32 and / or 33), the node dielectric 35, and the second electrode (37 and / or 38). In one embodiment, the device structure includes: a first metal interconnect structure (612, 618, 622, 628, 22), which electrically connects the first electrode (32 and / or 33) to the drain region of a first field effect transistor (such as a write transistor WT) located on the substrate 9, and is connected to the gate electrode 754 of a second field effect transistor (such as a read transistor RT or a second read transistor RT2) located on the substrate 9; and a second metal interconnect structure (28, EG) electrically connected to the second electrode (37 and / or 38) and electrically grounded.

[0094] Various embodiments of the present disclosure can be used to provide a capacitor structure 30 with a higher capacitance per unit area without the need for high temperature annealing at more than 400 degrees Celsius. Therefore, the capacitor structure 30 of the various embodiments of the present disclosure is compatible with back-end process technologies known in the art. The capacitor structure 30 of the various embodiments of the present disclosure can be used in various applications, an example of which is a gain unit memory device using two transistors or three transistors. However, the capacitor structure 30 of the various embodiments of the present disclosure can also be used for any application of a capacitor architecture 30 that needs to be constructed without being subjected to high temperature (such as a temperature above 400 degrees Celsius) thermal cycling. For example, the capacitor structure 30 of the various embodiments of the present disclosure can also be used for dynamic random access memory (DRAM) applications using capacitors as charge storage devices. In addition, the capacitor structure 30 of the various embodiments of the present disclosure can be used for any other application, wherein the capacitor formed in the back-end process structure can be advantageously used for device operation or device performance enhancement.

[0095] According to one aspect of an embodiment of the present application, a semiconductor device structure is provided, comprising: a first electrode, overlying a substrate; a node dielectric, contacting the first electrode and comprising a dielectric material having a dielectric constant greater than 30; and a second electrode, contacting the node dielectric, wherein a first of the first electrode and the second electrode comprises a first catalytic metal plate, the first catalytic metal plate is in direct contact with the node dielectric, and has a first electronegativity not greater than the electronegativity of molybdenum.

[0096] In some embodiments, a majority volume fraction of the dielectric material is in a symmetric crystal structure selected from the group consisting of a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure.

[0097] In some embodiments, the majority volume fraction comprises at least 80% of the entire volume of the node dielectric.

[0098] In some embodiments, the second of the first electrode and the second electrode comprises a second catalytic metal plate and has a second electronegativity no greater than the electronegativity of platinum.

[0099] In some embodiments, the second catalytic metal plate is in direct contact with the node dielectric.

[0100] In some embodiments, the first of the first electrode and the second electrode further comprises a first non-catalytic material plate having a third electronegativity greater than that of molybdenum and separated from the node dielectric by the first catalytic metal plate.

[0101] In some embodiments, the second of the first electrode and the second electrode includes a second non-catalytic material plate having a fourth electronegativity greater than that of molybdenum and separated from the node dielectric by a second catalytic metal plate.

[0102] In some embodiments, the semiconductor device structure also includes: a first field effect transistor located on the top surface of the substrate; a second field effect transistor located on the top surface of the substrate; and a first metal interconnect structure electrically connecting the source / drain region of the first field effect transistor, the gate electrode of the second field effect transistor, and the first electrode.

[0103] In some embodiments, the semiconductor device structure further includes: a first dielectric material layer embedded in the first metal interconnect structure; and a planar passivation dielectric layer overlying the first dielectric material layer and contacting a bottom surface of the first electrode.

[0104] In some embodiments, the semiconductor device structure further includes a conformal passivation dielectric layer contacting a top surface of the second electrode and contacting sidewalls of the first electrode, the node dielectric, and the second electrode.

[0105] According to another aspect of an embodiment of the present application, a semiconductor device structure is provided, comprising: a first electrode, overlying a substrate; a node dielectric, contacting the first electrode and comprising a dielectric material, wherein a major volume fraction of the dielectric material is a symmetric crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure; and a second electrode, contacting the node dielectric, wherein a first of the first electrode and the second electrode comprises a first catalytic metal plate, the first catalytic metal plate is in direct contact with the node dielectric, and comprises a metal having a first electronegativity not greater than 1.50.

[0106] In some embodiments, the first catalytic metal plate includes an alkali metal or an alkaline earth metal.

[0107] In some embodiments, the second of the first electrode and the second electrode includes a second catalytic metal plate and has a second electronegativity of no greater than 1.50.

[0108] In some embodiments, the semiconductor device structure further includes: a planar passivation dielectric layer contacting a bottom surface of the first electrode; and a conformal passivation dielectric layer contacting a top surface of the second electrode and contacting sidewalls of the first electrode, the node dielectric, and the second electrode.

[0109] In some embodiments, the semiconductor device structure further includes: a first metal interconnect structure electrically connecting the first electrode to a drain region of a first field effect transistor located on the substrate and a gate electrode of a second field effect transistor located on the substrate; and a second metal interconnect structure electrically connecting the second electrode and electrically grounding.

[0110] According to another aspect of an embodiment of the present application, a method for forming a semiconductor device structure is provided, the method comprising: forming a first metal interconnect structure in a first dielectric material layer on a substrate; forming a stack of a first electrode, a node dielectric, and a second electrode above the first dielectric material layer, wherein the first electrode is formed on a top surface of one of the first metal interconnect structures, the node dielectric comprises an amorphous phase dielectric material, and the first of the first electrode and the second electrode comprises a first catalytic metal plate, the first catalytic metal plate is in direct contact with the node dielectric, and has a first electronegativity not greater than that of molybdenum; and annealing the dielectric material so that the first catalytic metal plate induces catalytic crystallization of the amorphous phase dielectric material into a crystalline phase dielectric material having a dielectric constant greater than 30.

[0111] In some embodiments, a majority volume fraction of the crystalline phase dielectric material is in a symmetric crystal structure selected from the group consisting of a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure.

[0112] In some embodiments, the majority volume fraction comprises at least 80% of the entire volume of the node dielectric.

[0113] In some embodiments, the second of the first electrode and the second electrode comprises a second catalytic metal plate and has a second electronegativity no greater than the electronegativity of platinum.

[0114] In some embodiments, the method also includes: forming a first field effect transistor on the top surface of the substrate; and forming a second field effect transistor on the top surface of the substrate, wherein the first metal interconnect structure electrically connects the source / drain region of the first field effect transistor, the gate electrode of the second field effect transistor, and the first electrode.

[0115] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Each embodiment described using the term "comprising" also inherently discloses that the term "comprising" can be replaced with "consisting essentially of..." or replaced by the term "consisting of..." in some embodiments, unless otherwise explicitly disclosed herein. Whenever two or more elements are listed as alternatives in the same paragraph or in different paragraphs, the Markush combination of the list including two or more elements can also be implicitly disclosed in some embodiments. Whenever the auxiliary verb "may" is used in the present disclosure to describe the formation of an element or the execution of a processing step, it is also explicitly envisioned that such an element or such a processing step is not performed, as long as the resulting device or equipment can provide an equivalent result. Therefore, whenever the formation of such an element or such a processing is omitted, the auxiliary verb "may" applied to the formation of the element or the execution of the processing step should also be interpreted as "may" or "may or may not". Provide the same result or an equivalent result, and an equivalent result includes a slightly superior result and a slightly inferior result. Those skilled in the art will appreciate that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device structure, comprising: A first electrode overlying the substrate; a node dielectric contacting the first electrode and comprising a dielectric material having a dielectric constant greater than 30; as well as a second electrode contacting the node dielectric, Wherein, a first one of the first electrode and the second electrode includes a first catalytic metal plate, the first catalytic metal plate is in direct contact with the node dielectric and has a first electronegativity no greater than the electronegativity of molybdenum.

2. The semiconductor device structure according to claim 1, wherein: A major volume fraction of the dielectric material is a symmetrical crystal structure selected from the group consisting of a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure.

3. The semiconductor device structure according to claim 2, wherein: The majority volume fraction comprises at least 80% of the entire volume of the node dielectric.

4. The semiconductor device structure according to claim 1, wherein: A second one of the first electrode and the second electrode includes a second catalytic metal plate and has a second electronegativity not greater than that of platinum.

5. The semiconductor device structure according to claim 4, wherein: The second catalytic metal plate is in direct contact with the node dielectric.

6. The semiconductor device structure according to claim 4, wherein: The first of the first electrode and the second electrode also includes a first non-catalytic material plate having a third electronegativity greater than that of platinum and separated from the node dielectric by the first catalytic metal plate.

7. The semiconductor device structure according to claim 6, wherein: The second one of the first and second electrodes includes a second non-catalytic material plate having a fourth electronegativity greater than that of platinum and spaced from the node dielectric by the second catalytic metal plate.

8. The semiconductor device structure according to claim 1, further comprising: A first field effect transistor is located on the top surface of the substrate; A second field effect transistor, located on the top surface of the substrate; as well as The first metal interconnection structure electrically connects the source / drain region of the first field effect transistor, the gate electrode of the second field effect transistor and the first electrode.

9. A semiconductor device structure, comprising: A first electrode overlying the substrate; a node dielectric contacting the first electrode and comprising a dielectric material, wherein a major volume fraction of the dielectric material is a symmetrical crystal structure selected from a cubic crystal structure, a tetragonal crystal structure, and a hexagonal crystal structure; and a second electrode contacting the node dielectric, The first one of the first electrode and the second electrode includes a first catalytic metal plate, the first catalytic metal plate is in direct contact with the node dielectric and includes a metal having a first electronegativity not greater than 1.

50.

10. A method for forming a semiconductor device structure, the method comprising: forming a first metal interconnect structure within a first dielectric material layer on a substrate; forming a stack of a first electrode, a node dielectric, and a second electrode over the first dielectric material layer, wherein the first electrode is formed on a top surface of one of the first metal interconnect structures, the node dielectric comprises an amorphous phase dielectric material, and a first of the first electrode and the second electrode comprises a first catalytic metal plate, the first catalytic metal plate is in direct contact with the node dielectric and has a first electronegativity no greater than that of molybdenum; as well as The dielectric material is annealed so that the first catalytic metal plate induces the amorphous phase dielectric material to catalytically crystallize into a crystalline phase dielectric material with a dielectric constant greater than 30.

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