Semiconductor device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, relating to the technical field of semiconductor, the method comprising: providing a substrate structure comprising a substrate, a plurality of fins spaced on the substrate, and a gate structure across the plurality of fins; forming a first mask layer having an opening on the gate structure; forming a first insulating layer on the first mask layer; forming a patterned sacrificial layer on the first insulating layer; forming a second insulating layer covering the sacrificial layer; removing a portion of the second insulating layer covering other regions than the sidewall of the sacrificial layer and the sacrificial layer, and retaining a portion of the second insulating layer covering the sidewall of the sacrificial layer as a sidewall; forming a third insulating layer surrounding the sidewall; removing the sidewall to form a trench defined by the third insulating layer, a first portion of the trench having a first projection on the substrate within a second projection on the substrate of the opening and overlapping a third projection on the substrate of the gate structure; performing etching to remove a portion of the gate structure along the first portion of the trench, thereby truncating the gate structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In related technologies, two photomasks are used to define the area of ​​the gate structure that needs to be cut off during the process of cutting off the gate structure.

[0003] To meet the need for further reduction in critical dimensions, higher precision lithography machines are required to define the regions where the gate structure needs to be cut off. Summary of the Invention

[0004] In view of this, the present disclosure proposes the following technical solution, which enables the reduction of the size of the area to be cut off in the gate structure using a low-precision photolithography machine without increasing the photomask.

[0005] According to one aspect of the present disclosure, a method of manufacturing a semiconductor device is provided, comprising: providing a substrate structure including a substrate, a plurality of fins spaced apart on the substrate, and a gate structure spanning the plurality of fins; forming a first mask layer having an opening on the gate structure; forming a first insulating layer on the first mask layer; forming a patterned sacrificial layer on the first insulating layer; forming a second insulating layer covering the sacrificial layer; removing portions of the second insulating layer covering other areas outside the sidewalls of the sacrificial layer and the sacrificial layer, retaining portions of the second insulating layer covering the sidewalls of the sacrificial layer as sidewalls; forming a third insulating layer surrounding the sidewalls; removing the sidewalls to form a trench defined by the third insulating layer, a first portion of the trench having an orthographic projection on the substrate within the orthographic projection of the opening on the substrate and overlapping with the orthographic projection of the gate structure on the substrate; and performing etching to remove a portion of the gate structure along the first portion of the trench, thereby truncating the gate structure.

[0006] In some embodiments, the substrate structure includes a plurality of the gate structures, the first mask layer has a plurality of the openings, and the trench has a plurality of spaced first portions, the orthographic projections of different first portions on the substrate being within the orthographic projections of different openings on the substrate and overlapping with the orthographic projections of different gate structures on the substrate.

[0007] In some embodiments, the orthographic projection of at least one of the first portions of the trench onto the substrate overlaps with the orthographic projections of at least two of the gate structures onto the substrate.

[0008] In some embodiments, the orthographic projection of at least one of the first portions of the trench onto the substrate overlaps with the orthographic projection of a gate structure onto the substrate.

[0009] In some embodiments, the orthographic projection of the second portion of the trench onto the substrate lies within the orthographic projection of the first mask layer onto the substrate; performing etching includes: using the first mask layer as a stop layer, removing a portion of the first insulating layer located on the first mask layer along the second portion of the trench.

[0010] In some embodiments, performing etching includes: performing a first etching to remove a portion of the first insulating layer on the first mask layer along the second portion of the trench, and removing another portion of the first insulating layer on the gate structure along the first portion of the trench; and performing a second etching to remove the portion of the gate structure along the first portion of the trench, thereby truncating the gate structure.

[0011] In some embodiments, forming a first mask layer with an opening on the gate structure includes: forming a fourth insulating layer on the gate structure; forming a first mask material layer on the fourth insulating layer; and patterning the first mask material layer to form the first mask layer.

[0012] In some embodiments, the method further includes: after cutting off the gate structure, removing the first mask layer using the fourth insulating layer as a stop layer.

[0013] In some embodiments, the fourth insulating layer is made of a different material than the first insulating layer.

[0014] In some embodiments, forming a third insulating layer around the sidewall includes: forming a third insulating material layer covering the sidewall; and removing a portion of the third insulating material layer such that the upper surface of the remaining portion of the third insulating material layer is flush with the upper surface of the sidewall, the remaining portion of the third insulating material layer serving as the third insulating layer.

[0015] In some embodiments, the thickness of the sacrificial layer is 50 nanometers to 100 nanometers.

[0016] In some embodiments, the thickness of the second insulating layer is 10 nanometers to 40 nanometers.

[0017] In some embodiments, the material of the first mask layer includes a metal nitride.

[0018] In some embodiments, the gate structure is a pseudo-gate structure.

[0019] In some embodiments, the materials of the first insulating layer and the second insulating layer are different.

[0020] According to another aspect of the present disclosure, a semiconductor device is provided, comprising: a substrate structure including a substrate, a plurality of fins spaced apart on the substrate, and a plurality of gate structures extending along a first direction, wherein adjacent gate structures are separated by trenches in the first direction, and each gate structure spans at least one fin; and a first mask layer having an opening located on the plurality of gate structures, wherein the orthographic projection of the portion of the trench located between the adjacent two gate structures on the substrate lies within the orthographic projection of the opening on the substrate.

[0021] In the semiconductor device manufacturing method provided in this disclosure, firstly, a first mask layer with an opening is formed on the gate structure of a substrate structure to define the region of the gate structure that needs to be cut off. Then, a patterned sacrificial layer and a second insulating layer covering the sacrificial layer are sequentially formed on a first insulating layer, retaining a portion of the sidewalls of the second insulating layer covering the sacrificial layer as sidewalls. By forming a third insulating layer around the sidewalls and then removing the sidewalls, a trench defined by the third insulating layer can be formed. Finally, etching is performed to remove a portion of the gate structure overlapping the trench below the opening, along a portion of the trench above the opening. In this manner, the minimum linewidth of the cut-off gate structure can be defined using the sidewalls formed by the portion of the second insulating layer covering the sidewalls of the sacrificial layer, and the first mask layer can be used as a stop layer to protect the region of the gate structure that does not need to be cut off. Thus, the requirements for gate cut-off processes with reduced dimensions can be met using a low-precision lithography machine.

[0022] Other features, aspects, and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0023] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.

[0024] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:

[0025] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0026] Figures 2A to 15 This is a schematic diagram of various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0027] Figure 16AThis is a top view of a semiconductor device according to some embodiments of the present disclosure;

[0028] Figure 16B This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0029] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not necessarily drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation

[0030] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0031] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0032] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0033] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0034] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0035] Figure 1 This is a schematic flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figures 2A to 15 This is a schematic diagram of various stages of a method for manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0036] The following is combined Figure 1 as well as Figures 2A to 15 The present disclosure describes methods for manufacturing semiconductor devices according to some embodiments.

[0037] like Figure 1 As shown, the method for manufacturing a semiconductor device includes steps S102 to S118. The semiconductor device may include, for example, a fin field-effect transistor.

[0038] In step S102, a substrate structure is provided.

[0039] The following is combined Figures 2A to 2C The substrate structures of some embodiments of this disclosure will be described.

[0040] Figure 2A This is a top view of a substrate structure according to some embodiments of the present disclosure. Figure 2B It is based on some embodiments of this disclosure along Figure 2A The diagram shows the cross-section cut by line B-B'. Figure 2C It is along Figure 2A The diagram shows a cross-section cut along line C-C'.

[0041] like Figures 2A to 2C As shown, the substrate structure 10 includes a substrate 11, a plurality of fins 12 spaced apart on the substrate 11, and a gate structure 13 spanning the plurality of fins 12.

[0042] The substrate 11 can be a semiconductor substrate. For example, the semiconductor substrate can be silicon (Si), germanium (Ge), or other elemental semiconductor substrates, or it can be a compound semiconductor substrate such as gallium arsenide (GaAs). The material of the fin 12 can be the same as or different from the material of the substrate.

[0043] The fins 12 can be formed in various ways. In some implementations, multiple fins 12 are integrally disposed with the substrate 11. For example, a substrate material can be provided and etched to obtain an integrally disposed substrate 11 and multiple fins 12. In other implementations, the multiple fins 12 are not integrally disposed with the substrate 11. For example, fin material can be formed on the substrate 11, and then the fin material can be patterned to form non-integrated fins 12 and substrate 11. For example, the fin material can be patterned using a self-aligned double patterning (SADP) process to obtain smaller fins 12.

[0044] See Figure 2B and 2C The gate structure 13 may include a gate 131 and a gate dielectric layer 132. The gate dielectric layer 132 may cover the sidewalls and the upper surface of the fin 12. The gate 131 is located on the gate dielectric layer 132.

[0045] In some embodiments, the gate structure 13 may be a dummy gate structure. In this case, the gate 131 may be a dummy gate, which can be replaced with a metal gate by subsequent processes. The dummy gate may, for example, comprise amorphous silicon. The material of the gate dielectric layer 132 may comprise an oxide of silicon, such as silicon oxide (SiO2).

[0046] In some embodiments, see Figure 2A The substrate structure 10 also includes a plurality of spaced isolation regions 14 on the substrate 11. Fins 12 may protrude between adjacent isolation regions 14. See also, as some implementations, [link to relevant documentation]. Figure 2A The gate dielectric layer 132 also covers the upper surface of the isolation region 14.

[0047] It should be understood that, in order to make the accompanying drawings clearer, Figure 2A The plurality of spaced isolation regions 14 on the substrate 11 are not shown.

[0048] In some embodiments, see Figure 2C The substrate structure 10 also includes a spacer layer SW1 covering the sidewalls of the gate structure 13. The spacer layer SW1 can be a single-layer structure or a multi-layer structure. As some implementations, the material of the spacer layer SW1 can include silicon nitrides, such as silicon nitride (Si3N4).

[0049] In some embodiments, the substrate structure 10 further includes source and drain regions located on both sides of the gate structure 13. For example, the source and drain regions are raised source and drain regions to introduce stress into the channel region, thereby improving carrier mobility. For example, the fin 12 is etched to form a recess, and the source and drain regions are then formed within the recess by an epitaxial process. As an example, the material of the source and drain regions may include germanium silicide (SiGe) or silicon phosphide (SiP).

[0050] In some embodiments, such as Figure 2A As shown, the substrate structure 10 includes multiple gate structures 13. The multiple fins 12 spanned by different gate structures 13 may be the same or different.

[0051] To more clearly illustrate the other material layers formed, they will be primarily incorporated into the following text. Figure 2A and Figure 2B The description is based on other material layers formed on this basis.

[0052] Next, in step S104, a first mask layer with an opening is formed on the gate structure.

[0053] As one implementation method, the first mask layer can be formed according to the following process.

[0054] First, a gate structure 13 can be formed. Figure 3 The insulating layer 15 shown is the fourth insulating layer 15. As some implementations, the material of the fourth insulating layer 15 may include at least one of silicon nitride, silicon carbonitride, and silicon oxycarbonitride. The silicon nitride may, for example, be silicon nitride. The silicon carbonitride may, for example, be silicon carbonitride (SiCN). The silicon oxycarbonitride may, for example, be silicon oxycarbonitride (SiOCN).

[0055] Then, the fourth insulating layer 15 is formed. Figure 3 The first mask material layer 16' is shown. As some implementations, the material of the first mask material layer 16' may include a metal nitride. The metal nitride may include, but is not limited to, titanium nitride (TiN), tantalum nitride (TaN), etc.

[0056] Finally, the first mask material layer 16' can be patterned to form Figure 4A and Figure 4B The first mask layer 16 shown has an opening V.

[0057] like Figure 4A and 4B As shown, in some embodiments, the first mask layer 16 may include a plurality of openings V.

[0058] In the above implementation, a fourth insulating layer 15 is first formed on the gate structure 13, and then a first mask material layer 16' is formed on the fourth insulating layer 15. The first mask material layer 16' is then patterned to form a first mask layer 16 with an opening V. In this way, the fourth insulating layer 15 can protect the gate structure 13 located under the fourth insulating layer 15 during the patterning of the first mask material layer 16'.

[0059] As one implementation method, the first mask material layer 16' can be patterned according to the following procedure.

[0060] like Figure 3 As shown, firstly, a hard mask layer 17 can be formed on the first mask material layer 16'. The hard mask layer 17 may include, for example, a carbon layer formed by a spin coating process, i.e., a spin-coated carbon layer.

[0061] Then, a layer can be formed on the hard mask layer 17. Figure 3 The anti-reflective layer 18 is shown. The anti-reflective layer 18 may be, for example, a silicon-containing anti-reflective layer.

[0062] Subsequently, a patterned photoresist 19 (also known as photoresist) can be formed on the anti-reflective layer 18. The patterned photoresist 19 can define the pattern of the opening V. For example, the patterned photoresist 19 can be obtained by photolithography on the photoresist material under the photomask.

[0063] Next, using photoresist 10 as a mask, the antireflective layer 18 (if present), hard mask layer 17, and first mask material layer 16' are etched. After etching, the remaining portions of the antireflective layer 18 and hard mask layer 17 are removed, and the remaining portion of the first mask material layer 16' is the first mask layer 16 with an opening V.

[0064] In some implementations, the anti-reflective layer 18 may not be formed; instead, patterned photoresist 19 may be formed directly on the hard mask layer 17.

[0065] Then, in step S106, a first insulating layer is formed on the first mask layer.

[0066] As some implementation methods, such Figure 5 As shown, a first insulating layer 20 can be formed on the first mask layer 16 by deposition. It should be understood that the first insulating layer 20 fills the opening V. The material of the first insulating layer 20 may, for example, include silicon oxide. Silicon oxide may, for example, be silicon oxidized.

[0067] Next, in step S108, a patterned sacrificial layer is formed on the first insulating layer.

[0068] As one implementation method, a patterned sacrificial layer can be formed on the first insulating layer according to the following process.

[0069] First, such as Figure 6 As shown, a sacrificial material layer 21' can be formed on the first insulating layer 20. The material of the sacrificial material layer 21' may, for example, include amorphous silicon.

[0070] Then, a hard mask layer 22 can be formed on the sacrificial material layer 21'. The hard mask layer 22 may, for example, include a carbon layer formed by a spin coating process.

[0071] Next, an anti-reflective layer 23 is formed on the hard mask layer 22. The anti-reflective layer 23 may be, for example, a silicon-containing anti-reflective layer.

[0072] Subsequently, a patterned photoresist 24 is formed on the anti-reflection layer 23. For example, the photoresist material under the photomask can be photolithographically etched using a photomask to obtain the patterned photoresist 24.

[0073] Next, using patterned photoresist 24 as a mask, the antireflective layer 23 (if present), hard mask layer 22, and sacrificial material layer 21' are etched. After etching, the remaining portions of the antireflective layer 23 and hard mask layer 22 are removed, and the remaining portion of the sacrificial material layer 21' is... Figure 7 The sacrificial layer 21 is shown. In the SADP process, the sacrificial layer 21 can also be called the core layer.

[0074] Then, in step S110, a second insulating layer covering the sacrificial layer is formed.

[0075] As some implementation methods, such Figure 8 As shown, a second insulating layer 25 covering the sacrificial layer 21 can be formed by deposition. The material of the second insulating layer 25 may, for example, include a silicon nitride. The silicon nitride may, for example, be silicon nitride.

[0076] Next, in step S112, the portion of the second insulating layer covering the other area outside the sidewall of the sacrificial layer and the sacrificial layer are removed, leaving the portion of the second insulating layer covering the sidewall of the sacrificial layer as a sidewall.

[0077] Figure 9 A schematic diagram is shown of the sidewall SW2 (i.e., the portion of the sidewall of the sacrificial layer 21 covered by the second insulating layer 25) that remains after step S112.

[0078] As one implementation, the second insulating layer 25 can be etched to remove the portion of the second insulating layer 25 covering the area outside the sidewalls of the sacrificial layer 21; after etching, the sacrificial layer 21 is removed, thereby obtaining... Figure 9 The side wall SW2 is shown.

[0079] It should be understood that during the etching process of the second insulating layer 25, a portion of the second insulating layer 25 covering the sidewall of the sacrificial layer 21 may also be etched.

[0080] In some embodiments, the thickness of the sacrificial layer 21 is 50 nanometers to 100 nanometers, for example, 50 nanometers to 80 nanometers. As some implementations, the thickness of the sacrificial layer 21 is 55 nanometers, 60 nanometers, 70 nanometers, 75 nanometers, or 90 nanometers, etc.

[0081] In other embodiments, the thickness of the second insulating layer 25 is 10 nanometers to 40 nanometers, for example, 18 nanometers to 30 nanometers. As some implementations, the thickness of the second insulating layer 25 is 15 nanometers, 20 nanometers, 23 nanometers, 26 nanometers, 29 nanometers, or 35 nanometers, etc.

[0082] In some other embodiments, the thickness of the sacrificial layer 21 is 50 nanometers to 100 nanometers, and the thickness of the second insulating layer 25 is 10 nanometers to 40 nanometers. In some implementations, the thickness of the sacrificial layer 21 is 50 nanometers to 80 nanometers, and the thickness of the second insulating layer 25 is 18 nanometers to 30 nanometers.

[0083] Then, in step S114, a third insulating layer is formed around the sidewall.

[0084] As one implementation method, a third insulation layer can be formed around the sidewalls by following the steps below.

[0085] First, such as Figure 10 As shown, a third insulating material layer 26' can be formed to cover the sidewall SW2. The material of the third insulating material layer 26' may include, for example, silicon oxide, spin-coated carbon, etc. Silicon oxide may be, for example, silicon oxide.

[0086] Then, as Figure 11 As shown, a portion of the third insulating material layer 26' can be removed so that the upper surface of the remaining portion of the third insulating material layer 26' is flush with the upper surface of the sidewall SW2. In this case, the remaining portion of the third insulating material layer 26' serves as the third insulating layer 26.

[0087] In this way, a third insulating layer 26 can be formed around the sidewall SW2.

[0088] As one implementation method, the third insulating material layer 26' can be etched back or planarized by etching or chemical mechanical polishing to expose the sidewall SW2, so that the upper surface of the remaining portion of the third insulating material layer 26' is flush with the upper surface of the sidewall SW2.

[0089] It should be noted that the "flush" mentioned in this article refers to the flush within the range of semiconductor process deviations.

[0090] Next, in step S116, the sidewalls are removed to form a trench defined by the third insulating layer.

[0091] As one implementation method, the sidewall SW2 can be removed by a dry etching process or a wet etching process to form a trench T defined by the third insulating layer 26.

[0092] Figure 12A A top view of the trench T defined by the third insulating layer 26 is shown. Figure 12B A cross-sectional view of the trench T defined by the third insulating layer 26 is shown.

[0093] like Figure 12A and Figure 12B As shown, the orthographic projection of a portion T1 of the trench T (hereinafter referred to as the first portion T1) on the substrate 11 is located within the orthographic projection of the opening V on the substrate 11 and overlaps with the orthographic projection of the gate structure 13 on the substrate 11.

[0094] In some embodiments, see Figure 12A and 12B The orthographic projection of the other part T2 of the trench T (hereinafter referred to as the second part T2) on the substrate 11 is outside the orthographic projection of the opening V on the substrate 11.

[0095] In some embodiments, such as Figure 12A and 12B As shown, a plurality of trenches T defined by the third insulating layer 26 can be formed. Each trench T includes a first portion T1 whose orthogonal projection on the substrate 11 is located within the orthogonal projection of the opening V on the substrate 11 and overlaps with the orthogonal projection of the gate structure 13 on the substrate 11. Furthermore, each trench T also includes a second portion T2 whose orthogonal projection on the substrate 11 is located outside the orthogonal projection of the opening V on the substrate 11.

[0096] Finally, in step S118, etching is performed to remove a portion of the gate structure along the first portion T1 of the trench, thereby truncending the gate structure.

[0097] It should be understood that the portion of the gate structure 13 that is removed includes the portion that overlaps with the orthographic projection of the first portion T1 of the trench T onto the substrate 11.

[0098] In some embodiments, the orthographic projection of the second portion T2 of the trench T onto the substrate 11 is outside the orthographic projection of the opening V onto the substrate 11. In this case, during the etching process, the first mask layer 16 is used as a stop layer, and a portion of the first insulating layer 20 located on the first mask layer 16 is removed along the second portion T2 of the trench T.

[0099] In other words, the opening V of the first mask layer 16 can define the area of ​​the gate structure 13 that needs to be cut off. When the trench T includes a first portion T1 and a second portion T2, the first mask layer 16 can act as a stop layer during etching to protect the area of ​​the gate structure 13 that does not need to be cut off, so that only the portion of the gate structure 13 that overlaps with the first portion T1 of the trench T is cut off.

[0100] As one implementation method, etching can be performed according to the following process.

[0101] First, see Figure 13 The first etching can be performed to remove a portion of the first insulating layer 20 located on the first mask layer 16 along the second portion T2 of the trench T, and to remove another portion of the first insulating layer 20 located on the gate structure 13 along the first portion T1 of the trench T.

[0102] Then, see Figure 14 A second etching can be performed to remove a portion of the gate structure 13 along the first portion T1 of the trench T, thereby cutting off the gate structure 13.

[0103] In this approach, different etchants can be used to perform the first and second etching processes to improve the efficiency of the first and second etching processes, thereby improving the manufacturing efficiency of semiconductor devices.

[0104] As some implementations, the second etching includes a first sub-etch and a second sub-etch. The first sub-etch is used to remove a portion of the fourth insulating layer 15 along the first portion T1 of the trench T; the second sub-etch is used to remove a portion of the gate structure 13 along the first portion T1 of the trench T, thereby cutting off the gate structure 13.

[0105] In this approach, different etchants can be used to perform the first and second sub-etches, further improving the efficiency of the second etching. This, in turn, can further improve the manufacturing efficiency of semiconductor devices.

[0106] In the semiconductor device manufacturing method of this disclosure embodiment, firstly, a first mask layer with an opening is formed on the gate structure of a substrate structure to define the region of the gate structure that needs to be cut off. Then, a patterned sacrificial layer and a second insulating layer covering the sacrificial layer are sequentially formed on a first insulating layer, retaining a portion of the sidewalls of the second insulating layer covering the sacrificial layer as sidewalls. By forming a third insulating layer around the sidewalls and then removing the sidewalls, a trench defined by the third insulating layer can be formed. Finally, etching is performed to remove a portion of the gate structure overlapping the trench below the opening, along a portion of the trench above the opening. In this manner, the minimum linewidth of the cut-off gate structure can be defined using the sidewalls formed by the portion of the second insulating layer covering the sidewalls of the sacrificial layer, and the first mask layer can be used as a stop layer to protect the region of the gate structure that does not need to be cut off. Thus, the requirements for gate cut-off processes with reduced dimensions can be met using a low-precision lithography machine.

[0107] Figure 15 This is a top view of a truncated gate structure according to some embodiments of the present disclosure.

[0108] In some embodiments, see Figure 15 The substrate structure 10 includes a plurality of gate structures 13, the first mask layer 16 has a plurality of openings V, and the trench T has a plurality of spaced first portions T1. The orthographic projections of different first portions T1 on the substrate 11 lie within the orthographic projections of different openings V on the substrate 11, and the orthographic projections of different first portions T1 on the substrate 11 overlap with the orthographic projections of different gate structures 13 on the substrate 11.

[0109] In this case, by performing etching to remove a portion of multiple gate structures 13 at once along multiple first portions T1 of the trench T, multiple different gate structures 13 can be cut off at once. This can improve the manufacturing efficiency of semiconductor devices.

[0110] In some embodiments, the orthographic projection of at least one first portion T1 of trench T onto substrate 11 overlaps with the orthographic projection of a gate structure 13 onto substrate 11.

[0111] In other embodiments, see Figure 15 The orthographic projection of at least one first portion T1 of the trench T onto the substrate 11 overlaps with the orthographic projections of at least two gate structures 13 onto the substrate 11. In this case, by performing etching to remove a portion of each of at least two gate structures 13 at once along a first portion T1 of the trench T, more gate structures 13 can be cut off at once. Thus, the manufacturing efficiency of the semiconductor device can be further improved.

[0112] In some other embodiments, the orthographic projection of a first portion T1 of trench T onto substrate 11 overlaps with the orthographic projection of a gate structure 13 onto substrate 11, and the orthographic projection of another first portion T1 of trench T onto substrate 11 overlaps with the orthographic projections of at least two gate structures 13 onto substrate 11. In this case, by performing etching to remove a portion of one gate structure 13 at once along one first portion T1 of trench T, and to remove a portion of each of at least two gate structures 13 at once along the other first portion T1 of trench T, it is possible to cut off one gate structure 13 at once using one or more first portions T1, and to cut off multiple gate structures 13 at once using one or more first portions T2. Thus, different cutoff requirements for different gate structures 13 can be met using a single trench T, thereby further improving the manufacturing efficiency of semiconductor devices.

[0113] In some embodiments, after the gate structure 13 is cut off, the third insulating layer 26, the first insulating layer 20, and the first mask layer 16 can be removed using the fourth insulating layer 15 as a stop layer. For example, the third insulating layer 26, the first insulating layer 20, and the first mask layer 16 can be removed using a dry etching process or a wet etching process.

[0114] In some implementations, the fourth insulating layer 15 is made of a different material than the first mask layer 16. For example, the material of the fourth insulating layer 15 may include a silicon nitride (e.g., silicon nitride), while the material of the first mask layer 16 may include a metal nitride (e.g., titanium nitride or tantalum nitride). Since metal nitrides tend to have high etch selectivity, including a metal nitride in the first mask layer 16 can reduce the difficulty of manufacturing semiconductor devices.

[0115] The manufacturing process of semiconductor devices has been illustrated above with reference to some embodiments. It is understood that after the gate structure is cut off, other processes can be performed according to standard procedures. For example, the fourth insulating layer 15 can be removed, the gate 131 in the gate structure 13 can be replaced with a metal gate, and contact holes can be formed.

[0116] The semiconductor device manufacturing method of the present disclosure can be applied to, but is not limited to, 7-nanometer and below processes.

[0117] This disclosure also provides a semiconductor device, which will be described below in conjunction with embodiments thereof. Figure 16A and Figure 16B Please provide an explanation.

[0118] Figure 16A This is a top view of a semiconductor device according to some embodiments of the present disclosure; Figure 16B It is based on some embodiments of this disclosure along Figure 16A The diagram shows a cross-section cut by line D-D'.

[0119] like Figure 16A and 16B As shown, the semiconductor device includes a substrate structure 10. The substrate structure 10 includes a substrate 11, a plurality of fins 12 spaced apart on the substrate 11, and a plurality of gate structures 13 extending along a first direction. Each gate structure 13 spans at least one fin 12. The plurality of gate structures are spaced apart by trenches T in the first direction.

[0120] In some embodiments, the semiconductor device may include multiple sets of gate structures 13. Each set of gate structures 13 includes a plurality of gate structures 13 extending along a first direction. Here, different sets of gate structures 13 are parallel to each other in a direction perpendicular to the first direction.

[0121] like Figure 16A and 16B As shown, the semiconductor device also includes a first mask layer 16 with an opening V. Here, the orthogonal projection of the portion of the trench T located between two adjacent gate structures 13 along the first direction onto the substrate 11 lies within the orthogonal projection of the opening V onto the substrate 11.

[0122] The semiconductor devices of this disclosure can be obtained, but are not limited to, by the manufacturing method of any of the semiconductor devices described above.

[0123] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0124] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: A substrate structure is provided, the substrate structure including a substrate, a plurality of fins spaced apart on the substrate, and a gate structure spanning the plurality of fins; A first mask layer with an opening is formed on the gate structure; A first insulating layer is formed on the first mask layer; A patterned sacrificial layer is formed on the first insulating layer; A second insulating layer is formed covering the sacrificial layer; Remove the portion of the second insulating layer covering the area outside the sidewall of the sacrificial layer, and the sacrificial layer itself, leaving the portion of the second insulating layer covering the sidewall of the sacrificial layer as a sidewall; A third insulating layer is formed around the sidewall; The sidewalls are removed to form a trench defined by the third insulating layer, wherein the orthographic projection of a first portion of the trench onto the substrate lies within the orthographic projection of the opening onto the substrate and overlaps with the orthographic projection of the gate structure onto the substrate; as well as Etching is performed to remove a portion of the gate structure along the first portion of the trench, thereby truncating the gate structure.

2. The method according to claim 1, wherein: The substrate structure includes a plurality of gate structures, and the first mask layer has a plurality of openings. The trench has a plurality of spaced-apart first portions, the orthographic projections of different first portions on the substrate being within the orthographic projections of different openings on the substrate, and overlapping with the orthographic projections of different gate structures on the substrate.

3. The method according to claim 2, wherein, The orthographic projection of at least one of the first portions of the trench onto the substrate overlaps with the orthographic projections of at least two of the gate structures onto the substrate.

4. The method according to claim 2 or 3, wherein, The orthographic projection of at least one of the first portions of the trench onto the substrate overlaps with the orthographic projection of one of the gate structures onto the substrate.

5. The method according to any one of claims 1-3, wherein, The second portion of the trench is projected onto the substrate in an orthographic projection that falls within the first mask layer's orthographic projection onto the substrate. The etching process includes: Using the first mask layer as a stop layer, a portion of the first insulating layer located on the first mask layer is removed along the second portion of the trench.

6. The method according to claim 5, wherein, The etching process includes: Perform a first etching to remove a portion of the first insulating layer located on the first mask layer along the second portion of the trench, and to remove another portion of the first insulating layer located on the gate structure along the first portion of the trench; and A second etching is performed to remove a portion of the gate structure along the first portion of the trench, thereby trunculating the gate structure.

7. The method according to claim 1, wherein, Forming a first mask layer with an opening on the gate structure includes: A fourth insulating layer is formed on the gate structure; A first masking material layer is formed on the fourth insulating layer; and The first mask material layer is patterned to form the first mask layer.

8. The method according to claim 7, further comprising: After the gate structure is cut off, the first mask layer is removed using the fourth insulating layer as a stop layer.

9. The method according to claim 7, wherein, The fourth insulating layer is made of a different material than the first insulating layer.

10. The method according to claim 1, wherein, Forming a third insulating layer around the sidewall includes: A third insulating material layer is formed covering the sidewalls; and A portion of the third insulating material layer is removed so that the upper surface of the remaining portion of the third insulating material layer is flush with the upper surface of the sidewall, and the remaining portion of the third insulating material layer serves as the third insulating layer.

11. The method according to claim 1, wherein, The thickness of the sacrificial layer is 50 nanometers to 100 nanometers.

12. The method according to claim 1, wherein, The thickness of the second insulating layer is 10 nanometers to 40 nanometers.

13. The method according to claim 1, wherein, The material of the first mask layer includes metal nitrides.

14. The method according to claim 1, wherein, The gate structure is a pseudo-gate structure.

15. The method according to claim 1, wherein, The materials of the first insulating layer and the second insulating layer are different.

16. A semiconductor device, comprising: The substrate structure includes a substrate, a plurality of fins spaced apart on the substrate, and a plurality of gate structures extending along a first direction, wherein two adjacent gate structures are separated by trenches in the first direction, and each gate structure spans at least one fin. as well as A first mask layer with an opening is located on the plurality of gate structures, wherein the orthogonal projection of the portion of the trench located between two adjacent gate structures onto the substrate lies within the orthogonal projection of the opening onto the substrate.

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