A low-resistance and high-reliability trench gate silicon carbide VDMOS and a preparation method thereof

Abstract

The present invention provides a low-resistance and high-reliability trench-gate silicon carbide VDMOS and a preparation method thereof, comprising: depositing metal on the lower side of a silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; forming a barrier layer, etching, and ion implanting to form a masking layer, a buried layer, a P-type well region, a P-type source region, and an N-type source region; reforming the barrier layer, etching to form a first groove, and oxidizing to form an insulating dielectric layer, wherein a groove is provided on the insulating dielectric layer; reforming the barrier layer, etching, and depositing to form a gate metal layer and a source metal layer, wherein the low resistance and high reliability of the device are achieved by designing the masking layer and the buried layer structure.

Description

Technical Field

[0001] The invention relates to a low-resistance and high-reliability trench gate silicon carbide VDMOS and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and is widely used in electric vehicles, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the requirements for device performance in different fields have different focuses, but the overall requirements are higher voltage resistance, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), and lower body diode conduction loss. Low resistance and high reliability can effectively improve the efficiency and reliability of systems developed based on power devices, so they have become the goals that device design constantly pursues. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a low-resistance and high-reliability trench gate silicon carbide VDMOS and a preparation method thereof, and achieve both low resistance and high reliability of the device through the design of the masking layer and the buried layer structure.

[0004] In a first aspect, the present invention provides a method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS, comprising the following steps:

[0005] Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer;

[0006] Step 2, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and ion implanting to form a masking layer;

[0007] Step 3, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implanting to form a buried layer;

[0008] Step 4, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implanting to form a P-type well region;

[0009] Step 5, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implanting to form a P-type source region;

[0010] Step 6, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implanting to form an N-type source region;

[0011] Step 7, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer, the P-type well region, the buried layer and the masking layer to form a first groove, and oxidizing to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a groove;

[0012] Step 8, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer;

[0013] Step 9: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer to the upper side of the P-type well region, deposit metal to form a source metal layer, remove the barrier layer, and complete the preparation.

[0014] In a second aspect, the present invention provides a low-resistance and high-reliability trench gate silicon carbide VDMOS, wherein the silicon carbide VDMOS is prepared by the method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the first aspect.

[0015] The advantages of the present invention are:

[0016] 1. The masking layer of the present invention is distributed just below the corner of the device trench gate, which can effectively protect the gate reliability problem caused by the electric field concentration at the corner of the trench gate;

[0017] Second, the buried layer of the present invention is divided into two parts, one part is distributed in the area directly below the gate, which can realize the shielding of the gate to the drain capacitance, reduce the gate-drain capacitance of the device and improve the switching speed of the device, and the other part is distributed on the left and right sides of the gate of the device, and contacts the P-type well area of ​​the device close to the gate insulating medium, which can effectively reduce the on-resistance of the conductive channel area of ​​the device;

[0018] 3. The cross-distribution structure of the masking layer and the buried layer can protect the trench gate and reduce the on-resistance, thereby achieving both low resistance and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0020] Figure 1 The schematic diagram of the low-resistance and high-reliability trench-gate silicon carbide VDMOS of the present invention is shown.

[0021] Figure 2 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 1 .

[0022] Figure 3 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 2 .

[0023] Figure 4 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 3 .

[0024] Figure 5A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 4 .

[0025] Figure 6 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 5 .

[0026] Figure 7 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 6 .

[0027] Figure 8 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 7 .

[0028] Fig. 9 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 8 .

[0029] Fig.10 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 9 .

[0030] Fig.11 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 10 .

[0031] Fig.12 A cross-sectional view of the process of manufacturing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to the present invention Figure 10 one. DETAILED DESCRIPTION

[0032] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0034] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0035] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0036] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0037] like Figures 1 to 12 As shown, the embodiment of the present application provides a method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS, comprising the following steps:

[0038] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110; epitaxially growing a drift layer 102 on the upper side of the silicon carbide substrate 101;

[0039] Step 2: forming a barrier layer 111 on the drift layer 102, etching the barrier layer 111 to form a through hole, and performing ion implantation to form a masking layer 104;

[0040] Step 3, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and ion implanting to form a buried layer 103;

[0041] Step 4, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and ion implanting to form a P-type well region 106;

[0042] Step 5, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and ion implanting to form a P-type source region 105;

[0043] Step 6, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and ion implanting to form an N-type source region 1061;

[0044] Step 7, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, and etching the drift layer 102, the P-type well region 106, the buried layer 103 and the masking layer 104 to form a first groove 1021, and oxidizing to form an insulating dielectric layer 107, wherein the insulating dielectric layer 107 is provided with a groove 1071;

[0045] Step 8, removing the original barrier layer 111, re-forming the barrier layer 111, etching the barrier layer 111 to form a through hole, depositing metal, and forming a gate metal layer 108;

[0046] Step 9, remove the original barrier layer 111, re-form the barrier layer 111, etch the barrier layer 111 to form a through hole, and etch the drift layer 102 to the upper side of the P-type well region 106, deposit metal to form a source metal layer 109, remove the barrier layer 111, and complete the preparation.

[0047] In this embodiment, preferably, the doping concentration of the P-type source region 105 is greater than the doping concentration of the P-type well region 106 , and the doping concentration of the P-type source region 105 is greater than the doping concentration of the drift layer 102 .

[0048] In this embodiment, preferably, the doping concentration of the masking layer 104 is greater than the doping concentration of the buried layer 103 .

[0049] In this embodiment, preferably, both sides of the lower side of the insulating dielectric layer 107 are connected to the upper side of the masking layer 104 .

[0050] In this embodiment, preferably, the upper side surface of the buried layer 103 is higher than the upper side surface of the masking layer 104 .

[0051] In this embodiment, preferably, the lower side of the gate metal layer 108 is lower than the upper side of the drift layer 102 .

[0052] In this embodiment, preferably, the thickness of the P-type source region 105 and the P-type well region 106 are equal.

[0053] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0054] Silicon carbide substrate 101,

[0055] A drift layer 102, wherein the lower side of the drift layer 102 is connected to the upper side of the silicon carbide substrate 101, and a first groove 1021 is provided in the drift layer 102;

[0056] A buried layer 103, wherein the buried layer 103 is disposed in the first groove 1021, and a through hole 1031 and a second groove (not shown in the figure) are disposed in the buried layer 103;

[0057] A masking layer 104, wherein the masking layer 104 is disposed in the through hole 1031;

[0058] A P-type source region 105 , wherein the lower side of the P-type source region 105 is connected to the upper side of the drift layer 102 ;

[0059] A P-type well region 106, wherein the lower side of the P-type well region 106 is connected to the upper side of the drift layer 102 and the upper side of the buried layer 103; the outer side of the P-type well region 106 is connected to the inner side of the P-type source region 105, and an N-type source region 1061 is provided in the P-type well region 106;

[0060] An insulating dielectric layer 107, wherein the lower portion of the insulating dielectric layer 107 is disposed in the second groove, the outer side surface of the insulating dielectric layer 107 is respectively connected to the inner side of the P-type well region 106 and the inner side of the N-type source region 1061, and the lower side surface of the insulating dielectric layer 107 is connected to the masking layer 104 and the buried layer 103; a groove 1071 is disposed in the insulating dielectric layer 107;

[0061] A gate metal layer 108, wherein the gate metal layer 108 is disposed in the groove 1071;

[0062] A source metal layer 109 , wherein the source metal layer 109 is respectively connected to the N-type source region 1061 , the P-type well region 106 , and the P-type source region 105 ;

[0063] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .

[0064] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 102 is 1-5e16cm -3 , the doping concentration of the P-type masking layer 104 is 8-12e17cm -3 , the doping concentration of the N-type buried layer 103 is 1-5e17cm -3 , the doping concentration of the P-type well region 106 is 1-5e17cm -3 , the doping concentration of the N-type source region 1061 is 2-8e18cm -3 , the doping concentration of the P-type source region 105 is 1-5e19cm -3 , the material of the insulating dielectric layer 107 may be silicon dioxide;

[0065] The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of low-resistance ohmic contact with the drain metal layer 111, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse withstand voltage and on-resistance of the device; the doping concentration of the P-type well region 106 is mainly considered in two aspects: one is to achieve the protection of the gate and source structure of the device, so the doping concentration must be high; the other is to ensure that the charge of the gate is small, so a low concentration must be ensured, and a compromise is made between the two; the main function of the P-type shielding layer 104 is to protect the gate corner of the device from being broken down by the concentrated electric field, without affecting the on-characteristics of the device, so the doping concentration there is relatively large ; The doping concentration of the N-type buried layer 103 is mainly to reduce the on-resistance of the device and shield the gate-drain capacitance of the device. In order to reduce the process steps of the device and reduce the manufacturing cost, the doping concentration of the N-type buried layer directly below the device gate and on the left and right sides is the same. The doping concentration on the left and right sides of the device gate cannot be too high, otherwise it will affect the withstand voltage characteristics of the P-type well region of the device. The increase in the doping concentration of the N-type buried layer directly below the device gate can suppress the gate-drain capacitance. This doping concentration is selected as a compromise between the two and the process cost; the N-type source region 1061 and the P-type source region 105 are to reduce the ohmic contact resistance of the device source while preventing the device lattice from being damaged by ion implantation due to too high a concentration, thereby affecting the stability of the device;

[0066] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, the thickness of the N-type drift layer 102 is 30-100 μm, and it is adjusted within the above range according to different requirements for the withstand voltage characteristics of the device. The thickness of the P-type masking layer 104 is 1 μm, the thickness of the N-type buried layer 103 directly below the gate is also 1 μm, the thickness of the N-type buried layer 103 on the left and right sides of the gate is 1.2 μm, the thickness of the P-type well region 106 below the N-type source region 1061 is 600nm, the thickness of the P-type well region 106 below the source metal layer 109 is 1 μm, the thickness of the N-type source region 1061 of the device is 400nm, the thickness of the P-type source region 105 is 1 μm, the thickness of the gate metal layer 108 is 1.22 μm, the thickness of the source metal layer 109 is 300nm, and the bottom thickness of the insulating dielectric layer 107 is 8 0nm, the thickness on both sides is 50nm; the width of the P-type well region 106 accounts for 40-60% of the total width of the device, the width of the gate metal layer 109 accounts for 20-30% of the total width of the device, this is to ensure the freewheeling capability of the device parasitic body diode, the width of the device P-type shielding layer 104 accounts for 40-60% of the width of the insulating dielectric layer 107, this is to ensure that when the device drain voltage impacts, the P-type shielding layer 104 protects the device gate while suppressing the parasitic capacitance of the device gate to the drain, thereby improving the switching speed of the device; the width of the N-type buried layer 103 on the left and right sides of the gate is 500-1000nm, which is designed according to the width of the P-type well region 106 controlled by the gate of the device. If its width continues to increase, it will no longer improve the conduction characteristics of the device, but will affect its withstand voltage characteristics;

[0067] The P-type shielding layer 104 of the present invention is distributed directly below the corner of the device trench gate, which can effectively protect the gate reliability problem caused by the electric field concentration at the corner of the trench gate. The present invention designs an N-type buried layer 103, which is divided into two parts. One part is distributed in the area directly below the gate. This part of the area can realize the shielding of the gate to the drain capacitance, reduce the device gate-drain capacitance and improve the device switching speed. The other part is distributed on the left and right sides of the device's gate and contacts the device's P-type well area 106 close to the gate insulating dielectric layer 107, which can effectively reduce the on-resistance of the device's conductive channel area. The cross-distributed structure of the device's P-type shielding layer 104 and the N-type buried layer 103 can protect the trench gate and reduce the on-resistance, thereby achieving both low resistance and high reliability.

[0068] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS, characterized in that: The steps include: Step 1: depositing metal on the lower side of the silicon carbide substrate to form a drain metal layer; epitaxially growing on the side of the silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and ion implanting to form a masking layer; Step 3, removing the barrier layer of step 2, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implanting to form a buried layer; Step 4, removing the barrier layer of step 3, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implanting to form a P-type well region; Step 5, removing the barrier layer of step 4, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implanting to form a P-type source region; Step 6, removing the barrier layer of step 5, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implanting to form an N-type source region; Step 7, removing the barrier layer of step 6, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer, the P-type well region, the buried layer and the masking layer to form a first groove, and oxidizing to form an insulating dielectric layer, wherein the insulating dielectric layer is provided with a groove; Step 8, removing the barrier layer of step 7, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, and forming a gate metal layer; Step 9, removing the barrier layer of step 8, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to the upper side of the P-type well region, depositing metal to form a source metal layer, removing the barrier layer, and completing the preparation; The buried layer is arranged in the first groove, and a second groove is arranged in the buried layer; the lower part of the insulating dielectric layer is arranged in the second groove, and the lower side of the insulating dielectric layer is connected to the masking layer and the buried layer; the lower side of the P-type source region is connected to the upper side of the drift layer; the lower side of the P-type well region is connected to the upper side of the drift layer and the upper side of the buried layer; the outer side of the P-type well region is connected to the inner side of the P-type source region; and an N-type source region is arranged in the P-type well region.

2. The method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the P-type source region is greater than the doping concentration of the P-type well region, and the doping concentration of the P-type source region is greater than the doping concentration of the drift layer.

3. The method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The doping concentration of the masking layer is greater than the doping concentration of the buried layer.

4. The method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: Both sides of the lower side of the insulating medium layer are connected to the upper side of the shielding layer.

5. The method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The upper side surface of the buried layer is higher than the upper side surface of the shielding layer.

6. The method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The lower side of the gate metal layer is lower than the upper side of the drift layer.

7. The method for preparing a low-resistance and high-reliability trench gate silicon carbide VDMOS according to claim 1, characterized in that: The thickness of the P-type source region is equal to that of the P-type well region.

8. A low-resistance and high-reliability trench gate silicon carbide VDMOS, characterized in that: The silicon carbide VDMOS is prepared by the preparation method described in any one of claims 1 to 7.

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