Semiconductor device, preparation method and electronic equipment

Abstract

The embodiment of the invention discloses a semiconductor device, a preparation method and electronic equipment, the semiconductor device comprises a transistor, a first insulating layer, a first contact, a second insulating layer and a second contact, the second contact is in contact with at least a partial area in the surface of one side, deviating from the first insulating layer, of a second electrode through a second contact hole, therefore, a signal is transmitted to the second electrode through the second contact. Moreover, the first contact is in contact with at least part of the surface of the side, facing the first insulating layer, of the first electrode through the first contact hole, so that power is supplied to the transistor through the first contact. The first electrode comprises the first electrode part and the second electrode part, the second electrode part surrounds the first electrode part in the cross section perpendicular to the first direction, the material of the first electrode part is the same as that of the second electrode, and the material of the second electrode part is the metal compound; consequently, the contact resistance between the first contact and the first electrode part can be reduced by the metal compound.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method and an electronic device. Background Art

[0002] In a semiconductor device, a bottom contact hole is usually provided at the bottom of the semiconductor device, a bottom contact is filled in the bottom contact hole, and a metal line in a backside power delivery network (BSPDN) is electrically connected to a source or drain in a transistor through the bottom contact, thereby using the BSPDN to deliver a power signal to the source or drain of the transistor to supply power to the transistor. However, if the contact resistance between the bottom contact and the source or drain is high, the power consumption of the semiconductor device will increase. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor device, a manufacturing method, and an electronic device for reducing contact resistance and reducing power consumption of the semiconductor device.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a transistor, a first insulating layer, a first contact, a second insulating layer and a second contact, wherein the first insulating layer is arranged on one side of the transistor, and the second insulating layer is arranged on the side of the transistor away from the first insulating layer. In addition, the transistor comprises a channel, a first electrode and a second electrode, wherein the channel has a first end and a second end arranged oppositely in a first direction, the first electrode is arranged on the side of the first end of the channel away from the second end of the channel and in contact with the first end of the channel, and the second electrode is arranged on the side of the second end of the channel away from the first end of the channel and in contact with the second end of the channel. In addition, the second insulating layer has a second contact hole, and the orthographic projection of the second contact hole on the reference plane and the orthographic projection of at least a portion of the surface of the second electrode away from the first insulating layer on the reference plane have an overlapping area, so as to expose at least a portion of the surface of the second electrode away from the first insulating layer through the second contact hole. In order to input a signal to the transistor, the second contact can be contacted with at least a portion of the surface of the second electrode away from the first insulating layer through the second contact hole, so as to transmit a signal to the second electrode through the second contact. Furthermore, in order to supply power to the transistor, the first insulating layer is provided with a first contact hole, and the orthographic projection of the first contact hole on the reference plane overlaps with the orthographic projection of at least a portion of the surface of the first electrode on the side facing the first insulating layer on the reference plane, so as to expose at least a portion of the surface of the first electrode on the side facing the first insulating layer through the first contact hole, and the first contact is in contact with at least a portion of the surface of the first electrode on the side facing the first insulating layer through the first contact hole, so as to supply power to the transistor through the first contact. The first electrode includes a first electrode portion and a second electrode portion, and in a cross section of the first electrode perpendicular to the first direction, the second electrode portion surrounds the first electrode portion, and the material of the first electrode portion is the same as that of the second electrode, and the material of the second electrode portion is a metal compound, so that the contact resistance between the first contact and the first electrode portion can be reduced by the metal compound.

[0005] In addition, the stacking direction of the first insulating layer and the transistor is perpendicular to the reference plane.

[0006] Exemplarily, the metal compound includes metal silicide. For example, the metal silicide includes: one or a combination of titanium silicon compound, cobalt silicon compound, and nickel silicon compound. Of course, the metal silicide can also be other materials, which are not limited here.

[0007] In order to transmit a signal to the first electrode, the second insulating layer is provided with a third contact hole, and the orthographic projection of the third contact hole on the reference plane overlaps with the orthographic projection of at least a portion of the surface of the first electrode on the side away from the first insulating layer on the reference plane, so that at least a portion of the surface of the first electrode on the side away from the first insulating layer is exposed through the third contact hole. In addition, a third contact is also provided in the semiconductor device, and the third contact is contacted with at least a portion of the surface of the first electrode on the side away from the first insulating layer through the third contact hole, so that a signal is transmitted to the first electrode through the third contact.

[0008] In order to reduce the contact resistance between the second contact and the second electrode, the second electrode includes a third electrode portion and a fourth electrode portion, and the fourth electrode portion is arranged on the side of the third electrode portion away from the first insulating layer. In addition, the third electrode portion is made of the same material as the first electrode portion, and the fourth electrode portion is made of the same material as the second electrode portion.

[0009] Exemplarily, a cross-sectional shape of the first electrode in a direction perpendicular to the first direction is a first shape, a cross-sectional shape of the second electrode in a direction perpendicular to the first direction is a second shape, and the first shape is different from the second shape.

[0010] Furthermore, in order to reduce the contact resistance, the semiconductor device is further provided with at least one interface layer. Among them, the at least one interface layer can be provided between the first contact and the side wall of the first contact hole. Alternatively, the at least one interface layer is provided between the first contact and the first electrode. Alternatively, the at least one interface layer is provided between the first contact and the side wall of the first contact hole, and the at least one interface layer is provided between the first contact and the first electrode.

[0011] In the present application, the first insulating layer includes an isolation dielectric layer and an insulating dielectric layer, and the isolation dielectric layer is arranged between the insulating dielectric layer and the transistor. In addition, the isolation dielectric layer includes a first opening that penetrates the isolation dielectric layer in the stacking direction, the insulating dielectric layer covers the surface of the isolation dielectric layer away from the transistor, and the insulating dielectric layer has a through hole, and the orthographic projection of the through hole on the reference plane covers the orthographic projection of the first opening on the reference plane. The first contact hole is formed by making the first opening and the through hole.

[0012] Furthermore, the interface layer includes a low resistivity material. Exemplarily, the material of the interface layer is a semiconductor material. For example, the interface layer may include silicon or silicon and carbon with a high-activity dopant (the high-activity dopant is, for example, one or both of phosphorus and arsenic). In one embodiment, the active dopant concentration is 4E20cm -3 or larger.

[0013] In the transistor, the channel includes: a first connection area, a second connection area, and a channel area arranged between the first connection area and the second connection area, the first electrode contacts the first connection area, and the second electrode contacts the second connection area. The transistor also includes a gate, and the gate covers the channel area through the gate dielectric layer, so that the channel area is controlled by the gate to realize the conduction and disconnection between the first electrode and the second electrode. In addition, the second insulating layer is arranged on both sides of the gate.

[0014] Exemplarily, the channel includes a plurality of channel layers sequentially arranged along the stacking direction, and the plurality of channel layers are arranged at intervals from each other. By surrounding the channel region of each channel layer with a gate through a gate dielectric layer, the transistor in the present application is formed as a gate all around field-effect transistor (GAAFET). Furthermore, the channel layer may be set as a nanosheet channel layer or a nanowire channel layer.

[0015] In addition, the transistor also includes an inner spacer, a gate spacer, and a gate barrier layer. Two inner spacers are respectively arranged between two adjacent channel layers, and the orthogonal projection of one of the two inner spacers on the reference plane has an overlapping area (or coincides) with the orthogonal projection of the first connection area on the reference plane, and the orthogonal projection of the other inner spacer on the reference plane has an overlapping area (or coincides) with the orthogonal projection of the second connection area on the reference plane. The gate spacer is arranged on both sides of the gate, that is, each gate is respectively provided with a gate spacer on both sides, and the orthogonal projection of the gate spacer on one side of the gate on the reference plane has an overlapping area (or coincides) with the orthogonal projection of the first connection area on the reference plane, and the orthogonal projection of the gate spacer on the other side on the reference plane has an overlapping area (or coincides) with the orthogonal projection of the second connection area on the reference plane. And, the gate barrier layer covers the gate, and the orthogonal projection of the gate barrier layer on the reference plane has an overlapping area (or coincides) with the orthogonal projection of the gate on the reference plane. In addition, the surface of the gate barrier layer facing away from the isolation dielectric layer may be substantially flush with the surface of the gate spacer facing away from the isolation dielectric layer.

[0016] In order to further improve the performance of the transistor, the transistor also includes a bottom dielectric isolation (BDI), which is arranged between the channel and the isolation dielectric layer, and the orthographic projection of the BDI on the reference plane and the orthographic projection of the channel on the reference plane have an overlapping area (or coincidence), and there is a gate between the BDI and the channel.

[0017] In addition, an interconnection layer and a carrier wafer are also arranged on the side of the transistor away from the isolation dielectric layer, and the interconnection layer has a first metal interconnection line and a second metal interconnection line, the first metal interconnection line is respectively connected to the second contact and the carrier wafer, and the second metal interconnection line is respectively connected to the third contact and the carrier wafer. Due to the arrangement, the signal can be transmitted on the transmission path formed by the second electrode, the second contact, the first metal interconnection line and the carrier wafer, and the signal can be transmitted on the transmission path formed by the first electrode, the third contact, the second metal interconnection line and the carrier wafer.

[0018] In the second aspect, the embodiment of the present application further provides an electronic device, which includes a circuit board and a semiconductor device, and the semiconductor device is connected to the circuit board. The semiconductor device is a semiconductor device such as the first aspect or various embodiments of the first aspect. In addition, the principle of solving the problem by the electronic device is similar to that of the aforementioned semiconductor device, so the implementation of the electronic device can refer to the implementation of the aforementioned semiconductor device, and the repeated parts will not be repeated.

[0019] In a third aspect, an embodiment of the present application further provides a method for preparing a semiconductor device, comprising:

[0020] An isolation dielectric layer, a transistor and a second insulating layer are formed on a semiconductor substrate; the transistor includes a channel, a first electrode and a second electrode, the channel has a first end and a second end oppositely arranged in a first direction, the first electrode is arranged on a side of the first end of the channel away from the second end of the channel and in contact with the first end of the channel, the second electrode is arranged on a side of the second end of the channel away from the first end of the channel and in contact with the second end of the channel, a substrate fin is provided between the second electrode of the transistor and the semiconductor substrate, the second insulating layer has a second contact hole, the orthographic projection of the second contact hole on a reference plane has an overlapping area with the orthographic projection of at least a part of the surface of the second electrode away from the first insulating layer on the reference plane, the isolation dielectric layer includes a first opening penetrating the isolation dielectric layer in the stacking direction of the isolation dielectric layer and the transistor, and the first opening is filled with a sacrificial contact; wherein the first electrode includes a first electrode portion and a second electrode portion, and in a cross section of the first electrode perpendicular to the first direction, the second electrode portion surrounds the first electrode portion; the material of the second electrode portion is a metal compound;

[0021] Depositing a second contact, wherein the second contact contacts at least a portion of a surface of the second electrode facing away from the first insulating layer through a second contact hole;

[0022] The semiconductor substrate is removed to expose a surface of the isolation dielectric layer facing away from the transistor, a surface of the sacrificial contact facing away from the transistor, and a surface of the substrate fin facing away from the transistor;

[0023] After etching away the substrate fin to expose a portion of the channel away from the transistor, an insulating dielectric layer is deposited on the side of the isolation dielectric layer away from the transistor, so that the insulating dielectric layer covers the surface of the isolation dielectric layer away from the transistor, and the insulating dielectric layer has a through hole, which exposes the first opening and forms a first contact hole with the first opening;

[0024] A first contact is filled in the first contact hole, and the first contact is made to contact at least a portion of the surface of the first electrode facing the isolation dielectric layer through the first contact hole.

[0025] The formation of the isolation dielectric layer, the transistor and the second insulating layer may include the following processes:

[0026] An isolation dielectric layer, a fin structure, a dummy gate structure and a gate sidewall are formed on a semiconductor substrate, so as to define the area where the fin structure is located through the isolation dielectric layer, the fin structure includes a device fin portion and a substrate fin portion which are stacked, the substrate fin portion is arranged between the semiconductor substrate and the device fin portion, the device fin portion includes alternating layers of a sacrificial layer and a channel layer, the dummy gate structure spans the fin structure and covers the channel region of the fin structure, and the gate sidewalls are arranged on both sides of the dummy gate structure;

[0027] Etching and removing the device fins on both sides of the dummy gate structure and the substrate fins at the first end of the device fins facing away from the second end thereof, forming a first opening in the isolation dielectric layer, and retaining the substrate fins in the remaining area;

[0028] depositing a sacrificial contact in the first opening;

[0029] forming a first electrode and a second electrode, and making the first electrode contact with the first end of the device fin, and making the second electrode contact with the second end of the device fin; wherein the first electrode includes a first electrode portion and a second electrode portion, and in a cross section of the first electrode perpendicular to the first direction, the second electrode portion surrounds the first electrode portion; and the material of the second electrode portion is a metal compound;

[0030] forming a second insulating layer on both sides of the dummy gate structure;

[0031] Etching and removing the dummy gate structure to form a gate opening;

[0032] Etching and removing the sacrificial layer in the gate opening of the device fin to form a channel;

[0033] In the gate opening, a gate is formed to surround the channel layer through the gate dielectric layer;

[0034] A second contact hole is formed in the second insulating layer, and at least a portion of a surface of the second electrode facing away from the isolation dielectric layer is exposed through the second contact hole.

[0035] In order to further form the first electrode portion and the second electrode portion, after depositing a sacrificial contact in the first opening, the method further includes:

[0036] A partial area of ​​the sacrificial contact is etched to a set distance, and the sacrificial contact is retained on the side wall of the first opening along the first direction to form a groove in the sacrificial contact, and the set distance is the distance between the surface of the substrate fin facing away from the semiconductor substrate and the surface where the bottom of the groove is located.

[0037] The formation of the first electrode and the second electrode may include the following process: epitaxially growing the first electrode and the second electrode. Then, depositing a metal layer on the surface of the first electrode so that the metal layer surrounds the first electrode in a cross section perpendicular to the first direction. Then, using an annealing process, the first electrode is formed into a first electrode portion and a second electrode portion, and the second electrode portion surrounds the first electrode portion in a cross section perpendicular to the first direction; the material of the second electrode portion is a metal compound.

[0038] In some embodiments, when the annealing process is adopted, the process further includes: reducing the thickness of the metal layer so that the first electrode forms a first electrode portion and a second electrode portion, and in a cross section of the first electrode perpendicular to the first direction, the second electrode portion surrounds the first electrode portion, and the metal layer with reduced thickness surrounds the second electrode portion. Thereafter, etching to remove the metal layer with reduced thickness.

[0039] In some other embodiments, when the annealing process is adopted, it also includes: the metal layer completely enters the first electrode, and at this time, there is no need to etch and remove the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A schematic diagram of the structure of an electronic device in an embodiment of the present application;

[0041] Figure 2a A schematic diagram of a top view of a semiconductor device in an embodiment of the present application;

[0042] Figure 2b for Figure 2a A schematic diagram of a cross-sectional structure along the AA' direction;

[0043] Figure 2c for Figure 2a A schematic diagram of a cross-sectional structure along the BB' direction;

[0044] Figure 2d for Figure 2a A schematic diagram of a cross-sectional structure along the CC' direction;

[0045] Figure 2e for Figure 2a A schematic diagram of a cross-sectional structure along the DD' direction;

[0046] Figure 3a for Figure 2aAnother schematic diagram of a cross-sectional structure along the BB' direction;

[0047] Figure 3b for Figure 2a A schematic diagram of another cross-sectional structure along the DD' direction;

[0048] Figure 4a for Figure 2a Another schematic diagram of a cross-sectional structure along the BB' direction;

[0049] Figure 4b for Figure 2a A schematic diagram of another cross-sectional structure along the CC' direction;

[0050] Figure 5a A schematic diagram of a top view of the structure of a semiconductor device in an embodiment of the present application during the preparation process;

[0051] Figure 5b for Figure 5a Schematic diagram of the cross-sectional structure along the AA' direction;

[0052] Figure 6a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0053] Figure 6b for Figure 6a Schematic diagram of the cross-sectional structure along the AA' direction;

[0054] Figure 6c for Figure 6a Schematic diagram of the cross-sectional structure along the BB' direction;

[0055] Figure 6d for Figure 6a Schematic diagram of the cross-sectional structure along the CC' direction;

[0056] Figure 7a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0057] Figure 7b for Figure 7a Schematic diagram of the cross-sectional structure along the AA' direction;

[0058] Figure 7c for Figure 7a Schematic diagram of the cross-sectional structure along the BB' direction;

[0059] Figure 7d for Figure 7a Schematic diagram of the cross-sectional structure along the CC' direction;

[0060] Figure 8aIt is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0061] Figure 8b for Figure 8a Schematic diagram of the cross-sectional structure along the AA' direction;

[0062] Figure 8c for Figure 8a Schematic diagram of the cross-sectional structure along the BB' direction;

[0063] Figure 8d for Figure 8a Schematic diagram of the cross-sectional structure along the CC' direction;

[0064] Figure 9a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0065] Figure 9b for Figure 9a Schematic diagram of the cross-sectional structure along the AA' direction;

[0066] Fig.9c for Figure 9a Schematic diagram of the cross-sectional structure along the BB' direction;

[0067] Figure 9d for Figure 9a Schematic diagram of the cross-sectional structure along the CC' direction;

[0068] Fig.9e for Figure 9a Schematic diagram of the cross-sectional structure along the DD' direction;

[0069] Fig.10a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0070] Fig.10b for Fig.10a Schematic diagram of the cross-sectional structure along the AA' direction;

[0071] Fig.10c for Fig.10a Schematic diagram of the cross-sectional structure along the BB' direction;

[0072] Fig.10d for Fig.10a Schematic diagram of the cross-sectional structure along the CC' direction;

[0073] Fig.10e for Fig.10a Schematic diagram of the cross-sectional structure along the DD' direction;

[0074] Fig.11aIt is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0075] Fig.11b for Fig.11a Schematic diagram of the cross-sectional structure along the AA' direction;

[0076] Fig.11c for Fig.11a Schematic diagram of the cross-sectional structure along the BB' direction;

[0077] Fig.11d for Fig.11a Schematic diagram of the cross-sectional structure along the CC' direction;

[0078] Fig.11e for Fig.11a Schematic diagram of the cross-sectional structure along the DD' direction;

[0079] Fig.12a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0080] Figure 12b for Fig.12a Schematic diagram of the cross-sectional structure along the AA' direction;

[0081] Fig.12c for Fig.12a Schematic diagram of the cross-sectional structure along the BB' direction;

[0082] Fig.12d for Fig.12a Schematic diagram of the cross-sectional structure along the CC' direction;

[0083] Fig.12e for Fig.12a Schematic diagram of the cross-sectional structure along the DD' direction;

[0084] Fig.13a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0085] Fig.13b for Fig.13a Schematic diagram of the cross-sectional structure along the AA' direction;

[0086] Fig.13c for Fig.13a Schematic diagram of the cross-sectional structure along the BB' direction;

[0087] Fig.13d for Fig.13a Schematic diagram of the cross-sectional structure along the CC' direction;

[0088] Fig.13e for Fig.13aSchematic diagram of the cross-sectional structure along the DD' direction;

[0089] Fig.14a It is another schematic diagram of a top view of the structure of the semiconductor device in the embodiment of the present application during the preparation process;

[0090] Fig.14b for Fig.14a Schematic diagram of the cross-sectional structure along the AA' direction;

[0091] Fig.14c for Fig.14a Schematic diagram of the cross-sectional structure along the BB' direction;

[0092] Fig.14d for Fig.14a Schematic diagram of the cross-sectional structure along the CC' direction;

[0093] Fig.14e for Fig.14a Schematic diagram of the cross-sectional structure along the DD' direction.

[0094] Reference numerals:

[0095] 100-housing; 200-circuit board; 300-semiconductor device; 400-first insulating layer; 410-isolation dielectric layer; 420-insulating dielectric layer; 500-transistor; 510-channel; 511 / 22a / 22b / 22c-channel layer; 521-first electrode; 522-second electrode; 531-gate; 532-gate dielectric layer; 533-inner sidewall; 535-gate sidewall; 534-gate barrier layer; 540-second insulating layer; 550-bottom electrical isolation layer; 710-first contact; 720-second contact; 730-third contact; 810-interconnection layer; 820-carrier wafer; 5211-first electrode portion; 5212-second electrode portion; 5221-third electrode portion; 5222-fourth electrode portion Pole; 711-interface layer; 10-semiconductor substrate; 11-first semiconductor layer; 12-etching barrier layer; 13-second semiconductor layer; F1-first direction; F2-second direction; F3-stacking direction; SC-reference plane; SD1-first surface; SD2-second surface; KK1-first opening; KK2-second opening; KK3-third opening; TG-through hole; TK1-first contact hole; B1-first connection area; B2-second connection area; B3-channel area; 21a, 21b, 21c-sacrificial layer; 20-stacked film layer; 30-initial bottom electrical isolation layer; 20'-fin structure; 23-substrate fin; 41-dummy gate structure; 11'-semiconductor substrate; 710'-sacrificial contact; 521'-metal layer. DETAILED DESCRIPTION

[0096] In the description of the present application, "at least one" means one or more, wherein "a plurality" means two or more. In view of this, "a plurality" may also be understood as "at least two" in the embodiments of the present application. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships, for example, A and / or B, which may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship. In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, the example embodiments can be implemented in a variety of forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present application more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. In addition, the same reference numerals in the figures represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in this application are all explained by taking the drawings as examples, but they can be changed as needed, and the changes are all included in the protection scope of this application. The drawings of this application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0097] In order to facilitate the understanding of the semiconductor device, preparation method and electronic device provided in the embodiment of the present application, the application scenario is first introduced below. The semiconductor device provided in the embodiment of the present application can be widely used in various electronic devices, including various terminal devices and electronic devices. For example, terminal devices include but are not limited to smart phones, smart TVs, smart TV set-top boxes, smart watches, personal computers (personal computers, PCs), wearable devices, smart broadband and other devices. Electronic devices include but are not limited to wireless networks, fixed networks, servers and other communication equipment, as well as device modules, memory and other devices, which are not listed one by one here.

[0098] Figure 1 Schematic diagram of a structure of an electronic device in an embodiment of the present application. Figure 1 The electronic device includes: a housing 100, a circuit board 200 disposed in the housing 100, and a semiconductor device 300 fixed on the circuit board 200. The semiconductor device 300 and the circuit board 200 can be connected by bonding, bonding, etc. to achieve electrical connection between the semiconductor device 300 and the circuit board 200, so that signals can be transmitted between the semiconductor device 300 and the circuit board 200.

[0099] Figure 2a is a schematic diagram of a top view of a semiconductor device in an embodiment of the present application, Figure 2b for Figure 2a A schematic diagram of a cross-sectional structure along the AA' direction, Figure 2c for Figure 2a A schematic diagram of a cross-sectional structure along the BB' direction, Figure 2d for Figure 2a A schematic diagram of a cross-sectional structure along the CC' direction, Figure 2e for Figure 2a A schematic diagram of a cross-sectional structure along the DD' direction. Figure 2a to Figure 2e , the semiconductor device includes: a first insulating layer 400, a transistor 500 and a second insulating layer 540. The first insulating layer 400 and the transistor 500 are stacked, that is, the first insulating layer 400 is arranged on one side of the transistor 500, the first insulating layer 400 has a first contact hole TK1, and the orthographic projection of the first contact hole TK1 on the reference plane SC has an overlapping area with the orthographic projection of at least part of the surface of the first electrode 521 facing the first insulating layer 400 on the reference plane SC. Exemplarily, the first insulating layer 400 includes: an isolation dielectric layer 410 and an insulating dielectric layer 420, and the isolation dielectric layer 410 is arranged between the insulating dielectric layer 420 and the transistor 500. Furthermore, the isolation dielectric layer 410 has a first surface SD1 and a second surface SD2 along the stacking direction F3 of the isolation dielectric layer 410 and the transistor 500, the transistor 500 is arranged on the first surface SD1 of the isolation dielectric layer 410, the second insulating layer 540 is arranged on the side of the transistor 500 away from the isolation dielectric layer 410, and the insulating dielectric layer 420 is arranged on the second surface SD2 of the isolation dielectric layer 410. The isolation dielectric layer 410 includes a first opening KK1, a second opening KK2, and a third opening KK3 extending from the first surface SD1 to the second surface SD2, that is, the first opening KK1, the second opening KK2, and the third opening KK3 extend through the isolation dielectric layer 410 in the stacking direction F3, respectively. The insulating dielectric layer 420 fills the second opening KK2 and the third opening KK3 and covers the second surface SD2 of the isolation dielectric layer 410. The insulating dielectric layer 420 has a through hole TG, and a reference plane SC is set, which is perpendicular to the stacking direction F3. The orthographic projection of the through hole TG on the reference plane SC covers the orthographic projection of the first opening KK1 on the reference plane SC, that is, the orthographic projection of the insulating dielectric layer 420 on the reference plane SC does not overlap with the orthographic projection of the first opening KK1 on the reference plane SC, so that the insulating dielectric layer 420 does not fill the first opening KK1, but exposes the first opening KK1. Based on this, the first opening KK1 and the through hole TG can constitute a first contact hole.

[0100] Continue to refer to Figure 2a to Figure 2eThe transistor 500 includes a channel 510, a first electrode 521, a second electrode 522, one or more gates 531, and a gate dielectric layer 532, wherein the first electrode 521, the channel 510, and the second electrode 522 are arranged along a first direction F1, the gate 531 extends along a second direction F2 and is arranged across the channel 510, the first electrode 521 is arranged at a first end of the channel 510 away from a side of the second end of the channel 510 and contacts the first end of the channel 510, so that the first electrode 521 is electrically connected to the channel 510, and the second electrode 522 is arranged at a second end of the channel 510 away from a side of the first end of the channel 510 and contacts the second end of the channel 510, so that the second electrode 522 is electrically connected to the channel 510. Furthermore, the orthographic projection of the first electrode 521 on the reference plane SC has an overlapping area with the orthographic projection of the first opening KK1 on the reference plane SC, so that at least a portion of the surface of the first electrode 521 facing the isolation dielectric layer 410 is exposed through the first opening KK1. The orthographic projection of the second electrode 522 on the reference plane SC has an overlapping area with the orthographic projection of the second opening KK2 on the reference plane SC, so that at least a portion of the surface of the second electrode 522 facing the isolation dielectric layer 410 is exposed through the second opening KK2. The orthographic projection of the channel 510 on the reference plane SC has an overlapping area with the orthographic projection of the third opening KK3 on the reference plane SC, and the orthographic projection of the first opening KK1 on the reference plane SC and the orthographic projection of the second opening KK2 on the reference plane SC do not overlap with the orthographic projection of the channel 510 on the reference plane SC. In addition, the first opening KK1, the second opening KK2 and the third opening KK3 are connected to each other in the first direction F1, and the side walls of the first opening KK1, the second opening KK2 and the third opening KK3 in the second direction F2 are respectively formed by the isolation dielectric layer 410. Moreover, since the insulating dielectric layer 420 fills the second opening KK2 and the third opening KK3, not only the insulating dielectric layer 420 contacts the surface of the second electrode 522 facing the isolation dielectric layer 410 through the second opening KK2, and the insulating dielectric layer 420 contacts the surface of the channel 510 facing the isolation dielectric layer 410 through the third opening KK3, but also the side wall of the first opening KK1 in the first direction F1 is formed by the insulating dielectric layer 420.

[0101] Continue to refer to Figure 2a to Figure 2e, the channel 510 includes a first connection area B1, a second connection area B2, and a channel area B3 arranged between the first connection area B1 and the second connection area B2, the first electrode 521 contacts the first connection area B1, the second electrode 522 contacts the second connection area B2, and the gate 531 covers the channel area B3 through the gate dielectric layer 532. Further, the channel 510 includes a plurality of channel layers 511 arranged in sequence along the stacking direction F3, and the plurality of channel layers 511 are arranged at intervals from each other, and the gate 531 surrounds the channel area B3 of each channel layer 511 through the gate dielectric layer 532, so that the transistor 500 in the present application is formed as a GAAFET. In addition, the above-mentioned channel layer 511 can be set as a nanosheet channel layer or a nanowire channel layer. It is understandable that the first electrode 521 can be set as the source of the transistor 500 and the second electrode 522 can be set as the drain of the transistor 500. Alternatively, the first electrode 521 may be provided as the drain of the transistor 500 , and the second electrode 522 may be provided as the source of the transistor 500 .

[0102] In addition, the transistor 500 further includes an inner spacer 533, a gate spacer 535, and a gate barrier layer 534. Two inner spacers 533 are respectively disposed between two adjacent channel layers 511, and the orthographic projection of one of the two inner spacers 533 on the reference plane SC has an overlapping area (or coincides) with the orthographic projection of the first connection area B1 on the reference plane SC, and the orthographic projection of the other inner spacer 533 on the reference plane SC has an overlapping area (or coincides) with the orthographic projection of the second connection area B2 on the reference plane SC. The gate spacers 535 are arranged on both sides of the gate 531, that is, each gate 531 is provided with a gate spacer 535 on both sides, and the orthographic projection of the gate spacer 535 on one side of the gate 531 on the reference plane SC has an overlapping area (or coincides) with the orthographic projection of the first connection area B1 on the reference plane SC, and the orthographic projection of the gate spacer 535 on the other side on the reference plane SC has an overlapping area (or coincides) with the orthographic projection of the second connection area B2 on the reference plane SC. In addition, the gate barrier layer 534 covers the gate 531, and the orthographic projection of the gate barrier layer 534 on the reference plane SC has an overlapping area (or coincides) with the orthographic projection of the gate 531 on the reference plane SC. In addition, the surface of the gate barrier layer 534 facing away from the isolation dielectric layer 410 and the surface of the gate spacer 535 facing away from the isolation dielectric layer 410 can be substantially flush.

[0103] In order to further improve the performance of transistor 500, refer to Figure 2b and Figure 2cThe transistor 500 further includes a bottom dielectric isolation layer (BDI) 550, which is disposed between the channel 510 and the isolation dielectric layer 410, and the orthographic projection of the BDI 550 on the reference plane SC has an overlapping region (or coincides) with the orthographic projection of the channel 510 on the reference plane SC, and a gate 531 is provided between the BDI 550 and the channel 510. In addition, when the BDI 550 is provided, the insulating dielectric layer 420 contacts the surface of the BDI 550 facing the isolation dielectric layer 410 through the third opening KK3.

[0104] Continue to refer to Figure 2a to Figure 2e , the second insulating layer 540 is arranged between adjacent gates 531, and a gate spacer 535 is also arranged between the second insulating layer 540 and the gate 531. In order to realize signal transmission to the second electrode 522, a second contact hole is also arranged in the second insulating layer 540, penetrating the second insulating layer 540 along the stacking direction F3, and the orthographic projection of the second contact hole on the reference plane SC and the orthographic projection of at least a part of the surface of the second electrode 522 on the side away from the isolation dielectric layer 410 on the reference plane SC have an overlapping area, so that at least a part of the surface of the second electrode 522 on the side away from the isolation dielectric layer 410 is exposed through the second contact hole. Based on this, a second contact 720 is also arranged in the semiconductor device, and the second contact 720 fills the second contact hole, so that the second contact 720 contacts the surface of the second electrode 522 on the side away from the isolation dielectric layer 410 through the second contact hole, so as to realize electrical connection between the second contact 720 and the second electrode 522. In this way, a signal can be transmitted to the second electrode 522 through the second contact 720.

[0105] In order to achieve signal transmission to the first electrode 521, continue to refer to Figure 2c and Figure 2d , a third contact hole penetrating the second insulating layer 540 along the stacking direction F3 is further provided in the second insulating layer 540, and the orthographic projection of the third contact hole on the reference plane SC overlaps with the orthographic projection of at least a portion of the surface of the first electrode 521 on the side away from the isolation dielectric layer 410 on the reference plane SC, so as to expose at least a portion of the surface of the first electrode 521 on the side away from the isolation dielectric layer 410 through the third contact hole. Based on this, a third contact 730 is further provided in the semiconductor device, and the third contact 730 fills the third contact hole, so that the third contact 730 contacts the surface of the first electrode 521 on the side away from the isolation dielectric layer 410 through the second contact hole, so as to realize the electrical connection between the third contact 730 and the first electrode 521. In this way, a signal can be transmitted to the first electrode 521 through the third contact 730.

[0106] Continue to refer to Figure 2a to Figure 2eAn interconnection layer 810 and a carrier wafer 820 are also provided on the side of the transistor 500 away from the isolation dielectric layer 410. The interconnection layer 810 has a first metal interconnection line and a second metal interconnection line. The first metal interconnection line is respectively connected to the second contact 720 and the carrier wafer 820, and the second metal interconnection line is respectively connected to the third contact 730 and the carrier wafer 820. Due to the arrangement, the signal can be transmitted on the transmission path formed by the second electrode 522, the second contact 720, the first metal interconnection line and the carrier wafer 820, and the signal can be transmitted on the transmission path formed by the first electrode 521, the third contact 730, the second metal interconnection line and the carrier wafer 820.

[0107] In order to realize power supply to transistor 500, continue to refer to Figure 2a to Figure 2e , a first contact 710 is provided at the bottom of the transistor 500 (i.e., the second surface SD2 of the isolation dielectric layer 410), and the first contact 710 fills the first contact hole TK1, and the first contact 710 contacts at least a part of the surface of the first electrode 521 facing the isolation dielectric layer 410 through the first contact hole TK1, so as to realize the electrical connection between the first contact 710 and the first electrode 521, that is, the first contact 710 is equivalent to the bottom contact. Thus, after forming a BSPDN on the side of the isolation dielectric layer 410 away from the transistor 500, the metal line in the BSPDN is electrically connected to the first contact 710, so as to realize the use of the BSPDN to transmit the power signal to the first electrode 521 of the transistor 500, so as to supply power to the transistor 500. In addition, the first electrode 521 includes a first electrode portion 5211 and a second electrode portion 5212, and the material of the first electrode portion is the same as the material of the second electrode, and the material of the second electrode portion is a metal compound. Furthermore, in a cross section of the first electrode 521 perpendicular to the first direction (i.e., the stacking direction), the second electrode portion 5212 surrounds the first electrode portion 5211, so that the metal compound can be disposed around the surface of the first electrode portion 5211. Since the first contact 710 is electrically connected to the first electrode portion 5211 through the metal compound, the contact resistance between the first contact 710 and the first electrode portion 5211 is reduced through the metal compound.

[0108] Exemplarily, the metal compound includes metal silicide. For example, the metal silicide includes: one or a combination of titanium silicon compound, cobalt silicon compound, and nickel silicon compound. Of course, the metal silicide can also be other materials, which are not limited here.

[0109] Reference Figure 2d and Figure 2eThe cross-sectional shape of the first electrode 521 in the direction perpendicular to the second direction F2 is a first shape, the cross-sectional shape of the second electrode 522 in the direction perpendicular to the second direction F2 is a second shape, and the first shape is different from the second shape.

[0110] Furthermore, in order to reduce the contact resistance between the second contact 720 and the second electrode 522, Figure 3a for Figure 2a Another cross-sectional structural diagram along the BB' direction, Figure 3b for Figure 2a Another cross-sectional structural diagram along the DD' direction, refer to Figure 3a and Figure 3b The second electrode 522 includes a third electrode portion 5221 and a fourth electrode portion 5222, and the fourth electrode portion 5222 is disposed on the side of the third electrode portion 5221 away from the first insulating layer 400. In addition, the third electrode portion 5221 is made of the same material as the first electrode portion 5211, and the fourth electrode portion 5222 is made of the same material as the second electrode portion 5212. With this arrangement, the contact resistance between the second contact 720 and the second electrode 522 can be reduced.

[0111] Furthermore, in order to reduce the contact resistance, Figure 4a for Figure 2a Another cross-sectional structural diagram along the BB' direction, Figure 4b for Figure 2a Another cross-sectional structural diagram along the CC' direction, refer to Figure 4a and Figure 4b , an interface layer 711 is also provided in the semiconductor device, wherein the interface layer 711 can be provided between the first contact 710 and the sidewall of the first contact hole TK1, or the interface layer 711 is provided between the first contact 710 and the first electrode 521, or the interface layer 711 is provided between the first contact 710 and the sidewall of the first contact hole TK1, and between the first contact 710 and the first electrode 521. Based on this, the contact resistance between the first contact 710 and the first electrode 521 can be further reduced by the interface layer 711. Moreover, the interface layer 711 includes a low resistivity material. Exemplarily, the material of the interface layer 711 is a semiconductor material. For example, the interface layer 711 may include silicon or silicon and carbon with a high-activity dopant (the high-activity dopant is, for example, one or both of phosphorus and arsenic). In one embodiment, the active dopant concentration is 4E20cm -3 or greater. It is understandable that Figure 3a and Figure 3b One interface layer 711 is used as an example for illustration. In practical applications, two, three or more stacked interface layers 711 may be provided, which is not limited here.

[0112] The present application also provides a method for preparing the semiconductor device, which may include the following contents:

[0113] Reference Figure 5a and Figure 5b , Figure 5a is a schematic diagram of a top view of the structure of a semiconductor device in an embodiment of the present application during the preparation process, Figure 5b for Figure 5a Schematic diagram of the cross-sectional structure along the AA' direction. Exemplarily, a semiconductor substrate 10 is provided, and the semiconductor substrate 10 includes a first semiconductor layer 11, an etch stop layer 12 (Etch stop layer, ESL) and a second semiconductor layer 13, wherein the material of the first semiconductor layer 11 includes but is not limited to Si, Ge, etc., the material of the etch stop layer 12 includes but is not limited to SiGe, SiO2, etc., and the material of the second semiconductor layer 13 includes but is not limited to Si, Ge, etc. Exemplarily, the semiconductor substrate 10 can be set as a silicon-on-insulator (SOI) substrate, in which the bottom silicon layer in the SOI substrate serves as the second semiconductor layer 13, the buried oxide layer (such as SiO2) serves as the etch stop layer 12, and the top silicon layer serves as the first semiconductor layer 11. Afterwards, an initial BDI 30 is epitaxially grown on the first semiconductor layer 11 of the semiconductor substrate 10. Afterwards, sacrificial layers 21a-21c and channel layers 22a-22c are epitaxially grown alternately on the initial BDI 30 to form a stacked film layer 20. Furthermore, the present application does not limit the number of channel layers and sacrificial layers in the stacked film layer 20 , and the number may be, for example, 3 to 7 layers. Figure 4b Take three channel layers and three sacrificial layers as an example for illustration. In addition, the present application does not limit the materials of the sacrificial layer and the channel layer. Different types of sacrificial layer materials may be matched with different channel materials according to the requirements of etching selectivity. The sacrificial layer not only plays a certain supporting role for the channel layer, but also needs to be selectively etched and removed, that is, when etching and removing the sacrificial layer, the material of the sacrificial layer has high selectivity compared with the material of the channel layer. Moreover, the sacrificial layer sometimes needs to provide stress for the channel layer. For example, when the material of the channel layer is Si, the material of the corresponding sacrificial layer can be SiGe, and the material of the initial BDI 30 is SiC or SiGe with a different concentration from that of the sacrificial layer.

[0114] Reference Figures 6a to 6d , Figure 6a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 6b for Figure 6a Schematic diagram of the cross-sectional structure along the AA' direction, Figure 6c for Figure 6a Schematic diagram of the cross-sectional structure along the BB' direction, Figure 6d for Figure 6aSchematic diagram of the cross-sectional structure along the CC' direction. Exemplarily, the above-mentioned stacked film layer 20, the initial BDI 30 and the first semiconductor layer 11 are patterned, and shallow grooves are formed in the first semiconductor layer 11, as well as a plurality of fin structures 20' spaced apart from each other and limited by the shallow grooves. The plurality of fin structures 20' extend along the first direction F1 and are arranged along the second direction F2. In addition, the fin structure 20' includes: a substrate fin 23 and a device fin, the portion of the first semiconductor layer 11 limited by the shallow groove serves as the substrate fin 23, and the portion of the first semiconductor layer 11 between the plane where the bottom of the shallow groove is located and the ESL12 serves as the retained substrate 11'. In addition, the device fin includes: a patterned initial BDI30 and a stacked structure, and the stacked structure includes alternating layers of sacrificial layers 21a~21c and channel layers 22a~22c. In addition, the channel layer in the stacked structure can be formed as a nanosheet channel layer (or a nanowire channel layer). Afterwards, in order to isolate adjacent fin structures 20', a dielectric material may be filled in the shallow trench to form a shallow trench isolation (STI) structure, and the formed STI structure is the isolation dielectric layer 410. Afterwards, a plurality of dummy gate structures 41 are formed that span the channel regions B3 of each stacked structure and are spaced apart from each other, and the plurality of dummy gate structures 41 extend along the second direction F2 and are arranged along the first direction F1. Moreover, the same dummy gate structure 41 may span multiple fin structures 20'. In addition, for silicon-based devices, the dummy gate structure 41 may include a dummy gate electrode layer and a dummy gate oxide layer disposed between the dummy gate electrode layer and the stacked structure. Optionally, the material of the dummy gate electrode layer includes, but is not limited to, polysilicon. Afterwards, gate sidewalls 535 are formed on both sides of the dummy gate structure 41 along the first direction F1 to reduce the short channel effect. Furthermore, the gate spacer 535 covers the surface of the dummy gate structure 41 on the side away from the fin structure 20', and the area where the fin structure 20' is located between the gate spacers 535 of two adjacent dummy gate structures 41 is the source and drain region. Optionally, the dielectric material forming the STI structure includes but is not limited to one or more of SiO2, SiON, and SiNx. Furthermore, the material forming the gate spacer 535 includes but is not limited to one or more of SiNx and SiON. In addition, Figures 6a to 6d In the figure, one fin structure 20 ′ and three dummy gate structures 41 are taken as an example for illustration.

[0115] Reference Figures 7a to 7d , Figure 7a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 7b for Figure 7a Schematic diagram of the cross-sectional structure along the AA' direction, Figure 7c for Figure 7a Schematic diagram of the cross-sectional structure along the BB' direction, Figure 7dfor Figure 7a Schematic diagram of the cross-sectional structure along the CC' direction. Exemplarily, the stacked structure and the initial BDI 30 in the source and drain regions are removed by etching, the dummy gate structure 41 and the stacked structure and the initial BDI 30 below the gate spacer 535 are retained, and the sides of the sacrificial layers 21a-21c and the channel layers 22a-22c below the gate spacer 535 are exposed, and the substrate fin 23 in the source and drain regions is exposed.

[0116] Reference Figures 8a to 8d , Figure 8a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 8b for Figure 8a Schematic diagram of the cross-sectional structure along the AA' direction, Figure 8c for Figure 8a Schematic diagram of the cross-sectional structure along the BB' direction, Figure 8d for Figure 8a Schematic diagram of the cross-sectional structure along the CC' direction. Exemplarily, the initial BDI 30 is removed by isotropic etching, and the BDI film layer is deposited by a deposition process (such as atomic layer deposition). Afterwards, the BDI film layer is etched to retain the BDI film layer under the dummy gate structure 41 and the gate sidewall 535, and the BDI film layer in the remaining area is removed to form BDI550. Optionally, the material forming the BDI film layer includes but is not limited to one or more of SiO2, SiCN, SiON, and SiN. It is understandable that this step is an optional scheme, that is, this step may be performed or not, and is not limited here.

[0117] Reference Figures 9a to 9e , Figure 9a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 9b for Figure 9a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.9c for Figure 9a Schematic diagram of the cross-sectional structure along the BB' direction, Figure 9d for Figure 9a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.9e for Figure 9aSchematic diagram of the cross-sectional structure along the DD' direction. For example, in the source and drain region where the backside contact (BSC) is to be formed, the substrate fin 23 is etched to remove the substrate fin 23 in the region. Since the sidewall of the substrate fin 23 in the region is the isolation dielectric layer 410, after the substrate fin 23 is removed, the first opening KK1 is formed in the isolation dielectric layer 410. Of course, the first semiconductor layer 11 below the substrate fin 23 can be further etched by a certain distance d1 to form a hole below the first opening KK1.

[0118] Reference Figures 10a to 10d , Fig.10a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Fig.10b for Fig.10a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.10c for Fig.10a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.10d for Fig.10a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.10e for Fig.10a Schematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, a sacrificial contact film layer is deposited by a deposition process (such as atomic layer deposition), and the sacrificial contact film layer is etched to retain the sacrificial contact film layer in the first opening KK1 and the hole, and the sacrificial contact film layer in the remaining area is etched away, and the sidewalls of the sacrificial layer 21a~21c and the channel layer 22a~22c under the dummy gate structure 41 and the gate spacer 535 are exposed, thereby forming a sacrificial contact 710' in the first opening KK1 and the hole. Optionally, the material forming the sacrificial contact film layer includes but is not limited to one or more of SiC, Si / Ge, SiN, and C.

[0119] Reference Figures 11a to 11d , Fig.11a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Fig.11b for Fig.11a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.11c for Fig.11a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.11d for Fig.11a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.11e for Fig.11aSchematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, a partial area of ​​the sacrificial contact 710' is etched to a set distance d2, and the sacrificial contact 710' is retained on the side wall of the first opening KK1 along the first direction F1 to form a groove AX in the sacrificial contact 710'. The set distance d2 is the distance between the surface of the substrate fin 23 facing away from the side of the retained substrate 11' and the surface where the bottom of the groove AX is located. The set distance d2 can be determined according to the needs of the actual application to meet the process requirements. It can be understood that this step is an optional scheme, that is, this step can be performed or not, and is not limited here.

[0120] Reference Figures 12a to 12d , Fig.12a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Figure 12b for Fig.12a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.12c for Fig.12a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.12d for Fig.12a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.12e for Fig.12aSchematic diagram of the cross-sectional structure along the DD' direction. Exemplarily, an inner sidewall 533 is formed below the gate sidewall 535. Afterwards, a first electrode 521 and a second electrode 522 connected to the channel layer are epitaxially formed in the source and drain regions on both sides of the dummy gate structure 41. A metal layer 521' is deposited on the surface of the first electrode 521. Due to the presence of the groove AX, the metal layer 521' surrounds the first electrode 521 in a cross section perpendicular to the first direction F1. In addition, a metal layer 521' is also deposited on the side of the second electrode 522 away from ESL12. Afterwards, an annealing process is used to diffuse the material in the metal layer 521' into the surface of the first electrode 521, so that the first electrode 521 forms a first electrode portion 5211 and a second electrode portion 5212, and the second electrode 522 forms a third electrode portion 5221 and a fourth electrode portion 5222. Furthermore, when the annealing process is adopted, the thickness of the metal layer 521' is reduced, so that the first electrode 521 forms a first electrode portion 5211 and a second electrode portion 5212, and the metal layer 521' with reduced thickness surrounds the second electrode portion 5212. Afterwards, the metal layer 521' with reduced thickness is etched away. In practical applications, the metal layer 521' may also enter the first electrode 521 and the second electrode 522 in the annealing process, and then it is not necessary to etch away the metal layer 521'. For example, if the first electrode 521 and the second electrode 522 include Si and a dopant, and the metal layer 521' includes one or a combination of titanium, titanium and nickel, a self-aligned silicide process can be used to form metal silicide on the surface of the first electrode 521 and the second electrode 522, thereby reducing the contact resistance.

[0121] Reference Figures 13a to 13d , Fig.13a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Fig.13b for Fig.13a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.13c for Fig.13a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.13d for Fig.13a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.13e for Fig.13aSchematic diagram of the cross-sectional structure along the DD' direction in FIG. 4 . Exemplarily, a second insulating layer 540 is deposited on the first electrode 521 and the second electrode 522, and the second insulating layer 540 also enters the groove through the gap between the first electrode 521 and the groove to fill the groove. Afterwards, the dummy gate structure 41 is etched away to form a gate opening. Afterwards, the sacrificial layer in the gate opening is etched away to release the channel region of the channel layer 22a to 22c. A dielectric material with a high dielectric constant (for example, a dielectric material with a dielectric constant greater than that of silicon oxide) is sampled to form a gate dielectric layer 532 coated on the channel region B3. In the gate opening, a gate 531 is formed surrounding each channel region. Exemplarily, the gate 531 is a metal gate 531, wherein the metal gate 531 is generally a multi-layer structure, which includes but is not limited to a combination of a work function metal (possibly multiple layers of work function metal), a liner layer, a wetting layer, an adhesion layer, a metal conductive layer or a metal silicide. For example, the metal gate 531 includes but is not limited to titanium (Ti), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), titanium aluminum (TiAl), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), tungsten (W), etc. Afterwards, a second contact hole is formed in the second insulating layer 540 on the first electrode 521 to expose a partial area or the entire area of ​​the surface of the first electrode 521 away from the ESL12 through the second contact hole. In addition, a first contact hole is formed in the second insulating layer 540 on the second electrode 522 to expose a partial area or the entire area of ​​the surface of the second electrode 522 away from the ESL12 through the first contact hole. Afterwards, a metal material is deposited and a third contact 730 is filled in the second contact hole so that the third contact 730 contacts the first electrode 521 through the second contact hole, thereby realizing electrical connection between the third contact 730 and the first electrode 521. Furthermore, the second contact 720 is filled in the first contact hole, so that the second contact 720 contacts the second electrode 522 through the first contact hole, thereby achieving electrical connection between the second contact 720 and the second electrode 522 .

[0122] Reference Figures 14a to 14d , Fig.14a FIG. 1 is another schematic top view of the semiconductor device in the embodiment of the present application during the preparation process. Fig.14b for Fig.14a Schematic diagram of the cross-sectional structure along the AA' direction, Fig.14c for Fig.14a Schematic diagram of the cross-sectional structure along the BB' direction, Fig.14d for Fig.14a Schematic diagram of the cross-sectional structure along the CC' direction, Fig.14e for Fig.14aSchematic diagram of the cross-sectional structure along the DD' direction. For example, an interconnection layer 810 is formed on the side of the transistor 500 away from the ESL12, and a carrier wafer 820 is bonded to the side of the interconnection layer 810 away from the ESL12. Afterwards, the semiconductor device is turned over, and the back side of the semiconductor substrate 10 is thinned by a thinning process to remove the second semiconductor layer 13, and the thinning stops at the interface between the ESL12 and the second semiconductor layer 13. Afterwards, the ESL12 is removed by etching. Afterwards, the retained substrate 11' is removed by etching to expose the sacrificial contact 710'.

[0123] Reference Figure 2a , Figure 2b , Figure 2d , Figure 3a as well as Figure 3b , exemplarily, the substrate fin 23 on the side of BDI220 away from the channel layer is etched away, and the substrate fin 23 on the side of the second electrode 522 away from the second contact 720 is removed, and the second opening KK2 and the third opening KK3 are formed in the isolation dielectric layer 410. Afterwards, an insulating dielectric layer 420 is deposited on the side of the isolation dielectric layer 410 away from BDI550, and the insulating dielectric layer 420 fills the second opening KK2 and the third opening KK3, and the insulating dielectric layer 420 covers the surface of the isolation dielectric layer 410 away from the BDI side. Afterwards, the insulating dielectric layer 420 is planarized by a chemical mechanical polishing (CMP) process to expose the surface of the sacrificial contact away from the BDI side. It is understandable that the material of the insulating dielectric layer 420 may be the same as or different from the material of the isolation dielectric layer 410, and is not limited here. Afterwards, the sacrificial contact 710' is removed by etching, and a part or all of the surface of the first electrode 521 facing the insulating dielectric layer 420 is exposed through the first opening KK1. Afterwards, a metal layer is deposited on the side of the insulating dielectric layer 420 away from the isolation dielectric layer 410, and the metal layer fills the first opening KK1, and the metal layer covers the surface of the insulating dielectric layer 420 away from the BDI550. Afterwards, the metal layer is planarized by a CMP process, and the metal layer covering the surface of the insulating dielectric layer 420 away from the BDI550 is removed, exposing the insulating dielectric layer 420, thereby forming the first contact 710 in the first opening KK1. Alternatively, refer to Figure 4a and Figure 4b, an interface layer is deposited on the side of the insulating dielectric layer 420 away from the isolation dielectric layer 410, and the interface layer covers the surface of the first electrode in the first opening KK1, and covers the sidewall of the first opening KK1. Then, a metal layer is deposited on the side of the insulating dielectric layer 420 away from the isolation dielectric layer 410, and the metal layer fills the first opening KK1, and the metal layer covers the surface of the insulating dielectric layer 420 away from the BDI550. Then, the metal layer is planarized by a CMP process, and the metal layer covering the surface of the insulating dielectric layer 420 away from the BDI550 is removed, exposing the insulating dielectric layer 420, thereby forming a first contact 710 in the first opening KK1.

[0124] The above contents are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: A transistor, comprising a channel, a first electrode and a second electrode, wherein the channel has a first end and a second end arranged opposite to each other in a first direction, the first electrode is arranged at a side of the first end of the channel away from the second end of the channel and in contact with the first end of the channel, and the second electrode is arranged at a side of the second end of the channel away from the first end of the channel and in contact with the second end of the channel; wherein the first electrode comprises a first electrode portion and a second electrode portion, and in a cross section of the first electrode perpendicular to the first direction, the second electrode portion surrounds the first electrode portion; the material of the first electrode portion is the same as that of the second electrode, and the material of the second electrode portion is a metal compound; a first insulating layer, disposed on one side of the transistor, the first insulating layer having a first contact hole, an orthographic projection of the first contact hole on a reference plane and an orthographic projection of at least a portion of a surface of the first electrode facing the first insulating layer on the reference plane having an overlapping area, and a stacking direction of the first insulating layer and the transistor being perpendicular to the reference plane; a first contact, the first contact being in contact with at least a portion of a surface of the first electrode facing the first insulating layer through the first contact hole; A second insulating layer is provided on a side of the transistor away from the first insulating layer, the second insulating layer having a second contact hole, an orthographic projection of the second contact hole on a reference plane and an orthographic projection of at least a portion of a surface of the second electrode away from the first insulating layer on the reference plane having an overlapping area; A second contact point is provided, wherein the second contact point contacts at least a portion of a surface of the second electrode on a side facing away from the first insulating layer through the second contact hole.

2. The semiconductor device according to claim 1, wherein The metal compound includes a metal silicide.

3. The semiconductor device according to claim 2, wherein: The metal silicide includes: one or a combination of titanium silicon compounds, cobalt silicon compounds, and nickel silicon compounds.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The second insulating layer further has a third contact hole, and an orthographic projection of the third contact hole on the reference plane has an overlapping area with an orthographic projection of at least a portion of a surface of the first electrode on a side away from the first insulating layer on the reference plane; The semiconductor device further includes a third contact, wherein the third contact contacts at least a portion of a surface of the first electrode on a side facing away from the first insulating layer through the third contact hole.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The second electrode includes a third electrode portion and a fourth electrode portion, and the fourth electrode portion is arranged on a side of the third electrode portion away from the first insulating layer; The third electrode portion is made of the same material as the first electrode portion, and the fourth electrode portion is made of the same material as the second electrode portion.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The cross-sectional shape of the first electrode perpendicular to the first direction is a first shape, and the cross-sectional shape of the second electrode perpendicular to the first direction is a second shape, and the first shape is different from the second shape.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The semiconductor device further comprises: at least one interface layer; The at least one interface layer is disposed between the first contact and the sidewall of the first contact hole; and / or, The at least one interface layer is disposed between the first contact and the first electrode.

8. The semiconductor device according to claim 7, wherein: The first insulating layer includes: an isolation dielectric layer and an insulating dielectric layer, wherein the isolation dielectric layer is arranged between the insulating dielectric layer and the transistor; The isolation dielectric layer comprises a first opening penetrating the isolation dielectric layer in the stacking direction, the insulating dielectric layer covers the surface of the isolation dielectric layer facing away from the transistor, and the insulating dielectric layer has a through hole, and the orthographic projection of the through hole on the reference plane covers the orthographic projection of the first opening on the reference plane; The first contact hole includes the first opening and the through hole.

9. The semiconductor device according to claim 7 or 8, characterized in that The material of the interface layer is semiconductor material.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The channel includes: a first connection region, a second connection region, and a channel region disposed between the first connection region and the second connection region, the first electrode is connected to the first connection region, and the second electrode is connected to the second connection region; The transistor further includes a gate, and the gate covers the channel region via a gate dielectric layer.

11. The semiconductor device according to claim 10, wherein: The channel includes: a plurality of channel layers stacked together, and the gate surrounds a channel region of each channel layer via the gate dielectric layer.

12. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in any one of claims 1 to 11, wherein the semiconductor device is connected to the circuit board.

13. A method for preparing a semiconductor device, characterized in that: include: An isolation dielectric layer, a transistor and a second insulating layer are formed on a semiconductor substrate; the transistor comprises a channel, a first electrode and a second electrode, the channel has a first end and a second end arranged opposite to each other in a first direction, the first electrode is arranged on a side of the first end of the channel away from the second end of the channel and in contact with the first end of the channel, the second electrode is arranged on a side of the second end of the channel away from the first end of the channel and in contact with the second end of the channel, a substrate fin is provided between the second electrode of the transistor and the semiconductor substrate, the second insulating layer has a second contact hole, the orthographic projection of the second contact hole on a reference plane has an overlapping area with the orthographic projection of at least a part of the surface of the second electrode away from the first insulating layer on the reference plane, the isolation dielectric layer comprises a first opening penetrating the isolation dielectric layer in the stacking direction of the isolation dielectric layer and the transistor, the first opening is filled with a sacrificial contact; wherein the first electrode comprises a first electrode portion and a second electrode portion, and in a cross section of the first electrode perpendicular to the first direction, the second electrode portion surrounds the first electrode portion; the material of the second electrode portion is a metal compound; Depositing a second contact, wherein the second contact contacts at least a portion of a surface of the second electrode facing away from the first insulating layer through the second contact hole; Removing the semiconductor substrate to expose a surface of the isolation dielectric layer facing away from the transistor, a surface of the sacrificial contact facing away from the transistor, and a surface of the substrate fin facing away from the transistor; After etching away the substrate fin to expose a portion of the channel away from the transistor, an insulating dielectric layer is deposited on the side of the isolation dielectric layer away from the transistor, so that the insulating dielectric layer covers the surface of the isolation dielectric layer away from the transistor, and the insulating dielectric layer has a through hole, which exposes the first opening and forms a first contact hole with the first opening; A first contact is filled in the first contact hole, and the first contact is made to contact at least a portion of the surface of the first electrode facing the isolation dielectric layer through the first contact hole.

14. The preparation method according to claim 13, characterized in that: The step of forming an isolation dielectric layer, a transistor and a second insulating layer on a semiconductor substrate comprises: The isolation dielectric layer, the fin structure, the dummy gate structure and the gate sidewalls are formed on the semiconductor substrate, so as to define the area where the fin structure is located through the isolation dielectric layer, the fin structure includes a device fin portion and a substrate fin portion which are stacked, the substrate fin portion is arranged between the semiconductor substrate and the device fin portion, the device fin portion includes alternating layers of a sacrificial layer and a channel layer, the dummy gate structure spans the fin structure and covers the channel region of the fin structure, and the gate sidewalls are arranged on both sides of the dummy gate structure; Etching and removing the device fins on both sides of the dummy gate structure and the substrate fins at the first end of the device fins facing away from the second end thereof, forming a first opening in the isolation dielectric layer, and retaining the substrate fins in the remaining area; depositing a sacrificial contact in said first opening; forming a first electrode and a second electrode, and making the first electrode contact with the first end of the device fin, and making the second electrode contact with the second end of the device fin; wherein the first electrode includes a first electrode portion and a second electrode portion, and in a cross section of the first electrode perpendicular to the first direction, the second electrode portion surrounds the first electrode portion; and the material of the second electrode portion is a metal compound; forming a second insulating layer on both sides of the dummy gate structure; Etching and removing the dummy gate structure to form a gate opening; Etching and removing the sacrificial layer in the gate opening in the device fin to form a channel; In the gate opening, a gate is formed to surround the channel layer via a gate dielectric layer; A second contact hole is formed in the second insulating layer, and at least a portion of a surface of the second electrode facing away from the isolation dielectric layer is exposed through the second contact hole.

15. The preparation method according to claim 14, characterized in that: After depositing a sacrificial contact in the first opening, the method further comprises: A partial area of ​​the sacrificial contact is etched to a set distance, and the sacrificial contact is retained on the side wall of the first opening along the first direction to form a groove in the sacrificial contact, wherein the set distance is the distance between the surface of the substrate fin facing away from the semiconductor substrate and the surface where the bottom of the groove is located.

16. The preparation method according to claim 15, characterized in that: The forming of the first electrode and the second electrode comprises: epitaxially growing the first electrode and the second electrode; Depositing a metal layer on the surface of the first electrode so that the metal layer surrounds the first electrode in a cross section of the first electrode perpendicular to the first direction; The first electrode is formed into the first electrode portion and the second electrode portion by an annealing process. In a cross section of the first electrode perpendicular to the first direction, the second electrode portion surrounds the first electrode portion. The material of the second electrode portion is a metal compound.

17. The preparation method according to claim 16, characterized in that: Also includes: When the annealing process is adopted, the thickness of the metal layer is reduced, so that the first electrode forms a first electrode portion and a second electrode portion, and in a cross section of the first electrode perpendicular to the first direction, the second electrode portion surrounds the first electrode portion, and the metal layer with reduced thickness surrounds the second electrode portion; The metal layer with reduced thickness is removed by etching.

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