A novel heterojunction field plate gallium oxide mosfet device

Abstract

The application belongs to the technical field of power semiconductors, and relates to a novel heterojunction field plate gallium oxide MOSFET device. The heterojunction field plate is composed of P-type oxide above the drift region and regrown gallium oxide on the drain side, can play a role of modulating the surface electric field distribution of the device, and improves the voltage resistance of the device. The P-type oxide and the drift region gallium oxide are similar to the P / N columns of super junction, introduce auxiliary depletion effect, improve the doping concentration of the drift region, reduce the on-resistance, and do not have the substrate auxiliary depletion effect of the silicon-based lateral device, and can better regulate the charge balance. The P-type oxide adopts a sputtering process, avoiding the interface problem caused by etching.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductors, and relates to a novel heterojunction field plate gallium oxide MOSFET device. BACKGROUND

[0002] The development of power supplies, motor drives and electric vehicles puts forward higher requirements for energy-saving electronic systems and high-efficiency semiconductor power devices. Among all emerging semiconductor materials, beta-Ga2O3 has a super-wide band gap of 4.5-4.9 eV and a theoretical breakdown field strength (E C ) of up to 8 MV / cm, which has a unique advantage compared with SiC / GaN materials. With the continuous development of Ga2O3 power devices, in order to fully utilize the high critical breakdown field strength of Ga2O3 to realize high breakdown voltage (BV), various electric field management strategies are adopted, including vertical fin-type channel structure, field plate structure, super junction (SJ) technology and heterojunction gate, but some structures inevitably introduce process complexity and negative effects. Due to the trade-off between R ON，SP and BV, the specific on-resistance (R ON，SP ) will increase when high breakdown voltage (BV) is obtained, and the device performance needs to be further improved. SUMMARY

[0003] The purpose of the application is to provide a novel heterojunction field plate gallium oxide MOSFET device to solve the above problems.

[0004] The technical scheme of the application is as follows:

[0005] A novel heterojunction field plate gallium oxide MOSFET device, comprising a gallium oxide substrate layer 1, a gallium oxide buffer layer 2 and a gallium oxide epitaxial layer 3 which are sequentially stacked in the vertical direction of the device from bottom to top.

[0006] Characterized in that the N+ source region 5 and the N+ drain region 6 are respectively arranged at both ends of the upper surface of the gallium oxide epitaxial layer 3, and the bottoms of the N+ source region 5 and the N+ drain region 6 are embedded in the upper layer of the gallium oxide epitaxial layer 3; the source electrode 11 and the drain electrode 12 are respectively arranged on the upper surfaces of the N+ source region 5 and the N+ drain region 6; the dielectric layer 10 is arranged on the upper surface of the gallium oxide epitaxial layer 3 between the N+ source region 5 and the N+ drain region 6, and the upper surface of the dielectric layer 10 is flush with the upper surfaces of the N+ source region 5 and the N+ drain region 6 in the lateral direction of the device; the first P-type oxide 8 and the second P-type oxide 7 are connected on the side of the dielectric layer 10 which is in contact with the N+ drain region 6, and the side surface of the second P-type oxide 7 is in contact with the side surface of the N+ drain region 6, so that the first P-type oxide 8, the second P-type oxide 7 and the N+ drain region 6 form a heterojunction field plate structure; the HFP electrode 13 is arranged on the upper surface of the first P-type oxide 8, and the HFP electrode 13 is connected with the source electrode 11.

[0007] A gate electrode 9 is provided in the dielectric layer 10 between the first P-type oxide 8 and the N+ source region 5, the lower end of the gate electrode 9 is embedded in the dielectric layer 10 and has a spacing with the upper surface of the gallium oxide epitaxial layer 3, the upper end of the gate electrode 9 extends out of the dielectric layer 10, the two ends of the gate electrode 9 have a spacing with the N+ source region 5 and the first P-type oxide 8, a thermal oxidation region 4 is provided in the gallium oxide epitaxial layer 3 below the gate electrode 9, the thermal oxidation region 4 penetrates the gallium oxide epitaxial layer 3 in the vertical direction, the lower surface of the thermal oxidation region 4 is in contact with the upper surface of the gallium oxide buffer layer 2, and the upper surface of the thermal oxidation region 4 is in contact with the lower surface of the dielectric layer 10.

[0008] Further, the first P-type oxide 8 and the second P-type oxide 7 adopt nickel oxide as the material.

[0009] The beneficial effects of the present application are:

[0010] 1) The structure can modulate the surface electric field distribution of the device by introducing a heterojunction field plate, and improve the device withstand voltage.

[0011] 2) The P-type oxide and the drift region gallium oxide are similar to the P / N columns of super junction, which introduces auxiliary depletion effect, increases the doping concentration of the drift region, and reduces the on-resistance.

[0012] 3) Without the substrate auxiliary depletion effect of silicon-based lateral devices, the charge balance can be better controlled.

[0013] 4) The P-type oxide adopts a sputtering process, which avoids the interface problems caused by etching.

[0014] 5) The local thermal oxidation region under the gate can better deplete the channel and realize the enhancement mode device. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of example 1;

[0016] Figure 2 It is a process flow schematic diagram of the new heterojunction field plate gallium oxide MOSFET device. DETAILED DESCRIPTION

[0017] The technical solutions of the present application will be described in detail below in combination with the drawings and examples:

[0018] Example 1

[0019] As Figure 1As shown, the novel heterojunction field plate gallium oxide MOSFET device of this example includes a gallium oxide substrate layer 1, a gallium oxide buffer layer 2, and a gallium oxide epitaxial layer 3 arranged sequentially from bottom to top along the vertical direction of the device. A locally thermally oxidized region 4 is located below the gate in the gallium oxide epitaxial layer 3. N+ source regions 5 and N+ drain regions 6 are located on the upper surface of the epitaxial layer 3 near the source and drain electrodes, respectively. The upper surface of these regions is respectively the source electrode 11 and the drain electrode 12. A dielectric layer 10 lies between the N+ source regions 5 and N+ drain regions 6. The dielectric layer 10 has a heterojunction field plate structure near the drain; the heterojunction field plate structure is composed of a first P-type oxide 8, a second P-type oxide 7 and an N+ drain region 6; the first P-type oxide 8 and the second P-type oxide 7 are located in the dielectric layer 10 near the drain, and the second P-type oxide 7 is in contact with the drain region 10; the gate electrode 9 is located in the dielectric layer 10 near the source and is not in contact with the first P-type oxide 8; the first P-type oxide 8 leads out an HFP electrode 13 and short-circuit it with the source electrode 11.

[0020] The working principle of this example is as follows:

[0021] This invention proposes a novel heterojunction field plate gallium oxide MOSFET device. When the applied gate voltage is less than the threshold voltage and the drain voltage is greater than 0, the device is in the off state. The first P-type oxide 8 and the second P-type oxide 7 in the heterojunction field plate structure help to deplete the gallium oxide epitaxial layer 3, similar to the P / N pillars of a superjunction structure, thereby regulating the electric field distribution and improving the device's breakdown voltage. Simultaneously, the diode reverse bias formed by the P-type oxide and the N+ drain region 6 helps suppress leakage current in the heterojunction field plate HFP. When the gate voltage is greater than the threshold voltage, the auxiliary depletion effect of the heterojunction field plate structure can increase the doping concentration of the gallium oxide epitaxial layer 3, thereby reducing the on-resistance of the device in the on-state.

[0022] like Figure 2 As shown in (a)-(h) in the diagram, this is a schematic diagram of the process flow of Embodiment 1 of the present invention. The process steps are as follows:

[0023] 1) Remove the gallium oxide substrate sample and clean the sample surface.

[0024] 2) An unintentionally doped layer and a gallium oxide drift region of a certain concentration are grown on a gallium oxide substrate by MOCVD to form a gallium oxide buffer layer 2 and a gallium oxide epitaxial layer 3.

[0025] 3) Use MOCVD to regenerate N+ epitaxy to form N+ source region 5 and N+ drain region 6.

[0026] 4) The deposited mask layer acts as a barrier layer against thermal oxidation, and thermally oxidizes the local area under the gate in an oxygen atmosphere, forming a local thermal oxidation region 4.

[0027] 5) Source and drain photolithography and evaporation of source and drain metal, source and drain metal adopts Ti / Au double-layer metal, forming source electrode 11 and drain electrode 12.

[0028] 6) Growth of gate dielectric aluminum oxide by using ALD coating method, forming dielectric layer 10.

[0029] 7) Magnetron sputtering of P-type oxide, forming first P-type oxide 8 and second P-type oxide 7 with different concentrations by adjusting the O2 content during growth.

[0030] 8) Evaporation of gate metal Ni / Au and heterojunction field plate HFP metal by EBE method, and obtaining gate electrode 9 and heterojunction field plate HFP electrode 10 by stripping process.

Claims

1. A novel heterojunction field plate gallium oxide MOSFET device, comprising a gallium oxide substrate layer (1), a gallium oxide buffer layer (2), and a gallium oxide epitaxial layer (3) stacked in sequence from bottom to top along the vertical direction of the device; characterized in that The gallium oxide epitaxial layer (3) has N+ source region (5) and N+ drain region (6) at both ends of the upper surface, respectively, and the bottom of the N+ source region (5) and the N+ drain region (6) is embedded in the upper layer of the gallium oxide epitaxial layer (3); the upper surface of the N+ source region (5) and the N+ drain region (6) has a source electrode (11) and a drain electrode (12), respectively; the upper surface of the gallium oxide epitaxial layer (3) between the N+ source region (5) and the N+ drain region (6) has a dielectric layer (10), the upper surface of the dielectric layer (10) is flush with the upper surface of the N+ source region (5) and the N+ drain region (6) along the lateral direction of the device; the side of the dielectric layer (10) in contact with the N+ drain region (6) has a first P-type oxide (8) and a second P-type oxide (7) connected in sequence, wherein the side of the second P-type oxide (7) is in contact with the side of the N+ drain region (6), so that the first P-type oxide (8), the second P-type oxide (7) and the N+ drain region (6) form a heterojunction field plate structure; the upper surface of the first P-type oxide (8) has an HFP electrode (13), and the HFP electrode (13) is connected with the source electrode (11); The dielectric layer (10) between the first P-type oxide (8) and the N+ source region (5) has a gate electrode (9), the lower end of the gate electrode (9) is embedded in the dielectric layer (10) and has a spacing with the upper surface of the gallium oxide epitaxial layer (3); the upper end of the gate electrode (9) extends out of the dielectric layer (10), and the gate electrode (9) has a spacing between the N+ source region (5) and the first P-type oxide (8) at both ends; the gallium oxide epitaxial layer (3) below the gate electrode (9) has a thermal oxidation region (4), which penetrates the gallium oxide epitaxial layer (3) along the vertical direction, the lower surface of the thermal oxidation region (4) is in contact with the upper surface of the gallium oxide buffer layer (2), and the upper surface of the thermal oxidation region (4) is in contact with the lower surface of the dielectric layer (10).

2. A novel heterojunction field plate gallium oxide MOSFET device as claimed in claim 1, wherein, The materials of the first P-type oxide (8) and the second P-type oxide (7) are nickel oxide.

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