Semiconductor device

Abstract

The invention relates to a semiconductor device. A transistor device includes: a semiconductor substrate having a first main surface; and one or more transistor cells. Each transistor cell may include a columnar trench formed in a semiconductor substrate. The columnar trench includes a field dielectric, a substrate, and sidewalls. A sidewall may extend from the base to the first major surface. A field dielectric may lay over the substrate and sidewalls of the columnar trench. A first thickness of the field dielectric at a first distance from the substrate is less than a second thickness of the field dielectric at a second distance from the substrate. The first distance is greater than the second distance. A columnar field plate may be disposed in the columnar trench. A first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance. The columnar field plate includes a cavity.

Description

Background Art

[0001] Silicon (Si) semiconductor materials are often used to process transistor devices used in power electronics applications. Common transistor devices for power applications include Si Si power MOSFET and Si insulated gate bipolar transistor (IGBT).

[0002] A transistor device for power applications may be based on the charge compensation principle and may include an active primitive field including a plurality of trenches, each trench including a field plate for charge compensation. In some designs, the trenches and the mesas formed between adjacent trenches both have an elongated stripe structure. In some other designs, the trenches and the field plates both have a columnar needle shape.

[0003] Further improvements would be desired to further improve the performance of transistor devices having columnar field plates, for example by reducing the on-state resistance RDS(on).Area. Summary of the invention

[0004] In one embodiment, a transistor device includes: a semiconductor substrate having a first main surface; and one or more transistor cells. Each transistor cell may include a columnar trench formed in the semiconductor substrate. The columnar trench includes a field dielectric, a base, and a sidewall. The sidewall may extend from the base to the first main surface. The field dielectric may line the base and sidewalls of the columnar trench. A first thickness of the field dielectric at a first distance from the base is less than a second thickness of the field dielectric at a second distance from the base. The first distance is greater than the second distance. A columnar field plate may be arranged in the columnar trench. A first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance.

[0005] In another embodiment, a method includes: forming a columnar trench in a first main surface of a semiconductor substrate having a first conductivity type. The columnar trench includes a base and a sidewall extending from the base to the first main surface. The method may also include: forming a first dielectric layer on the base and sidewalls of the columnar trench; and depositing a second dielectric layer on the first dielectric layer. The method may also include: removing at least a portion of the second dielectric layer from an upper portion of the columnar trench; and inserting a conductive material in the columnar trench to form a field plate. The conductive material may cover the base and sidewalls of the columnar trench. The conductive material may only partially fill the columnar trench. The conductive material may form a columnar field plate including a cavity.

[0006] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings, wherein like reference numerals refer to similar or identical elements. The elements of the drawings are not necessarily drawn to scale relative to each other. The features of the various illustrated examples can be combined unless they exclude each other.

[0008] Exemplary embodiments are depicted in the drawings and are described in detail in the following description.

[0009] Figures 1A to 1C The semiconductor device is shown in the figure, Figure 1A and 1B shows a schematic top view according to two embodiments and Figure 1C A cross-sectional view is shown.

[0010] Figures 2A to 2D A cross-sectional view of a pillar trench including a field plate according to various embodiments is illustrated.

[0011] Figures 3A to 3J A cross-sectional view of a pillar trench including a field plate according to various embodiments is illustrated.

[0012] Figure 3K and 3L A cross-sectional view of a pillar trench including a field plate according to various embodiments is illustrated.

[0013] Figures 4A to 4B The diagram shows a lateral arrangement of four transistor cells.

[0014] Figure 5A and 5B Show Figure 4A A top view of one of the columnar grooves.

[0015] Figures 6A to 6K A method of fabricating a columnar trench having a columnar field plate and a field dielectric is shown.

[0016] Figures 7A to 7H A method for machining an annular contact of a cylindrical field plate located within a cylindrical trench is shown. DETAILED DESCRIPTION

[0017] In the detailed description below, reference is made to the accompanying drawings, which form a part of the detailed description, and in which specific embodiments of the present invention are illustrated as diagrams. In this respect, directional terms such as "top", "bottom", "front", "back", "head", "tail", etc. are used with reference to the orientation of the (one or more) accompanying drawings being described. Because the parts of the embodiments can be placed in many different orientations, directional terms are used for illustrative purposes and are not restrictive in any way. It should be understood that other embodiments can be used and structural or logical changes can be made without departing from the scope of the present invention. The detailed description below should not be understood in a restrictive sense, and the scope of the present invention is defined by the appended claims.

[0018] A number of exemplary embodiments will be explained below. In this case, identical structural features are identified by identical or similar reference numerals in the various figures. In the context of this description, "lateral" or "lateral direction" should be understood to mean a direction or extent extending substantially parallel to the lateral extent of a semiconductor material or semiconductor carrier. The lateral direction therefore extends substantially parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction extending substantially perpendicular to these surfaces or sides and therefore perpendicular to the lateral direction. The vertical direction therefore extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0019] As used in this specification, when an element (such as a layer, region or substrate) is referred to as being “on” or “extending onto” another element, it can be directly on or directly extend onto the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “extending directly onto” another element, there are no intervening elements present.

[0020] As employed in this specification, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0021] As used herein, various device types and / or doped semiconductor regions may be identified as having n-type or p-type, but this is merely for convenience of description and is not intended to be limiting, and such identification may be replaced by a more general description of having a "first conductivity type" or a "second, opposite conductivity type," where the first type may be either n or p-type and the second type then either p or n-type.

[0022] The accompanying drawings illustrate relative doping concentrations by indicating "-" or "+" immediately after the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.

[0023] In an embodiment, a transistor device with a needle trench structure is provided, which can be used for devices operating in a medium voltage range, for example from about 60V to 200V, which enables a further reduction of the RDS(on)x Area while keeping the FOM at least constant or improving them.

[0024] In an embodiment, a trench MOSFET is provided, which includes charge carrier compensation provided by a needle-shaped (columnar) field plate groove and its associated needle-shaped (columnar) field plate and a separate gate groove, wherein the field plate groove and the field plate can be arranged in a staggered lattice pattern. In some embodiments, the gate groove forms a gate grid, and the gate grid surrounds the individual needle-shaped grooves in the needle-shaped grooves. In other embodiments, a plurality of separate gate grooves are used, which extend in a line between the needle-shaped grooves on the surface of the semiconductor chip. The line can be straight or tortuous, such as zigzag, to follow the shape of the needle-shaped groove, such as a needle-shaped groove with a hexagonal shape (area). The field plate grooves can all have a field dielectric, such as a field oxide, whereby the thickness of the field oxide decreases from the top to the bottom of the groove. The contactor can have a ring shape (e.g., a torus shape) and is connected to both the source region and the field plate in the mesa. In some embodiments, the needle-shaped field plate groove has a hexagonal profile, and the gate grid follows this hexagonal shape. The field plate in the field plate trench may have a cavity.In an embodiment, the field plate may be at least partially filled with a filling material (eg, with a dielectric such as an oxide).

[0025] In the staggered layout of needle-shaped trenches, the individual transistor cells are not arranged in an orthogonal grid, but in a mutually displaced or staggered grid. Hexagonal geometries of the lateral shapes of the field plate trenches, field plates, and gate grids can be used. The increase in the effective mesa width at the intersection is minimal, which enables higher doping in the drift band. The staggered design also results in a lower area-specific on-resistance.

[0026] In an example, the field dielectric may be a stepped field dielectric. In some examples, only two dielectric thicknesses may be implemented, the difference between the two thicknesses being greater than the difference caused by process variations. For a silicon substrate, the field dielectric may be an oxide, such as SiO x .

[0027] In order to achieve the design of the device that ensures the appropriate process window for the breakdown voltage, the field oxide thickness can be precisely controlled. This includes the precise control of the oxide thickness in the upper part of the trench. In an embodiment, by additional wet etching, the reduced thickness of the oxide in the upper part of the trench is achieved, in which case a type of 'etch stop' can be effectively adopted. In an embodiment, this is achieved by using different etching rates of thermally grown field oxide and deposited oxide. A field dielectric can be formed by a dielectric layer, for example, a thermally grown field oxide and a deposited oxide. The difference in the etching rates of these layers can be used so that the oxide thickness of the field oxide is equal to the thickness of the target reduced oxide thickness in the upper part of the trench, that is, the field oxide in the upper part of the trench is provided by the thermally grown field oxide. By depositing an additional oxide layer on the thermally grown field oxide, for example, by using a TEOS deposition process to deposit a second oxide layer on the thermally grown oxide layer, the full oxide thickness used in the lower part of the trench is provided. Because the etching rate of the TEOS layer is even higher than the etching rate of the thermally grown oxide, the etching stop is provided by the thermally grown oxide layer below. After the etching process, the TEOS layer may be densified.

[0028] The needle-shaped grooves reach the surface, which allows a simple process that is more easily controlled and can achieve cost savings. The combination with the stepped field oxide enables the use of narrower annular (e.g., donut-shaped) groove contacts. The benefits of the ring contact of the mesa can include process integration simplification because it can allow a single contactor scheme and an increased lithography process window because the mesa contact critical dimensions are in the order of magnitude similar to the edge termination contact critical dimensions. The stepped or conical field oxide enables the ring contact because the thin field oxide in the upper needle-shaped portion means that only a tiny mesa contact width is required to contact both the mesa and the field plate.

[0029] In an embodiment, the process sequence for realizing the recess contacts includes two etching steps - first opening the interlayer dielectric with an oxide etch, followed by a recess etch in the silicon.

[0030] The trapezoidal arrangement of the gate trench layout can be used in both orthogonal and staggered designs to improve the reliability of the gate dielectric, for example, to reduce the number of crystal planes in the gate dielectric.

[0031] Instead of a continuous gate grid, gate fins (i.e., interrupted gate grids) can be used. The proposed structure can also be used in combination with structural variants for gate charge optimization (i.e., individual gate strips with current spread injection) or, for hexagonal pins, with zigzag gate trenches, planar gate structures.

[0032] A suitable doping profile of the semiconductor substrate can also be used to improve device performance. In an embodiment, a graded epitaxial profile is used, where the doping increases continuously from the front surface towards the epi-substrate junction and comprises (at least) two parts with different grading. The graded epitaxial profile is located in a mesa that is completely around the needle-shaped groove in the lateral direction (e.g. 360° around the needle-shaped groove of the basic unit).

[0033] Figure 1A 1 shows a top view of a semiconductor device 10 according to an embodiment. Figure 1B A top view of a semiconductor device 10 according to another embodiment is shown. Figure 1C Diagram Figure 1A and 1B 1 and 2. A cross-sectional view of a portion of one or both of the semiconductor devices 10. The semiconductor device 10 may be a transistor device, such as a vertical power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device.

[0034] Reference Figure 1A and 1B , the semiconductor device 10 includes an active region 11 and an edge termination region 12 disposed in a semiconductor substrate 13. The edge termination region 12 laterally surrounds the active region 11 on all sides. The semiconductor substrate 13 may be formed of silicon (eg, single crystal silicon or an epitaxial silicon layer).

[0035] The semiconductor device 10 includes one or more transistor cells 15 located in the active region 11. A plurality of active transistor cells 15 are electrically connected in parallel to each other to switch a load and provide a transistor device. The transistor device may be a power MOSFET device and may have a vertical drift path. Each transistor cell 15 includes a columnar trench 14 and a mesa 16 formed by a portion of the semiconductor substrate 13 that laterally surrounds the columnar trench 14. Figure 1A and 1B As indicated in , the semiconductor substrate may surround the pillar trench 14 on all sides of the pillar trench 14. Figure 1C In the cross-sectional view of the substrate, the columnar groove 14 has a small or narrow perimeter or width proportional to its height / depth in the substrate. For example, the depth is at least twice the width. The columnar groove 14 may also be referred to as a needle-shaped groove or a needle-shaped groove or a thorn-shaped groove.

[0036] Reference Figure 1A and 1B A top view of the embodiment of the present invention provides a plurality of columnar grooves 14 arranged in an array. Figure 1AIn the embodiment illustrated in FIG. 1 , the columnar grooves 14 are arranged in rows and columns that are arranged orthogonal to each other and form a square grid array, wherein the spacing or interval d between the columnar grooves 14 of each row and between the columnar grooves 14 of each column is substantially the same. However, the spacing between adjacent columnar grooves 14 in the diagonal direction is greater than d. Figure 1B In the embodiment illustrated in FIG. 1 , the columnar grooves 14 are arranged in offset or staggered rows and form a hexagonal pattern in which the spacing d between adjacent columnar grooves 14 within each row (column) and between adjacent columnar grooves 14 in adjacent rows is substantially the same.

[0037] exist Figure 1A In the embodiment illustrated in FIG. 1 , the columnar groove 14 is illustrated as having a square lateral form in the top view. However, the columnar groove 14 may have other lateral forms in the top view. For example, the columnar or needle-shaped groove 14 may have an octagonal, circular or hexagonal shape in the plan view. Figure 1B An embodiment is illustrated in which the columnar trenches 14 have a hexagonal shape in a top view and are arranged in a hexagonal array.

[0038] In cross section, the columnar trenches 14 may have the same structure regardless of the lateral shapes or patterns of the arrays of the columnar trenches 14 and the columnar field plates 21 . Figure 1C Diagram Figure 1A and 1B 1 is a cross-sectional view of one of the pillar trenches 14 of the semiconductor device.

[0039] Reference Figure 1C , individual columnar trenches 14 in the columnar trenches 14 include a base 17 and sidewalls 18, and the sidewalls 18 extend from the base 17 to the first main surface 19 of the semiconductor substrate 13. Individual columnar trenches 14 in the columnar trenches 14 also include a field dielectric 20, which lines the base 17 and the sidewalls 18 of the columnar trenches 14. A columnar conductive field plate 21 is arranged in each columnar trench 14 and fills each columnar trench 14, and is electrically separated from the semiconductor substrate 13 by the field dielectric 20. The field plate 20 extends to the first main surface 19 and has an upper surface 22, which is coplanar with the first main surface 19 of the semiconductor substrate 13.

[0040] The field dielectric 20 has a first thickness t1 at a first distance d1 from the substrate 17, and has a second thickness t2 at a second distance d2 from the substrate 17 of the columnar trench 14. The first thickness t1 is less than the second thickness t2. The first distance d1 is greater than the second distance d2. Therefore, the field dielectric 20 is thinner toward the top of the trench 14 and thicker toward the substrate 17 of the trench 14. The difference between thickness t1 and t2 is greater than the difference caused by process variations. In some embodiments, t1≤1.15t2, and therefore, is greater than typical process variations. In some embodiments, the difference is greater, so that t1≤1.2t2 or t1≤1.5t2.

[0041] The field dielectric 20 may include one or more sub-layers having the same or different compositions. For example, the field dielectric 20 may be an oxide SiO x . For example, the field plate 21 is conductive and may be formed of polysilicon. The columnar field plate 21 has a first perimeter at a first distance d1 from the base 16 of the columnar trench 14, and a second perimeter at a second distance d2 from the base 17. The first perimeter is greater than the second perimeter, that is, the length l1 of the first perimeter is greater than the length l2 of the second perimeter. The difference between the first and second perimeters is greater than the difference caused by process variations. In some embodiments, l1≥1.15l2, and therefore, is greater than typical process variations. In some embodiments, the difference is greater, so that l1≥1.2l2 or l1≥1.5l2. In other words, the field plate 21 is wider at the first distance d1 in the lateral direction than at the second distance d2 from the base 16. Because the field plate 21 and the field dielectric 20 fill the columnar trench 14 together, the field plate 21 has a larger width w1 in the upper portion of the trench 14 than the width w2 of the field plate 21 in the lower portion of the trench 14. In cross section, the field plate 21 may have a T-shape or a tapered V-shape.

[0042] exist Figure 1A and 1B In the embodiment shown in FIG. 1 , the field plates 21 may have the same lateral shape as the columnar trenches 14, such as a square or a hexagon. Alternatively, the field plates 21 may have a lateral shape different from the lateral shape of the columnar trenches 14, for example, the field plates 21 may have a circular shape in the top view and be located in the columnar trenches 14 having a hexagonal shape in the top view.

[0043] In the embodiment where the columnar trench 14 is circular in plan view, the columnar trench 14 has a single sidewall 18. If the columnar trench 14 is square in plan view, such as Figure 1A As shown in , the side wall 19 is divided into four side wall sections arranged substantially perpendicular to each other. If the columnar groove 14 is hexagonal in plan view, such as Figure 1B, the side wall 19 has six side wall segments. If the columnar trench 14 is octagonal in plan view, the side wall 18 has eight side wall segments, and so on.

[0044] Reference Figure 1C In some embodiments, the field dielectric 20 includes an abrupt transition from a first thickness t1 to a second thickness t2 that forms a step 25, so that the field dielectric 20 can be considered to have a step shape. In some embodiments, the field dielectric 20 has a smaller thickness t1 at a first height h1 of the columnar trench 14 in the upper portion, and has a larger thickness t2 at a second height h2 of the columnar trench 14 in the lower portion.

[0045] The field plate 21 also has an abrupt transition between a larger width w1 in the upper portion of the trench 14 and a smaller width w2 towards the lower portion of the trench 14. The field plate 21 can be seen as having a step 26 in its outer surface 27 corresponding to the step 25 formed in the field dielectric 20. Figure 1C The field plate 21 illustrated in FIG. 2 can be viewed as having a T-shape in cross-section. Alternatively, the field plate 21 may have a tapered shape, such as ranging from a first thickness t1 at a distance d1 from the substrate 17 to a second thickness t2 at a second distance d2 from the substrate 17, without the step 26, but with a smoother transition between the first thickness and the second thickness.

[0046] The mesa 16 of each transistor cell 15 is formed by a region of the semiconductor substrate 13 that laterally surrounds the columnar trench 14 of the active transistor cell 15. Figure 1C As shown in FIG. 1 , in the active region 11, each mesa 16 includes a drift region 28 of a first conductivity type (e.g., n-type) and a body region 29 of a second conductivity type (e.g., if the drift region is n-type, the second conductivity type is p-type). The body region 29 is arranged above the drift region 28 and forms a pn junction with the drift region 20. The mesa 16 also includes a source region 30 of the first conductivity type, which is arranged on the body region 29 and forms a pn junction with the body region 29. The drain region 31 of the first conductivity type is more highly doped than the drift region 28 and is arranged on the second main surface 99 of the semiconductor substrate 13, and the second main surface 99 is opposite to the first main surface 19. Figure 1C A gate electrode, not shown in FIG. 1 , is located on or in the mesa 16 and is electrically separated from the mesa 16 by a gate dielectric.

[0047] In some embodiments, the field dielectric 20 has a first thickness t1 in a first region of the sidewall 18 adjacent to the body region 29, and has a second thickness t2 in a second region of the sidewall 18 adjacent to the drift region 28. The step 25 is located at a depth d relative to the first main surface 19 of the semiconductor substrate 13, and the depth d corresponds to the height h1. The pn junction formed between the body region 29 and the drift region 28 is located at a depth d relative to the first main surface of the semiconductor substrate. pn , where h1>d pn The step 25 is arranged laterally adjacent to the drift region 28 .

[0048] Figures 2A to 2D 1 and 2. A cross-sectional view of a columnar trench 14 according to various embodiments is shown. The columnar trench 14 includes a conductive field plate 21, which is electrically separated from the semiconductor substrate 13 by a field dielectric 20. The columnar trench 14 of any of these embodiments can be used as a transistor cell 15 (e.g., Figure 1A or Figure 1B 1 . A portion of a transistor cell 15 of the transistor device 10 shown in FIG.

[0049] Reference Figure 2A In this embodiment, the columnar groove 14 and Figure 1C The difference of the columnar trench 14 illustrated in FIG is that the columnar field plate 21 has a fourth perimeter, which is arranged at a fourth distance d4 from the base 17 of the columnar trench 14. The fourth perimeter is smaller than the first perimeter. In other words, the length l4 of the fourth perimeter is smaller than the length l1 of the first perimeter by an amount greater than the amount caused by process variation. In this embodiment, the fourth distance d4 relative to the base 17 is greater than the first distance d1 relative to the base 17, so that the fourth perimeter l4 is arranged closer to the first main surface 19 than the first perimeter l1.

[0050] exist Figure 2A In the embodiment illustrated in , the field plate 21 includes a fourth section having a fourth width w4, the fourth section being disposed adjacent to the first main surface 19. The fourth section has a fourth width w4 at a height h4 and is disposed between the first main surface 19 and the middle portion of the field plate 21 having a width w1. The width w4 is smaller than the width w1 by an amount greater than an amount caused by process variations. A shoulder 26' is formed between the upper portion of the field plate 21 and the side end surface 27 of the middle portion. The shoulder 26' forms a portion of the base 34 of the recess 32.

[0051] In addition, in this embodiment, the columnar trench 14 includes an enlarged recess 32, which is adjacent to the first main surface 19 in the lateral direction and extends a certain distance in the semiconductor substrate 13, and the certain distance corresponds to the height of the fourth portion of the field plate. The base 34 of the recess 32 can be arranged to be adjacent to the body region 29 in the lateral direction and is arranged at a distance h4 from the first main surface 19.

[0052] The sidewall 18 of the columnar trench 14 has a step formed between a narrower lower portion and an enlarged recess 32 formed in the first main surface 19. The step forms a base 34 of the recess 32 and has a continuous ring shape (when viewed from the top). The field plate 21 extends to the first main surface 19 of the semiconductor substrate 13 so that its upper surface is substantially coplanar with the first main surface. The portion of the enlarged recess 32 not occupied by the field plate 21 has a ring shape and surrounds the field plate 21 laterally.

[0053] The recess 32 can be used to form a contact of the field plate 21. Figure 2B The cross-sectional view and Figure 2C , a conductive material is formed in the recess 32 to form a conductive contact 33. The contact 33 is at least partially located within the columnar trench 14 and extends between the side end surface 27 of the field plate 21 and the side wall 35 of the recess 32. In some embodiments, the contact 33 is completely disposed within the columnar trench 14 and has an upper surface that is coplanar with the upper surface 22 of the field plate 21 and coplanar with the first main surface 19. The contact 33 has an annular shape and is in continuous and uninterrupted contact with the side end surface 27 of the field plate 21, and is in continuous and uninterrupted contact with the side wall 18 of the trench, and therefore is in continuous and uninterrupted contact with the surrounding mesa 16. Since the side wall 35 of the recess 32 is formed by the source region 30 and the body region 29, the contact 33 electrically connects the field plate 21 to the body region 29 and the source region 30 in the mesa 16. The annular contact 33 extends over the entire width t1 of the field dielectric 21, which is arranged on the side wall 18 of the columnar trench 14 in the lower part of the columnar trench 14. The width of the annular contact 33 corresponds to the spacing between the side end surface 27 of the field plate 21 and the side wall 35 of the enlarged recess 32, and is greater than the first thickness t1 of the field dielectric 20.

[0054] In some embodiments, a central region 36 of the upper surface 22 of the field plate 21 remains exposed by the contact 33 and also remains exposed by any other conductive material. In other words, the contact of the field plate 21 is formed at the perimeter of the field plate 21 only at a position within the columnar trench 14, rather than being formed by a contact disposed in the middle of the width and lateral regions of the field plate 21 or by a contact in direct contact with the upper surface of the field plate 21. The contact 33 can be considered a buried contact because it is disposed within the columnar trench 14 and disposed below the first main surface 19 of the semiconductor substrate 13.

[0055] The annular contactor 33 may have different lateral forms in a plan view, such as a circle, a square, a hexagon, an octagon. The lateral form of the annular contactor 33 depends on the lateral form of the columnar groove 14 and the columnar field plate 21. For example, for a circular columnar groove 14 and a circular field plate 21, the contactor 33 may have a circular ring shape. For a hexagonal columnar groove 14 and a hexagonal field plate 21, the contactor 33 may have a hexagonal ring shape. The annular contactor 33 may include two or more sublayers that may have different compositions, and / or may be formed of tungsten. For example, one or more barrier layers (e.g., TiN) may be formed, and then the recess is filled with tungsten.

[0056] exist Figure 2C In the perspective cross-sectional view of the columnar trench 14, the lateral form of the columnar trench 14 and the field plate 21 can be seen to be hexagonal. The contact 33 has a continuous hexagonal annular form and completely covers the field dielectric 20 located between the side end face 27 of the field plate 21 and the side wall 18 of the columnar trench 14 (in particular, the side wall 35 of the recess 32 of the columnar trench 14).

[0057] In reference Figure 2B and 2C Describe and Figure 2B and 2C In a variation of the embodiment illustrated in , the contact 33 is formed as part of the field plate 21 so that there is no distinguishable interface between the enlarged upper portion of the field plate 21 that provides the contact 33 with the body region 29 and the source region 30 and the remaining portion of the field plate 21. The field plate 21 includes a constituent contact portion 33 in its upper portion, and the upper surface 22 of this constituent contact 33 is coplanar with the first major surface 19. In these embodiments, the columnar field plate 21 has a fourth perimeter that is disposed at a fourth distance d4 from the base 17 of the columnar trench 14. The fourth perimeter is greater than the first perimeter. In other words, the length l4 of the fourth perimeter is greater than the length l1 of the first perimeter by an amount that is greater than the amount caused by process variations. In this embodiment, the fourth distance d4 relative to the base 17 is greater than the first distance d1 relative to the base 17 so that the fourth perimeter l4 is disposed closer to the first major surface 19 than the first perimeter.

[0058] The field plate 21 includes a fourth section having a width w4, which is greater than the width w1 by an amount greater than the amount caused by process variations. The contact portion 33 of the field plate 21 has a fourth width w4 at a height h4 and is disposed between the first main surface 19 and the middle portion of the field plate 21 having the width w1. The shoulder 26' is formed between the upper portion of the field plate 21 and the side end surface 27 of the middle portion.

[0059] Figure 2D The transistor device 10 is shown in cross-section, and two transistor cells 15 are shown, each transistor cell 15 comprising a columnar trench 14 and a mesa 16 laterally surrounding the trench 14. In this embodiment, the columnar trench 14 and the mesa 16 are Figure 2B and 2C The columnar trench 14 is different in that it does not include a recess at the top. The width and area of ​​the columnar trench 14 are substantially uniform over its depth from the first major surface 19 to its base 17.

[0060] In some embodiments, each columnar trench 14 has a field plate 21 having a single abrupt transition or step 26 in a side end surface 27. Figure 1C , and an annular contact 33 is disposed in each of the columnar trenches 14. In this embodiment, the contact 33 has a width substantially the same as the width of the first thickness t1 of the field dielectric 20, and continuously and uninterruptedly contacts the entire perimeter of the field plate 21 and the sidewall 18 of the columnar trench 14. The annular contact 33 is disposed in the columnar trench 14, and extends from the side end surface 27 of the field plate 21 to the sidewall 18 of the columnar trench to electrically connect the field plate 21 to the mesa 16 and to the body region 29 and the source region 30 at a position below the first main surface 19. The contact 33 has an upper surface that is substantially coplanar with the upper surface 22 of the field plate 21 and coplanar with the first main surface 19.

[0061] Figure 2DAlso shown is a gate electrode 37 of the transistor cell 15, which is disposed in a gate trench 38 formed in the mesa 16 such that the gate trench 38 is disposed equidistantly with respect to two adjacent ones of the pillar trenches 14. The gate electrode 37 is electrically separated from the semiconductor substrate 13 by a gate dielectric 39, which lines a base 40 and sidewalls 41 of the gate trench 38. In other embodiments (not shown), the transistor device 10 includes a planar gate structure in which the conductive gate electrode 37 is disposed on the mesa 16, and in particular on the first main surface 19 of the semiconductor substrate 13 forming the mesa 16. The conductive gate electrode 37 is electrically separated from the semiconductor substrate 13 by an intervening gate dielectric layer 38 arranged on the first main surface 19.

[0062] In any of the embodiments described herein, the thickness of the field dielectric 20 located on the base 17 and the lower portion of the sidewall 18 of the columnar trench 14 can be substantially uniform, or the thickness of the field dielectric 20 arranged on the base 16 of the columnar trench 14 can be greater than the maximum thickness of the field dielectric 20 arranged on the sidewall 18 of the trench 14.

[0063] Figures 3A to 3J Shown with Figures 1C to 2D A similar structure, wherein the difference is that the field plate 21 includes a cavity 100. For the sake of simplicity, the above has been about Figures 1C to 2D Described in Figures 3A to 3I Elements in the same manner (such as elements indicated by the same reference numerals) will not be reinterpreted. Figures 3A to 3J , the transistor device may include: a semiconductor substrate 13 having a first main surface 19; and one or more transistor cells 15. Each of the one or more transistor cells may include a columnar trench 14 formed in the semiconductor substrate 13. The columnar trench 14 may include a field dielectric 20, a base 17, and a sidewall 18. The sidewall 18 may extend from the base 17 to the first main surface 19. The field dielectric 20 may line the base 17 and the sidewall 18 of the columnar trench 14. A first thickness t1 of the field dielectric 20 at a first distance d1 from the base 17 may be less than a second thickness t2 of the field dielectric 20 at a second distance d2 from the base 17. The first distance d1 may be greater than the second distance d2. A columnar field plate 21 may be arranged in the columnar trench 14. A first perimeter l1 of the columnar field plate 21 at the first distance d1 may be greater than a second perimeter l2 of the columnar field plate 21 at the second distance d2. The cylindrical field plate 21 includes a cavity 100 , as described in further detail below.

[0064] The cavity 100 of the columnar field plate 21 may increase the resistance of the columnar field plate 21 , which may result in suppression of oscillations during switching (eg, connecting / disconnecting the columnar field plate 21 to the source terminal).

[0065] Refer to Figure 3A (It is similar to Figure 1C ), Figure 1A and 1B A cross-sectional view of one of the columnar trenches 14 of the semiconductor device of is illustrated. In addition to Figure 1C components of, the columnar field plate 21 may further include a cavity 100.

[0066] In one embodiment, the cavity 100 may extend at least from a first distance d1 to a first major surface 19 of the semiconductor substrate 13. The cavity 100 may be disposed at the first distance d1 (at which the field dielectric 20 may have a first thickness t1), and the cavity 100 may not be disposed at a second distance d2 from the substrate 17 (at which the field dielectric 20 may have a second thickness t2; t1 < t2, as discussed in more detail above with respect to Figure 1C ). In some embodiments, the cavity 100 in the field plate 21 may be provided at a third height h3 of the columnar trench 14 in the upper portion. For example, the cavity 100 may span from a region above the step 25 to the first major surface 19 of the semiconductor substrate.

[0067] In another embodiment, the cavity 100 may also extend deeper in the field plate 21, for example, from the first major surface 19 to a distance d2 from the substrate 17 (at which the field dielectric 20 may have a second thickness t2; t1 < t2). In this example, the cavity may span from a region below the step 25 to the first major surface 19 of the semiconductor substrate. Additionally, the cavity 100 may not extend to the first major surface 19, but may be completely surrounded by the field plate 21 ( Figure 3A not shown in). Figure 3A A cross-sectional view in a plane orthogonal to the first major surface 19 is shown. The columnar field plate 21 may include a first section between the field dielectric 20 disposed on one side of the columnar trench 14 and a first side of the cavity 100 at the first distance d1 and a second section between a second side of the cavity 100 and the field dielectric 20 on the opposite side of the columnar trench 14 (e.g., as can be seen at a distance d1 from the substrate 17 in Figure 3A ). In other words, in a plane orthogonal to the first major surface 19 of the semiconductor substrate 13, at the first distance d1, the columnar field plate 21 does not extend from the field dielectric 20 on one side of the columnar trench to the field dielectric 20 on the opposite side of the columnar trench 14 (but it may be interrupted by the cavity 100).

[0068] In addition, as Figure 3AAs shown (e.g., in a plane orthogonal to the first main surface 19), at a second distance d2 (at which the field dielectric 20 may have a second thickness t2; t1 < t2), the columnar field plate 21 may extend from the field dielectric 20 on one side of the columnar trench 14 to the field dielectric 20 on the opposite side of the columnar trench 14. In other words, at the second distance d2, the columnar field plate 21 may not be interrupted by the cavity 100. In other embodiments, the cavity 100 in the field plate 20 may also be present at the distance d2.

[0069] Still referring to Figure 3A (e.g., in a plane orthogonal to the first main surface 19), at a third distance d3 from the substrate 17, the columnar field plate 21 may extend from the field dielectric 20 on one side of the columnar trench 14 to the field dielectric 20 on the opposite side of the columnar trench 14. The third distance d3 may be greater than the second distance d2, and the third distance d3 may be less than the first distance d1. The third perimeter l3 of the columnar field plate 21 at the third distance d3 may be greater than the second perimeter l2 of the columnar field plate 21 at the second distance d2. For example, the third perimeter l3 may be equal to or less than the first perimeter l1 at the first distance d1. Similarly, the field dielectric 20 may have a third thickness t3 at the third distance d3. The third thickness t3 may be equal to or greater than the first thickness t1 and less than the second thickness t2.

[0070] Figures 3B to 3D Corresponding respectively to Figures 2A to 2C , and additionally showing the field plate 21 (such as including the cavity 100) as explained above with respect to Figure 3A . For the sake of brevity, Figures 3B to 3D The elements shown in Figures 2A to 2C and with respect to Figure 3A explained will not be repeated, and reference is made to the detailed discussion above. Figure 3B and 3C show cross-sectional views in a plane orthogonal to the first main surface 19. As Figure 3B and 3C shown, at a fourth distance d4, a first section of the columnar field plate 21 may (in a plane orthogonal to the first main surface 19 of the semiconductor substrate 13) be located between the contactor 33 and the cavity 100 on one side of the columnar trench, and a second section of the columnar field plate 21 may be located between the cavity 100 and the contactor 33 on the opposite side of the columnar trench 14. As can be seen in Figure 3B and 3C , the columnar trench 14 at the fourth distance d4 may have a fifth width w5. In some embodiments, the cavity 100 in the field plate 21 may be provided at a third height h3 of the columnar trench 14 in the upper part. For example, the cavity 100 may span from a region located below the height h4 of the contactor 33 (and, for example, above the step 25) to the first main surface 19 of the semiconductor substrate.

[0071] As in Figures 3A to 3D As can be seen in FIG. 1 , the width w3 of the cavity 100 and / or the height h3 of the cavity can affect the resistance of the columnar field plate 21. In general, the larger the width w3 of the cavity 100 and the larger the height h3 of the cavity 100, the higher the resistance of the field plate. By increasing the resistance of the columnar field plate, oscillations during switching of the transistor device can be suppressed. This can be applied to a surface contact (the surface contact can be located above the first main surface 19 and in contact with the columnar field plate 21, such as Figure 3A ) and embedded contactors (as shown in Figure 3C As shown and as about Figure 3C There are two cases of contacting the source terminal as discussed).

[0072] As follows about Figures 6A to 6K (Such as, in Fig.6I As will be further described in detail in the accompanying drawings, the width w3 and / or height h3 of the cavity 100 can be accurately controlled according to the present disclosure.

[0073] Now refer to Figure 3E , Figure 3E Corresponds to Figure 2D And furthermore, a columnar field plate 21 with a cavity 100 is shown, as described above with respect to Figures 3A to 3D Explained. Figure 3E A cross-sectional view in a plane orthogonal to the first major surface 19 is shown.

[0074] The above about Figures 3A to 3E , cavity 100 is shown as having a uniform width w3 along height h3. However, other distributions of cavity 100 (such as including a non-uniform width along height h3) are possible and contemplated by the present disclosure. For example, similar to Figure 3A of Figure 3F A cross-sectional view in a plane normal to the first major surface 19 is shown, wherein the cavity 100 has a non-uniform width along the height h3, such as a tapered form, wherein the width gradually decreases along the height h3.

[0075] Figures 3G to 3J A top view of a cross section of one of the pillar trenches 14 of a transistor device according to an example of the present disclosure is shown. Figures 3G to 3J The cross section is located in a plane parallel to the first major surface 19. In particular, Figure 3G The cross section in may be located in a plane parallel to the first major surface 19 and spaced apart from the base 17 of the groove 14 by a distance d1, Figure 3H The cross section in may be located in a plane parallel to the first major surface 19 at a distance d3, Fig. 3I The cross section in may be located in a plane parallel to the first major surface 19 at a distance d2, and Figure 3JThe cross section in the figure may be located in a plane parallel to the first major surface 19 at a distance d4 (the distance d1 to d4 is also in the plane parallel to the first major surface 19). Figures 3G to 3J In another cross section orthogonal to the cross section shown in Figure 3C exemplarily indicated in ).

[0076] exist Figures 3G to 3J , from a top view, the trench 14, the columnar field plate 21, the contact 33 and the cavity 100 are indicated as having a circular shape. However, as already discussed above, other shapes are also possible, such as square, hexagonal, etc. In addition, it is also envisioned that the trench 14 may have a different shape than the field plate 21 and / or the cavity 100.

[0077] Reference Figure 3G , showing a cross section in a plane parallel to the first main surface 19 at a first distance d1. At the first distance d1, the columnar field plate 21 may surround the cavity 100. In other words, at the first distance d1, the field plate 21 may be perforated by the cavity 100. For example, in the case where the cavity 100 has the same width along the height h3, the cavity 100 may have a third width w3 at the first distance. In other examples (such as, Figure 3F ), the cavity 100 may have a width less than the width w3 at the first distance d1. The field dielectric 20 may surround the field plate 21 and may have a thickness t1. The columnar field plate 21 may include or be made of a conductive material 55. The columnar field plate 21 may have a first width w1 and a first perimeter l1 at the first distance d1 (as described above with respect to Figure 1C , 2A , 2B, 3A, 3B and 3C).

[0078] Reference Figure 3H , shown is a cross-section in a plane parallel to the first main surface 19 at a third distance d3. The third distance d3 may be greater than the second distance d2, and the third distance d3 may be less than the first distance d1. The third perimeter l3 of the columnar field plate 21 at the third distance d3 may be greater than the second perimeter l2 of the columnar field plate 21 at the second distance d2. For example, the third perimeter l3 may be equal to or less than the first perimeter l1 of the first distance d1. Similarly, the field dielectric 20 may have a third thickness t3 at the third distance d3. The third thickness t3 may be equal to or greater than the first thickness t1, and may be less than the second thickness t2. The cavity 100 may not exist at the third distance d3. In other words, at the third distance d3, the columnar field plate 21 may not be perforated. In this way, the columnar field plate 21 may span from one side of the field dielectric 20 to the opposite side of the field dielectric 20 in the trench 14.

[0079] In some embodiments, the third distance d3 is located above the step 25. In other words, the cavity 100 may extend only in a region where the thickness of the field dielectric 20 is less than the second thickness t2.

[0080] Reference Fig. 3I , shown in a cross-section in a plane parallel to the first major surface 19 at a second distance d2. At the second distance, the field dielectric 20 may have a thickness t2, and the columnar field plate 21 may have a width w2 and a perimeter l2. The cavity 100 may not exist at the second distance d2. In other words, at the second distance d2, the columnar field plate 21 may not be perforated (similar to at the third distance d3). The third perimeter l3 of the columnar field plate 21 at the third distance d3 may be larger than the second perimeter l2 of the columnar field plate 21 at the second distance d2.

[0081] Reference Figure 3J , showing a cross section in a plane parallel to the first major surface 19 at a fourth distance d4 from the base 17 of the columnar groove 14. The fourth distance d4 may be greater than each of the first distance d1, the second distance d2, and the third distance d3. In some embodiments, at the fourth distance d4, the contact 33 may exist. Figure 2B , 3C 3J, the contact may have a ring shape having a width w5. At distance d4, the columnar field plate 21 may be recessed and have a fourth width w4, which may be less than the first width w1 of the columnar field plate 21 at the first distance d1. The field dielectric 18 may be covered by the contact 33 and may not be visible in the cross-section at the fourth distance d4. For example, where the cavity 100 has the same width along the height h3, the cavity 100 may have a third width w3 at the fourth distance. In other examples (such as, Figure 3F In the example shown in FIG. 1 , the cavity 100 may have a width smaller than the third width w3 at the fourth distance d4. In general, the higher the volume of the cavity 100, the higher the resistance of the field plate 21 may be. Figure 3K and 3L Shown with Figures 3A to 3J A similar structure, with the difference that the cavity 100 may be at least partially filled with a filling material 56 . Figure 3K and 3L Only for the above Figure 3A The example shown in FIG. 5 shows a filling material 56. Of course, the filling material 56 may also be present in the example shown in FIG. Figures 3A to 3J in any of the accompanying drawings.

[0082] Figure 3K A cross-sectional view in a plane normal to the first major surface 19 is shown. Figure 3A1 , the semiconductor device may further include a filling material 56 that partially fills the cavity 100 in addition to the elements shown in FIG. 1 . The filling material 56 may include an electrical insulator, such as an oxide. The filling material 56 may cover the base and sidewalls of the cavity 100, so that the cavity 100 is only partially filled with the filling material 56 (e.g., the cavity 100 is not completely filled). In this case, a gap 110 may exist, which is surrounded by the filling material 56 within the cavity 100. In an embodiment, the gap 110 and the filling material 56 may serve as a buffer zone, which may allow the overall stress in the semiconductor body 10 to be reduced, and thereby may result in a reduction in wafer bow.

[0083] Figure 3L A cross-sectional view in a plane normal to the first major surface 19 is shown. Figure 3A In addition to the elements shown in FIG. 1 , the semiconductor device may further include a filling material 56 that completely fills the cavity 100. In an embodiment, the filling material 56 may be a strain-inducing material, such as a material that introduces strain into the columnar field plate 21. The columnar field plate 21 with the embedded strain-inducing material may be under tensile stress or compressive stress. In an embodiment, the strain-inducing material may enhance or at least partially offset the stress of the columnar field plate 21 within the columnar trench 14 so that the mobility of charge carriers that contribute to the flow of current may be increased in a region of the semiconductor substrate 13 adjacent to the columnar trench 14, such as the mesa 16.

[0084] Figure 4A and 4B The diagram shows a top view of a portion of a first main surface 19 of a semiconductor substrate 13 including a transistor device 10 having a plurality of columnar trenches 14, each of which includes a field plate 21 and a field dielectric 20. The columnar trenches 14 may have Figure 2B , 2C , 3C and 3D, wherein the field dielectric 20 is covered by the contact 33. The cavity 100 and the filling material 56 are not shown in FIG. Figure 4A and 4B middle, Figure 4A and 4B Both illustrate a lateral arrangement of four transistor cells 15 arranged in two rows 40 , 41 .

[0085] exist Figure 4A In the embodiment shown in FIG. 1 , each of the transistor cells 15 comprises a columnar trench 14 having a hexagonal shape in a top view. The columnar trenches 14 are arranged in rows, two of which 40 and 41 are shown in FIG. Figure 4A and 4B. Using a Cartesian coordinate system, the columnar grooves 14 are aligned in the y-direction in each row 40 and 41. The columnar grooves 14 of adjacent rows 40, 41 are not aligned with each other in the x-direction, but are typically offset relative to each other in the y-direction by half of the spacing d, i.e., d / 2. Therefore, the array or layout of the grooves 14 includes offset or staggered rows. The spacing or spacing d between adjacent columnar grooves 14 in a row 40 and between adjacent columnar grooves 14 in adjacent rows 40, 41 is substantially the same. The columnar grooves 14 are arranged in a hexagonal array.

[0086] Each of the columnar trenches 14 includes a columnar field plate 21, which also has a hexagonal shape in plan view, like Figure 2B , 2C , 3C and 3D. Figure 4A As can be seen in the top view of FIG. 1 , the contact 33 extends around the field plate 21 and contacts the perimeter of the field plate 21 and also has a hexagonal ring form. The lateral form of the gate electrode 37 (and in embodiments including a trench gate arrangement, the gate trench 38) can also be seen in FIG. Figure 4A . In this embodiment, the gate electrode 37 also has a hexagonal ring form and is disposed in the mesa 16 around each of the columnar trenches 14 in a concentric manner and is separated from the columnar trench 14 by a portion of the mesa 16. The gate electrode 37 can be regarded as including a plurality of hexagonal rings, one hexagonal ring being arranged concentrically with each of the hexagonal columnar trenches 14. These hexagonal rings are connected to each other or form a common gate at positions between adjacent columnar trenches 14 in the columnar trenches 14, so that the gate electrode 37 has a continuous structure and has a continuous hexagonal grid structure.

[0087] Figure 4B A top view of a portion of a first main surface 19 of a semiconductor substrate 13 of a transistor device 10 according to another embodiment is shown. In this embodiment, the columnar grooves 14 have a square shape in the top view. In this embodiment, the field plate 21 in each of the columnar grooves 14 also has a square shape. The contactor 33 has a continuous, uninterrupted ring shape and extends from the side end surface 27 of the field plate 21 to the side wall 18 of the columnar groove 14. The contactor 33 has a ring shape that is square in the lateral direction. The gate electrode 37 also has a square ring shape and is arranged in a concentric manner with each of the columnar grooves 14, and is arranged to be separated from each of the columnar grooves 14. The square sections around the adjacent columnar grooves 14 in the columnar grooves 14 contact each other to form a continuous square grid.

[0088] exist Figure 4BIn the embodiment illustrated in FIG. 4 , the columnar grooves 14 are arranged in offset or staggered rows. Thus, the square rings of one row 40 are aligned in the y direction and offset relative to the square rings of the next row 41 of the array located in the x direction. Using a Cartesian coordinate system, the rings of adjacent rows 40, 41 are typically offset relative to each other in the y direction by half of the spacing d, i.e., d / 2.

[0089] Figure 5A and 5B Show Figure 4A An enlarged top view of one of the columnar grooves 14, whereby Figure 5A A lateral hexagonal columnar trench 14 , a lateral hexagonal field plate 21 and a lateral hexagonal ring contact 33 are shown. Figure 5B Only the metal portion of the ring contact 33 is shown. The ring contact 33 exposes the central portion of the field plate 21, and extends over the concave portion of the field plate 21, and extends over the field dielectric 20, and extends into the concave portion of the mesa 16. Figure 4A , 4B , 5A and 5B, the cavity 100 is shown to have the same shape as the contactor 33 and the field plate 21 (such as, in Figure 4A , 5A , 5B is a hexagon, and like Figure 4B However, the cavity 100 may also have a shape different from that of the contactor 33 and the field plate 21.

[0090] Figures 6A to 6K The method of processing the columnar trench 14 is shown in the figure. The columnar trench 14 has: a field dielectric 20 and a field plate 21, having Figures 3A to 3I In the form of diagram.

[0091] Reference Fig. 6A , a plurality of columnar trenches 14 are formed in a first main surface 19 of a semiconductor substrate 13. The semiconductor substrate 13 is formed of silicon (e.g., single crystal silicon or epitaxial silicon grown on a substrate) and includes a first conductivity type. Each of the columnar trenches 14 has a depth greater than its maximum width (e.g., at least twice the maximum width). The columnar trenches 14 may have different lateral forms, such as circular, square, hexagonal, or octagonal (when viewed from the top).

[0092] Reference Figure 6B , a first dielectric sublayer 50 is formed on the exposed surface of the semiconductor substrate 13, which covers the base 17 and the sidewalls 18 of the pillar trench 14 and the first main surface 19. The first dielectric sublayer 50 can be formed by thermal growth (that is, thermal oxidation of silicon), for example, by thermal annealing of the semiconductor substrate 13, and can be formed of silicon dioxide.

[0093] Reference Figure 6C, the second dielectric sublayer 51 is deposited on the first dielectric sublayer 50 so that it covers the base 17 and the sidewalls 18 of the pillar trench 14 and also covers the first major surface 19. The second dielectric sublayer 51 surrounds the void 53 formed in the pillar trench 14. For example, the second dielectric layer 51 can be deposited using a TEOS (tetraethyl silicate) process.

[0094] Reference Fig.6D , material 52 is then applied, which fills the void 53 in the central region of the columnar trench 14 and also covers the first main surface 19. Material 52 can be conductive (e.g., polysilicon) and can be selected to be suitable for forming a field plate 21 within the columnar trench 14. In other embodiments, material 52 can be a sacrificial material that is then completely removed at a later stage in the process. The material can be conductive or insulating. For example, material 52 can be a photoresist and is electrically insulating. In another example, the sacrificial material that is then completely removed at a later stage in the process can be formed of the same material as the field plate 21 (e.g., polysilicon).

[0095] Material 52 should be selectively removable relative to at least the material of second dielectric sublayer 51 and optionally also relative to the material of both first dielectric sublayer 50 and second dielectric sublayer 51. For example, for a specific etch and / or specific etching conditions, material 52 should be selectively etchable, that is, have a higher etch rate, than first dielectric sublayer 50 and second dielectric sublayer 51.

[0096] Reference Fig. 6E In some embodiments, a planarization process is then performed to remove material 52 from first major surface 19 and expose second dielectric sublayer 51 disposed on first major surface 19. Fig. 6F , a portion of the material 52 is then removed from the upper portion of the columnar trench 14 to form a recess 54, which is lined with a second dielectric layer 51 arranged on the sidewalls 18 of the upper portion of the columnar trench 14 and has a base formed by the remaining portion of the material 52 arranged on the lower portion of the columnar trench 14.

[0097] Reference Figure 6G, the exposed portion of the second dielectric sublayer 51 is removed from the sidewalls 18 of the pillar trench 14 and from the first major surface 19, thereby exposing the first dielectric sublayer 50 below. The first dielectric sublayer 50 and the second dielectric sublayer 51 are formed of materials having different etching rates, so that the second dielectric sublayer 51 can be preferentially or selectively removed relative to the first dielectric sublayer 50 below. This can be achieved by selecting different materials or by using different formation routes of the same material. For example, the first dielectric layer 50 can be a thermally grown silicon dioxide layer, and the second dielectric sublayer 51 can be silicon dioxide formed by a TEOS deposition process. Silicon dioxide formed by a TEOS process has a higher etching rate than silicon dioxide formed by thermal growth. Therefore, the first dielectric layer 50 formed by thermal growth can be used as an etch stop layer, allowing the second dielectric sublayer 51 to be preferentially removed relative to the first dielectric sublayer 50 and also relative to the material 52.

[0098] In some embodiments, an upper portion of the second dielectric layer 51 disposed between the remaining material 52 and the sidewalls 18 of the pillar trench 14 is removed so that an upper portion of the remaining portion of the material 52 protrudes above a remaining portion of the second dielectric sublayer 51 disposed toward the bottom of the pillar trench 14. In some embodiments in which the material 52 comprises a material of a field plate, the method continues by inserting a conductive material in the pillar trench 14 and filling the pillar trench 14 to form the field plate 21. In other embodiments, the method is as follows Figure 6H Continue as shown in .

[0099] Reference Figure 6H , the remaining portion of the material 52 is removed from the pillar trench 14, thereby providing a pillar trench 14 in which the base 17 and the entire sidewall 18 are covered by the first dielectric sublayer 50, and in which the second dielectric sublayer 51 is arranged only on the base 16 and the lower portion of the sidewall 18. Therefore, in the lower portion of the pillar trench 14, the pillar trench 14 is lined with a thicker dielectric layer than in the upper portion of the pillar trench 14. Such a dielectric layer with a non-uniform thickness can provide a field dielectric 20 in the final transistor device.

[0100] Reference Fig.6I , the conductive material 55 is then inserted into the trench 14 and also covers the first main surface 19. In particular, the conductive material 55 is inserted into the trench 14 so that it only partially fills the trench 14. Thus, a gap exists in the trench 14, which leaves (such as forms) a cavity 100 in the conductive material 55. In this process step, the thickness of the deposition of the conductive material 55 is controllable, and thus, the width of the cavity 100 (in Figure 3A , 3B It is equally controllable as the one named w3 in 3C.

[0101] Reference Figure 6J (It may be an optional step of the method of machining a columnar trench), a filling material 56 is then (optionally) inserted into the cavity 100 within the corresponding trench 14 and also on the first main surface 19. The filling material 56 may cover the conductive material 55. The filling material 56 may include an electrical insulator (such as an oxide). Figure 6J , fill material 56 is illustrated as completely filling cavity 100. However, it is also contemplated that fill material 56 may only partially fill cavity 100. For example, fill material can cover only the base and sidewalls of cavity 100 so that a gap may remain in the cavity, which is only partially filled with fill material 56.

[0102] The planarization process is then performed, as Figure 6K , to remove the conductive material 55 and the (optional) filling material 56 from the first main surface 19 and to form an individual columnar field plate 21 in each of the columnar trenches 14. Each of the field plates 21 has a first perimeter in the upper part of the trench 14, the first perimeter being larger than a second perimeter of the field plate 21 in the lower part of the trench 14. The field plates 21 have a step 26 in their side end faces 27 between the narrower lower part and the wider upper part. Similarly, the field dielectric 20 includes a step 25 between the field dielectric 20 in the lower part of the trench 14 formed by the two dielectric sublayers 50, 51 and in the upper part of the trench 14 where the field dielectric 20 is formed only by the first dielectric sublayer 50. In the upper part of the trench 14, the field dielectric 20 has a smaller width than in the lower part of the trench 14. The first dielectric sublayer 50 may provide a thickness t1, and the first dielectric sublayer 50 and the second dielectric sublayer 51 together provide Figures 2A to 2D The thickness t2 of the field dielectric 20 of the columnar trench shown in any of the figures. Figures 3A to 3J As shown and further described, a cavity 100 exists, optionally with a filler material 56 (as described with respect to Figure 3K and 3L shown and discussed).

[0103] Figures 7A to 7H A method for machining a ring contactor for a columnar field plate located in a columnar trench is shown. Figures 6A to 6K After describing the method, refer to Figures 7A to 7H The method described can be implemented, but can also be used for Figures 6A to 6K A semiconductor device including a columnar field plate in a columnar trench fabricated by a method other than the method shown and described. The method may be used to form a Figures 2B to 2D , 3A to 3H, 4A, 4B, 5A and 5B are shown and referred to Figures 2B to 2D, 3A to 3H, 4A, 4B, 5A and 5B describe the ring-shaped contactor 33 of the transistor cell 15 of the semiconductor device 10.

[0104] Reference Fig. 7A After processing the columnar trench 14 with the field plate 21, the transistor structure of the transistor cell 15 can be completed by implanting dopants of the second conductivity type into the first main surface 19 of the semiconductor substrate 13 to form a body region 29 and implanting dopants of the first conductivity type to form a source region 30 on the body region 29. A gate trench 38 can be formed in the mesa 16, lined with a gate dielectric 39, and filled with a conductive material to form a gate electrode 37 in the gate trench 38. Alternatively, a planar gate 37 can be formed on the first main surface 19 of the semiconductor substrate 13. The first main surface 19 is then covered by an electrically insulating layer, which can be a first interlayer dielectric (ILD) 60 of a metallization structure formed on the first main surface 19 of the semiconductor substrate 13. In the example, the gate trench or the planar gate can also be formed on the first main surface 19 of the semiconductor substrate 13. Figures 7A to 7H The described method steps are then formed.

[0105] Reference Figure 7B , a mask 61 is formed on the first interlayer dielectric 60, and openings 62 are formed in the mask 61, thereby exposing the first interlayer dielectric 60. The openings 62 are arranged so that each opening 62 is arranged above the columnar trench 14. Each opening 62 has an annular form, the outer wall is arranged above the mesa 16 that surrounds the columnar trench 14 in the lateral direction and the inner wall is arranged above the upper surface 22 of the field plate 21. The central area of ​​the upper surface 22 of the field plate 21 is covered by the mask 61.

[0106] Reference Figure 7C , the region of the interlayer dielectric 60 exposed by the opening 62 is removed, for example by etching, to form an opening 64 having a size substantially corresponding to the size of the opening 62. The opening 64 exposes the periphery of the upper surface 22 of the field plate 21, the first dielectric sublayer, and the region of the first major surface 19 adjacent to the pillar trench 14. In some embodiments, the opening 64 may also expose a portion of the fill material 56. The portion of the first dielectric sublayer 51 disposed on the uppermost portion of the sidewall 18 of the pillar trench 14 is then removed to form a recess 63 in the upper portion of the pillar trench 14, the recess 63 extending between the side end surface 27 of the field plate 21 and the sidewall of the pillar trench. The side end surface 27 of the field plate 21 and the sidewall 18 of the pillar trench 14 are exposed from the first dielectric sublayer 50.

[0107] Reference Fig.7D The mask 61 is then removed. The peripheral region of the upper surface of the field plate 21 and the portion of the mesa 16 adjacent to the pillar trench 14 are exposed by the opening 64 in the interlayer dielectric 60 .

[0108] Reference Fig. 7E , the interlayer dielectric 60 with its opening 64 is used as a mask, and another etching process is performed. By removing the exposed adjacent portion of the mesa 16 and the exposed peripheral portion of the field plate 21 to form an enlarged annular recess 32 at the top of the pillar trench 14, the width of the recess 63 is increased. In some embodiments, the first dielectric layer 50 within the trench 14 may extend above the base 34 of the recess 32. The field plate 21 now has an upper portion having a fourth perimeter disposed adjacent to the first main surface 19 in a vertical direction. The fourth perimeter is smaller than the first perimeter of the middle portion of the field plate 21. The lower portion of the field plate 21 has a second perimeter smaller than the first perimeter.

[0109] Reference Figure 7F In some embodiments, contact implantation may occur in the periphery of the base 34 of the recess 32 (as schematically indicated by arrow 66 ) and in the body region 29 to form a contact region 65 of the second conductivity type, which is more highly doped than the body region 29 .

[0110] Reference Figure 7G , the conductive material 66 is then inserted into the recess 32 to form an annular contact 33, which extends between the side end surface 27 of the field plate 21 and the sidewall 35 of the recess 32 and electrically connects the field plate 21 to the body region 29 and the source region 30 at a position within the columnar trench 14. In some embodiments, the annular contact 33 electrically connects the field plate 21 to the body region 29 and the source region 30 only at a position within the columnar trench 14.

[0111] Another interlayer dielectric layer 67 may then be deposited, such as Figure 7H As shown in FIG. 1 , interlayer dielectric layer 67 covers field plate 21, annular contact 33 and first main surface 19 of semiconductor substrate 13. Interlayer dielectric 60 not only forms a mask for forming enlarged annular recess 32 at the top of pillar trench 14, but also provides a part of the metallization structure of the transistor device.

[0112] Although specific examples have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific examples shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific examples discussed herein. Therefore, it is intended that the present invention is limited only by the claims and their equivalents.

[0113] It should be noted that the methods and apparatus as outlined in this document including preferred embodiments thereof may be used independently or in combination with other methods and apparatus disclosed in this document. In addition, features outlined in the context of an apparatus also apply to the corresponding method and vice versa. In addition, all aspects of the methods and apparatus outlined in this document may be combined arbitrarily. In particular, the features of the claims may be combined with each other in any manner.

[0114] It should be noted that the description and drawings illustrate only the principles of the proposed method and system. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the present invention and are included in the spirit and scope of the present invention. In addition, all examples and embodiments outlined in this document are primarily intended to be used explicitly only for explanation purposes to help the reader understand the principles of the proposed method and system. In addition, all statements providing the principles, aspects and embodiments of the present invention and specific examples of the present invention in this article are intended to cover their equivalents.

[0115] Although the present disclosure is not limited in this regard, the following numbered examples demonstrate one or more aspects of the present disclosure.

[0116] Example

[0117] Example 1: A transistor device comprises: a semiconductor substrate having a first main surface; and one or more transistor cells, each transistor cell comprising: a columnar trench formed in the semiconductor substrate, wherein the columnar trench comprises a field dielectric, a base and sidewalls, wherein the sidewalls extend from the base to the first main surface, wherein the field dielectric lines the base and sidewalls of the columnar trench, wherein a first thickness of the field dielectric at a first distance from the base is less than a second thickness of the field dielectric at a second distance from the base, and wherein the first distance is greater than the second distance; and a columnar field plate arranged in the columnar trench, wherein a first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance, wherein the columnar field plate comprises a cavity.

[0118] Example 2: The transistor arrangement of Example 1, wherein the cavity is at least partially filled with a filling material, and / or wherein the transistor arrangement further comprises a mesa arranged around the pillar-shaped trench.

[0119] Example 3: The transistor device of Example 1 or 2 further includes: a contact at least partially located within the pillar trench and forming an electrical contact between the field plate and the mesa.

[0120] Example 4: The transistor device of Example 3, wherein a central region of the field plate remains exposed by the contact.

[0121] Example 5: The transistor device of any one of Examples 1 to 4, wherein a fourth perimeter of the columnar field plate at a fourth distance from the substrate is smaller than the first perimeter,

[0122] Example 6: The transistor device of any one of Examples 1 to 4, wherein a fourth perimeter of the columnar field plate at a fourth distance from the substrate is smaller than the first perimeter to form a contact integral with the field plate.

[0123] Example 7: The transistor device of Example 5 or Example 6, wherein the fourth distance is greater than the first distance.

[0124] Example 8: The transistor device of any one of Examples 2 to 7, wherein the contact has a width greater than the first thickness of the field dielectric.

[0125] Example 9: The transistor device of any one of Examples 2 to 8, wherein the contactor comprises a ring shape.

[0126] Example 10: The transistor device of any one of Examples 1 to 9, wherein the contact is located entirely within the pillar-shaped trench.

[0127] Example 11: A transistor device as described in any one of Examples 1 to 10, wherein the columnar trench includes a circular shape, a square shape, a hexagonal shape, or an octagonal shape in a plan view, and the contactor includes a circular ring or a square ring or a hexagonal ring or an octagonal ring in a top view, respectively.

[0128] Example 12: A transistor device as described in any one of Examples 2 to 11, wherein the mesa includes: a drift region of a first conductivity type; a body region of a second conductivity type opposite to the first conductivity type, the body region being arranged on the drift region; and a source region of the first conductivity type, being arranged on the body region.

[0129] Example 13: The transistor device of Example 12, wherein the contact is in electrical contact with the field plate, the source region, and the body region.

[0130] Example 14: The transistor device of Example 12 or 13, wherein a doping concentration in the drift region increases along a direction pointing from the first main surface to a second main surface of the semiconductor substrate opposite to the first main surface.

[0131] Example 15: The transistor device of any of Examples 3 to 14, wherein the contact and the field plate extend to the first main surface.

[0132] Example 16: The transistor device of any of Examples 1 to 15, wherein an upper surface of the field plate and an upper surface of the contact are substantially coplanar with the first major surface.

[0133] Example 17: The transistor device of any one of Examples 1 to 16, wherein the field dielectric has a thickness that increases from a top of the pillar-shaped trench toward a base.

[0134] Example 18: A transistor device as described in any one of Examples 1 to 17, wherein each columnar trench includes a field dielectric, which is arranged on the substrate and the sidewalls and has a thickness t1 in a first region of the sidewall adjacent to the body region and a thickness t2 in a second region of the sidewall adjacent to the drift region, wherein t1≤1.15t2 or t1≤1.2t2 or t1≤1.5t2.

[0135] Example 19: A transistor device as described in any one of Examples 1 to 18, wherein the side end surface of the field plate includes a step so that the upper portion of the field plate has a width greater than the width of the lower portion of the field plate, and so that the field dielectric has a thickness t1 in a first region of the side wall of the columnar trench and a thickness t2 in a second region of the side wall of the columnar trench, wherein t1≤1.15t2 or t1≤1.2t2 or t1≤1.5t2.

[0136] Example 20: The transistor device of any one of Examples 1 to 19, wherein the step is located at a depth d1 relative to the first main surface of the semiconductor substrate, and the pn junction formed between the body region and the drift region has a depth d pn , where d1>d pn .

[0137] Example 21 The transistor device of any one of Examples 1 to 20, wherein a plurality of pillar-shaped trenches are provided, and the pillar-shaped trenches are arranged in offset rows.

[0138] Example 22: The transistor device of any one of Examples 1 to 21, wherein the pillar-shaped trench is substantially square or substantially hexagonal or substantially octagonal in top view.

[0139] Example 23: A transistor device as described in any one of Examples 1 to 22, wherein the one or more transistor cells also include a gate trench formed in the table, wherein the gate trench includes: a base and sidewalls; a gate dielectric lining the base and sidewalls of the gate trench; and a gate electrode arranged in the gate trench, wherein the gate trench surrounds the columnar trench.

[0140] Example 24: The transistor device of any one of Examples 1 to 22, wherein the one or more transistor cells further include a planar gate electrode disposed on the mesa, wherein the planar gate electrode laterally surrounds the pillar-shaped trench.

[0141] Example 25: The transistor device of Example 24, wherein the gate electrode has a grid structure in a top view, the grid structure comprising a square or hexagonal or octagonal grid structure.

[0142] Example 26: A transistor device as described in any one of Examples 1 to 25, wherein the field dielectric includes a first layer and a second layer, and wherein the first thickness of the field dielectric is substantially equal to the thickness of the first layer, and the second thickness of the field dielectric is substantially equal to the sum of the thickness of the first layer and the thickness of the second layer.

[0143] Example 27: The transistor device of any of Examples 1 to 26, wherein the cavity extends from at least the first distance to the first major surface.

[0144] Example 28: The transistor device of any one of Examples 1 to 27, wherein the cavity is arranged at a first distance, and wherein the cavity is not arranged at a second distance.

[0145] Example 29: A transistor device as described in any one of Examples 1 to 28, wherein in a plane orthogonal to the first main surface, at a first distance, the columnar field plate includes a first segment arranged between a field dielectric on one side of the columnar trench and a filling material embedded in the cavity and a second segment arranged between the filling material embedded in the cavity and the field dielectric on the opposite side of the columnar trench.

[0146] Example 30: A transistor device as described in any one of Examples 1 to 29, wherein in a plane orthogonal to the first major surface, at a first distance, the columnar field plate does not extend from the field dielectric on one side of the columnar trench to the field dielectric on the opposite side of the columnar trench.

[0147] Example 31: A transistor device as described in any one of Examples 1 to 30, wherein in a plane orthogonal to the first major surface, at a second distance, the columnar field plate extends from the field dielectric on one side of the columnar trench to the field dielectric on the opposite side of the columnar trench.

[0148] Example 32: A transistor device as described in any one of Examples 1 to 31, wherein in a plane orthogonal to the first major surface, at a third distance from the substrate, the columnar field plate extends from the field dielectric on one side of the columnar trench to the field dielectric on the opposite side of the columnar trench, wherein the third distance is greater than the second distance and the third distance is less than the first distance, wherein a third perimeter of the columnar field plate at the third distance is greater than the second perimeter of the columnar field plate at the second distance.

[0149] Example 33: The transistor device of any of Examples 1 to 32, wherein in a plane parallel to the first main surface, at a first distance, the columnar field plate surrounds a filling material embedded in the cavity.

[0150] Example 34: The transistor device of any one of Examples 1 to 33, wherein in a plane parallel to the first major surface, at the second distance, the columnar field plate is not perforated.

[0151] Example 35: A transistor device as described in any one of Examples 1 to 34, wherein in a plane parallel to the first major surface, the columnar field plate is not perforated at a third distance from the substrate, wherein the third distance is greater than the second distance and the third distance is less than the first distance, wherein a third perimeter of the columnar field plate at the third distance is greater than the second perimeter of the columnar field plate at the second distance.

[0152] Example 36 A method comprising: forming a columnar trench in a first main surface of a semiconductor substrate having a first conductivity type, the columnar trench comprising a base and sidewalls, the sidewalls extending from the base to the first main surface; forming a first dielectric layer on the base and sidewalls of the columnar trench; depositing a second dielectric layer on the first dielectric layer; removing at least a portion of the second dielectric layer from an upper portion of the columnar trench; inserting a conductive material in the columnar trench to form a field plate, wherein the conductive material covers the base and sidewalls of the columnar trench, wherein the conductive material only partially fills the columnar trench, and wherein the conductive material forms a columnar field plate including a cavity.

[0153] Example 37: The method of Example 36, wherein forming a first dielectric layer on a base and sidewalls of the pillar-shaped trench comprises thermally growing the first dielectric layer.

[0154] Example 38: The method of Example 36 or 37, wherein depositing the second dielectric layer comprises depositing the second dielectric layer on the first dielectric layer using a TEOS process.

[0155] Example 39: The method of Example 38 further includes: after depositing the second dielectric layer on the first dielectric layer using the TEOS process, performing an annealing process to densify the second dielectric layer.

[0156] Example 40: The method as described in any one of Examples 36 to 39 further includes: selectively removing the second dielectric layer from an upper portion of the trench and exposing the first dielectric layer.

[0157] Example 41: The method of any one of Examples 36 to 40 further includes inserting a material in the columnar trench after depositing the second dielectric layer on the first dielectric layer.

[0158] Example 42: A method as described in Example 41, wherein the material is a sacrificial material or a conductive material.

[0159] Example 43: The method as described in Example 41 or 42 further includes: removing a portion of the material from an upper portion of the columnar trench and exposing the second dielectric layer on the sidewall of the upper portion of the columnar trench.

[0160] Example 44: A method as described in any one of Examples 41 to 43, wherein the material is a sacrificial material, and the method further includes: after selectively removing the exposed second dielectric liner layer from the sidewalls of the upper portion of the columnar trench, removing the material from the lower portion of the trench and exposing the second dielectric layer in the lower portion of the trench, and then inserting a conductive material into the columnar trench and forming a field plate.

[0161] Example 45: A method as described in any one of Examples 41 to 43, wherein the material is a conductive material, and the method further includes: forming a conductive material on the first main surface when the conductive material is inserted into the columnar trench, performing a planarization process, and forming a field plate in the columnar trench.

[0162] Example 46: A method for processing a transistor device, the method comprising: performing a method as described in any one of Examples 36 to 45, wherein the semiconductor substrate has a first conductivity type; injecting a second conductivity type dopant opposite to the first conductivity type into the first main surface and forming a body region; injecting a first conductivity type dopant into the first main surface and forming a source region on the body region; and forming a gate trench in the mesa, the gate trench comprising a gate electrode and a gate dielectric.

[0163] Example 47: The method as described in Example 46 also includes: removing a portion of the first dielectric layer and the second dielectric layer from the upper portion of the columnar groove, and forming an annular opening, the annular opening exposing the perimeter and the table of the field plate; and inserting a conductive material into the annular opening to form an annular contact, which is in electrical contact with the field plate and the table.

[0164] Example 48: The method as described in any one of Examples 36 to 47, further comprising: forming a dielectric layer on the first main surface; forming an annular opening in the dielectric layer, the annular opening exposing the perimeter of the field plate and the adjacent area of ​​the first main surface; removing the first dielectric layer from the upper portion of the columnar groove, and removing the dielectric layer from the exposed adjacent area of ​​the semiconductor substrate and the peripheral area of ​​the field plate, and forming an annular opening; and inserting a conductive material into the annular opening, and forming an annular contact, the annular contact being in electrical contact with the field plate, the main region and the source region.

[0165] Example 49: The method as described in any one of Examples 36 to 48 further includes: injecting a second dopant into the annular opening.

[0166] Example 50: The method of Example 49 further includes removing material of the semiconductor substrate selectively relative to material of the first dielectric liner layer so that an upper section of the first dielectric liner layer protrudes from a base of the annular opening.

[0167] Example 51: A method as described in any of Examples 36 to 50, wherein forming the annular contact includes: forming one or more conductive layers in the annular opening and filling the annular opening with a conductive material.

[0168] Example 52: The method of any one of Examples 36 to 51 further includes: applying a conductive layer on the annular contact, the annular contact extending above the first major surface.

[0169] Example 53: The method of any one of Examples 36 to 52, further comprising: inserting a filling material in the columnar trench, wherein the filling material at least partially fills the cavity of the columnar field plate.

[0170] Spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to those depicted in the accompanying drawings. Additionally, terms such as "first," "second," etc. are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Similar terms refer to similar elements throughout the description.

[0171] As used herein, the terms "having", "containing", "comprising", "including", etc. are open terms that indicate the presence of stated elements or features, but do not exclude additional elements or features. The articles "a", "an", and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. It should be understood that the features of the various embodiments described herein may be combined with each other unless specifically noted otherwise.

[0172] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that various alternatives and / or equivalent implementations may replace the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptation or variation of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

1. A transistor device comprising: A semiconductor substrate (13) having a first main surface (19); and One or more transistor primitives (15), each transistor primitive comprising: A columnar trench (14) is formed in the semiconductor substrate, wherein: The columnar trench comprises a field dielectric (20), a base (17) and a sidewall (18), The sidewalls extend from the base to the first major surface, The field dielectric lines the base and the sidewalls of the columnar trench, a first thickness (t1) of the field dielectric at a first distance (d1) from the base is smaller than a second thickness (t2) of the field dielectric at a second distance (d2) from the base, and The first distance is greater than the second distance; and A columnar field plate (21) is arranged in the columnar trench, wherein: A first perimeter of the columnar field plate at the first distance is greater than a second perimeter of the columnar field plate at the second distance, and The columnar field plate comprises a cavity (100).

2. The transistor device according to claim 1, The cavity (100) extends at least from the first distance (d1) to the first major surface (19).

3. A transistor device as claimed in claim 1 or 2, The cavity (100) is at least partially filled with a filling material (56).

4. The transistor device according to any one of claims 1 to 3, wherein the cavity (100) is arranged at the first distance (d1), and Wherein the cavity is not arranged at the second distance (d2).

5. The transistor device as claimed in any one of claims 1 to 4, wherein in a plane orthogonal to the first main surface (19), at the first distance (d1), the columnar field plate (21) comprises a first section arranged between the field dielectric (20) on one side of the columnar trench (14) and a filling material (56) embedded in the cavity, and a second section arranged between the filling material embedded in the cavity and the field dielectric on the opposite side of the columnar trench; and / or in, In a plane orthogonal to the first major surface (19), at the first distance (d1), the columnar field plate (21) does not extend from the field dielectric (20) on one side of the columnar trench to the field dielectric on the opposite side of the columnar trench.

6. The transistor device as claimed in any one of claims 1 to 5, Wherein, in a plane orthogonal to the first main surface (19), at the second distance (d2), the columnar field plate (21) extends from the field dielectric (20) on one side of the columnar trench (14) to the field dielectric on the opposite side of the columnar trench.

7. The transistor device as claimed in any one of claims 1 to 6, wherein in a plane orthogonal to the first main surface (19), at a third distance (d3) from the substrate (17), the columnar field plate (21) extends from the field dielectric (20) on one side of the columnar trench to the field dielectric on the opposite side of the columnar trench, wherein the third distance (d3) is greater than the second distance (d2), and the third distance (d3) is less than the first distance (d1), The third perimeter of the columnar field plate at the third distance (d3) is greater than the second perimeter of the columnar field plate at the second distance (d2).

8. The transistor device as claimed in any one of claims 1 to 7, Wherein, in a plane parallel to the first main surface (19), at the first distance (d1), the columnar field plate (21) surrounds the filling material (56) embedded in the cavity ((100)).

9. The transistor device as claimed in any one of claims 1 to 8, Wherein in a plane parallel to the first main surface (19), at the second distance (d2), the columnar field plate (21) is not perforated.

10. The transistor device as claimed in any one of claims 1 to 9, wherein in a plane parallel to the first main surface (19), at a third distance (d3) from the substrate (17), the columnar field plate (21) is not perforated, wherein the third distance (d3) is greater than the second distance (d2), and the third distance (d3) is less than the first distance (d1), The third perimeter of the columnar field plate at the third distance (d3) is greater than the second perimeter of the columnar field plate at the second distance (d2).

11. A method comprising: Forming a columnar trench (14) in a first main surface (19) of a semiconductor substrate (13) having a first conductivity type, the columnar trench comprising a base (17) and a sidewall (18), the sidewall (18) extending from the base to the first main surface; forming a first dielectric layer (50) on the base and sidewalls of the columnar trench; depositing a second dielectric layer (51) on the first dielectric layer; removing at least a portion of the second dielectric layer from an upper portion of the pillar trench; and A conductive material (55) is inserted into the columnar trench, wherein the conductive material covers the base and the sidewalls of the columnar trench, wherein the conductive material only partially fills the columnar trench, and wherein the conductive material forms a columnar field plate (21), wherein the columnar field plate (21) includes a cavity (100).

12. The method of claim 11, further comprising inserting a filling material (56) in the pillar trench (14), wherein the filling material at least partially fills the cavity (100) of the pillar field plate (21).

13. The method of claim 11, wherein forming the first dielectric layer on the base and the sidewalls of the pillar trench comprises thermally growing the first dielectric layer.

14. The method of claim 11 or 13, wherein depositing the second dielectric layer comprises depositing the second dielectric layer on the first dielectric layer using a TEOS process.

15. The method of claim 14, further comprising: After the second dielectric layer is deposited on the first dielectric layer using the TEOS process, an annealing process is performed to densify the second dielectric layer.

16. The method according to any one of claims 11 to 15, further comprising: The second dielectric layer is selectively removed from an upper portion of the trench, and the first dielectric layer is exposed.

17. The method according to any one of claims 11 to 16, further comprising: After depositing a second dielectric layer on the first dielectric layer, a material is inserted in the pillar-shaped trenches.

18. The method of claim 17, wherein the material is a sacrificial material or a conductive material.

19. The method of claim 17 or 18, further comprising: A portion of the material is removed from an upper portion of the pillar trench, and the second dielectric layer on the sidewalls of the upper portion of the pillar trench is exposed.

20. The method of any one of claims 17 to 19, wherein the material is a sacrificial material, and the method further comprises: After selectively removing the exposed second dielectric liner layer from the sidewalls of the upper portion of the pillar trench, removing the material from the lower portion of the trench and exposing the second dielectric layer in the lower portion of the trench, a conductive material is then inserted in the pillar trench and a field plate is formed.

21. The method of any one of claims 17 to 18, wherein the material is a conductive material, and the method further comprises: A conductive material is formed on the first main surface while inserting the conductive material in the pillar-shaped trench, a planarization process is performed, and a field plate is formed in the pillar-shaped trench.

Images