A semiconductor device and a manufacturing method thereof

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductor, and aims at relieving the signal line congestion problem caused by device miniaturization. The semiconductor device comprises a substrate, a first layer semiconductor structure, a second layer semiconductor structure, a first contact structure and a second contact structure. The second layer semiconductor structure is arranged above the first layer semiconductor structure in a thickness direction of the substrate. The first contact structure is arranged in the substrate. The first contact structure comprises a first contact part electrically connected with a first source / drain region of a transistor in the first layer semiconductor structure, and a second contact part electrically connected with a first gate stack structure. The second contact structure is arranged on a side of the second layer semiconductor structure away from the first layer semiconductor structure. The second contact structure comprises a third contact part electrically connected with a second source / drain region of a transistor in the second layer semiconductor structure, and a fourth contact part electrically connected with a second gate stack structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Integrated circuit interconnection technology is a key and necessary part in packaging. Specifically, integrated circuit interconnection technology is a technology of connecting various independent components in the same chip into a circuit module with certain functions through a certain way, which has high importance in advanced packaging. The chip receives power, exchanges signals and finally operates through packaging interconnection. Since the speed, density and function of semiconductor products vary according to the interconnection method, the interconnection method is also constantly changing and developing.

[0003] However, with the miniaturization of devices, after interconnecting various independent components in the existing semiconductor device, the problem of signal line congestion is prone to occur, which leads to poor voltage drop and low working performance of the semiconductor device. SUMMARY

[0004] The present application aims to provide a semiconductor device and a manufacturing method thereof, which can alleviate the problem of signal line congestion caused by device miniaturization, reduce voltage drop, improve the working performance of the semiconductor device, and facilitate the increase of the yield of the semiconductor device.

[0005] To achieve the above-mentioned purpose, in a first aspect, the present application provides a semiconductor device, comprising: a substrate, a first layer semiconductor structure, a second layer semiconductor structure, a first contact structure and a second contact structure. The first layer semiconductor structure is arranged on the substrate. The second layer semiconductor structure is arranged above the first layer semiconductor structure in the thickness direction of the substrate. The first layer semiconductor structure and the second layer semiconductor structure each comprise a plurality of transistors distributed in the thickness direction of the substrate. The first contact structure is arranged in the substrate. The first contact structure comprises a first contact part electrically connected to a first source / drain region of the transistors in the first layer semiconductor structure, and a second contact part electrically connected to a first gate stack structure of at least part of the transistors in the first layer semiconductor structure. The first contact part and the second contact part are insulated from each other. The second contact structure is arranged on a side of the second layer semiconductor structure away from the first layer semiconductor structure. The second contact structure comprises a third contact part electrically connected to a second source / drain region of the transistors in the second layer semiconductor structure, and a fourth contact part electrically connected to a second gate stack structure of at least part of the transistors in the second layer semiconductor structure. The third contact part and the fourth contact part are insulated from each other.

[0006] In the semiconductor device, the first layer semiconductor structure and the second layer semiconductor structure are spaced apart along the thickness direction of the substrate, so that the integration of the semiconductor device is improved, and the semiconductor device is further miniaturized. In addition, for the first layer semiconductor structure at the lower layer, the first source / drain region and the at least partial first gate stack structure are electrically connected to the first contact portion and the second contact portion of the first contact structure respectively, and the first contact structure is arranged below the first layer semiconductor structure, that is, the first source / drain region and the at least partial first gate stack structure in the first layer semiconductor structure are connected in a downward interconnection mode. For the second layer semiconductor structure at the upper layer, the second source / drain region and the at least partial second gate stack structure are electrically connected to the third contact portion and the fourth contact portion of the second contact structure respectively, and the second contact structure is arranged on the side of the second layer semiconductor structure away from the first layer semiconductor structure, that is, the second source / drain region and the at least partial second gate stack structure in the second layer semiconductor structure are connected in an upward interconnection mode. Compared with the prior art in which the two adjacent semiconductor structures are connected in an upward interconnection mode or in a backside power supply mode in which only the source / drain region of the two adjacent semiconductor structures is connected in a downward interconnection mode, when the first layer semiconductor structure at the lower layer is connected in a downward interconnection mode and the second layer semiconductor structure at the upper layer is connected in an upward interconnection mode, at least most of the interconnection contact structures of different layers are spaced apart along the thickness direction of the substrate, so that the problem of signal line congestion caused by device miniaturization is solved, the length of the interconnection transmission path is reduced, the voltage drop is reduced, and the working performance of the semiconductor device is improved. In addition, the first contact portion and the second contact portion of the first contact structure are insulated from each other, and the third contact portion and the fourth contact portion of the second contact structure are insulated from each other, so that the yield of the semiconductor device is improved.

[0007] In an example, the first contact portion and the first source / drain region are directly connected in a backside interconnection mode.

[0008] In an example, the second contact portion and the at least partial first gate stack structure are directly connected in a backside interconnection mode.

[0009] In an example, the first contact portion and the first source / drain region are self-aligned.

[0010] In an example, the semiconductor device further comprises a dielectric side wall arranged between the first contact portion and the second contact portion, and the dielectric side wall is arranged below the first gate side wall of at least one transistor in the first layer semiconductor structure.

[0011] In one example, the first contact, the second contact and the dielectric spacer are aligned away from the end of the second layer semiconductor structure.

[0012] In a second aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising: first, forming a first layer semiconductor structure and a substrate. The first layer semiconductor structure is disposed on the substrate. Next, forming a first contact structure within the substrate. Next, forming a second layer semiconductor structure disposed above the first layer semiconductor structure along a thickness direction of the substrate. The first layer semiconductor structure and the second layer semiconductor structure each comprise a plurality of transistors spaced along a direction perpendicular to the thickness direction of the substrate. The first contact structure comprises a first contact electrically contacting a first source / drain region included in the transistors in the first layer semiconductor structure, and a second contact electrically contacting a first gate stack structure included in at least some of the transistors in the first layer semiconductor structure. The first contact and the second contact are insulated from each other. Next, forming a second contact structure disposed on a side of the second layer semiconductor structure facing away from the first layer semiconductor structure. The second contact structure comprises a third contact electrically contacting a second source / drain region included in the transistors in the second layer semiconductor structure, and a fourth contact electrically contacting a second gate stack structure included in at least some of the transistors in the second layer semiconductor structure. The third contact and the fourth contact are insulated from each other.

[0013] In one example, forming the first layer semiconductor structure comprises: providing a semiconductor substrate. Next, forming a plurality of fin structures spaced along a direction perpendicular to a thickness direction of the substrate on the semiconductor substrate, and forming a mask structure spanning over the fin structures. Next, selectively removing a portion of each fin structure exposed outside the mask structure. Next, under the protection of the mask structure, selectively etching a portion of the semiconductor substrate to form a first opening slot; and forming a pre-formed structure filled in the first opening slot. The pre-formed structure and the semiconductor substrate are of different materials. Next, forming a first source / drain region above the pre-formed structure. Next, forming a first channel region included in the transistors in the first layer semiconductor structure based on the remaining fin structures; and forming a first gate stack structure around the first channel region.

[0014] In one example, forming the substrate and the first contact structure includes: selectively removing the semiconductor substrate. Next, forming the substrate on a side of the first layer semiconductor structure facing away from the second layer semiconductor structure. The substrate and the pre-formed structure are flush on a side of the first layer semiconductor structure facing away from the substrate, and the material of the substrate and the pre-formed structure are different. Next, selectively removing the pre-formed structure; and forming the first contact portion in the first opening slot. Next, selectively removing the substrate under the first gate stack structure to form the second opening slot. Next, forming the dielectric sidewall covering at least the sidewall of the first contact portion in the second opening slot along the length direction of the first gate stack structure. And forming the second contact portion in the remaining second opening slot to obtain the first contact structure.

[0015] In one example, the material of the pre-formed structure includes at least one of silicon nitride, silicon oxynitride, and amorphous carbon.

[0016] In one example, after forming the second layer semiconductor structure spaced apart along the thickness direction of the substrate above the first layer semiconductor structure, forming the substrate and the first contact structure in the substrate.

[0017] The beneficial effects of the second aspect and various implementations thereof in the present application can be analyzed with reference to the beneficial effects of the first aspect and various implementations thereof, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:

[0019] Figure 1 (1) and (2) in FIG. 1 and FIG. 2 respectively show the structure of a semiconductor device in the manufacturing process according to an embodiment of the present application Figure One and a schematic Figure Two ;

[0020] Figure 2 (1) and (2) in FIG. 1 and FIG. 2 respectively show the structure of a semiconductor device in the manufacturing process according to an embodiment of the present application Figure Three and a schematic Figure Four ;

[0021] Figure 3 (1) and (2) in FIG. 1 and FIG. 2 respectively show the structure of a semiconductor device in the manufacturing process according to an embodiment of the present application Figure Five and a schematic Figure Six ;

[0022] Figure 4 (1) and (2) in FIG. 1 and FIG. 2 respectively show the structure of a semiconductor device in the manufacturing process according to an embodiment of the present applicationFigure Seven and indication Figure Eight ;

[0023] Figure 5 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure Nine and indication Figure Ten ;

[0024] Figure 6 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure Ten One and illustration Figure Ten two;

[0025] Figure 7 Parts (1) and (2) in the figure are schematic diagrams of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure Ten Three and diagram Figure Ten Four;

[0026] Figure 8 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure Ten five;

[0027] Figure 9 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure Ten six;

[0028] Figure 10 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure Ten seven;

[0029] Figure 11 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure Ten eight;

[0030] Figure 12 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure Ten Nine;

[0031] Figure 13 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure Two ten;

[0032] Figure 14 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure Two eleven;

[0033] Figure 15 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure Two twelve;

[0034] Figure 16 Structure of semiconductor device in manufacturing process Figure Two Thirteen;

[0035] Figure 17 Structure of semiconductor device in manufacturing process Figure Two Fourteen.

[0036] Reference numerals: 11 is a substrate, 12 is a first layer of semiconductor structure, 13 is a second layer of semiconductor structure, 14 is a transistor, 15 is a first contact structure, 16 is a first contact portion, 17 is a second contact portion, 18 is a first source / drain region, 19 is a first gate stack structure, 20 is a second contact structure, 21 is a third contact portion, 22 is a fourth contact portion, 23 is a second source / drain region, 24 is a second gate stack structure, 25 is a dielectric spacer, 26 is a first gate spacer, 27 is a semiconductor substrate, 28 is a fin structure, 29 is a mask structure, 30 is a first opening slot, 31 is a pre-formed structure, 32 is a first channel region, 33 is a second opening slot, 34 is a second channel region, 35 is a second gate spacer, 36 is a sacrificial gate, 37 is an interlayer dielectric layer. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It should be understood, however, that the description which follows is merely exemplary and is not intended to limit the scope of the application. Furthermore, in the following description, well-known structures and techniques have not been described in detail in order not to unnecessarily obscure the understanding of the application.

[0038] In the drawings, various structural diagrams according to embodiments of the present application are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity, and certain details can be omitted. The shapes of various regions, layers, and the relative sizes and positional relationships between them shown in the drawings are merely exemplary, and in actuality can be deviated due to manufacturing tolerances or technical limitations, and regions / layers having different shapes, sizes, and relative positions can be additionally designed by those skilled in the art according to actual needs.

[0039] In the context of the present application, when one layer / element is said to be located "on" another layer / element, the layer / element can be located directly on the other layer / element, or there can be intervening layers / elements. In addition, if one layer / element is located "on" another layer / element in one orientation, the layer / element can be located "under" the other layer / element when the orientation is reversed. In order to make the technical problems to be solved, technical solutions and beneficial effects of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0040] In addition, the terms "first", "second", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of the technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited. The meaning of "several" is one or more, unless otherwise explicitly specified and limited.

[0041] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0042] Integrated circuit interconnection technology is a key and necessary part in packaging. Specifically, integrated circuit interconnection technology is a technology for connecting various independent components in the same chip into a circuit module with certain functions through a certain way, which has high importance in advanced packaging. Chips are interconnected through packaging to receive power, exchange signals and finally operate. Since the speed, density and function of semiconductor products vary according to the interconnection method, the interconnection method is also constantly changing and developing.

[0043] However, with the miniaturization of the device, after interconnecting the individual components in the existing semiconductor device, the problem of signal line congestion is prone to occur, leading to poor voltage drop and low working performance of the semiconductor device. Although, the skilled in the art has developed a backside power supply network to improve the bottleneck of power supply and signal line and battery utilization by arranging power supply wiring on the back of the wafer, due to the small size of the device, when making the buried power layer directly electrically connected with the source / drain region included in the transistor on the back, there is a problem of alignment accuracy, the buried power layer is prone to short with the gate stack structure of the transistor, leading to device failure, which is still not conducive to improving the working performance of the semiconductor device.

[0044] To solve the above technical problems, the embodiments of the present application provide a semiconductor device and a manufacturing method thereof. In the semiconductor device provided by the embodiments of the present application, when the first source / drain region and at least part of the first gate stack structure included in the first layer semiconductor structure located in the lower layer are interconnected downward, and the second source / drain region and at least part of the second gate stack structure included in the second layer semiconductor structure located in the upper layer are interconnected upward, at least most of the interconnection contact structures of different layers can be separated along the thickness direction of the substrate, which can alleviate the problem of signal line congestion caused by device miniaturization.

[0045] Specifically, in one aspect, Figure 13 and Figure 17 the semiconductor device provided by the embodiments of the present application comprises: a substrate 11, a first layer semiconductor structure 12, a second layer semiconductor structure 13, a first contact structure 15 and a second contact structure 20. The first layer semiconductor structure 12 is arranged on the substrate 11. The second layer semiconductor structure 13 is arranged above the first layer semiconductor structure 12 along the thickness direction of the substrate 11. The first layer semiconductor structure 12 and the second layer semiconductor structure 13 both comprise a plurality of transistors 14 distributed along the thickness direction perpendicular to the substrate 11. The first contact structure 15 is arranged in the substrate 11. The first contact structure 15 comprises a first contact part 16 electrically connected with the first source / drain region 18 included in the transistor 14 in the first layer semiconductor structure 12, and a second contact part 17 electrically connected with the first gate stack structure 19 included in at least part of the transistor 14 in the first layer semiconductor structure 12. The first contact part 16 and the second contact part 17 are insulated from each other. The second contact structure 20 is arranged on the side of the second layer semiconductor structure 13 away from the first layer semiconductor structure 12. The second contact structure 20 comprises a third contact part 21 electrically connected with the second source / drain region 23 included in the transistor 14 in the second layer semiconductor structure 13, and a fourth contact part 22 electrically connected with the second gate stack structure 24 included in at least part of the transistor 14 in the second layer semiconductor structure 13. The third contact part 21 and the fourth contact part 22 are insulated from each other.

[0046] In the case of the above technical solution, if Figure 13 and Figure 17 In the semiconductor device provided by the embodiment of the present application, the first layer semiconductor structure 12 and the second layer semiconductor structure 13 are spaced apart along the thickness direction of the substrate 11, which facilitates the improvement of the integration of the semiconductor device and the further miniaturization of the semiconductor device. In addition, for the first layer semiconductor structure 12 located at the lower layer, the first source / drain region 18 and the at least partial first gate stack structure 19 included in the first layer semiconductor structure 12 are electrically connected to the first contact part 16 and the second contact part 17 included in the first contact structure 15, respectively; and the first contact structure 15 is arranged below the first layer semiconductor structure 12, that is, the first source / drain region 18 and the at least partial first gate stack structure 19 in the first layer semiconductor structure 12 are connected in a downward interconnection mode. For the second layer semiconductor structure located at the upper layer, the second source / drain region 23 and the at least partial second gate stack structure 24 included in the second layer semiconductor structure 13 are electrically connected to the third contact part 21 and the fourth contact part 22 included in the second contact structure 20, respectively; and the second contact structure 20 is arranged on the side of the second layer semiconductor structure 13 away from the first layer semiconductor structure 12, that is, the second source / drain region 23 and the at least partial second gate stack structure 24 in the second layer semiconductor structure 13 are connected in an upward interconnection mode. In this case, compared with the prior art in which the two adjacent semiconductor structures are connected in an upward interconnection mode or in which only the source / drain region in the two adjacent semiconductor structures is connected in a downward interconnection mode, when the first source / drain region 18 and the at least partial first gate stack structure 19 included in the first layer semiconductor structure 12 located at the lower layer are connected in a downward interconnection mode and the second source / drain region 23 and the at least partial second gate stack structure 24 included in the second layer semiconductor structure located at the upper layer are connected in an upward interconnection mode, at least most of the interconnection contact structures of different layers can be spaced apart along the thickness direction of the substrate 11, which can alleviate the problem of signal line congestion caused by the miniaturization of the device, and also facilitates the reduction of the length of the interconnection transmission path, the reduction of the voltage drop and the improvement of the working performance of the semiconductor device; and the first contact part 16 and the second contact part 17 included in the first contact structure 15 are insulated from each other, and the third contact part 21 and the fourth contact part 22 included in the second contact structure 20 are insulated from each other, which prevents short-circuit failure and facilitates the increase of the yield of the semiconductor device.

[0047] In actual application, the structure and material of the substrate are not limited in the embodiment of the present application, and any material that can be applied to the semiconductor device provided by the embodiment of the present application can be used. For example, the material of the substrate can include an insulating material such as silicon oxide, silicon nitride or silicon oxynitride, which can further reduce the risk of leakage between the first contact part and the second contact part in the first contact structure arranged in the substrate.

[0048] Specifically, the substrate can be a single-layer structure comprising only one material. Alternatively, the substrate can be a laminated structure comprising at least two materials. In this case, the distribution of different material regions within the substrate can be determined based on the specific manufacturing process of the substrate, and is not specifically limited here. For example, different material regions within the substrate can be stacked along the thickness direction of the substrate.

[0049] For the first and second semiconductor layers described above, the first semiconductor layer is located below the second semiconductor layer along the thickness direction of the substrate, and the spacing between them can be set according to actual needs. Furthermore, the number and type of transistors included in the first and second semiconductor layers, as well as the distribution of different transistors, can be set according to the actual application scenario, as long as they can be applied to the semiconductor device provided in this embodiment of the invention. For example, the different transistors included in the first and / or second semiconductor layers can be fin field-effect transistors and / or gate-around transistors. Specifically, for the same first or second semiconductor layer, the device types of different transistors can be the same, such as all different transistors being fin field-effect transistors or gate-around transistors; or, the device types of different transistors can be different, such as some transistors being fin field-effect transistors and the rest being gate-around transistors. The device types of the transistors included in the first and second semiconductor layers can be the same or different.

[0050] For a single transistor, such as Figure 17 As shown, the transistor 14 in the first semiconductor structure 12 includes a first source / drain region 18, a first channel region 32, and a first gate stack structure 19. The first channel region 32 is located between the first source / drain regions 18 and contacts the first source / drain regions 18 on both sides along its length. The first gate stack structure 19 is located on the outer periphery of the first channel region 32. Furthermore, the transistor in the first semiconductor structure 12 may also include first gate sidewalls 26 located at least on both sides of the first gate stack structure 19 along its length. Additionally, if the transistor 14 in the first semiconductor structure 12 is a gate-to-ring transistor, the transistor 14 in the first semiconductor structure 12 may also include a first inner sidewall located between the first gate stack structure 19 and the first source / drain regions 18.

[0051] The materials of the first source / drain region and the first channel region can include any semiconductor material such as silicon, silicon germanium, or germanium. The first gate stack structure can include a first gate dielectric layer and a first gate located on the outer periphery of the first channel region. The material of the first gate dielectric layer can include insulating materials with high dielectric constants such as HfO2, ZrO2, TiO2, or Al2O3. The material of the first gate can be a conductive material such as TiN, TaN, or TiSiN. The materials of the first gate sidewalls and inner sidewalls can include insulating materials such as SiO2, SiN, SiCO, or SiCON.

[0052] As for the transistors in the second-layer semiconductor structure, such as Figure 17 As shown, it includes a second source / drain region 23, a second channel region 34, and a second gate stack structure 24. The second channel region 34 is located between the second source / drain regions 23 and contacts the second source / drain regions 23 on both sides along its length. The second gate stack structure 24 is located on the outer periphery of the second channel region 34. Furthermore, the transistor 14 in the second semiconductor structure 13 may also include second gate sidewalls 35 located at least on both sides of the second gate stack structure 24 along its length. Additionally, if the transistor 14 in the second semiconductor structure 13 is a gate-to-ring transistor, the transistor 14 in the second semiconductor structure 13 may also include a second inner sidewall located between the second gate stack structure 24 and the second source / drain regions 23.

[0053] As for the materials of the second source / drain region, the second channel region, the second gate stack structure, the second gate sidewall, and the second inner sidewall, they can refer to the materials of the first source / drain region, the first channel region, the first gate stack structure, the first gate sidewall, and the first inner sidewall described above, and will not be repeated here.

[0054] For the aforementioned first contact structure, such as Figure 17 As shown, a first contact structure 15 is disposed within the substrate 11 to bring out the first source / drain region 18 and at least a portion of the first gate stack structure 19 in the first semiconductor structure 12 via a downward interconnection. Specifically, the first contact structure 15 includes a first contact portion 16 electrically contacting the first source / drain region 18 and a second contact portion 17 electrically contacting the first gate stack structure 19 included in at least a portion of the transistor 14. The materials of the first contact portion 16 and / or the second contact portion 17 may include conductive materials such as copper, tungsten, silver, or doped polysilicon. The materials of the first contact portion 16 and the second contact portion 17 may be the same or different.

[0055] Secondly, the first contact portion and the first source / drain region are interconnected using a deep trench via (DTV); or, as... Figure 17As shown, the contact method between the first contact portion 16 and the first source / drain region 18 can also be direct contact on the back side, so as to further reduce the occupied area of ​​the first contact structure 15 and further reduce the voltage drop; in addition, in this case, the first contact portion 16 can be self-aligned with the first source / drain region 18, which reduces the risk of leakage current and helps to reduce the difficulty of subsequent interconnection processes.

[0056] As for the second contact portion, the contact method between the second contact portion and at least a portion of the first gate stack structure can be a deep trench or a direct back-side contact. Alternatively, it can be that different second contact portions make electrical contact with all the first gate stack structures included in the first layer semiconductor structure; or, in all the first gate stack structures, some of the first gate stack structures are led out through the second contact portion by downward interconnection, while the remaining first gate stack structures are led out through the fifth contact portion included in the second contact structure by upward interconnection.

[0057] Furthermore, the first contact portion and the second contact portion are insulated from each other; specifically, they can be insulated from each other via a non-conductive substrate. Alternatively, as... Figure 17 As shown, the semiconductor device may further include a dielectric sidewall 25 located between the first contact 16 and the second contact 17, and below the first gate sidewall 26 of at least a portion of the transistors 14 in the first semiconductor structure 12. In this case, the first contact 16 and the second contact 17 can be electrically isolated by the dielectric sidewall 25, and since the dielectric sidewall 25 is located below the first gate sidewall 26, the presence of the dielectric sidewall 25 along the arrangement direction of the first contact 16 and the second contact 17 will not occupy too much of the formation space of the first contact 16 and the second contact 17, ensuring that the first contact 16 and the second contact 17 have a large lateral transmission area.

[0058] Specifically, the material of the dielectric sidewall can include any insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Additionally, such as Figure 17 As shown, the ends of the first contact portion 16, the second contact portion 17, and the dielectric sidewall 25 that are away from the second semiconductor structure 13 can be aligned to prevent the first contact portion 16 and the second contact portion 17 from short-circuiting and failing during the formation of the second contact portion 17 after the formation of the first contact portion 16 and the dielectric sidewall 25, if the second contact material on the first contact portion 16 and the dielectric sidewall 25 is not completely removed, thus ensuring that the semiconductor device has high electrical reliability.

[0059] For the second contact structure mentioned above, such as Figures 1 to 17As shown, the second contact structure 20 is disposed on the second layer semiconductor structure 13 away from the first layer semiconductor structure 12, so as to lead out the second source / drain region 23 and at least part of the second gate stack structure 24 in the second layer semiconductor structure 13 in an upward interconnection manner. Specifically, the second contact structure 20 comprises a third contact part 21 electrically contacting the second source / drain region 23, and a fourth contact part 22 electrically contacting at least part of the second gate stack structure 24. The present embodiment does not make specific limitation on the contact manner between the third contact part 21 and the second source / drain region 23, and the contact manner between the fourth contact part 22 and at least part of the second gate stack structure 24. The materials of the third contact part 21 and the fourth contact part 22 can refer to the materials of the first contact part 16 and the second contact part 17 as described above, which will not be repeated here. In addition, the third contact part 21 and the fourth contact part 22 can be insulated from each other by an interlayer dielectric layer 37 or the like insulating structure.

[0060] In a second aspect, the present embodiment provides a manufacturing method of a semiconductor device. The following will be described according to the manufacturing process of the semiconductor device shown in the sectional view of the operation. Figure 1 The manufacturing process of the semiconductor device will be described in detail with reference to the sectional view of the operation shown in the following figures. Specifically, the manufacturing method of the semiconductor device comprises the following steps:

[0061] Firstly, a first layer semiconductor structure and a substrate are formed. The first layer semiconductor structure is disposed on the substrate.

[0062] Next, a first contact structure is formed in the substrate.

[0063] Next, a second layer semiconductor structure is formed above the first layer semiconductor structure spaced apart along the thickness direction of the substrate. Both the first layer semiconductor structure and the second layer semiconductor structure comprise a plurality of transistors spaced apart along the thickness direction perpendicular to the substrate. The first contact structure comprises a first contact part electrically contacting a first source / drain region included in the transistors in the first layer semiconductor structure, and a second contact part electrically contacting a first gate stack structure included in at least part of the transistors in the first layer semiconductor structure. The first contact part and the second contact part are insulated from each other.

[0064] Next, a second contact structure is formed disposed on the second layer semiconductor structure away from the first layer semiconductor structure. The second contact structure comprises a third contact part electrically contacting a second source / drain region included in the transistors in the second layer semiconductor structure, and a fourth contact part electrically contacting a second gate stack structure included in at least part of the transistors in the second layer semiconductor structure. The third contact part and the fourth contact part are insulated from each other.

[0065] The beneficial effects of the second aspect and various implementation manners thereof in the present embodiment can be referred to the beneficial effect analysis of the first aspect and various implementation manners thereof, which will not be repeated here.

[0066] Specifically, the semiconductor device manufactured in the second aspect of the embodiments of the present application has the same structure as the semiconductor device provided in the first aspect described above. Therefore, the specific structure and materials of the first layer semiconductor structure, the substrate, the first contact structure, the second layer semiconductor structure and the second contact structure in the semiconductor device manufactured in the second aspect can refer to the description above, and will not be described here again.

[0067] For example, the formation of the first layer semiconductor structure can include the following steps: first, a semiconductor substrate is provided. The semiconductor substrate can be a substrate made of any semiconductor material, such as a silicon substrate, a silicon-on-insulator substrate, a germanium-silicon substrate or a germanium substrate.

[0068] Next, a plurality of fin structures spaced apart along the thickness direction perpendicular to the substrate are formed on the semiconductor substrate, and a mask structure is formed across the fin structures.

[0069] Specifically, the specific manufacturing process of the fin structure can be determined according to the type of the transistor included in the first layer semiconductor structure. For example, in the case where the transistor included in the first layer semiconductor structure is a fin field effect transistor, photolithography and etching processes can be used to directly etch the semiconductor substrate to obtain a fin portion; then deposition and other processes are used to form a shallow trench isolation structure, wherein the portion of the fin portion exposed outside the shallow trench isolation structure is the fin structure. Alternatively, an epitaxial process can be used to first form a semiconductor layer on the semiconductor substrate, and then photolithography and etching processes are used to etch the semiconductor layer and part of the semiconductor substrate to obtain a fin portion; then deposition and other processes are used to form a shallow trench isolation structure (the top of the shallow trench isolation structure is less than or equal to the bottom of the semiconductor layer), wherein the portion of the fin portion exposed outside the shallow trench isolation structure is the fin structure.

[0070] For another example, in the case where the transistor included in the first layer semiconductor structure is a gate-all-around transistor, an epitaxial process can be used to first form alternatingly stacked sacrificial layers and channel layers on the semiconductor substrate, wherein the film layer at the bottom of the alternatingly stacked sacrificial layers and channel layers is the sacrificial layer; then photolithography and etching processes are used to etch the alternatingly stacked sacrificial layers and channel layers and part of the semiconductor substrate to obtain a fin portion; then deposition and other processes are used to form a shallow trench isolation structure (the top of the shallow trench isolation structure is less than or equal to the bottom of the semiconductor layer), wherein the portion of the fin portion exposed outside the shallow trench isolation structure is the fin structure.

[0071] After the fin structure is formed, deposition and etching processes can be used to form the mask structure. The embodiments of the present application do not make specific limitations on the specific structure and materials of the mask structure. For example, the mask structure can include a sacrificial gate. For another example, as shown in FIG. 2B, the mask structure can include a gate-all-around structure 20. Figure 1As shown in the (1) and (2) parts of FIG. 1, the mask structure 29 can include a sacrificial gate 36 and a first gate sidewall 26 on both sides of the sacrificial gate 36 along the length direction.

[0072] Next, as shown in the (1) and (2) parts of FIG. 2, the exposed part of each fin structure 28 can be removed by using a wet etching or dry etching process. Figure 2

[0073] Next, as shown in the (1) and (2) parts of FIG. 3, the semiconductor substrate 27 can be selectively etched to form a first opening slot 30 under the protection of the mask structure 29; as shown in the (1) and (2) parts of FIG. 4, a pre-formed structure 31 can be formed in the first opening slot 30. Figure 3 Figure 4

[0074] Specifically, the first opening slot is used for filling to form a first contact, and the pre-formed structure plays a pre-occupying role. After at least forming a first layer semiconductor structure, the first opening slot can be released by selectively removing the pre-formed structure, so as to prevent the direct formation of the first contact from affecting the formation of other structures and affecting the formation quality of the first contact. The material of the pre-formed structure can include a dielectric material or a semiconductor material, as long as it is different from the material of the semiconductor substrate. For example, the material of the pre-formed structure can include at least one of silicon nitride, silicon oxynitride, and amorphous carbon.

[0075] Next, as shown in the (1) and (2) parts of FIG. 5, a first source / drain region 18 can be formed above the pre-formed structure 31 by using an epitaxy process. Figure 5

[0076] Next, as shown in the (1) and (2) parts of FIG. 6, an interlayer dielectric layer 37 can be formed on the semiconductor substrate 27 by using a deposition and chemical mechanical polishing process, and the top of the interlayer dielectric layer 37 is flush with the top of the mask structure 29. The material of the interlayer dielectric layer 37 can include an insulating material such as silicon oxide or silicon nitride. Figure 6

[0077] Next, as shown in the (1) and (2) parts of FIG. 7, a first channel region 32 included in a transistor in a first layer semiconductor structure can be formed based on the remaining fin structure; as shown in the (1) and (2) parts of FIG. 8, a first gate stack structure 19 can be formed on the outer periphery of the first channel region 32. Figure 7 Figure 8

[0078] ​​​​​​​Specifically, the specific process of forming the first channel region and the first gate stack structure can be determined according to the device type of the transistor included in the first layer semiconductor structure, which is not specifically limited here.

[0079] For example, in the case where the transistor included in the first layer semiconductor structure is a fin field effect transistor, a wet etching or dry etching process can be used to selectively remove at least part of the mask structure. At this time, the remaining fin structure forms the first channel region. Then, an atomic layer deposition process is used to form the first gate stack structure.

[0080] For another example, in the case where the transistor included in the first layer semiconductor structure is a gate-all-around transistor, a wet etching or dry etching process can be used to selectively remove at least part of the mask structure and remove the remaining sacrificial layer. At this time, the remaining channel layer forms the first channel region. Then, an atomic layer deposition process is used to form the first gate stack structure.

[0081] As shown in parts (1) and (2) of FIG. 1 and FIG. 2, Figure 9 After the first layer semiconductor structure 12 is formed, the second layer semiconductor structure 13 can be formed first. The specific manufacturing process of the second layer semiconductor structure 13 can refer to the manufacturing process of the first layer semiconductor structure 12 described above, which is not repeated here. The difference is that the first opening slot and the pre-formed structure do not need to be formed when manufacturing the second layer semiconductor structure 13. Then, a base is formed, and the first contact structure is formed in the base.

[0082] Alternatively, the base and the first contact structure can also be formed before the second layer semiconductor structure is formed. The specific formation sequence of the base and the first contact structure can be determined according to actual needs, which is not specifically limited here.

[0083] For example, the formation of the base and the first contact structure can include the steps of: as shown in parts (1) and (2) of FIG. 3 and FIG. 4, Figure 10 and Figure 11 A wet etching or dry etching process can be used to selectively remove the semiconductor substrate. At this time, because the material of the pre-formed structure 31 is different from that of the semiconductor substrate, the pre-formed structure 31 is retained after the semiconductor substrate is removed.

[0084] Next, as shown in parts (1) and (2) of FIG. 5 and FIG. 6, Figure 12As shown in the (1) and (2) parts of FIG. 1, the base 11 can be formed on the side of the first semiconductor structure 12 away from the second semiconductor structure 13 by deposition, chemical mechanical polishing, or the like. The base 11 and the pre-formed structure 31 are flush on the side away from the first semiconductor structure 12, and the materials of the base 11 and the pre-formed structure 31 are different. Specifically, the material and structure of the base 11 can refer to the foregoing. Wherein, the base 11 and the pre-formed structure 31 are flush on the side away from the first semiconductor structure 12, so that the pre-formed structure 31 is exposed, facilitating the subsequent selective removal of the pre-formed structure 31.

[0085] Next, as shown in the (1) and (2) parts of FIG. 2, the pre-formed structure can be selectively removed by wet etching or dry etching, or the like. At this time, the first opening slot 30 is released. Figure 13 Next, as shown in the (1) and (2) parts of FIG. 2, the pre-formed structure can be selectively removed by wet etching or dry etching, or the like. At this time, the first opening slot 30 is released. Figure 14 Next, as shown in the (1) and (2) parts of FIG. 3, the first contact portion 16 can be formed in the first opening slot by sputtering or evaporation, or the like.

[0086] Figure 14 Next, as shown in the (1) and (2) parts of FIG. 4, the part of the base 11 under the first gate stack structure 19 can be selectively removed by wet etching or dry etching, or the like, to form a second opening slot 33. The second opening slot 33 is at least used to fill the second contact portion.

[0087] It should be noted that, in the process of forming the second opening slot, only the part of the base under the first gate stack structure can be removed; or, as shown in the (1) and (2) parts of FIG. 4, the part of the base 11 in contact with the first gate dielectric layer can also be removed at the same time, so that the subsequently formed second contact portion can be directly in electrical contact with the first gate electrode, reducing the contact resistance. Figure 15 Next, as shown in the (1) and (2) parts of FIG. 5, a dielectric side wall 25 covering at least the sidewall of the first contact portion 16 can be formed in the second opening slot 33 and along the length direction of the first gate stack structure 19 by deposition and etching, or the like. The material of the dielectric side wall 25 can refer to the foregoing.

[0088] Figure 16 Next, as shown in the (1) and (2) parts of FIG. 6, the second contact portion 17 can be formed in the remaining second opening slot by sputtering or evaporation, or the like, to obtain a first contact structure 15.

[0089] Next, as shown in the (1) and (2) parts of FIG. 6, the second contact portion 17 can be formed in the remaining second opening slot by sputtering or evaporation, or the like, to obtain a first contact structure 15. Figure 17 It should be noted that, if the first contact portion and the second contact portion are separated by the base, the manufacturing process of the dielectric side wall described above can not be performed.

[0090]

[0091] ​​​As for the manufacturing process of the second contact structure, such as ​ As shown in parts (1) and (2), a process such as deposition can be used to first form an interlayer dielectric layer 37 on the side of the second semiconductor structure 13 away from the substrate. Then, a process such as etching is used to form contact holes; and a process such as sputtering or evaporation is used to form a third contact portion 21 and a fourth contact portion 22 filling the contact holes, thereby obtaining the second contact structure 20.

[0092] It should be noted that the above-described second contact structure and second semiconductor structure can be formed in various ways. How to form the above structure is not the main feature of this invention; therefore, it is only briefly described in this specification to enable those skilled in the art to easily implement this invention. Those skilled in the art can certainly conceive of other ways to fabricate the above-described second contact structure and second semiconductor structure.

[0093] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0094] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A semiconductor device, characterized by, comprising a substrate, a first layer of semiconductor structures disposed on the substrate; a second layer of semiconductor structures disposed above the first layer of semiconductor structures along a thickness direction of the substrate; the first and second layers of semiconductor structures each comprising a plurality of transistors spaced along a direction perpendicular to the thickness direction of the substrate; a first contact structure disposed within the substrate; the first contact structure comprising a first contact portion electrically contacting first source / drain regions of the transistors in the first layer of semiconductor structures, and a second contact portion electrically contacting first gate stack structures of at least some of the transistors in the first layer of semiconductor structures; the first contact portion and the second contact portion being insulated from each other; a second contact structure disposed on a side of the second layer of semiconductor structures facing away from the first layer of semiconductor structures; the second contact structure comprising a third contact portion electrically contacting second source / drain regions of the transistors in the second layer of semiconductor structures, and a fourth contact portion electrically contacting second gate stack structures of at least some of the transistors in the second layer of semiconductor structures; the third contact portion and the fourth contact portion being insulated from each other.

2. The semiconductor device according to claim 1, wherein the first contact portion and the first source / drain regions are in backside direct contact; and / or the second contact portion and the first gate stack structures are in backside direct contact.

3. The semiconductor device of claim 1, wherein the first contact portion is self-aligned to the first source / drain regions.

4. The semiconductor device of claim 1, wherein the semiconductor device further comprises a dielectric spacer between the first contact portion and the second contact portion, and below first gate spacers of at least some of the transistors in the first layer of semiconductor structures.

5. The semiconductor device according to claim 4, wherein end portions of the first contact portion, the second contact portion, and the dielectric spacer are aligned away from the second layer of semiconductor structures.

6. A method of manufacturing a semiconductor device, characterized by comprising: forming a first layer of semiconductor structures and a substrate; the first layer of semiconductor structures is disposed on the substrate; forming a first contact structure within the substrate; forming a second layer of semiconductor structures disposed above the first layer of semiconductor structures along a thickness direction of the substrate; the first and second layers of semiconductor structures each comprising a plurality of transistors spaced along a direction perpendicular to the thickness direction of the substrate; the first contact structure comprising a first contact portion electrically contacting first source / drain regions of the transistors in the first layer of semiconductor structures, and a second contact portion electrically contacting first gate stack structures of at least some of the transistors in the first layer of semiconductor structures; the first contact portion and the second contact portion being insulated from each other; forming a second contact structure disposed on a side of the second layer of semiconductor structures facing away from the first layer of semiconductor structures; the second contact structure comprising a third contact portion electrically contacting second source / drain regions of the transistors in the second layer of semiconductor structures, and a fourth contact portion electrically contacting second gate stack structures of at least some of the transistors in the second layer of semiconductor structures; the third contact portion and the fourth contact portion being insulated from each other.

7. The method of manufacturing a semiconductor device according to claim 6, wherein forming the first layer semiconductor structure includes: providing a semiconductor substrate; forming a plurality of fin structures spaced along a thickness direction perpendicular to the substrate and a mask structure across the fin structures on the semiconductor substrate; selectively removing a portion of each of the fin structures exposed outside the mask structure; selectively etching a portion of the semiconductor substrate under the protection of the mask structure to form a first opening groove and a pre-formed structure filled in the first opening groove; the pre-formed structure and the semiconductor substrate are of different materials; forming the first source / drain region above the pre-formed structure; forming a first channel region included in the transistor in the first layer semiconductor structure based on the remaining fin structures and forming the first gate stack structure around the first channel region.

8. The method of manufacturing a semiconductor device according to claim 7, wherein forming the substrate and the first contact structure includes: selectively removing the semiconductor substrate; forming the substrate on a side of the first layer semiconductor structure facing away from the second layer semiconductor structure; the substrate and the pre-formed structure are flush on a side of the first layer semiconductor structure facing away from the substrate and the pre-formed structure are of different materials; selectively removing the pre-formed structure and forming the first contact in the first opening groove; selectively removing a portion of the substrate under the first gate stack structure to form a second opening groove; forming a dielectric side wall covering at least a sidewall of the first contact along a length direction of the first gate stack structure in the second opening groove and forming the second contact in the remaining second opening groove to obtain the first contact structure.

9. The method of manufacturing a semiconductor device according to Claim 7, wherein the material of the pre-formed structure includes at least one of silicon nitride, silicon oxynitride and amorphous carbon.

10. The method of manufacturing a semiconductor device according to any one of claims 6 to 9, wherein forming the substrate and the first contact structure after forming the second layer semiconductor structure spaced above the first layer semiconductor structure along a thickness direction of the substrate.

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