Cascode type normally-off gallium nitride power device and preparation method thereof

Abstract

The invention relates to the field of semiconductor devices, in particular to a cascode type normally-off gallium nitride power device and a preparation method thereof. The cascode type normally-off gallium nitride power device comprises a diamond MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a depletion type GaN JFET which are interconnected; a first drain electrode, a plurality of first grid electrodes and a first source electrode are arranged on the depletion type GaN JFET, the diamond MOSFET is in metal interconnection with the depletion type GaN JFET, a second drain electrode, a second grid electrode and a second source electrode are arranged on the diamond MOSFET, the plurality of first grid electrodes are connected in parallel and then connected with the second source electrode in series, and the first source electrode is communicated with the second drain electrode. By using the cascode structure, the low-loss diamond MOSFET can control the turn-off of the high-voltage normally-open gallium nitride JFET in a smaller space, the advantages of the gallium nitride material are maintained, the heat dissipation performance of the device is effectively enhanced, the electrical performance of the device is improved, and the service life of the device is prolonged.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to a common-source and common-gate normally-off gallium nitride power device and a preparation method thereof. Background Art

[0002] With the rapid development of new technology fields such as artificial intelligence, autonomous driving, 5G networks and the Internet of Things, the requirements for the performance indicators, integration density and environmental adaptability of electronic devices are becoming increasingly stringent.

[0003] Compared with silicon and silicon carbide, gallium nitride (GaN) materials have higher electron mobility, saturated electron velocity and breakdown electric field. Based on the material advantages, GaN power devices can achieve smaller on-resistance and gate charge (which means better conduction and switching performance). In high-frequency applications, they can effectively improve the efficiency and power density of the converter. Therefore, GaN power devices are widely used in power adapters, car charging, data centers and other fields.

[0004] At present, for GaN JFET (Junction Field-Effect Transistor), it is often designed as a depletion-mode device for performance and cost considerations, that is, at room temperature, GaN JFET is a normally-on device, and it will only be turned off when the gate increases the negative bias. This means that once there is a depletion-mode GaN JFET in the circuit, the complexity of the gate drive design will increase, and it is easy to mis-conduct, with a potential threat of direct conduction, which will reduce the stability and safety of the circuit. To solve this problem, relevant researchers proposed to connect the enhancement-mode silicon MOSTET (Metal Oxide Semiconductor Field-Effect Transistor) and the depletion-mode GaN JFET in series to construct a monolithic enhancement-mode GaN transistor, and to control the turn-off of the GaN JFET by using the turn-off of the silicon MOSTET to achieve an enhanced working mode, that is, the device will only be turned on when the positive bias is applied, and the device will be in the off state when the gate is negatively biased and zero biased, thereby reducing the complexity of the circuit and improving the stability and safety.

[0005] However, the total resistance of the enhancement mode device formed by connecting two transistors in series will also be large, which will increase the power consumption of the enhancement mode device and cause greater heat accumulation in the circuit, thereby significantly reducing the electrical performance of the power device and shortening the service life of the electronic device. Summary of the invention

[0006] Therefore, the technical problem to be solved by the present invention is to overcome the defects of poor electrical performance and short service life of enhancement mode devices in the prior art, thereby providing a common-source and common-gate normally-off gallium nitride power device and a preparation method thereof.

[0007] A common-source and common-gate normally-off gallium nitride power device comprises an interconnected diamond MOSFET and a depletion-mode GaN JFET; wherein the depletion-mode GaN JFET comprises a first drain electrode, a first substrate and an n-GaN layer which are sequentially stacked, a plurality of p-GaN layers are arranged at intervals on a side of the n-GaN layer opposite to the first substrate, the plurality of p-GaN layers are spaced apart along the surface of the n-GaN layer, a first gate is arranged on the p-GaN layer in a one-to-one correspondence, and a first source is connected to the n-GaN layer; the diamond MOSFET is metal-interconnected with the n-GaN layer, a second drain electrode, a second gate and a second source are arranged on the diamond MOSFET, a plurality of the first gates are connected in parallel and connected in series with the second source, and the first source is connected to the second drain electrode.

[0008] In one of the embodiments, a first separation groove for dividing the n-GaN layer into a first gallium nitride portion and a second gallium nitride portion is provided on a side of the n-GaN layer opposite to the first substrate, a first metal layer is provided on a side of the first gallium nitride portion opposite to the first substrate, the diamond MOSFET includes a second metal layer, the first metal layer is bonded to the second metal layer, and the plurality of p-GaN layers are provided on the second gallium nitride portion.

[0009] In one of the embodiments, a plurality of embedded grooves are spaced apart on the second gallium nitride portion, the p-GaN layer is embedded in the embedded grooves, the first gate is arranged on a side of the p-GaN layer away from a bottom of the embedded groove, and the first source is arranged on a side of the n-GaN layer opposite to the first substrate and is located between two adjacent first gates.

[0010] In one embodiment, the diamond MOSFET also includes a second substrate, an n-diamond layer and a p-diamond layer stacked in sequence on the second metal layer; a second separation groove for separating the p-diamond layer into a first diamond part and a second diamond part is provided on the side of the p-diamond layer opposite to the n-diamond layer, the second source is provided on the first diamond part, the second drain electrode is provided on the second diamond part, a gate oxide layer is further provided on the second separation groove, two ends of the gate oxide layer extend along the bottom wall of the second separation groove to connect with the second drain electrode and the second source, and the second gate is stacked on the gate oxide layer.

[0011] In one embodiment, the first metal layer includes a titanium layer and a copper layer stacked in sequence, the titanium layer has a thickness of 5 nm, the copper layer has a thickness of 25 nm, the titanium layer is located between the copper layer and the n-GaN layer, and the second metal layer is a copper layer with a thickness of 25 nm.

[0012] In one embodiment, the thickness of the first substrate is 300-500μm, and the first substrate material is diamond; the thickness of the n-GaN layer is 2μm-20μm; the thickness of the p-GaN layer is 100nm-1000nm; the first drain electrode is selected from one or more layers of a 25nm thick Ti layer, a 75nm thick Au layer, a 75nm thick Al layer, and a 25nm thick Ni layer; the first source electrode is selected from one or more layers of a 25nm thick Ti layer and a 100nm thick Al layer; the first gate is selected from one or more layers of a 20nm thick Ni layer and a 100nm thick Au layer.

[0013] In one embodiment, the thickness of the second substrate is 300-400μm, and the material of the second substrate is selected from one or more of silicon, silicon carbide, and diamond; the thickness of the n-diamond layer is 1μm-10μm; the thickness of the p-diamond layer is 200nm-1μm; the thickness of the gate oxide layer is 50-70nm, and the material of the gate oxide layer is aluminum oxide; the second source and the second drain are respectively selected from one or more layers of a 20nm thick Ti layer and a 50nm thick Al layer; the second gate is selected from one or more layers of a 30nm thick Ti layer, a 30nm thick Pt layer, and a 100nm thick Au layer.

[0014] A method for preparing a commingled-source and commingled-gate normally-off gallium nitride power device as described in any one of the above schemes comprises the following steps:

[0015] A depletion-mode GaN JFET and a diamond MOSFET are provided. The depletion-mode GaN JFET is provided with a first metal layer, a first drain electrode, a plurality of first gate electrodes and a first source electrode, and the diamond MOSFET is provided with a second metal layer, a second drain electrode, a second gate electrode and a second source electrode. The first metal layer and the second metal layer are subjected to surface activation treatment by a neutral atom beam in the same vacuum chamber, and then vertical alignment bonding is performed. After a plurality of the first gate electrodes are connected in parallel, the second source electrode is connected in series, and the first source electrode is connected to the second drain electrode.

[0016] In one embodiment, the depletion-mode GaN JFET is prepared according to the following steps:

[0017] Providing a first substrate; growing an n-GaN layer on the first substrate; doping silicon in the n-GaN layer at a doping concentration of 1×10 16 cm -3 -8x10 17 cm -3 ; forming a first separation groove on the side of the n-GaN layer opposite to the first substrate, dividing the n-GaN layer into a first gallium nitride portion and a second gallium nitride portion; growing a first metal layer on the side of the first gallium nitride portion opposite to the first substrate; forming a first source electrode and an embedded groove on the side of the second gallium nitride portion opposite to the first substrate; growing a p-GaN layer in the embedded groove; doping magnesium in the p-GaN layer at a doping concentration of about 1×10 18 cm -3 ; forming a first gate on a side of the p-GaN layer opposite to the n-GaN layer; and forming a first drain on a side of the first substrate opposite to the n-GaN layer.

[0018] In one embodiment, the diamond MOSFET is prepared according to the following steps: providing a second substrate; growing n-type diamond on the second substrate to form an n-diamond layer; doping phosphorus in the n-diamond layer at a doping concentration of 1×10 16 cm -3 ; growing p-type diamond on the side of the n-diamond layer opposite to the second substrate to form a p-diamond layer; doping boron in the p-diamond layer at a doping concentration of 1×10 20 cm -3; forming a second separation groove on the side of the p-diamond layer opposite to the n-diamond layer to separate the p-diamond layer into a first diamond part and a second diamond part; forming a second source electrode on the side of the first diamond part opposite to the n-diamond layer; forming a second drain electrode on the side of the second diamond part opposite to the n-diamond layer; growing a gate oxide layer in the second separation groove, with both ends of the gate oxide layer extending along the bottom wall of the second separation groove to connect with the second drain electrode and the second source electrode respectively; forming a second gate on the gate oxide layer; forming a second metal layer on the side of the second substrate opposite to the n-diamond layer.

[0019] The technical solution of the present invention has the following advantages:

[0020] 1. The compositive-compositive-gate normally-off gallium nitride power device provided by the present invention realizes the turn-off of the depletion-type gallium nitride JFET controlled by a low-loss diamond MOSFET by using a compositive-compositive-gate structure, which not only gives full play to the advantages of high thermal conductivity of diamond and high electron mobility of gallium nitride, but also optimizes the device performance through the design of the compositive-compositive-gate structure, effectively enhances the heat dissipation performance of the device while maintaining the advantages of gallium nitride materials, and improves the electrical performance and service life of the device.

[0021] 3. The preparation method of the common-source and common-gate normally-off gallium nitride power device provided by the present invention can effectively enhance the bonding stability of the two devices and reduce the alignment error caused by uneven thickness by using a neutral atomic beam to perform surface activation treatment on the diamond MOSFET and the depletion-mode gallium nitride JFET before bonding. It can also effectively realize multi-layer vertical stacking of diamond MOSFET and depletion-mode gallium nitride JFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 is a schematic structural diagram of a common-source and common-gate normally-off gallium nitride power device in Embodiment 1 of the present invention;

[0024] Figure 2 This is a flow chart for preparing a common-source and common-gate normally-off gallium nitride power device in Example 1 of the present invention;

[0025] Reference numerals:

[0026] 1. Depletion-mode GaN JFET; 11. First drain electrode; 12. First substrate; 13. n-GaN layer; 131. First gallium nitride portion; 132. Second gallium nitride portion; 14. p-GaN layer; 15. First gate; 16. First source; 17. First separation groove; 18. First metal layer; 2. Diamond MOSFET 2; 21. Second drain electrode; 22. Second gate; 23. Second source; 24. Second metal layer; 25. Second substrate; 26. n-diamond layer; 27. p-diamond layer; 28. Second separation groove; 29. ​​Gate oxide layer. DETAILED DESCRIPTION

[0027] The following examples are provided for a better understanding of the present invention, but are not intended to limit the best mode of implementation, nor to limit the content and protection scope of the present invention. Any product identical or similar to the present invention obtained by anyone under the inspiration of the present invention or by combining the features of the present invention with other prior arts shall fall within the protection scope of the present invention.

[0028] If no specific experimental steps or conditions are specified in the examples, the conventional experimental steps or conditions described in the literature in the field can be used. If no manufacturer is specified for the reagents or instruments used, they are all conventional reagent products that can be obtained commercially.

[0029] The present invention relates to a common-source and common-gate normally-off gallium nitride power device, which can be used in control units in the fields of power adapters, vehicle chargers, data centers, etc.

[0030] Specifically, Figure 1 As shown, in one embodiment, a cascode normally-off gallium nitride power device includes a depletion-mode GaN JFET 1 and a diamond MOSFET 2 interconnected.

[0031] Among them, the depletion-mode GaN JFET1 includes a first drain electrode 11, a first substrate 12 and an n-GaN layer 13 which are stacked in sequence. A plurality of p-GaN layers 14 are arranged at intervals on the side of the n-GaN layer 13 opposite to the first substrate 12. The plurality of p-GaN layers 14 are distributed at intervals along the surface of the n-GaN layer 13. First gates 15 are arranged one by one on the p-GaN layers 14. The n-GaN layer 14 is also connected to a first source 16. The diamond MOSFET2 is metal-interconnected with the n-GaN layer 13. A second drain electrode 21, a second gate 22 and a second source 23 are arranged on the diamond MOSFET2. The plurality of first gates 15 are connected in parallel and connected in series with the second source 23. The first source 16 is connected to the second drain electrode 21.

[0032] The common source and common gate normally-off gallium nitride power device of this embodiment uses a common source and common gate structure to achieve the turn-off of the depletion-type gallium nitride JFET controlled by a low-loss diamond MOSFET, which not only gives full play to the advantages of diamond's high thermal conductivity and gallium nitride's high electron mobility, but also optimizes the device performance through the design of the common source and common gate structure. While maintaining the advantages of gallium nitride materials, the heat dissipation performance of the device is effectively enhanced, and the electrical performance and service life of the device are improved. At the same time, through monolithic heterogeneous integration and vertical interconnection structure, more functions can be integrated in a smaller space, improving the integration of the device, which is conducive to reducing the device area and optimizing the overall space utilization.

[0033] It should be noted that, in this embodiment, there are two p-GaN layers 14. In other embodiments, the number of p-GaN layers 14 can also be adjusted as needed.

[0034] In one embodiment, a first separation groove 17 for dividing the n-GaN layer 13 into a first gallium nitride portion 131 and a second gallium nitride portion 132 is provided on a side of the n-GaN layer 13 opposite to the first substrate 12, a first metal layer 18 is provided on a side of the first gallium nitride portion 131 opposite to the first substrate 12, the diamond MOSFET includes a second metal layer 24, the first metal layer 18 is bonded to the second metal layer 24, and the p-GaN layer 14 is provided on the second gallium nitride portion 132.

[0035] In one embodiment, a plurality of embedded grooves are spaced apart on the second gallium nitride portion 132 , the p-GaN layer 14 is embedded in the embedded grooves, the first gate 15 is arranged on a side of the p-GaN layer 14 away from the bottom of the embedded groove, and the first source 16 is arranged on a side of the n-GaN layer 13 opposite to the first substrate 12 and is located between two adjacent first gates 15 .

[0036] In one embodiment, the diamond MOSFET 2 further includes a second substrate 25, an n-diamond layer 26 and a p-diamond layer 27 which are sequentially stacked on the second metal layer 24; a second separation groove 28 for separating the p-diamond layer 27 into a first diamond portion and a second diamond portion is provided on a side of the p-diamond layer 27 opposite to the n-diamond layer 26, and the second source 23 is provided in the first diamond portion ( Figure 1 The second drain electrode 21 is arranged on the second diamond portion ( Figure 1 As shown in the right part, a gate oxide layer 29 is also provided on the second separation groove 28, and both ends of the gate oxide layer 29 extend along the bottom wall of the second separation groove 28 to connect with the second drain electrode 21 and the second source electrode 23, and the second gate 22 is stacked on the gate oxide layer 29.

[0037] By separating the p-diamond layer 27 into a first diamond portion and a second diamond portion, and providing a gate oxide layer 29 in the second separation groove 28, and connecting the gate oxide layer 29 to the second drain electrode 21 and the second source electrode 23, it can help reduce the capacitance of the device and improve the switching speed of the device.

[0038] In one embodiment, the first metal layer 18 includes a titanium layer and a copper layer stacked in sequence, the titanium layer is 5 nm thick, the copper layer is 25 nm thick, the titanium layer is located between the copper layer and the n-GaN layer, and the second metal layer 24 is a copper layer with a thickness of 25 nm.

[0039] In one embodiment, the first substrate 12 has a thickness of 200 μm and is made of diamond. The n-GaN layer 13 has a thickness of 5 μm and is doped with Si. The doping concentration of Si is 5×10 17 cm -3 The p-GaN layer 14 has a thickness of 500 nm and is doped with Mg, and the doping concentration of Mg is 1x10 18 cm -3 ; The first drain electrode 11 is a stack of a 25nm thick Ti layer, a 75nm thick Au layer, a 75nm thick Al layer, and a 25nm thick Ni layer; the first source electrode 16 is a stack of a 25nm thick Ti layer and a 100nm thick Al layer; the first gate 15 is a stack of a 20nm thick Ni layer and a 100nm thick Au layer.

[0040] In other embodiments, the thickness of the first substrate 12 may be 300-500 μm; the thickness of the n-GaN layer 13 may be 2 μm-20 μm and may not be ion doped, or the concentration of silicon doping may be 1×10 16 cm -3 -8x10 17 cm -3 ; The thickness of the p-GaN layer 14 can be 100nm-1000nm and ion doping may not be performed; the first drain electrode 11 can be selected from one or more layers of a 25nm thick Ti layer, a 75nm thick Au layer, a 75nm thick Al layer, and a 25nm thick Ni layer; the first source electrode 16 can be selected from one or more layers of a 25nm thick Ti layer and a 100nm thick Al layer; the first gate 15 can be selected from one or more layers of a 20nm thick Ni layer and a 100nm thick Au layer.

[0041] In one embodiment, the second substrate 25 has a thickness of 300 μm and is made of diamond; the n-diamond layer 26 has a thickness of 1 μm and is doped with phosphorus, and the doping concentration of phosphorus is 1×10 16 cm -3The p-diamond layer 27 has a thickness of 200 nm and is doped with boron at a doping concentration of 1×10 20 cm -3 ; The thickness of the gate oxide layer 29 is 60nm, and the material of the gate oxide layer 29 is aluminum oxide; the second source 23 and the second drain 21 are both stacked layers consisting of a 20nm thick Ti layer and a 50nm thick Al layer; the second gate 22 is a stacked layer consisting of a 30nm thick Ti layer, a 30nm thick Pt layer and a 100nm thick Au layer.

[0042] In other embodiments, the thickness of the second substrate 25 can be 300-400μm, and the second substrate material can be selected from one or more of silicon, silicon carbide, and diamond; the thickness of the n-diamond layer 26 can be 1μm-10μm and is not doped with ions; the thickness of the p-diamond layer 27 is 200nm-1μm and is not doped with ions; the thickness of the gate oxide layer 29 can be 50-70nm; the second source 23 and the second drain 21 can be selected from one or more layers of a 20nm thick Ti layer and a 50nm thick Al layer respectively; the second gate 22 can be selected from one or more layers of a 30nm thick Ti layer, a 30nm thick Pt layer, and a 100nm thick Au layer.

[0043] The present embodiment also relates to a preparation method, which is used to prepare the common-source and common-gate normally-off gallium nitride power device mentioned above.

[0044] Specifically, Figure 2 As shown, the preparation method comprises the following steps:

[0045] S1. Provide a depletion-mode GaN JFET and a diamond MOSFET, wherein the depletion-mode GaN JFET is provided with a first metal layer, a first drain electrode, a plurality of first gate electrodes and a first source electrode, and the diamond MOSFET is provided with a second metal layer, a second drain electrode, a second gate electrode and a second source electrode;

[0046] S2, performing surface activation treatment on the first metal layer and the second metal layer using a neutral atom beam in the same vacuum chamber, and then performing alignment bonding in a vertical direction;

[0047] A plurality of first gate electrodes are connected in parallel and then the second source electrodes are connected in series, and the first source electrodes are connected to the second drain electrode.

[0048] The method for preparing a common-source and common-gate normally-off gallium nitride power device provided in this embodiment uses a neutral atomic beam to perform surface activation treatment on a diamond MOSFET and a depletion-mode gallium nitride JFET before bonding. The surface activation treatment can form a reactive ion layer on the surface of the first metal layer and the second metal layer, thereby increasing the atomic activity and wettability of the surfaces of the first metal layer and the second metal layer. These ion layers can serve as a bonding "bridge" to connect the two materials, thereby achieving stable bonding between the two materials, and also helping to reduce alignment errors caused by uneven thickness, thereby effectively achieving multi-layer vertical stacking of diamond MOSFET and depletion-mode gallium nitride JFET.

[0049] In one embodiment, the surface activation treatment specifically includes the following steps:

[0050] S1. The surfaces of the first metal layer and the second metal layer are roughly polished by chemical-mechanical polishing (CMP), and then pre-treated by ultrasonic cleaning with isopropyl alcohol for 300 seconds and ultrasonic cleaning with deionized water for 240 seconds.

[0051] S2. Place the sample in an ultra-high vacuum chamber at 1.0E -7 ˉ6.0E -7 Under a vacuum pressure of 1.5 Pa, Ar plasma is used to remove pollutants and other impurities attached to the surface of the device, and then the first metal layer and the second metal layer are irradiated with Ar plasma. The irradiation voltage and current are 1 KV and 15 mA respectively, so that a uniform reactive ion layer is formed on the surface of the first metal layer and the second metal layer.

[0052] In one embodiment, the vertical bonding operation specifically includes the following steps: applying a pressure of 1000 MPa to the ultra-high vacuum chamber where the first metal layer and the second metal layer are located, and bonding at 250°C for a bonding time of 30 minutes to 3 hours. After the bonding is completed, the device is annealed at a temperature of 300°C for 2 hours.

[0053] The bonding conditions of 250°C and 1000Mpa can further improve the bonding strength and stability between the first metal layer and the second metal layer. During the annealing process, the first metal layer and the second metal layer will diffuse into each other to form a close permanent bond, thereby further optimizing the bonding quality and significantly improving the stability and high temperature resistance of the bonding structure.

[0054] In one embodiment, a depletion-mode GaN JFET is prepared according to the following steps:

[0055] S1, providing a first substrate; S2, growing an n-GaN layer on the first substrate; S3, doping silicon in the n-GaN layer with a doping concentration of 1x10 16 cm -3 -8x10 17 cm -3 ; S4, forming a first separation groove on the side of the n-GaN layer opposite to the first substrate, dividing the n-GaN layer into a first gallium nitride part and a second gallium nitride part; S5, growing a first metal layer on the side of the first gallium nitride part opposite to the first substrate; S6, forming a first source electrode and an embedded groove on the side of the second gallium nitride part opposite to the first substrate; S7, growing a p-GaN layer in the embedded groove; S8, doping magnesium in the p-GaN layer, with a doping concentration of about 1x10 18 cm -3 ; S9, forming a first gate on a side of the p-GaN layer opposite to the n-GaN layer; S10, forming a first drain on a side of the first substrate opposite to the n-GaN layer.

[0056] In one embodiment, the n-GaN layer is formed by hydride vapor phase epitaxy (HVPE). In other embodiments, the n-GaN layer may also be grown by molecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD).

[0057] In one embodiment, the first separation groove is formed by photolithography and ICP etching (O2 / BCl3); the p-GaN layer is grown by metal organic chemical vapor deposition (MOCVD) method, but it can be understood that the formation method of the first separation groove and the p-GaN layer is not limited and can be selected from any commonly used and feasible technical method in the field.

[0058] In one embodiment, the first drain electrode is obtained by evaporating a corresponding metal material by thermal evaporation and then annealing by rapid thermal annealing (RTA) at 800° C. for 30 seconds in a N2 atmosphere. In other embodiments, the first drain electrode can also be obtained by evaporating a metal film by magnetron sputtering or electron beam evaporation and then annealing.

[0059] In one embodiment, the first source is obtained by evaporating the corresponding metal material by thermal evaporation without an annealing process. In other embodiments, the first source can also be obtained by evaporating the corresponding metal material by magnetron sputtering or electron beam evaporation without an annealing process.

[0060] In one implementation, the first gate is obtained by magnetron sputtering a corresponding metal material and then annealing in air at 500° C. for 5 minutes. In other embodiments, the first gate can also be obtained by electron beam evaporation deposition.

[0061] In one embodiment, the first metal layer is obtained by thermal evaporation of the corresponding metal material. In other embodiments, the first metal layer can also be obtained by magnetron sputtering or electron beam evaporation.

[0062] In one embodiment, a diamond MOSFET is prepared according to the following steps:

[0063] S1, providing a second substrate; S2, growing n-type diamond on the second substrate to form an n-diamond layer; S3, doping phosphorus in the n-diamond layer with a doping concentration of 1x10 16 cm -3 ; S4, growing p-type diamond on the side of the n-diamond layer opposite to the second substrate to form a p-diamond layer; S5, doping boron in the p-diamond layer to a doping concentration of 1x10 20 cm -3 ; S6, forming a second separation groove on the side of the p-diamond layer opposite to the n-diamond layer, separating the p-diamond layer into a first diamond part and a second diamond part; S7, forming a second source electrode on the side of the first diamond part opposite to the n-diamond layer; S8, forming a second drain electrode on the side of the second diamond part opposite to the n-diamond layer; S9, growing a gate oxide layer in the second separation groove, with both ends of the gate oxide layer extending along the bottom wall of the second separation groove to connect with the second drain electrode and the second source electrode respectively; S10, forming a second gate on the gate oxide layer; S11, forming a second metal layer on the side of the second substrate opposite to the n-diamond layer.

[0064] In one embodiment, the n-diamond layer is obtained by growing n-type diamond using microwave plasma chemical vapor deposition (MPCVD). In other embodiments, the n-diamond layer can also be obtained by growing n-type diamond using direct current plasma chemical vapor deposition (DC-CVD).

[0065] In one embodiment, the second separation groove is formed by dry etching using photolithography and reactive ion etching (RIE) technology, with O2 and SF6 as the reaction gas. In other embodiments, the second separation groove is not limited in the formation method.

[0066] In one embodiment, the gate oxide layer is obtained by plasma enhanced chemical vapor deposition (PECVD). In other embodiments, the gate oxide layer can also be obtained by atomic layer deposition (ALD).

[0067] In one embodiment, the second gate, the second drain, the second source and the second metal layer are formed by the same method as the first gate, the first drain, the first source and the first metal layer, respectively. In other embodiments, the second gate, the second drain, the second source and the second metal layer are formed without limitation.

[0068] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A cascode normally-off gallium nitride power device, characterized in that: It comprises an interconnected diamond MOSFET and a depletion-mode GaN JFET; wherein the depletion-mode GaN JFET comprises a first drain electrode, a first substrate and an n-GaN layer which are sequentially stacked, a plurality of p-GaN layers are arranged at intervals on a side of the n-GaN layer opposite to the first substrate, the plurality of p-GaN layers are distributed at intervals along the surface of the n-GaN layer, a first gate is arranged on the p-GaN layer in a one-to-one correspondence, and a first source is also connected to the n-GaN layer; The diamond MOSFET is metal-interconnected with the n-GaN layer. A second drain electrode, a second gate electrode and a second source electrode are arranged on the diamond MOSFET. A plurality of the first gate electrodes are connected in parallel and connected in series with the second source electrode. The first source electrode is connected with the second drain electrode.

2. The cascode normally-off gallium nitride power device according to claim 1, characterized in that: A first separation groove for dividing the n-GaN layer into a first gallium nitride portion and a second gallium nitride portion is provided on a side of the n-GaN layer opposite to the first substrate, a first metal layer is provided on a side of the first gallium nitride portion opposite to the first substrate, the diamond MOSFET includes a second metal layer, the first metal layer is bonded to the second metal layer, and the plurality of p-GaN layers are provided on the second gallium nitride portion.

3. The cascode normally-off gallium nitride power device according to claim 2, characterized in that: A plurality of embedded grooves are arranged at intervals on the second gallium nitride portion, the p-GaN layer is embedded in the embedded grooves, the first gate is arranged on a side of the p-GaN layer away from a bottom of the embedded groove, and the first source is arranged on a side of the n-GaN layer opposite to the first substrate and is located between two adjacent first gates.

4. The cascode normally-off gallium nitride power device according to claim 2, characterized in that: The diamond MOSFET also includes a second substrate, an n-diamond layer and a p-diamond layer stacked in sequence on the second metal layer; a second separation groove for separating the p-diamond layer into a first diamond part and a second diamond part is provided on the side of the p-diamond layer opposite to the n-diamond layer, the second source is provided on the first diamond part, the second drain electrode is provided on the second diamond part, a gate oxide layer is also provided on the second separation groove, two ends of the gate oxide layer respectively extend along the bottom wall of the second separation groove to connect with the second drain electrode and the second source, and the second gate is stacked on the gate oxide layer.

5. The cascode normally-off gallium nitride power device according to claim 2, characterized in that: The first metal layer includes a titanium layer and a copper layer stacked in sequence, the titanium layer has a thickness of 5 nm, the copper layer has a thickness of 25 nm, the titanium layer is located between the copper layer and the n-GaN layer, and the second metal layer is a copper layer with a thickness of 25 nm.

6. The cascode normally-off gallium nitride power device according to claim 1, characterized in that: The thickness of the first substrate is 300-500μm, and the first substrate material is diamond; the thickness of the n-GaN layer is 2μm-20μm; the thickness of the p-GaN layer is 100nm-1000nm; the first drain electrode is selected from one or more layers of a 25nm thick Ti layer, a 75nm thick Au layer, a 75nm thick Al layer, and a 25nm thick Ni layer; the first source electrode is selected from one or more layers of a 25nm thick Ti layer and a 100nm thick Al layer; the first gate is selected from one or more layers of a 20nm thick Ni layer and a 100nm thick Au layer.

7. The cascode normally-off gallium nitride power device according to claim 4, characterized in that: The thickness of the second substrate is 300-400μm, and the material of the second substrate is selected from one or more of silicon, silicon carbide, and diamond; the thickness of the n-diamond layer is 1μm-10μm; the thickness of the p-diamond layer is 200nm-1μm; the thickness of the gate oxide layer is 50-70nm, and the material of the gate oxide layer is aluminum oxide; the second source and the second drain are respectively selected from one or more layers of a 20nm thick Ti layer and a 50nm thick Al layer; the second gate is selected from one or more layers of a 30nm thick Ti layer, a 30nm thick Pt layer, and a 100nm thick Au layer.

8. A method for preparing a cascode normally-off gallium nitride power device according to any one of claims 1 to 7, characterized in that: The following steps are involved: A depletion-mode GaN JFET and a diamond MOSFET are provided, wherein the depletion-mode GaN JFET is provided with a first metal layer, a first drain electrode, a plurality of first gate electrodes and a first source electrode, and the diamond MOSFET is provided with a second metal layer, a second drain electrode, a second gate electrode and a second source electrode; Performing surface activation treatment on the first metal layer and the second metal layer by using a neutral atom beam in the same vacuum chamber, and then performing alignment bonding in a vertical direction; A number of the first gates are connected in parallel and then the second source is connected in series, and the first source is connected to the second drain electrode.

9. The preparation method according to claim 8, characterized in that: The depletion-mode GaN JFET is prepared according to the following steps: providing a first substrate; growing an n-GaN layer on the first substrate; The n-GaN layer is doped with silicon at a doping concentration of 1x10 16 cm -3 -8x10 17 cm -3 ; forming a first separation groove on a side of the n-GaN layer opposite to the first substrate, dividing the n-GaN layer into a first gallium nitride portion and a second gallium nitride portion; growing a first metal layer on a side of the first gallium nitride portion opposite the first substrate; forming a first source electrode and a embedding groove on a side of the second gallium nitride portion opposite to the first substrate; growing a p-GaN layer in the embedded groove; Magnesium is doped into the p-GaN layer at a doping concentration of about 1x10 18 cm -3 ; forming a first gate on a side of the p-GaN layer opposite to the n-GaN layer; A first drain is formed on a side of the first substrate opposite to the n-GaN layer.

10. The preparation method according to claim 8, characterized in that: The diamond MOSFET is prepared according to the following steps: providing a second substrate; growing n-type diamond on the second substrate to form an n-diamond layer; Phosphorus is doped into the n-diamond layer at a doping concentration of 1x10 16 cm -3 ; growing p-type diamond on a side of the n-diamond layer opposite to the second substrate to form a p-diamond layer; Boron is doped into the p-diamond layer at a doping concentration of 1x10 20 cm -3 ; forming a second separation groove on a side of the p-diamond layer opposite to the n-diamond layer to separate the p-diamond layer into a first diamond portion and a second diamond portion; forming a second source electrode on a side of the first diamond portion opposite to the n-diamond layer; forming a second drain electrode on a side of the second diamond portion opposite to the n-diamond layer; Growing a gate oxide layer in the second separation groove, wherein two ends of the gate oxide layer extend along the bottom wall of the second separation groove to connect with the second drain electrode and the second source electrode respectively; forming a second gate on the gate oxide layer; A second metal layer is formed on a side of the second substrate opposite the n-diamond layer.

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