Array substrate and preparation method thereof, display panel and display device

Abstract

The invention discloses an array substrate and a preparation method thereof, a display panel and a display device, and relates to the technical field of display. The array substrate comprises a substrate body, and a first electrode layer, a first source and drain electrode layer and a second source and drain electrode layer which are stacked in sequence. The first source and drain electrode layer comprises a first signal line and a first pattern connected with a pixel electrode in the first electrode layer, and the second source and drain electrode layer comprises a second pattern connected with the first signal line and a third pattern connected with the first pattern. The first interval between the first signal line and the first pattern is larger than the second interval between the second pattern and the third pattern, so that the second pattern can be arranged on the edge of the first signal line in a climbing manner, and the third pattern can be arranged on the edge of the first pattern in a climbing manner. Due to the fact that the second pattern and the third pattern are good in climbing capacity, even if the offset of the climbing position is large, line breakage of the second pattern and the third pattern can be avoided, and the yield of products is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel, and a display device. Background Art

[0002] Liquid crystal display (LCD) panels are widely used in the display field due to their low power consumption.

[0003] In the related art, the array substrate in the liquid crystal display panel includes a plurality of driving circuits, pixel electrodes and common electrodes. The driving circuits are connected to the pixel electrodes to provide pixel signals to the pixel electrodes, so that the liquid crystal molecules of the liquid crystal layer in the liquid crystal display panel can be deflected under the common drive of the pixel electrodes and the common electrodes.

[0004] However, in the related art, some film layers in the driving circuit of the liquid crystal display panel may have a large step difference, which may easily cause other film layers subsequently formed at the step difference to short-circuit, resulting in failure of the driving circuit and low yield. Summary of the invention

[0005] The present application provides an array substrate and a manufacturing method thereof, a display panel, and a display device, which can solve the problem of low yield of driving circuits due to step difference in related technologies. The technical solution is as follows:

[0006] In one aspect, an array substrate is provided, wherein the array substrate comprises:

[0007] substrate substrate;

[0008] A first electrode layer, the first electrode layer is located on one side of the base substrate, and the first electrode layer includes a plurality of pixel electrodes arranged in an array;

[0009] a first source-drain electrode layer, the first source-drain electrode layer being located on a side of the first electrode layer away from the base substrate, the first source-drain electrode layer comprising a plurality of first signal lines arranged along a first direction and extending along a second direction, and a plurality of first patterns, each of the first patterns being connected to one of the pixel electrodes;

[0010] and a second source-drain electrode layer, the second source-drain electrode layer being located at a side of the first source-drain electrode layer away from the base substrate, the second source-drain electrode layer comprising a plurality of second patterns and a plurality of third patterns corresponding to the plurality of second patterns, each of the second patterns being connected to one of the first signal lines, and each of the third patterns being connected to one of the first patterns;

[0011] There is a first interval between the first signal line and the corresponding first pattern, there is a second interval between the second pattern and the corresponding third pattern, and the first interval is greater than the second interval.

[0012] Optionally, the array substrate includes a plurality of driving circuits, the plurality of driving circuits constitute a plurality of groups of driving circuits arranged along the first direction, each group of driving circuits includes a plurality of driving circuits arranged along the second direction, each of the first signal lines is connected to a group of driving circuits, and each of the driving circuits in each group of driving circuits is connected to a pixel electrode via one of the first patterns;

[0013] The first electrode layer further includes a plurality of second signal lines corresponding to the plurality of first signal lines, and the plurality of second signal lines are arranged along the first direction and extend along the second direction;

[0014] The first signal line includes a first edge and a second edge extending along the second direction and arranged oppositely, the first edge being closer to a target first pattern than the second edge, the target first pattern being a first pattern connected to any one of a group of drive circuits connected to the first signal line; the second signal line includes a third edge and a fourth edge extending along the second direction and arranged oppositely, the third edge being closer to a target pixel electrode than the fourth edge, the target pixel electrode being a pixel electrode connected to any one of a group of drive circuits connected to the first signal line corresponding to the second signal line;

[0015] The orthographic projection of the first edge on the base substrate and the orthographic projection of the third edge on the base substrate do not overlap, and the orthographic projection of the second edge on the base substrate and the orthographic projection of the fourth edge on the base substrate do not overlap.

[0016] Optionally, the orthographic projection of the first edge on the substrate and the orthographic projection of the second edge on the substrate are both located between the orthographic projection of the third edge on the substrate and the orthographic projection of the fourth edge on the substrate; or,

[0017] The orthographic projection of the first edge on the substrate substrate is closer to the orthographic projection of the second pattern on the substrate substrate than the orthographic projection of the third edge on the substrate substrate, and the orthographic projection of the second edge on the substrate substrate is located between the orthographic projection of the third edge on the substrate substrate and the orthographic projection of the fourth edge on the substrate substrate.

[0018] Optionally, the array substrate includes a plurality of driving circuits, the plurality of driving circuits constitute a plurality of groups of driving circuits arranged along the first direction, each group of driving circuits includes a plurality of driving circuits arranged along the second direction, each of the first signal lines is connected to a group of driving circuits, and each of the driving circuits in each group of driving circuits is connected to a pixel electrode via one of the first patterns;

[0019] The pixel electrode comprises: a connecting portion and a main region; the array substrate further comprises a second electrode layer, the second electrode layer comprises a common electrode; the connecting portion is connected to the first pattern, and the orthographic projection of the main region on the base substrate and the orthographic projection of the common electrode on the base substrate at least partially overlap;

[0020] The first pattern includes a fifth edge extending along the second direction, and a sixth edge arranged opposite to the fifth edge, the fifth edge is closer to a target first signal line than the sixth edge, and the target first signal line and the first pattern are connected to the same driving circuit; the connecting portion includes a seventh edge extending along the second direction, and an eighth edge arranged opposite to the seventh edge, the seventh edge is closer to a target second signal line than the eighth edge, and a first signal line corresponding to the target second signal line and the connecting portion are connected to the same driving circuit;

[0021] The orthographic projection of the fifth edge on the base substrate does not overlap with the orthographic projection of the seventh edge on the base substrate, and the orthographic projection of the sixth edge on the base substrate does not overlap with the orthographic projection of the eighth edge on the base substrate.

[0022] Optionally, the orthographic projection of the fifth edge on the substrate and the orthographic projection of the sixth edge on the substrate are both located between the orthographic projection of the seventh edge on the substrate and the orthographic projection of the eighth edge on the substrate; or,

[0023] The orthographic projection of the fifth edge on the substrate substrate is closer to the orthographic projection of the first signal line on the substrate substrate than the orthographic projection of the seventh edge on the substrate substrate, and the orthographic projection of the sixth edge on the substrate substrate is between the orthographic projection of the seventh edge on the substrate substrate and the orthographic projection of the eighth edge on the substrate substrate.

[0024] Optionally, the array substrate further comprises: a semiconductor layer located on a side of the second source and drain electrode layer away from the base substrate;

[0025] A length of an orthographic projection of the target portion of the semiconductor layer on the base substrate along the first direction is smaller than the first interval and larger than the second interval.

[0026] Optionally, the array substrate further comprises: a first insulating layer and a gate layer which are located on a side of the semiconductor layer away from the base substrate and are stacked;

[0027] The orthographic projection of the first insulating layer on the base substrate and the orthographic projection of the gate layer on the base substrate both overlap with the orthographic projection of the semiconductor layer on the base substrate.

[0028] Optionally, the array substrate further includes: a light shielding layer and a second insulating layer which are stacked and located between the first electrode layer and the base substrate;

[0029] The light shielding layer includes a plurality of light shielding portions, and a plurality of third signal lines arranged along the second direction and extending along the first direction;

[0030] The orthographic projection of the light shielding portion on the base substrate covers the orthographic projection of the channel portion on the base substrate, and the channel portion is a portion where the semiconductor layer overlaps with the gate layer and does not overlap with the second source and drain layer;

[0031] The third signal line is connected to the gate layer and is used to provide a gate signal to the gate layer.

[0032] Optionally, the array substrate further comprises: a third insulating layer located on a side of the gate layer away from the base substrate; the second electrode layer included in the array substrate is located on a side of the third insulating layer away from the base substrate; the second electrode layer further comprises: a transition portion;

[0033] One end of the transition portion is connected to the third signal line through a first via hole in the third insulating layer and the second insulating layer, and the other end of the transition portion is connected to the gate layer through a second via hole in the third insulating layer.

[0034] Optionally, the thickness of the first source-drain electrode layer is greater than the thickness of the second source-drain electrode layer.

[0035] In another aspect, a method for preparing an array substrate is provided, the method comprising:

[0036] Providing a substrate;

[0037] Forming a first electrode layer, a first source-drain electrode layer and a second source-drain electrode layer in sequence on one side of the base substrate;

[0038] Wherein, the first electrode layer includes a plurality of pixel electrodes arranged in an array; the first source-drain electrode layer is located on a side of the first electrode layer away from the base substrate, the first source-drain electrode layer includes a plurality of first signal lines arranged along a first direction and extending along a second direction, and a plurality of first patterns, each of which is connected to one of the pixel electrodes; the second source-drain electrode layer is located on a side of the first source-drain electrode layer away from the base substrate, the second source-drain electrode layer includes a plurality of second patterns, and a plurality of third patterns corresponding to the plurality of second patterns, each of which is connected to one of the first signal lines, and each of which is connected to one of the first patterns;

[0039] There is a first interval between the first signal line pattern and the corresponding first pattern, there is a second interval between the second pattern and the corresponding third pattern, and the first interval is greater than the second interval.

[0040] Optionally, forming the first electrode layer and the first source and drain layer includes:

[0041] Sequentially forming a first electrode film and a first source-drain film on one side of the base substrate;

[0042] A first optical adhesive layer is formed on a side of the first source-drain thin film away from the base substrate by using a half-tone mask, wherein the optical adhesive layer includes a first portion and a second portion, the thickness of the first portion is less than the thickness of the second portion, the area where the first portion is located is used to form a first electrode layer, and the area where the second portion is located is used to form a first source-drain electrode layer;

[0043] Etching the first electrode film and the first source-drain film based on the optical adhesive layer to obtain a first electrode layer and a second source-drain film;

[0044] Performing an ashing process on the optical adhesive layer to remove the first portion;

[0045] The second source-drain film is etched based on the second portion of the optical adhesive layer to obtain a first source-drain electrode layer.

[0046] Optionally, forming the first electrode layer and the first source and drain layer includes:

[0047] forming a first electrode film on one side of the base substrate;

[0048] Performing patterning on the first electrode film to obtain a first electrode layer;

[0049] forming a first source-drain thin film on a side of the first electrode layer away from the base substrate;

[0050] The first source-drain film is patterned to obtain a first source-drain electrode layer.

[0051] In another aspect, a display panel is provided, the display panel comprising: a color film substrate, a liquid crystal layer, and the array substrate as described in the above aspect;

[0052] The array substrate and the color filter substrate are arranged in a box-like manner, and the liquid crystal layer is located between the array substrate and the color filter substrate.

[0053] In another aspect, a display device is provided, comprising: a power supply component and the display panel as described in the above aspect;

[0054] Wherein, the power supply component is used to supply power to the display panel.

[0055] The beneficial effects of the technical solution provided by this application include at least:

[0056] The present application provides an array substrate and a preparation method thereof, a display panel, and a display device. The array substrate includes a base substrate, and a first electrode layer, a first source-drain layer, and a second source-drain layer stacked in sequence. The first source-drain layer includes a first signal line, and a first pattern connected to a pixel electrode in the first electrode layer, and the second source-drain layer includes a second pattern connected to the first signal line, and a third pattern connected to the first pattern. Since the first interval between the first signal line and the first pattern is greater than the second interval between the second pattern and the third pattern, the second pattern can be set to climb at the edge of the first signal line, and the third pattern can be set to climb at the edge of the first pattern. Since the second pattern and the third pattern have good climbing ability, even if the break difference of the climbing position is large, it will not cause too much impact on the performance of the second pattern and the third pattern, and the second pattern and the third pattern can be prevented from breaking, thereby ensuring the yield of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0058] Figure 1 is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0059] Figure 2 is a partial top view of an array substrate provided in an embodiment of the present application;

[0060] Figure 3is a partial top view of a first source and drain layer provided in an embodiment of the present application;

[0061] Figure 4 is a partial top view of the first electrode layer provided in an embodiment of the present application;

[0062] Figure 5 is a schematic diagram of a staggered arrangement of a first electrode layer and a first source and drain layer provided in an embodiment of the present application;

[0063] Figure 6 is another schematic diagram of the staggered arrangement of the first electrode layer and the first source and drain layer provided in an embodiment of the present application;

[0064] Figure 7 is a partial top view of a light shielding layer provided in an embodiment of the present application;

[0065] Figure 8 is a partial top view of an array substrate provided in an embodiment of the present application;

[0066] Fig. 9 is a partial schematic diagram of a light shielding layer provided in an embodiment of the present application;

[0067] Fig.10 is a partial schematic diagram of the first electrode layer provided in an embodiment of the present application;

[0068] Fig.11 It is a schematic diagram of the partial superposition of the light shielding layer and the first electrode layer provided in an embodiment of the present application;

[0069] Fig.12 is a partial schematic diagram of a first source and drain layer provided in an embodiment of the present application;

[0070] Fig.13 It is a schematic diagram of the partial superposition of the light shielding layer, the first electrode layer and the first source and drain electrode layer provided in an embodiment of the present application;

[0071] Fig.14 is a partial schematic diagram of a second source and drain layer provided in an embodiment of the present application;

[0072] Fig.15 It is a schematic diagram of partial superposition of a light shielding layer, a first electrode layer, a first source-drain electrode layer and a second source-drain electrode layer provided in an embodiment of the present application;

[0073] Fig.16 is a partial schematic diagram of a gate layer provided in an embodiment of the present application;

[0074] Fig.17 It is a schematic diagram of partial superposition of a light shielding layer, a first electrode layer, a first source-drain electrode layer, a second source-drain electrode layer, a semiconductor layer, a first insulating layer and a gate layer provided in an embodiment of the present application;

[0075] Fig.18 is a partial schematic diagram of a third insulating layer provided in an embodiment of the present application;

[0076] Fig.19 It is a schematic diagram of partial superposition of a light shielding layer, a first electrode layer, a first source-drain electrode layer, a second source-drain electrode layer, a semiconductor layer, a first insulating layer, a gate layer and a third insulating layer provided in an embodiment of the present application;

[0077] Fig. 20 is a partial schematic diagram of the second electrode layer provided in an embodiment of the present application;

[0078] Fig.21 It is a schematic diagram of partial superposition of a light shielding layer, a first electrode layer, a first source and drain electrode layer, a second source and drain electrode layer, a semiconductor layer, a first insulating layer, a gate layer, a third insulating layer and a second electrode layer provided in an embodiment of the present application;

[0079] Fig. 22 is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application;

[0080] Fig.23 is a schematic diagram of forming a light shielding layer provided in an embodiment of the present application;

[0081] Fig.24 is a schematic diagram of forming a second insulating film provided in an embodiment of the present application;

[0082] Fig.25 is a schematic diagram of forming a first electrode film and a first source-drain film provided in an embodiment of the present application;

[0083] Fig.26 is a schematic diagram of forming a photoresist layer provided in an embodiment of the present application;

[0084] Fig. 27 is a schematic diagram of forming a photoresist mask provided by an embodiment of the present application;

[0085] Fig.28 is a schematic diagram of etching the first electrode film and the first source and drain film provided in an embodiment of the present application;

[0086] Fig.29 is a schematic diagram of removing the second part of the photoresist mask provided by an embodiment of the present application;

[0087] Fig.30 is a schematic diagram of etching the first source-drain film provided in an embodiment of the present application;

[0088] Fig.31 is a schematic diagram of forming a second source-drain film provided in an embodiment of the present application;

[0089] Fig.32It is a schematic diagram of forming a semiconductor layer, a first insulating layer and a gate layer provided in an embodiment of the present application;

[0090] Fig.33 is a schematic diagram of forming a third insulating layer provided in an embodiment of the present application;

[0091] Fig.34 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0092] Fig.35 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0093] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0094] Figure 1 is a schematic diagram of the structure of an array substrate provided in an embodiment of the present application. Figure 1 The array substrate 10 may include: a base substrate 101 , a first electrode layer 102 , a first source-drain electrode layer 103 and a second source-drain electrode layer 104 .

[0095] The first electrode layer 102 is located on one side of the base substrate 101, and the first electrode layer 102 includes a plurality of pixel electrodes 1021 arranged in an array. The region where each pixel electrode 1021 is located can constitute a light-emitting region. The material of the first electrode layer 102 can be a transparent conductive material, for example, the material of the first electrode layer 102 can be indium tin oxide (ITO).

[0096] The first source-drain electrode layer 103 is located on a side of the first electrode layer 102 away from the substrate 101. The first source-drain electrode layer 103 includes a plurality of first signal lines 1031 arranged along the first direction X and extending along the second direction Y, and a plurality of first patterns 1032. Each first pattern 1032 is connected to a pixel electrode 1021.

[0097] The second source-drain electrode layer 104 is located on a side of the first source-drain electrode layer 103 away from the base substrate 101, and the second source-drain electrode layer 104 includes a plurality of second patterns 1041 and a plurality of third patterns 1042 corresponding to the plurality of second patterns 1041. Each second pattern 1041 is connected to a first signal line 1031, and each third pattern 1042 is connected to a first pattern 1032.

[0098] Among them, reference Figure 2There is a first interval d1 between the first signal line 1031 and the corresponding first pattern 1032 , and there is a second interval d2 between the second pattern 1041 and the corresponding third pattern 1042 , and the first interval d1 is greater than the second interval d2 .

[0099] In the embodiment of the present application, the connection between each second pattern 1041 and a first signal line 1031 may mean that the orthographic projection of each second pattern 1041 on the substrate 101 and the orthographic projection of a first signal line 1031 on the substrate 101 at least partially overlap, and the second pattern 1041 is directly connected to the first signal line 1031. The connection between each third pattern 1042 and a first pattern 1032 may mean that the orthographic projection of each third pattern 1042 on the substrate 101 and the orthographic projection of the first pattern 1032 on the substrate 101 overlap at least partially, and the third pattern 1042 is directly connected to the first pattern 1032.

[0100] Since the first interval d1 is greater than the second interval d2, and the second pattern 1041 is connected to a first signal line 1031, and the third pattern 1042 is connected to the first pattern 1032, the second pattern 1041 includes not only a portion overlapping with the first signal line 1031, but also a portion not overlapping with the first signal line 1031, and the third pattern 1042 includes not only a portion overlapping with the first pattern 1032, but also a portion not overlapping with the first pattern 1032. Therefore, the second pattern 1041 needs to climb at the edge of the first signal line 1031 close to the first pattern 1032, and the third pattern 1042 needs to climb at the edge of the first pattern 1032 close to the first signal line 1031.

[0101] Generally, since the first signal line 1031 in the first source-drain electrode layer 103 needs to transmit a signal, in order to ensure the reliability of signal transmission, the thickness of the first signal line 1031 needs to be relatively thick (approximately about 4000 angstroms). In addition, the first pattern 1032 can be made of the same material as the first signal line 1031 and can be prepared by the same preparation process, so the thickness of the first pattern 1032 can be the same as the thickness of the first signal line 1031.

[0102] Since the thickness of the first signal line 1031 and the first pattern 1032 is relatively thick, the step difference of the second pattern 1041 at the edge of the first signal line 1031 and the step difference of the third pattern 1042 at the edge of the first pattern 1032 are both relatively large. However, the material of the second source-drain electrode layer 104 is usually a metal material, and the metal material has a good climbing ability. Therefore, even if the step difference is relatively large, it will not have a significant impact on the performance of the second pattern 1041 and the third pattern 1042 in the second source-drain electrode layer 104, and the second pattern 1041 and the third pattern 1042 can be prevented from being disconnected, thereby ensuring the yield of the product.

[0103] In summary, an embodiment of the present application provides an array substrate, which includes a base substrate, and a first electrode layer, a first source-drain layer, and a second source-drain layer stacked in sequence. The first source-drain layer includes a first signal line, and a first pattern connected to a pixel electrode in the first electrode layer, and the second source-drain layer includes a second pattern connected to the first signal line, and a third pattern connected to the first pattern. Since the first interval between the first signal line and the first pattern is greater than the second interval between the second pattern and the third pattern, the second pattern can be set to climb at the edge of the first signal line, and the third pattern can be set to climb at the edge of the first pattern. Since the second pattern and the third pattern have good climbing ability, even if the break difference of the climbing position is large, it will not cause too much impact on the performance of the second pattern and the third pattern, and the second pattern and the third pattern can be prevented from breaking, thereby ensuring the yield of the product.

[0104] In an embodiment of the present application, the array substrate 10 includes a plurality of drive circuits. The plurality of drive circuits constitute a plurality of groups of drive circuits arranged along a first direction X. Each group of drive circuits includes a plurality of drive circuits arranged along a second direction Y. Each first signal line 1031 is connected to each drive circuit in a group of drive circuits. Furthermore, each drive circuit in each group of drive circuits is connected via a first pattern and a pixel electrode. That is, the drive circuit in the array substrate 10 can realize the connection between the first signal line 1031 and the pixel electrode 1021 to transmit the signal of the first signal line 1031 to the pixel electrode 1021.

[0105] Optionally, each driving circuit includes a thin film transistor (TFT), and the thin film transistor includes a gate, a source, and a drain. The source is connected to the first signal line 1031, the drain is connected to the pixel electrode, and the gate is connected to the gate signal line. When the gate signal line controls the gate to be in an on state, the source and the drain are connected, so that the first signal line 1031 transmits the signal to the pixel electrode 1021.

[0106] Combination Figure 1 and Figure 2 , the first electrode layer 102 further includes a plurality of second signal lines 1022 corresponding to the plurality of first signal lines 1031. The plurality of second signal lines 1022 are arranged along the first direction X and extend along the second direction Y. The plurality of first signal lines 1031 and the plurality of second signal lines 1022 may correspond one to one, and the correspondence between each first signal line 1031 and one second signal line 1022 may mean that the orthographic projection of the first signal line 1031 on the base substrate 101 at least partially overlaps with the orthographic projection of the corresponding second signal line 1022 on the base substrate 101.

[0107] The first signal line 1031 includes a first edge m1 and a second edge m2 extending along the second direction Y and arranged opposite to each other. The first edge m1 is closer to the target first pattern than the second edge m2. The target first pattern is a first pattern connected to any one of a group of drive circuits connected to the first signal line 1031. That is, the first signal line 1031 and the target first pattern can be connected to the same drive circuit. The relative positions of the first edge m1 and the second edge m2 in the first signal line 1031 are relative to the position of the first pattern connected to the same drive circuit as the first signal line 1031.

[0108] The second signal line 1022 includes a third edge m3 and a fourth edge m4 extending along the second direction Y and arranged opposite to each other, and the third edge m3 is closer to the target pixel electrode than the fourth edge m4. The target pixel electrode is a pixel electrode connected to any driving circuit in a group of driving circuits connected to a first signal line 1031 corresponding to the second signal line 1022. That is, the target pixel electrode can be connected to the same driving circuit as the first signal line corresponding to the second signal line. The relative positions of the third edge m3 and the fourth edge m4 of the second signal line 1022 are both relative to the pixel electrode connected to the same driving circuit as the first signal line corresponding to the second signal line 1022.

[0109] Since the second pattern 1041 needs to climb above the first signal line 1031, the thickness of the first electrode layer 102 and the thickness of the first source-drain electrode layer 103 will affect the climbing height of the second pattern 1041. For example, the climbing height of the second pattern 1041 is equal to the sum of the thickness of the first electrode layer 102 and the thickness of the first source-drain electrode layer 103.

[0110] In order to avoid a large step difference between the total thickness of the first electrode layer 102 and the first source-drain electrode layer 103, the edges of the first signal line 1031 and the second signal line 1022 may be staggered. That is, the orthographic projection of the first edge m1 on the base substrate 101 and the orthographic projection of the third edge m3 on the base substrate 101 do not overlap, and the orthographic projection of the second edge m2 on the base substrate 101 and the orthographic projection of the fourth edge m4 on the base substrate 101 do not overlap.

[0111] refer to Figure 4 , each side of the second pattern 1041 has two climbing areas. For example, for the side of the second pattern 1041 close to the third pattern 1042, the first climbing area is located at the first edge m1 of the first signal line 1031, and the second climbing area is located at the third edge m3 of the second signal line 1022. The climbing height of the second pattern 1041 at the first climbing area is the height of the first signal line 1031, and the climbing height of the second pattern 1041 at the second climbing area is the height of the second signal line 1022.

[0112] By staggering the edges of the first signal line 1031 and the second signal line 1022 , the climbing height of the second pattern 1041 can be decomposed into two small climbing heights, further preventing the second pattern 1041 from breaking during climbing, thereby ensuring the yield of the product.

[0113] In the embodiment of the present application, the first signal line 1031 and the second signal line 1022 may be staggered in three situations. Figure 4 , Scheme 1, the orthographic projection of the first edge m1 on the substrate 101 and the orthographic projection of the second edge m2 on the substrate 101 are both located between the orthographic projection of the third edge m3 on the substrate 101 and the orthographic projection of the fourth edge m4 on the substrate 101. That is, the length of the first signal line 1031 along the first direction X (i.e., the width of the first signal line 1031) is less than the length of the second signal line 1022 along the first direction X (i.e., the width of the second signal line 1022). Figure 5, Solution 2, the orthographic projection of the first edge m1 on the substrate 101 is closer to the orthographic projection of the first pattern 1032 on the substrate 101 relative to the orthographic projection of the third edge m3 on the substrate 101, and the orthographic projection of the second edge m2 on the substrate 101 is located between the orthographic projection of the third edge m3 on the substrate 101 and the orthographic projection of the fourth edge m4 on the substrate 101. That is, the width of the first signal line 1031 can be equal to the width of the second signal line 1022, and it is only necessary to stagger the first signal line 1031 and the second signal line 1022. Solution 3, the orthographic projection of the first edge m1 on the substrate 101 is closer to the orthographic projection of the first pattern 1032 on the substrate 101 relative to the orthographic projection of the third edge m3 on the substrate 101, and the orthographic projection of the second edge m2 on the substrate 101 is located at the orthographic projection of the fourth edge m4 on the substrate 101 farther from the orthographic projection of the first pattern 1032 on the substrate 101. That is, the width of the first signal line 1031 may be greater than the width of the second signal line 1022 .

[0114] In the embodiment of the present application, for the above-mentioned solution 1, in order to reduce the number of masks used in the preparation of the array substrate 10, the first electrode layer 102 and the first source and drain electrode layer 103 can be prepared using the same mask. The mask used in preparing the first electrode layer 102 and the first source and drain electrode layer 103 is a half-tone mask.

[0115] It should be noted that the second pattern 1041 of the second source and drain layer 104 may not need to be sloped at the second edge m2 and the fourth edge m4, thereby allowing the orthographic projection of the second edge m2 on the base substrate 101 to overlap with the orthographic projection of the fourth edge m4 on the base substrate 101.

[0116] refer to Figure 4 It can be seen that the pixel electrode 1021 may include: a connecting portion 10211 and a main region portion 10212. Figure 1 The array substrate 10 further includes a second electrode layer 105, and the second electrode layer 105 includes a common electrode 1051. The connecting portion 10211 is connected to the first pattern 1032. The orthographic projection of the main area portion 10212 on the base substrate 101 and the orthographic projection of the common electrode 1051 on the base substrate 101 at least partially overlap, and the main area portion 10212 and the common electrode 1051 jointly drive the deflection of liquid crystal molecules in the liquid crystal layer in the display panel.

[0117] The first pattern 1032 includes a fifth edge m5 and a sixth edge m6 extending along the second direction Y and arranged oppositely. The fifth edge m5 is closer to the target first signal line than the sixth edge m6. The target first signal line is connected to the same driving circuit as the first pattern. The connecting portion 10211 includes a seventh edge m7 and an eighth edge m8 extending along the second direction Y and arranged oppositely, and the seventh edge m7 is closer to the target second signal line than the eighth edge m8. The first signal line corresponding to the target second signal line and the connecting portion are connected to the same driving circuit.

[0118] That is, the relative positions of the fifth edge m5 and the sixth edge m6 in the first pattern 1032 are both relative to the position of the first signal line connected to the same driving circuit as the first pattern 1032. The relative positions of the seventh edge m7 and the eighth edge m8 of the connecting portion 10211 are both relative to the second signal line corresponding to the first signal line connected to the same driving circuit as the connecting portion 10211.

[0119] Since the third pattern 1042 needs to climb above the connection portion 10211, the thickness of the first electrode layer 102 and the thickness of the first source-drain electrode layer 103 will affect the climbing height of the third pattern 1042. For example, the climbing height of the third pattern 1042 is equal to the sum of the thickness of the first electrode layer 102 and the thickness of the first source-drain electrode layer 103.

[0120] In order to avoid a large step difference between the total thickness of the first electrode layer 102 and the first source-drain electrode layer 103, the edges of the first pattern 1032 and the connecting portion 10211 may be staggered. That is, the orthographic projection of the fifth edge m5 on the base substrate 101 and the orthographic projection of the seventh edge m7 on the base substrate 101 do not overlap, and the orthographic projection of the sixth edge m6 on the base substrate 101 and the orthographic projection of the eighth edge m8 on the base substrate 101 do not overlap.

[0121] refer to Figure 5 , each side of the third pattern 1042 has two climbing areas. For the side of the third pattern 1042 close to the second pattern 1041, the first climbing area is located at the fifth edge m5 of the first pattern 1032, and the second climbing area is located at the seventh edge m7 of the connecting portion 10211. The climbing height of the third pattern 1042 at the first climbing area is the height of the first pattern 1032, and the climbing height of the third pattern 1042 at the second climbing area is the height of the connecting portion 10211.

[0122] By staggering the edges of the first pattern 1032 and the connecting portion 10211 , the climbing height of the third pattern 1042 can be decomposed into two small climbing heights, thereby further preventing the third pattern 1042 from breaking when climbing, thereby ensuring the yield of the product.

[0123] In the embodiment of the present application, the first pattern 1032 and the edge of the connecting portion 10211 may be staggered in two situations. Figure 5 , Solution 1, the orthographic projection of the fifth edge m5 on the base substrate 101 and the orthographic projection of the sixth edge m6 on the base substrate 101 are both located at the orthographic projection of the seventh edge m7 on the base substrate 101 and the orthographic projection of the eighth edge m8 on the base substrate 101. That is, the length of the first pattern 1032 along the first direction X (i.e., the width of the first pattern 1032) is less than the length of the connecting portion 10211 along the first direction X (i.e., the width of the connecting portion 10211). Figure 6 , Solution 2, the orthographic projection of the fifth edge m5 on the substrate 101 is closer to the orthographic projection of the first signal line 1031 on the substrate 101 relative to the orthographic projection of the seventh edge m7 on the substrate 101, and the orthographic projection of the sixth edge m6 on the substrate 101 is located between the orthographic projection of the seventh edge m7 on the substrate 101 and the orthographic projection of the eighth edge m8 on the substrate 101. That is, the width of the connecting portion 10211 can be equal to the width of the first pattern 1032, and the connecting portion 10211 and the first pattern 1032 only need to be staggered. Solution 3, the orthographic projection of the fifth edge m5 on the substrate 101 is closer to the orthographic projection of the first signal line 1031 on the substrate 101 relative to the orthographic projection of the seventh edge m7 on the substrate 101, and the orthographic projection of the sixth edge m6 on the substrate 101 is located between the orthographic projection of the seventh edge m7 on the substrate 101 and the orthographic projection of the eighth edge m8 on the substrate 101 is farther away from the orthographic projection of the first signal line 1031 on the substrate 101. That is, the width of the first pattern 1032 may be greater than the width of the connection portion 10211 .

[0124] It should be noted that the third pattern 1042 of the second source and drain layer 104 may not need to be sloped at the sixth edge m6 and the eighth edge m8, thereby allowing the orthographic projection of the sixth edge m6 on the base substrate 101 and the orthographic projection of the eighth edge m8 on the base substrate 101 to overlap.

[0125] In the examples of this application, refer to Figure 3 , the sixth edge m6 of the first pattern 1032 may include a first sub-edge m61, a second sub-edge m62, and a third sub-edge m63 connecting the first sub-edge m61 and the second sub-edge m62. The first sub-edge m61 and the second sub-edge m62 both extend along the second direction Y, and the third sub-edge m63 extends along the first direction X. Figure 4The eighth edge m8 of the connecting portion 10211 may include a fourth sub-edge m81, a fifth sub-edge m82, and a sixth sub-edge m83 connecting the fourth sub-edge m81 and the fifth sub-edge m82. The fourth sub-edge m81 and the fifth sub-edge m82 both extend along the second direction Y, and the sixth sub-edge m83 extends along the first direction X.

[0126] Optionally, the staggered arrangement of the sixth edge m6 and the eighth edge m8 may refer to the staggered arrangement of the first sub-edge m61 and the fourth sub-edge m81, and the staggered arrangement of the second sub-edge m62 and the fifth sub-edge m82. For example, the orthographic projection of the sixth edge m6 on the substrate substrate 101 being located between the orthographic projection of the seventh edge m7 on the substrate substrate 101 and the orthographic projection of the eighth edge m8 on the substrate substrate 101 may refer to: the orthographic projection of the first sub-edge m61 on the substrate substrate 101 is located between the orthographic projection of the seventh edge m7 on the substrate substrate 101 and the orthographic projection of the fourth sub-edge m81 on the substrate substrate 101, and the orthographic projection of the second sub-edge m62 on the substrate substrate 101 is located between the orthographic projection of the seventh edge m7 on the substrate substrate 101 and the orthographic projection of the fifth sub-edge m82 on the substrate substrate 101.

[0127] refer to Figure 1 It can also be seen that the array substrate 10 further includes: a semiconductor layer 106 located on a side of the second source-drain electrode layer 104 away from the base substrate 101. The length of the orthographic projection of the target portion of the semiconductor layer 106 on the base substrate 101 along the first direction X is less than the first interval d1 and greater than the second interval d2. The material of the semiconductor layer 106 can be an organic semiconductor material (Organic semiconductor, OSC).

[0128] In the embodiment of the present application, the orthographic projection of the target portion of the semiconductor layer 106 on the base substrate 101 partially overlaps with the orthographic projection of the second source-drain electrode layer 104 on the base substrate 101, and does not overlap with the orthographic projection of the first source-drain electrode layer 103 on the base substrate 101. That is, a portion of the target portion of the semiconductor layer 106 overlaps and is connected to the second pattern 1041, a portion overlaps and is connected to the third pattern 1042, and another portion is located between the second pattern 1041 and the third pattern 1042. The target portion of the semiconductor layer 106 needs to climb at the ninth edge m9 of the second pattern 1041 close to the third pattern 1042, and also needs to climb at the tenth edge m10 of the third pattern 1042 close to the second pattern 1041.

[0129] Since the second pattern 1041 is connected to the first signal line 1031, the third pattern 1042 is connected to the first pattern 1032, and the semiconductor layer 106 is connected to the second pattern 1041 and the third pattern 1042, the semiconductor layer 106 is connected to the first signal line 1031 and the first pattern 1032. Furthermore, since the first pattern 1032 is also connected to the connecting portion 10211 of the pixel electrode 1021, the semiconductor layer 106 is connected to the first signal line 1031 and the connecting portion 10211.

[0130] In the embodiment of the present application, since the second pattern 1041 of the second source-drain electrode layer 104 is used to realize the overlap between the first signal line 1031 and the semiconductor layer 106, and the third pattern 1042 of the second source-drain electrode layer 104 is used to realize the overlap between the first pattern 1032 and the semiconductor layer 106, the second source-drain electrode layer 104 is only used to realize the overlap. Further, only realizing the overlap function does not require the thickness of the second source-drain electrode layer 104 to be designed too thick, for example, the thickness of the second source-drain electrode layer 104 ranges from 800A (angstroms) to 900A, for example, 850A.

[0131] Therefore, since the thickness of the second source-drain electrode layer 104 is relatively thin, the step difference at the ninth edge m9 of the second pattern 1041 and the tenth edge m10 of the third pattern 1042 is relatively small. Therefore, even if the semiconductor layer 106 needs to climb at the ninth edge m9 of the second pattern 1041 and the tenth edge m10 of the third pattern 1042, the semiconductor layer 106 will not be broken or damaged, and the yield of the semiconductor layer 106 can be guaranteed.

[0132] refer to Figure 1 It can also be seen that the array substrate 10 further includes: a first insulating layer 107 and a gate layer 108 which are stacked and located on a side of the semiconductor layer 106 away from the base substrate 101. The orthographic projection of the first insulating layer 107 on the base substrate 101 and the orthographic projection of the gate layer 108 on the base substrate 101 both overlap with the orthographic projection of the semiconductor layer 106 on the base substrate 101.

[0133] In the embodiment of the present application, in order to reduce the number of masks used in preparing the array substrate 10, the semiconductor layer 106, the first insulating layer 107 and the gate layer 108 can be prepared using the same mask. The process of preparing the semiconductor layer 106, the first insulating layer 107 and the gate layer 108 includes: forming a semiconductor film, a first insulating film and a gate film in sequence on the side of the second source and drain electrode layer 104 away from the base substrate 101; patterning the gate film using a mask to obtain the gate layer 108; and patterning the semiconductor film and the first insulating film using the gate layer 108 as a hard mask to obtain the semiconductor layer 106 and the first insulating layer 107.

[0134] refer to Figure 1 It can also be seen that the array substrate 10 further includes: a light shielding layer (LS) 109 and a second insulating layer 110 which are stacked and located between the first electrode layer 102 and the base substrate 101 .

[0135] Among them, reference Figure 7 The light shielding layer 109 includes a plurality of light shielding portions 1091, and a plurality of third signal lines 1092 arranged along the second direction Y and extending along the first direction X. The orthographic projection of the light shielding portion 1091 on the base substrate 101 covers the orthographic projection of the channel portion on the base substrate 101. The channel portion is a portion where the semiconductor layer 106 and the gate layer 108 overlap and do not overlap with the second source and drain layer 104. The light shielding portion 1091 covers the channel portion to prevent the channel portion from being affected by light from one side of the base substrate 101, thereby ensuring the effectiveness of the channel portion. In addition, the third signal line 1092 is connected to the gate layer 108 to provide a gate signal to the gate layer 108.

[0136] refer to Figure 1 , the array substrate 10 further includes: a third insulating layer 111 located on a side of the gate layer 108 away from the base substrate 101. The second electrode layer 105 is located on a side of the third insulating layer 111 away from the base substrate 101. The second electrode layer 105 further includes: a transition portion 1052. One end of the transition portion 1052 is connected to the light shielding portion 1091 through a first via hole k1 in the third insulating layer 111 and the second insulating layer 110, and the other end of the transition portion 1052 is connected to the gate layer 108 through a second via hole k2 in the third insulating layer 111. The material of the first electrode layer 105 can be ITO.

[0137] In the embodiment of the present application, the source of the thin film transistor in the driving circuit can be composed of the overlapping area of ​​the semiconductor layer 106 and the second pattern 1041, the drain can be composed of the overlapping area of ​​the semiconductor layer 106 and the third pattern 1042, and the gate can be composed of the gate pattern in the gate layer 108.

[0138] The third signal line 1092 may be a gate signal line, and the gate of the thin film transistor is connected to the third signal line 1092. The first signal line 1031 may be a data signal line, and the source of the thin film transistor is connected to the first signal line 1031 for receiving a data signal. The drain of the thin film transistor is connected to the connecting portion 10211 of the pixel electrode 1021, so that the pixel electrode 1021 can receive the data signal transmitted from the first signal line 1031 when the gate of the thin film transistor is in an on state.

[0139] In the embodiment of the present application, since the semiconductor layer 106, the first insulating layer 107 and the gate layer 108 can be obtained by a one-time preparation process, the gate layer 108 only includes a pattern constituting the gate of the thin film transistor, and does not include a gate signal line for transmitting a gate signal. Because if the gate layer 108 includes a gate signal line, the semiconductor layer 106 will have a semiconductor pattern at the corresponding position of the gate signal line, and the design of the thin film transistor cannot be realized. Based on the above reasons, since the gate layer 108 cannot be designed with a gate signal line, the gate signal line (third signal line 1092) can be designed in the light shielding layer 109.

[0140] In the examples of this application, refer to Figure 1 The array substrate 10 further includes a fourth insulating layer 112 , which is located between the base substrate 101 and the light shielding layer 109 .

[0141] The first insulating layer 107 is a gate insulator (GI). The second insulating layer 110 and the fourth insulating layer 112 can be planarization layers (PLN). The third insulating layer 111 can be a passivation layer (PVX). The thickness of the planarization layer is about 1 μm (micrometer), and the thickness of the passivation layer is less than that of the planarization layer. For example, the thickness of the passivation layer ranges from 1000A to 1 μm.

[0142] It should be noted that the embodiments of the present application Figure 1 It is only used to indicate the stacking relationship and connection relationship of each structure in the array substrate, and does not indicate the actual overlapping relationship of each structure. Figure 8 , the section line shown at position 1 is used to represent Figure 1 The cross-section line of the TFT structure in the middle frame line 1, the cross-section line shown in position 2 is used to represent Figure 1 The cross-section line of the transition structure in the middle frame line 2 and the cross-section line shown in position 3 are used to indicate Figure 1 Cross-section line of the capacitor structure in the middle frame line 3.

[0143] In the embodiment of the present application, in order to clearly represent each film layer, each film layer of the array substrate 10 is briefly introduced below in the form of each single layer and a step-by-step stacking method.

[0144] Fig. 9 Schematic diagram of a partial light shielding layer provided in an embodiment of the present application. Fig. 9 The light shielding layer 109 may include a plurality of light shielding portions 1091 and a plurality of third signal lines 1092 arranged along the second direction Y and extending along the first direction X.

[0145] Fig.10 It is a partial schematic diagram of the first electrode layer provided in an embodiment of the present application. Fig.11 Schematic diagram of partial superposition of the light shielding layer and the first electrode layer provided in the embodiment of the present application. Fig.10 and Fig.11 The first electrode layer 102 includes a plurality of second signal lines 1022 arranged in a first direction X and extending along a second direction Y, and a plurality of pixel electrodes 1021 arranged in an array.

[0146] Fig.12 It is a partial schematic diagram of the first source and drain layer provided in an embodiment of the present application. Fig.13 Schematic diagram of partial superposition of the light shielding layer, the first electrode layer and the first source and drain electrode layer provided in the embodiment of the present application. Fig.12 and Fig.13 The first source-drain layer 103 includes a plurality of first signal lines 1031 arranged along a first direction X and extending along a second direction Y, and a plurality of first patterns 1032 .

[0147] in, Fig.13 In the embodiment, the first signal lines 1031 correspond to the second signal lines 1022 one by one, and the first patterns 1032 correspond to the pixel electrodes 1021 one by one. In addition, the first signal lines 1031 and the second signal lines 1022 are not staggered, and the first patterns 1032 and the pixel electrodes 1021 are not staggered.

[0148] Fig.14 It is a partial schematic diagram of the second source and drain layer provided in an embodiment of the present application. Fig.15 Schematic diagram of partial superposition of the light shielding layer, the first electrode layer, the first source and drain electrode layer and the second source and drain electrode layer provided in the embodiment of the present application. Fig.14 and Fig.15 The second source-drain layer 104 includes a plurality of second patterns 1041 and a plurality of third patterns 1042 corresponding to the plurality of second patterns 1041 .

[0149] Each second pattern 1041 partially overlaps with a first signal line 1031 , and each third pattern 1042 partially overlaps with a first pattern 1032 .

[0150] Fig.16 It is a partial schematic diagram of the gate layer provided in an embodiment of the present application. Fig.17 It is a partial superposition diagram of the light shielding layer, the first electrode layer, the first source and drain electrode layer, the second source and drain electrode layer, the semiconductor layer, the first insulating layer and the gate layer provided in the embodiment of the present application. Fig.16 and Fig.17 The gate layer 108 includes a plurality of gate patterns 1081 , and each gate pattern 1081 can be used to form a gate of a thin film transistor.

[0151] Among them, since the semiconductor layer 106 and the first insulating layer 107 are both prepared using the same mask as the gate layer 108, the layout designs of the semiconductor layer 106 and the first insulating layer 107 are the same as the gate layer 108, and the embodiments of the present application will not be repeated here.

[0152] In addition, in the embodiments of the present application, reference is made to Figure 8 , the orthographic projection of the pattern of the gate layer 108 on the base substrate 101 overlaps with the orthographic projection of the first pattern 1032 in the first source-drain electrode layer 103 on the base substrate, so that the pattern of the gate layer 108 is connected to the third signal line 1092 of the light shielding layer 109 through the subsequently formed transition portion 1052. In addition, since the patterns of the semiconductor layer 106 and the gate layer 108 are the same, the orthographic projection of the semiconductor layer 106 on the base substrate 101 overlaps with the orthographic projection of the first pattern 1032 in the first source-drain electrode layer 103 on the base substrate, as shown in FIG. Figure 8 Position 4 shown. However, since this position does not need to be used as a channel of the thin film transistor, even if the semiconductor layer 106 slopes at the edge of the first pattern 1032, it will not affect the performance of the thin film transistor.

[0153] in, Figure 8 The position 5 shown may have a channel of a thin film transistor. In the embodiment of the present application, the length of the orthographic projection of the target portion of the semiconductor layer 106 on the substrate 101 along the first direction is less than the first interval and greater than the second interval. Figure 8 As shown in position 5, the target portion may constitute a channel of a thin film transistor.

[0154] Fig.18 It is a partial schematic diagram of the third insulating layer provided in an embodiment of the present application. Fig.19 It is a partial superposition diagram of the light shielding layer, the first electrode layer, the first source and drain electrode layer, the second source and drain electrode layer, the semiconductor layer, the first insulating layer, the gate layer and the third insulating layer provided in the embodiment of the present application. Fig.18 and Fig.19 , the third insulating layer 111 includes a plurality of first via holes k1 and a plurality of second via holes k2 .

[0155] The first via k1 can be used to connect the third signal line 1092 and the transition portion 1052 in the second electrode layer 105 formed subsequently, and the second via k2 can be used to connect the gate layer 108 and the transition portion 1052 in the second electrode layer 105 formed subsequently.

[0156] It should be noted that the second insulating layer 110 included in the array substrate 10 and located between the light shielding layer 109 and the first electrode layer 102 also has a first via hole k1, and the position of the first via hole k1 in the second insulating layer 110 corresponds to the position of the first via hole k1 in the third insulating layer 111. The first via hole k1 in the second insulating layer 110 and the first via hole k1 in the third insulating layer 111 are both used to realize the connection between the third signal line 1092 and the transition portion 1052.

[0157] Fig. 20 It is a partial schematic diagram of the second electrode layer provided in an embodiment of the present application. Fig.21 This is a partial superposition diagram of the light shielding layer, the first electrode layer, the first source and drain electrode layer, the second source and drain electrode layer, the semiconductor layer, the first insulating layer, the gate layer, the third insulating layer and the second electrode layer provided in the embodiment of the present application. Fig. 20 and Fig.21 The second electrode layer 105 includes a transition portion 1052 and a common electrode 1051 .

[0158] The transition portion 1052 is used to connect the third signal line 1092 and the gate layer 108, so that the third signal line 1092 transmits a gate signal to the gate layer 108. The orthographic projection of the common electrode 1051 on the base substrate 101 and the orthographic projection of the main area 10212 of the pixel electrode 1021 on the base substrate 101 partially overlap, so that the common electrode 1051 and the main area 10212 can jointly drive the deflection of the liquid crystal molecules in the liquid crystal layer.

[0159] In summary, an embodiment of the present application provides an array substrate, which includes a base substrate, and a first electrode layer, a first source-drain layer, and a second source-drain layer stacked in sequence. The first source-drain layer includes a first signal line, and a first pattern connected to a pixel electrode in the first electrode layer, and the second source-drain layer includes a second pattern connected to the first signal line, and a third pattern connected to the first pattern. Since the first interval between the first signal line and the first pattern is greater than the second interval between the second pattern and the third pattern, the second pattern can be set to climb at the edge of the first signal line, and the third pattern can be set to climb at the edge of the first pattern. Since the second pattern and the third pattern have good climbing ability, even if the break difference of the climbing position is large, it will not cause too much impact on the performance of the second pattern and the third pattern, and the second pattern and the third pattern can be prevented from breaking, thereby ensuring the yield of the product.

[0160] Fig. 22 is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application. Fig. 22 , the method comprising:

[0161] Step S101: provide a base substrate.

[0162] In the embodiment of the present application, when preparing the array substrate 10, a base substrate 101 may be obtained first. The base substrate 101 may be a glass substrate or a flexible substrate. The material of the flexible substrate may be a triacetate film.

[0163] In the case where the base substrate 101 is a flexible substrate, the base substrate 101 can be first formed on a glass substrate, and finally, after completing step S109, the glass substrate can be peeled off. In this case, the prepared array substrate 10 can be a flexible array substrate. The flexible array substrate can meet the bending requirements of liquid crystal display products.

[0164] Step S102: forming a fourth insulating layer on one side of the base substrate.

[0165] The fourth insulating layer 112 may entirely cover the base substrate 101 .

[0166] Step S103 , forming a light shielding layer on a side of the fourth insulating layer away from the base substrate.

[0167] In the examples of this application, refer to Fig.23 A light shielding layer 109 may be formed on a side of the fourth insulating layer 112 away from the base substrate 101. The light shielding layer 109 includes a plurality of light shielding portions 1091 and a plurality of third signal lines 1092 arranged along the second direction Y and extending along the first direction X.

[0168] The preparation process of the light shielding layer 109 includes: forming a light shielding film on the side of the fourth insulating layer 112 away from the base substrate 101, and patterning the light shielding film using a mask for forming the light shielding layer 109 to obtain the light shielding layer 109. The patterning process includes: photoresist coating, exposure, development, etching, and removing the photoresist.

[0169] Step S104 , forming a second insulating film on a side of the light shielding layer away from the base substrate.

[0170] In the examples of this application, refer to Fig.24 A second insulating film 110 a may be formed on a side of the light shielding layer 109 away from the base substrate 101 , and the second insulating film 110 a may cover the entire layer.

[0171] Step S105 , forming a first electrode layer and a first source-drain layer on a side of the second insulating film away from the substrate.

[0172] In the embodiment of the present application, the method of forming the first electrode layer 102 and the first source and drain layer 103 may include the following two methods.

[0173] Method 1: The first electrode layer 102 and the first source-drain electrode layer 103 can be prepared by the same process. The method includes:

[0174] Step S1051a, reference Fig.25 A first electrode film 102 a and a first source-drain film 103 a are formed on a side of the second insulating film 110 a away from the base substrate 101 .

[0175] Step S1052a, reference Fig.26 A photoresist layer is formed on a side of the first source / drain film 103 a away from the substrate 101 .

[0176] Step S1053a, reference Fig. 27 , the photoresist layer is processed using a half-tone mask to obtain a photoresist mask.

[0177] The photoresist mask includes a first portion n1 and a second portion n2, wherein the thickness of the first portion n1 is greater than the thickness of the second portion n2. The region where the first portion n1 is located is used to form the pattern of the first electrode layer 102 and the pattern of the first source-drain electrode layer 103, and the region where the second portion n2 is located is used to form the pattern of the first electrode layer 102, and the pattern of the first source-drain electrode layer 103 will not be formed in the region where the second portion n2 is located.

[0178] For example, refer to Fig. 27 The first portion n1 may include a first sub-portion n11 and a second sub-portion n12, wherein the first sub-portion n11 is used to form the second signal line 1022 of the first electrode layer 102 and the first signal line 1031 of the first source-drain electrode layer 103, and the second sub-portion n12 is used to form the connection portion 10211 of the pixel electrode 1021 of the first electrode layer 102 and the first pattern 1032 of the first source-drain electrode layer 103. The second portion n2 is used to form the main region 10212 of the pixel electrode 1021 of the first electrode layer 102.

[0179] Step S1054a: performing a first patterning process on the first electrode film and the first source and drain film using a photoresist mask.

[0180] refer to Fig.28After the first patterning process, the pattern of the first electrode film and the pattern of the first source and drain film that are the same as the image of the photoresist mask can be obtained. That is, the first electrode layer 102 includes a plurality of second signal lines 1022 and a plurality of pixel electrodes 1021. The thickness of the first electrode layer 102 is approximately 1000 Å (angstroms).

[0181] Step S1055a, reference Fig.29 , the photoresist mask is ashed to remove the second portion n2 of the photoresist mask and retain the first portion n1.

[0182] Step S1056a: performing a second patterning process on the first source / drain thin film based on the first portion n1 of the photoresist mask, and removing the first portion n1 of the photoresist mask.

[0183] refer to Fig.30 After the second patterning process, a plurality of first signal lines 1031 and a plurality of first patterns 1032 included in the first source and drain layer 103 can be obtained.

[0184] In the embodiment of the present application, the first signal line 1031 and the second signal line 1022 are staggered, and the first pattern 1032 and the pixel electrode 1021 are staggered, thereby preventing the second source and drain layer 104 formed subsequently from breaking when climbing. Fig.30 Take the non-misaligned setting as an example.

[0185] For example, the second signal line 1022 extends a portion relative to the first signal line 1031, and the first signal line 1031 and the second signal line 1022 form a stepped structure, which can avoid the second pattern 1041 of the second source and drain layer 104 from crossing the step formed by the two stacked layers. Among them, the second signal line 1022 serves as the first step, the first signal line 1031 serves as the second step, and the second pattern 1041 can climb the first step and the second step respectively. The step of climbing at the first step is the thickness of the second signal line 1022, and the step of climbing at the second step is the thickness of the first signal line 1031. That is, a larger step can be decomposed into two smaller steps, thereby avoiding the break of the second pattern 1041.

[0186] The connection portion 10211 of the pixel electrode 1021 extends a portion relative to the first pattern 1032, and the connection portion 10211 of the pixel electrode 1021 and the first pattern 1032 form a stepped structure, which can avoid the third pattern 1042 of the second source and drain layer 104 from crossing the step formed by the two stacked layers. Among them, the connection portion 10211 serves as the first step, the first pattern 1032 serves as the second step, and the third pattern 1042 can climb the first step and the second step respectively. The step climbing at the first step is the thickness of the connection portion 10211, and the step climbing at the second step is the thickness of the first pattern 1032. That is, a larger step can be decomposed into two smaller steps, thereby avoiding the third pattern 1042 from breaking.

[0187] In order to ensure the misalignment of the first electrode layer 102 and the first source-drain layer 103, it is necessary to consider the engineering deviation Tol1 when preparing the first electrode layer 102, the engineering deviation Tol2 when preparing the first source-drain layer 103, and the alignment deviation OVL of the first electrode layer 102 and the first source-drain layer 103. Optionally, the distance value of the first electrode layer 102 extending relative to the first source-drain layer 103 satisfies:

[0188]

[0189] For example, the engineering deviation Tol1 is equal to 1 μm (micrometer), the engineering deviation Tol2 when preparing the first source and drain layer 103 is equal to 1 μm, and the alignment deviation OVL between the first electrode layer 102 and the first source and drain layer 103 is equal to 0.6 μm. According to the above formula (1), it is calculated that the distance value of the first electrode layer 102 extending relative to the first source and drain layer 103 must be greater than 1 μm.

[0190] Method 2: The first electrode layer 102 and the first source-drain electrode layer 103 can be prepared by two processes respectively. The method includes:

[0191] Step S1051b: forming a first electrode film 102a on a side of the second insulating film 110a away from the base substrate 101.

[0192] Step S1052b: patterning the first electrode film 102a to obtain the first electrode layer 102.

[0193] The mask used in the patterning process is a mask used to form the first electrode layer 102. The patterning process includes: photoresist coating, exposure, development, etching, and removal of the photoresist.

[0194] Step S1053 b , forming a first source-drain thin film 103 a on a side of the first electrode layer 102 away from the base substrate 101 .

[0195] Step S1054b: patterning the first source-drain film 103a to obtain the first source-drain electrode layer 103.

[0196] The mask used in the patterning process is a mask used to form the first source and drain electrode layer 103. The patterning process includes: photoresist coating, exposure, development, etching, and removal of the photoresist.

[0197] In the second solution, the distance that the second signal line 1022 extends relative to the first signal line 1031 and the distance that the connecting portion 10211 of the pixel electrode 1021 extends relative to the first pattern 1032 can be determined by the above formula (1).

[0198] Step S106 , forming a second source-drain electrode layer on a side of the first source-drain electrode layer away from the substrate.

[0199] refer to Fig.31 The process of forming the second source-drain electrode layer 104 includes: forming a second source-drain film on a side of the first source-drain electrode layer 103 away from the substrate 101; patterning the second source-drain film using a mask for forming the second source-drain electrode layer 104 to obtain the second source-drain electrode layer 104. The patterning process includes: photoresist coating, exposure, development, etching, and removing the photoresist.

[0200] In the embodiment of the present application, since the first source-drain layer 103 is disposed on the side of the second source-drain layer 104 close to the base substrate 101, in order to prevent the etching process when forming the second source-drain layer 104 from affecting the first source-drain layer 103, the material of the second source-drain layer 104 can be different from the material of the first source-drain layer 103. Therefore, it is convenient to select different etching solutions to form the first source-drain layer 103 and the second source-drain layer 104, so as to prevent the etching solution when forming the second source-drain layer 104 from etching the first source-drain layer 103 on the lower side.

[0201] Optionally, the material of the first source-drain electrode layer 103 may be a three-layer structure of Ti (titanium), Al (aluminum), and Ti. Alternatively, the material of the first source-drain electrode layer 103 may be Mo (molybdenum). The thickness of the first source-drain electrode layer 103 is 4000 Å.

[0202] The material of the second source-drain electrode layer 104 can be Ag (silver) having a work function close to that of the material of the semiconductor layer 106 , and the thickness of the second source-drain electrode layer 104 is 850 Å.

[0203] Step S107, forming a semiconductor film, a first insulating film and a gate film in sequence on the side of the second source and drain layer away from the substrate, and patterning the semiconductor film, the first insulating film and the gate film to obtain a semiconductor layer, a first insulating layer and a gate layer.

[0204] In an embodiment of the present application, the process of patterning the semiconductor film, the first insulating film and the gate film includes: forming a photoresist layer on the side of the gate film away from the substrate 101; using a mask to process the photoresist layer to obtain a photoresist mask, and the area where the photoresist mask is located can be used to form a gate layer 108; using the photoresist mask to etch the gate film to obtain the gate layer 108; using the gate layer 108 as a mask to further etch the first insulating film and the semiconductor film to obtain a semiconductor layer 106 and a first insulating layer 107.

[0205] refer to Fig.32 , the orthographic projection of the semiconductor layer 106 on the base substrate 101 , the orthographic projection of the first insulating layer 107 on the base substrate 101 , and the orthographic projection of the gate layer 108 on the base substrate 101 all overlap.

[0206] Step S108 , forming a third insulating layer on a side of the gate layer away from the base substrate.

[0207] In the embodiment of the present application, a third gate film is first formed on the side of the gate layer 108 away from the base substrate 101 , and then the second gate film and the third gate film are patterned using a mask to obtain the second insulating layer 110 and the third insulating layer 111 .

[0208] refer to Fig.33 The second insulating layer 110 and the third insulating layer 111 include a first via hole k1, and the third insulating layer 111 includes a second via hole k2. The first via hole k1 is used to expose a portion of the third signal line 1092 in the light shielding layer 109, and the second via hole k2 is used to expose a portion of the gate layer 108.

[0209] Step S109: forming a second electrode layer on a side of the third insulating layer away from the base substrate.

[0210] In the embodiment of the present application, a second electrode film is first formed on a side of the third insulating layer 111 away from the base substrate 101, and then the second electrode film is processed using a mask to obtain the second electrode layer 105. The second electrode layer 105 includes a common electrode 1051 and a transition portion 1052. The orthographic projection of the common electrode 1051 on the base substrate 101 overlaps the orthographic projection of the main area 10212 of the pixel electrode 1021 on the base substrate 101, and one end of the transition portion 1052 is connected to the third signal line 1092 of the light shielding layer 109 through the first via k1, and the other end is connected to the gate layer 108 through the second via k2.

[0211] In an embodiment of the present application, if the first electrode layer 102 and the first source and drain layer 103 are prepared using a one-time preparation process, the following six masks are required in the preparation process of the array substrate: a mask 1 for preparing the light shielding layer 109; a half-tone mask 2 for preparing the first electrode layer 102 and the first source and drain layer 103; a mask 3 for preparing the second source and drain layer 104; a mask 4 for preparing the semiconductor layer 106, the first insulating layer 107 and the gate layer 108; a mask 5 for forming the first via holes in the second insulating layer and the third insulating layer, and the second via holes in the third insulating layer; and a mask 6 for forming the second electrode layer 105.

[0212] If the first electrode layer 102 and the first source and drain layer 103 are prepared using a two-step preparation process, the following seven masks are required in the preparation process of the array substrate: mask 1 for preparing the light shielding layer 109; mask 2 for preparing the first electrode layer 102; mask 3 for preparing the first source and drain layer 103; mask 4 for preparing the second source and drain layer 104; mask 5 for preparing the semiconductor layer 106, the first insulating layer 107 and the gate layer 108; mask 6 for forming the first via holes in the second insulating layer and the third insulating layer, and the second via holes in the third insulating layer; and mask 7 for forming the second electrode layer 105.

[0213] That is, the first electrode layer 102 and the first source-drain electrode layer 103 are prepared by adopting a one-time preparation process, which can reduce the number of masks, simplify the preparation process, and reduce the cost compared with adopting two preparation processes.

[0214] In summary, an embodiment of the present application provides a method for preparing an array substrate, which includes a base substrate, and a first electrode layer, a first source-drain layer, and a second source-drain layer stacked in sequence. The first source-drain layer includes a first signal line, and a first pattern connected to a pixel electrode in the first electrode layer, and the second source-drain layer includes a second pattern connected to the first signal line, and a third pattern connected to the first pattern. Since the first interval between the first signal line and the first pattern is greater than the second interval between the second pattern and the third pattern, the second pattern can be set to climb at the edge of the first signal line, and the third pattern can be set to climb at the edge of the first pattern. Since the second pattern and the third pattern have good climbing ability, even if the break difference of the climbing position is large, it will not cause too much impact on the performance of the second pattern and the third pattern, and the second pattern and the third pattern can be prevented from breaking, thereby ensuring the yield of the product.

[0215] Fig.34 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Fig.34 It can be seen that the display panel 01 includes: a color filter substrate 20, a liquid crystal layer 30, and an array substrate 10 as provided in the above embodiment.

[0216] The array substrate 10 and the color filter substrate 20 are arranged in a box, and the liquid crystal layer is located between the array substrate 10 and the color filter substrate 20 .

[0217] Optionally, the display panel 01 may be a liquid crystal display (LCD) display panel.

[0218] Since the display panel can have substantially the same technical effects as the array substrate described in the previous embodiment, the technical effects of the display panel will not be repeatedly described here for the purpose of brevity.

[0219] Fig.35 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.35 It can be seen that the display device includes: a power supply component 02 and a display panel 01 as provided in the above embodiment. The power supply component 02 can be used to supply power to the display panel 01 .

[0220] Optionally, the display device may be a liquid crystal display (LCD) display device, which may be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, e-books, and any other products or components with display functions.

[0221] Since the display device can have substantially the same technical effects as the array substrate described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.

[0222] The terms used in the embodiments of this application are only used to explain the embodiments of this application, and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should be the common meanings understood by people with general skills in the field to which this application belongs.

[0223] The terms used in the implementation mode of the present application are only used to explain the embodiments of the present application, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the implementation mode of the present application should be the common meanings understood by people with ordinary skills in the field to which the present application belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limit, but indicate that there is at least one. Words such as "include" or "include" and similar words mean that the elements or objects appearing in front of "include" or "include" include the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0224] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. An array substrate (10), characterized in that: The array substrate (10) comprises: A substrate base plate (101); A first electrode layer (102), the first electrode layer (102) being located on one side of the base substrate (101), the first electrode layer (102) comprising a plurality of pixel electrodes (1021) arranged in an array; a first source-drain electrode layer (103), the first source-drain electrode layer (103) being located on a side of the first electrode layer (102) away from the base substrate (101), the first source-drain electrode layer (103) comprising a plurality of first signal lines (1031) arranged along a first direction (X) and extending along a second direction (Y), and a plurality of first patterns (1032), each of the first patterns (1032) being connected to one of the pixel electrodes (1021); and a second source-drain electrode layer (104), the second source-drain electrode layer (104) being located on a side of the first source-drain electrode layer (103) away from the base substrate (101), the second source-drain electrode layer (104) comprising a plurality of second patterns (1041) and a plurality of third patterns (1042) corresponding to the plurality of second patterns (1041), each of the second patterns (1041) being connected to one of the first signal lines (1031), and each of the third patterns (1042) being connected to one of the first patterns (1032); There is a first interval (d1) between the first signal line (1031) and the corresponding first pattern (1032), there is a second interval (d2) between the second pattern (1041) and the corresponding third pattern (1042), and the first interval (d1) is greater than the second interval (d2).

2. The array substrate (10) according to claim 1, characterized in that: The array substrate (10) comprises a plurality of drive circuits, the plurality of drive circuits constitute a plurality of groups of drive circuits arranged along the first direction (X), each group of drive circuits comprises a plurality of drive circuits arranged along the second direction (Y), each of the first signal lines (1031) is connected to a group of drive circuits, and each of the drive circuits in each group of drive circuits is connected to a pixel electrode via a first pattern; The first electrode layer (102) further comprises a plurality of second signal lines (1022) corresponding to the plurality of first signal lines (1031), and the plurality of second signal lines (1022) are arranged along the first direction (X) and extend along the second direction (Y); The first signal line (1031) comprises a first edge (m1) and a second edge (m2) extending along the second direction (Y) and arranged opposite to each other, the first edge (m1) being closer to a target first pattern than the second edge (m2), the target first pattern being a first pattern connected to any one of a group of drive circuits connected to the first signal line (1031); the second signal line (1022) comprises a third edge (m3) and a fourth edge (m4) extending along the second direction (Y) and arranged opposite to each other, the third edge (m3) being closer to a target pixel electrode than the fourth edge (m4), the target pixel electrode being a pixel electrode connected to any one of a group of drive circuits connected to the first signal line (1031) corresponding to the second signal line (1022); The orthographic projection of the first edge (m1) on the base substrate (101) and the orthographic projection of the third edge (m3) on the base substrate (101) do not overlap, and the orthographic projection of the second edge (m2) on the base substrate (101) and the orthographic projection of the fourth edge (m4) on the base substrate (101) do not overlap.

3. The array substrate (10) according to claim 2, characterized in that: The orthographic projection of the first edge (m1) on the base substrate (101) and the orthographic projection of the second edge (m2) on the base substrate (101) are both located between the orthographic projection of the third edge (m3) on the base substrate (101) and the orthographic projection of the fourth edge (m4) on the base substrate (101); or, The orthographic projection of the first edge (m1) on the substrate (101) is closer to the orthographic projection of the second pattern (1041) on the substrate (101) than the orthographic projection of the third edge (m3) on the substrate (101), and the orthographic projection of the second edge (m2) on the substrate (101) is between the orthographic projection of the third edge (m3) on the substrate (101) and the orthographic projection of the fourth edge (m4) on the substrate (101).

4. The array substrate (10) according to claim 1, characterized in that: The array substrate (10) comprises a plurality of drive circuits, the plurality of drive circuits constitute a plurality of groups of drive circuits arranged along the first direction (X), each group of drive circuits comprises a plurality of drive circuits arranged along the second direction (Y), each of the first signal lines (1031) is connected to a group of drive circuits, and each of the drive circuits in each group of drive circuits is connected to a pixel electrode via a first pattern; The pixel electrode (1021) comprises: a connecting portion (10211) and a main region portion (10212); the array substrate (10) further comprises a second electrode layer (105), and the second electrode layer (105) comprises a common electrode (1051); the connecting portion (10211) is connected to the first pattern (1032), and an orthographic projection of the main region portion (10212) on the base substrate (101) and an orthographic projection of the common electrode (1051) on the base substrate (101) at least partially overlap; The first pattern (1032) includes a fifth edge (m5) extending along the second direction (Y), and a sixth edge (m6) arranged opposite to the fifth edge (m5), the fifth edge (m5) is closer to a target first signal line than the sixth edge (m6), and the target first signal line and the first pattern are connected to the same driving circuit; the connecting portion (10211) includes a seventh edge (m7) extending along the second direction (Y), and an eighth edge (m8) arranged opposite to the seventh edge (m7), the seventh edge (m7) is closer to a target second signal line than the eighth edge (m8), and a first signal line corresponding to the target second signal line and the connecting portion are connected to the same driving circuit; The orthographic projection of the fifth edge (m5) on the base substrate (101) and the orthographic projection of the seventh edge (m7) on the base substrate (101) do not overlap, and the orthographic projection of the sixth edge (m6) on the base substrate (101) and the orthographic projection of the eighth edge (m8) on the base substrate (101) do not overlap.

5. The array substrate (10) according to claim 4, characterized in that: The orthographic projection of the fifth edge (m5) on the base substrate (101) and the orthographic projection of the sixth edge (m6) on the base substrate (101) are both located between the orthographic projection of the seventh edge (m7) on the base substrate (101) and the orthographic projection of the eighth edge (m8) on the base substrate (101); or, The orthographic projection of the fifth edge (m5) on the substrate (101) is closer to the orthographic projection of the first signal line (1031) on the substrate (101) than the orthographic projection of the seventh edge (m7) on the substrate (101), and the orthographic projection of the sixth edge (m6) on the substrate (101) is between the orthographic projection of the seventh edge (m7) on the substrate (101) and the orthographic projection of the eighth edge (m8) on the substrate (101).

6. The array substrate (10) according to any one of claims 1 to 5, characterized in that: The array substrate (10) further comprises: a semiconductor layer (106) located on a side of the second source-drain electrode layer (104) away from the base substrate (101); The length of the orthographic projection of the target portion of the semiconductor layer (106) on the substrate (101) along the first direction (X) is smaller than the first interval (d1) and larger than the second interval (d2).

7. The array substrate (10) according to claim 6, characterized in that: The array substrate (10) further comprises: a first insulating layer (107) and a gate layer (108) which are located on a side of the semiconductor layer (106) away from the base substrate (101) and are stacked; The orthographic projection of the first insulating layer (107) on the base substrate (101) and the orthographic projection of the gate layer (108) on the base substrate (101) both overlap with the orthographic projection of the semiconductor layer (106) on the base substrate (101).

8. The array substrate (10) according to claim 7, characterized in that: The array substrate (10) further comprises: a light shielding layer (109) and a second insulating layer (110) which are located between the first electrode layer (102) and the base substrate (101) and are stacked; The light shielding layer (109) comprises a plurality of light shielding portions (1091), and a plurality of third signal lines (1092) arranged along the second direction (Y) and extending along the first direction (X); The orthographic projection of the light shielding portion (1091) on the base substrate (101) covers the orthographic projection of the channel portion on the base substrate (101), and the channel portion is the portion where the semiconductor layer (106) and the gate layer (108) overlap and does not overlap with the second source and drain layer (104); The third signal line (1092) is connected to the gate layer (108) and is used to provide a gate signal to the gate layer (108).

9. The array substrate (10) according to claim 8, characterized in that: The array substrate (10) further comprises: a third insulating layer (111) located on a side of the gate layer (108) away from the base substrate (101); the second electrode layer (105) included in the array substrate (10) is located on a side of the third insulating layer (111) away from the base substrate (101); the second electrode layer (105) further comprises: a transition portion (1052); One end of the transition portion (1052) is connected to the third signal line (1092) through a first via hole (k1) in the third insulating layer (111) and the second insulating layer (110), and the other end of the transition portion (1052) is connected to the gate layer (108) through a second via hole (k2) in the third insulating layer (111).

10. The array substrate (10) according to any one of claims 1 to 9, characterized in that: The thickness of the first source-drain electrode layer (103) is greater than the thickness of the second source-drain electrode layer (104).

11. A method for preparing an array substrate, characterized in that: The method comprises: Providing a substrate (101); A first electrode layer (102), a first source-drain electrode layer (103) and a second source-drain electrode layer (104) are sequentially formed on one side of the base substrate (101); The first electrode layer (102) comprises a plurality of pixel electrodes (1021) arranged in an array; the first source-drain electrode layer (103) is located on a side of the first electrode layer (102) away from the base substrate (101); the first source-drain electrode layer (103) comprises a plurality of first signal lines (1031) arranged along a first direction (X) and extending along a second direction (Y), and a plurality of first patterns (1032), each of the first patterns (1032) and one of the pixel electrodes (1021) The second source-drain electrode layer (104) is located on a side of the first source-drain electrode layer (103) away from the substrate (101), the second source-drain electrode layer (104) comprises a plurality of second patterns (1041), and a plurality of third patterns (1042) corresponding to the plurality of second patterns (1041), each of the second patterns (1041) is connected to one of the first signal lines (1031), and each of the third patterns (1042) is connected to one of the first patterns (1032); There is a first interval (d1) between the first signal line (1031) pattern and the corresponding first pattern (1032), and there is a second interval (d2) between the second pattern (1041) and the corresponding third pattern (1042), and the first interval (d1) is greater than the second interval (d2).

12. The method according to claim 11, characterized in that The first electrode layer (102) and the first source-drain layer (103) are formed, comprising: Sequentially forming a first electrode film and a first source-drain film on one side of the base substrate (101); A first optical adhesive layer is formed on a side of the first source-drain film away from the base substrate (101) using a half-tone mask, the optical adhesive layer comprising a first portion (n1) and a second portion (n2), the thickness of the first portion (n1) being less than the thickness of the second portion (n2), the area where the first portion (n1) is located is used to form a first electrode layer (102), and the area where the second portion (n2) is located is used to form a first source-drain electrode layer (103); Etching the first electrode film and the first source-drain film based on the optical adhesive layer to obtain a first electrode layer (102) and a second source-drain film; Performing an ashing process on the optical adhesive layer to remove the first portion (n1); The second source-drain film is etched based on the second part (n2) of the optical adhesive layer to obtain a first source-drain electrode layer (103).

13. The method according to claim 11, characterized in that The first electrode layer (102) and the first source-drain layer (103) are formed, comprising: Forming a first electrode film on one side of the base substrate (101); Performing patterning on the first electrode film to obtain a first electrode layer (102); forming a first source-drain thin film on a side of the first electrode layer (102) away from the base substrate (101); The first source-drain film is patterned to obtain a first source-drain electrode layer (103).

14. A display panel, characterized in that: The display panel (01) comprises: a color film substrate (20), a liquid crystal layer (30), and an array substrate (10) according to any one of claims 1 to 10; The array substrate (10) and the color film substrate (20) are arranged in a box, and the liquid crystal layer (30) is located between the array substrate (10) and the color film substrate (20).

15. A display device, characterized in that: The display device comprises: a power supply component (02) and a display panel (01) as claimed in claim 14; Wherein, the power supply component (02) is used to supply power to the display panel (01).

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