Electrostatic discharge protection device and method

Abstract

The invention describes a semiconductor device comprising an electrostatic discharge (ESD) protection device, the ESD protection device comprising a first PNP cell, the first PNP cell comprising: a substrate comprising an n-doped buried layer (NBL) extending laterally at a surface of the substrate, wherein the NBL includes a first NBL portion, a second NBL portion, and a third NBL portion disposed laterally at the surface of the substrate, where the second NBL portion is positioned between the first NBL portion and the third NBL portion, wherein the second NBL portion has a second n-doping level less than the first n-doping level of the first NBL portion and less than a third n-doping level of the third NBL portion; an epitaxial layer disposed on the surface of the substrate and comprising a PNP device, the PNP device comprising: a first p-doped region; a second p-doped region; and an n-doped region positioned between the first p-doped region and the second p-doped region, where the first p-doped region is aligned with the second NBL portion.

Description

Technical Field

[0001] The present disclosure relates to an electrostatic discharge (ESD) protection device and a method for manufacturing the same. Background Art

[0002] Integrated circuits fabricated on semiconductor devices may be damaged when receiving an electrostatic discharge (ESD) event from other circuits coupled to the semiconductor device or from people and / or machinery and tools contacting the semiconductor device. During an ESD event, the integrated circuit may receive an electrical charge that produces a relatively large voltage during a relatively short period of time. For example, if the integrated circuit collapses due to a high voltage and begins conducting the charge of the ESD event, a current of several amperes may flow through the integrated circuit during a relatively short period of time. These currents may cause irreparable damage to the integrated circuit. Summary of the invention

[0003] According to a first aspect of the present disclosure, a semiconductor device is provided, the semiconductor device comprising an electrostatic discharge (ESD) protection device, the ESD protection device comprising a first PNP unit, the first PNP unit comprising:

[0004] a substrate comprising an n-doped buried layer NBL extending laterally at a surface of the substrate, wherein the NBL comprises a first NBL portion, a second NBL portion, and a third NBL portion laterally arranged at the surface of the substrate, wherein the second NBL portion is positioned between the first NBL portion and the third NBL portion, wherein the second NBL portion has a second n-doping level that is less than a first n-doping level of the first NBL portion and less than a third n-doping level of the third NBL portion;

[0005] An epitaxial layer disposed on a surface of a substrate and comprising a PNP device, the PNP device comprising:

[0006] a first p-doped region;

[0007] a second p-doped region; and

[0008] an n-doped region located between the first p-doped region and the second p-doped region,

[0009] The first p-doped region is partially aligned with the second NBL.

[0010] Aligning the first p-doped region with the lower doped second NBL portion may advantageously increase the breakdown voltage of the ESD protection device relative to a similar device having a uniformly doped NBL having a second n-doping level without requiring additional die area or an increase in resistance.

[0011] In one or more embodiments, the first p-doped region is aligned with the second NBL portion in a vertical direction perpendicular to the surface of the substrate. In one or more embodiments, the first p-doped region is positioned above the second NBL portion. In one or more embodiments, the plane of the surface of the substrate defines a lateral plane. In one or more embodiments, a normal to the plane of the surface of the substrate defines a vertical direction.

[0012] In one or more embodiments, the first n-doping level of the NBL is equal to the third n-doping level of the NBL.

[0013] In one or more embodiments, a top surface of the first p-doped region includes an active opening for a first electrical contact, and the active opening of the first p-doped region is partially aligned with the second NBL.

[0014] In one or more embodiments, the active opening of the first p-doped region is vertically aligned with the second NBL portion. In one or more embodiments, the active opening of the first p-doped region is vertically positioned above the second NBL portion.

[0015] In one or more embodiments, the top surface of the first p-doped region includes:

[0016] an active opening for a first electrical contact;

[0017] a first shallow trench isolation (STI) region on a first side of the active opening; and

[0018] a second STI region on a second side of the active opening,

[0019] in:

[0020] At least a portion of the first STI region of the first p-doped region is partially aligned with the first NBL; and

[0021] At least a portion of the second STI region of the first p-doped region is partially aligned with the third NBL.

[0022] In one or more embodiments, at least a portion of the first STI region of the first p-doped region is vertically positioned above / aligned with the first NBL portion. In one or more embodiments, at least a portion of the second STI region of the first p-doped region is vertically positioned above / aligned with the third NBL portion.

[0023] In one or more embodiments, the lateral extent of the second NBL portion is within the lateral extent of the active opening.

[0024] In one or more embodiments, a distance from a first lateral edge of the first p-doped region to a corresponding first lateral edge of the active opening is greater than a distance from the first lateral edge of the first p-doped region to a corresponding first lateral edge of the second NBL portion. In one or more embodiments, a distance from a second lateral edge of the first p-doped region to a corresponding second lateral edge of the active opening is greater than a distance from the second lateral edge of the first p-doped region to a corresponding second lateral edge of the second NBL portion.

[0025] In one or more embodiments, the epitaxial layer includes a p-doped epitaxial layer having a body doping level, and the first p-doped region, the second p-doped region, and the n-doped region are arranged in the p-doped epitaxial layer. In one or more embodiments, the first p-doped region is a high voltage p-doped region having a first p-doping level higher than the body doping level, and the second p-doped region is a high voltage p-doped region having a second p-doping level higher than the body doping level.

[0026] In one or more embodiments, the n-doped region includes a deep n-doped column extending from the top surface of the epitaxial layer to the NBL.

[0027] In one or more embodiments, the PNP device includes a PNP transistor, wherein the first p-doped region includes a collector of the PNP transistor, the second p-doped region includes an emitter of the PNP transistor, and the n-doped region includes a base of the PNP transistor.

[0028] In one or more embodiments, the second p-doped region is used to connect to the IO terminal. In one or more embodiments, the first p-doped region is used to connect to the negative terminal.

[0029] In one or more embodiments, the ESD protection device includes a second PNP cell arranged in parallel with the first PNP cell to form a first PNP cell pair, wherein the second PNP cell includes the same structure as the first PNP cell.

[0030] In one or more embodiments, the ESD protection device includes a second PNP cell pair stacked in series with the first PNP cell pair, wherein the second PNP cell pair includes a third PNP cell and a fourth PNP cell arranged in parallel with the third PNP cell.

[0031] In one or more embodiments, the third PNP cell and the fourth PNP cell each include:

[0032] a further substrate comprising a further n-doped buried layer NBL extending laterally at the surface of the substrate, wherein the further NBL comprises a first n-doping level; and

[0033] another epitaxial layer disposed on the surface of the another substrate and comprising another PNP device, the another PNP device comprising:

[0034] another first p-doped region;

[0035] another second p-doped region; and

[0036] Another n-doped region is positioned between the another first p-doped region and the another second p-doped region.

[0037] In one or more embodiments, the third PNP cell and the fourth PNP cell include the same structure as the first PNP cell.

[0038] According to a second aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device including an electrostatic discharge (ESD) protection device, the method comprising:

[0039] fabricating an n-doped buried layer NBL in the substrate, the NBL extending laterally at a surface of the substrate, wherein the NBL comprises a first NBL portion, a second NBL portion and a third NBL portion laterally arranged at the surface of the substrate, wherein the second NBL portion is positioned between the first NBL portion and the third NBL portion, wherein the second NBL portion has a second n-doping level that is less than a first n-doping level of the first NBL portion and less than a third n-doping level of the third NBL portion; and

[0040] An epitaxial layer is provided on a surface of a substrate, the epitaxial layer comprising a PNP device, the PNP device comprising:

[0041] a first p-doped region;

[0042] a second p-doped region; and

[0043] an n-doped region located between the first p-doped region and the second p-doped region,

[0044] Wherein providing the epitaxial layer includes aligning the first p-doped region with the second NBL portion.

[0045] In one or more embodiments, manufacturing the NBL includes:

[0046] implanting an n-doped material in the substrate to provide an NBL having a second n-doping level;

[0047] masking a portion of the surface of the substrate to mask the second NBL portion and expose the first and third NBL portions; and

[0048] An n-dopant material is implanted in the first and third NBL portions to provide the first and third NBL portions with a first doping level.

[0049] In one or more embodiments, providing the epitaxial layer may include providing an active opening for the first electrical contact in a top surface of the first p-doped region, and aligning the active opening with the second NBL portion.

[0050] Aligning the active opening with the second NBL portion may include aligning the active opening with the second NBL portion such that a lateral extent of the second NBL portion is within a lateral extent of the active opening.

[0051] Although the present disclosure allows various modifications and alternative forms, the details have been shown in the drawings by way of example and will be described in detail. However, it should be understood that other embodiments beyond the specific embodiments described are also possible. All modifications, equivalents and alternative embodiments falling within the spirit and scope of the appended claims are also encompassed.

[0052] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim sets. The drawings and the following detailed description also illustrate various example embodiments. Various example embodiments may be more fully understood by considering the following detailed description in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0054] Figure 1 A simplified example ESD protection device is shown;

[0055] Figure 2 An example ESD protection device for a battery management system is shown;

[0056] Figure 3 An example ESD protection device having a breakdown voltage of 100V is shown;

[0057] Figure 4 An example ESD protection device according to an embodiment of the present disclosure is shown;

[0058] Figure 5 An example ESD protection device for a battery management system according to an embodiment of the present disclosure is shown;

[0059] Fig. 6A shows the Transmission Line Pulse (TLP) measurements for three candidate 100V ESD protection devices;

[0060] Figure 6B showing the variation of breakdown voltage based on spacing parameters; and

[0061] Figure 7 A method of manufacturing an ESD protection device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0062] The semiconductor circuit may include integrated ESD protection to protect the integrated circuit from ESD events. The ESD protection device may include a PNP structure arranged in an epitaxial layer above an n-buried layer (NBL). The ESD protection device may provide protection against ESD events up to a breakdown voltage (BV).

[0063] Figure 1 A simplified example ESD protection device 100 is shown that includes a PNP structure disposed above a NBL.

[0064] The ESD protection device 100 includes a substrate 102. The substrate 102 may include a p-doped substrate and lightly doped with a p-type material. An n-buried layer (NBL) 104 is fabricated in the substrate 102, for example, by masking and ion implantation. The NBL 104 includes a relatively large amount of n-type material. The NBL 104 forms a layer within the substrate 102 that extends laterally at the surface of the substrate 102 and vertically from the surface of the substrate 102 to the depth of the NBL. The substrate 102 may include a buried oxide layer underlying the NBL 104.

[0065] The ESD protection device 100 further includes an epitaxial layer 106 fabricated on the surface of the substrate 102. The epitaxial layer 106 includes a PNP structure including: a first p-doped region 108; a second p-doped region 110; and an n-doped region 112 positioned between the first p-doped region 108 and the second p-doped region 110. The first and second p-doped regions 108, 110 are high voltage p-doped regions (labeled PHV). The n-doped region 112 is a deep n-doped region (labeled DPN) and extends from the top surface of the epitaxial layer 106 through the epitaxial layer 106 to the NBL 104.

[0066] The substrate 102 and the epitaxial layer 106 together form a semiconductor substrate 114 on which an integrated circuit may be defined. The first p-doped region 108 includes a contact region for providing a first end of a first contact 116 (labeled NEG) for the integrated circuit. The first end is configured to be connected to a negative voltage or ground. The second p-doped region 110 includes a contact region for providing a second end of a second contact 118 (labeled IO) for the integrated circuit. The second end is configured to be electrically coupled to a structure of the IC that is sensitive to ESD events, such as an I / O pad of a semiconductor device.

[0067] The n-doped region 112 is positioned adjacent to (contacting) the second p-doped region 110 and laterally spaced apart from the first p-doped region 108. Providing spacing between the first p-doped region 108 and the n-doped region 112 increases the BV of the diode 120 formed between the two regions.

[0068] The first p-doped region 108 , the second p-doped region 110 and the n-doped region 112 form a PNP bipolar transistor 122 , wherein the first p-doped region 108 forms a collector, the second p-doped region forms an emitter and the n-doped region 112 forms a base.

[0069] In this example, a deep trench isolation (DTI) structure 123 separates the ESD protection device 100 from adjacent ESD protection devices on the same substrate 102 .

[0070] As an example operation of the ESD protection device, during a positive voltage ESD event at the second contact 118, the diode 120 is reverse biased. Once the voltage across the diode 120 exceeds the breakdown voltage of the diode, current flows from the second contact 118 through the second p-doped region 110, to the n-doped region 112 and to the first p-doped region 108. This current turns on the transistor 122, which can safely conduct the ESD event from the second contact 118 to the first contact 116 so that the ESD event does not flow through the integrated circuit and does not cause irreversible damage to the integrated circuit. The activation voltage of the ESD protection circuit 100 can be defined by the spacing between the first p-doped region 108 and the n-doped region 112, which defines the BV of the diode 120.

[0071] The breakdown voltage of transistor 122 between base and collector defines the maximum voltage or breakdown voltage of ESD protection circuit 100. This breakdown voltage is set by the vertical structure below first contact 116, i.e., the vertical structure from first p-doped region 108 to NBL 104. This PHV / NBL structure defines the breakdown voltage of transistor 122.

[0072] Figure 1 A simplified example of an ESD protection device is shown. Some applications have high BV requirements for integrated ESD protection devices. In some examples, the ESD protection device may include multiple PNP structures to provide a higher breakdown voltage. There are a variety of known ways to arrange one or more PNP structures, including coupling to an NPN structure and / or a silicon controlled rectifier (SCR). Figure 2 An example ESD protection device is shown that includes a plurality of HV-PNP cells, each HV-PNP cell including a plurality of PNP structures in the epitaxial layer 206 . Figure 1 Existing in Figure 2 Features have been given corresponding reference numerals in the 200 series and will not need to be described again here.

[0073] In this example, the ESD protection device 200 includes four HV-PNP cells 201 , wherein two parallel HV-PNP cells 201 are stacked in series with another two parallel HV-PNP cells 201 .

[0074] In this example, the epitaxial layer 206 of each HV-PNP cell 201 includes: three isolated first p-doped regions 208-1, 208-2, 208-3 (labeled as PHV) coupled to negative first contacts 216-1, 216-2, 216-3 (labeled as NEG); two second p-doped regions 216-1, 216-2 (labeled as PHV+PW (p-well)) coupled to IO second contacts 218-1, 218-2 (labeled as IO); and an n-doped region 212 including a DPN on either side of and contacting the second p-doped regions 210-1, 210-2. The PNP arrangement of each HV-PNP cell forms: two internal diodes 222-1, 222-2 (between the central first p-doped region 208-1 and the n-doped region 212 contacting the adjacent second p-doped regions 210-1, 210-2); two internal PNP transistors 222-1, 222-2 with floating bases DPN (between the central first p-doped region 208-1, the two adjacent second p-doped regions 210-1, 210-2, the intervening n-doped regions 212 and the NBL 204); and two internal PNP transistors 224-1, 224-2 with contacted bases DPN (between the second p-doped regions 210-1, 210-2, the NBL 204 and the n-doped regions 212 on the outer sides of the second p-doped regions 210-1, 210-2), as shown. Each HV-PNP cell 201 has a simplified representation in the circuit diagram as a PNP transistor having a diode coupling the collector and the base.

[0075] The ESD protection device 200 including four HV-PNP cells 201 can provide an ESD breakdown voltage of ˜95V and can be used in an automotive battery management system (BMS). However, new application requirements for BMS may require >100V protection and the clamping voltage should start at about 110V.

[0076] Used to increase Figure 2 One option to improve the breakdown voltage of the ESD protection circuit 200A is to reduce the doping of the NBL 204. However, reducing the doping may result in an undesirable increase in resistance, making this solution inefficient.

[0077] Figure 3 Another option of an ESD protection device 300 with an increased breakdown voltage is shown. In this example, another low voltage (eg, 5.5V) PNP structure 326 is coupled to Figure 2 The four HV-PNP cells are arranged in series stack. The disadvantage of this method is that the effective area of ​​the ESD protection device 300 is relatively Figure 2 The number of devices increased by 18% to 200.

[0078] Figure 4 FIG. 4 shows a cross section of an ESD protection device 400 according to an embodiment of the present disclosure. Figure 1 The corresponding means increase the BV. Figure 4 exists in Figure 1 and 2 Features in have been given corresponding reference numerals in the 400 series and will not need to be described again here.

[0079] The ESD protection device 400 includes a substrate 402 including a NBL 404. The NBL 404 extends laterally at a surface 403 of the substrate 402. The NBL 404 includes a first NBL portion 404-1 (labeled as NBL), a second NBL portion 404-2 (labeled as LNBL (light NBL)), and a third NBL portion 404-3 (labeled as NBL) laterally arranged at the surface 403 of the substrate 402, wherein the second NBL portion 404-2 is positioned between the first NBL portion 404-1 and the third NBL portion 404-3. The second NBL portion 404-2 has a second n-doping level that is less than both: (i) a first n-doping level of the first NBL portion 404-1; and (ii) a third n-doping level of the third NBL portion 404-3. The first n-doping level and the third n-doping level may be the same.

[0080] The ESD protection device 400 further includes an epitaxial layer 406 including a PNP device disposed on the surface 403 of the substrate. The PNP device (or PNP structure) includes: a first doped p-region 408; a second doped p-region 410; and an n-doped region 412 positioned between the first and second p-doped regions 408, 410. The first p-doped region 408 is positioned above (i.e., vertically aligned with) the second NBL portion 404-2.

[0081] As described herein, the terms lateral, laterally extending, etc. refer to a lateral plane, which is a plane parallel to the plane of the surface 403 of the substrate 402. As described herein, the term vertical and corresponding references to above or below correspond to a vertical direction / axis parallel to the normal to the surface 403 of the substrate 402.

[0082] By positioning the first p-doped region 408 (collector) vertically in line with the lower doped second NBL portion 404-2, the ESD protection device 400 has a higher Figure 1 The general concept of providing a relatively lightly doped NBL portion 404-2 below the first p-doped region 408 can be extended to any PNP structured ESD protection device, such as Figure 2In this way, the embodiment can provide a HV-PNP cell that meets the new 100V BMS requirements (see Figure 5 ) ESD protection device without increasing the die area or increasing the device resistance.

[0083] NBL 404 may be formed by masking and implantation. Implantation may be performed in two steps, with a first step providing doping of the second n-doping level for all NBL 404. In a second step, the second NBL portion may be masked during further implantation to increase the doping level in the first and third NBL portions. A buried oxide layer (not shown) may be formed underlying NBL 404.

[0084] The first and second p-doped regions 408 , 410 are high voltage p-doped regions (labeled PHV). The n-doped region 412 is a deep n-doped region (labeled DPN) and extends from the top surface of the epitaxial layer 406 through the epitaxial layer 406 to the NBL 404 .

[0085] The substrate 402 and the epitaxial layer 406 together form a semiconductor substrate 414 on which an integrated circuit may be defined. The epitaxial layer 406 may include a p-doped epitaxial layer including a bulk doping level. The p-doped epitaxial layer 406 may be formed on the substrate 402, and the first and second p-doped regions 408, 410 and the n-doped region 412 are then formed in the p-doped epitaxial layer 406 by sequential implantation and masking.

[0086] The first p-doped region 408 includes a contact area for providing a first end of a first contact 416 (labeled NEG) for an integrated circuit. The first end is configured to be connected to a negative voltage or ground. The second p-doped region 410 includes a contact area for providing a second end of a second contact 418 (labeled IO) for an integrated circuit. The second end is configured to be configured to be electrically coupled to a structure of an IC that is sensitive to ESD events, such as an I / O pad of a semiconductor device.

[0087] The n-doped region 412 is positioned adjacent to the second p-doped region 410 and laterally spaced apart from the first p-doped region 408. Providing a spacing between the first p-doped region 408 and the n-doped region 412 increases the BV of the diode 420 formed between the two regions.

[0088] The first p-doped region 408 , the second p-doped region 410 , and the n-doped region 412 form a PNP bipolar transistor 422 , wherein the first p-doped region 408 forms a collector, the second p-doped region 410 forms an emitter, and the n-doped region 412 forms a base.

[0089] The top surface of the first p-doped region 408 includes an active opening 428 to enable coupling of the first p-doped region 408 to the first contact 416. The active opening 428 of the first p-doped region 408 can be positioned above the second NBL portion 404-2. In some examples, the lateral extent of the second NBL portion 404-2 can be within the lateral extent of the active opening 428 (vertically aligned within the lateral extent of the active opening 428).

[0090] The top surface of the first p-doped region 408 may include shallow trench isolation (STI) regions 430 on either side of the active opening 428. The STI regions 430 may have an overlying oxide. At least a portion of the STI regions 430 may be positioned over at least a portion of the first NBL portion 404-1, and at least a portion of the STI regions 430 may be positioned over at least a portion of the third NBL portion 404-3.

[0091] The oxide overlying the STI region 430 results in a shallower implantation in the portion of the first p-doped region 408 below the STI region 430 relative to the portion of the first p-doped region 408 below the active opening 428. In other words, the first p-doped region 408 is deepest and becomes closest to the NBL 404 below the active opening 428. Therefore, positioning the active opening 428 above the lower doped second NBL portion 402-2 advantageously optimizes the position of the second NBL portion 404-2 to increase the BV of the ESD device 400. Limiting the lateral extent of the second NBL portion 404-2 to only within the lateral extent of the active opening 428 limits the size of the second NBL portion 404-2 and the resulting increase in the resistance of the device 400.

[0092] One or more spacing parameters may be used to define the lateral extent of the second NBL portion 404-2 relative to the lateral extent of the active opening 428. A first parameter a may define a distance from a lateral edge of the first p-doped region 408 to a lateral edge of the active opening 428. In other words, the first parameter a defines a portion of the first p-doped region 408 below the STI 430. A second parameter b may define a lateral extent (or width) of the active opening 428. A third parameter c may define a distance from a lateral edge of the first p-doped region 408 to a lateral edge of the second NBL portion 402-2. In some examples, the third parameter c may be greater than the first parameter a. In other words: (i) the distance from the first lateral edge of the first p-doped region 408 to the corresponding (same side) first lateral edge of the active opening 428 is greater than the distance from the first lateral edge of the first p-doped region 408 to the corresponding first lateral edge (same side) of the second NBL portion 404-2; and (ii) the distance from the second lateral edge of the first p-doped region 408 to the corresponding second lateral edge (same side) of the active opening 428 is greater than the distance from the second lateral edge of the first p-doped region 408 to the corresponding second lateral edge of the second NBL portion 404-2. In other words, the lateral extent of the second NBL portion 404-2 is less than the second parameter b and is within the lateral extent of the active opening 428.

[0093] As described above, the general concept of providing a lower doped NBL portion 404 - 2 below the first p-doped region 408 can be extended to any PNP structured ESD protection device. Figure 5 An example ESD protection device 500 including a plurality of HV-PNP cells 201, 501 according to an embodiment of the present disclosure is shown. The ESD protection device 500 may advantageously meet 100V automotive BMS application requirements.

[0094] In this example, the ESD protection device 500 includes two NBL HV-PNP cells 201 arranged in parallel, each cell 201 having Figure 2 The structure is the same as the uniformly doped NBL structure. Figure 2 500. The ESD protection device 500 further includes two NBL / LNBL HV-PNP cells 501, wherein the NBL 504 has different portions 504-1, 504-2 with different doping. The two NBL HV-PNP cells 201 are stacked in series with the two NBL / LNBL HV-PNP cells 501 to provide an ESD protection circuit 500 that meets the 100V requirement. Other example ESD protection devices may include four NBL / LNBL HV-PNP cells 501 to provide a still higher BV, even at a higher resistance.

[0095] In this example, the NBL / LNBL HV-PNP cell 501 is the same as the NBL HV-PNP cell 201 except that the NBL 504 of the NBL / LNBL HV-PNP cell 501 includes a first NBL portion 504-1 having a first n-doping level and a second NBL portion 504-2 having a second n-doping level, wherein the second n-doping level is less than the first n-doping level. The epitaxial layer 506 includes three first p-doped regions 508-1, 508-2, 508-3, each of which is arranged above a corresponding second NBL portion 504-2. Specifically, the active opening of each first p-doped region 508-1, 508-2, 508-3 is arranged above the corresponding second NBL portion 504-2. The lateral extent of the second NBL portion 504-2 is within the lateral extent of the corresponding active opening of the first p-doped region 508. Both second p-doped regions 510-1, 510-2 are arranged above the respective first NBL portion 504-1. An n-doped region 512 is also arranged above the first NBL portion 504-1.

[0096] Fig. 6A 63 shows transmission line pulse (TLP) measurements for three ESD protection devices. TLP measurements allow evaluation of device performance in the absence of destructive thermal effects that would otherwise occur under DC current. The first curve 632 shows a NBL based on uniform doping. Figure 2 The current-voltage (IV) performance of the first 95V ESD protection device of the four HV-PNP cell structures of FIG. 63 is shown in FIG. 64. The NBL has high doping to reduce BV, but this results in low resistance, as can be seen by the steeper slope of the first curve 632. Due to the higher doping, the breakdown voltage is limited to 95V. The second curve 634 shows the current-voltage (IV) performance of the first 95V ESD protection device based on the four HV-PNP cell structures of FIG. 63. Figure 3 The IV performance of the second 100V ESD protection device of the structure is similar to the first curve 632, but requires a significantly increased area. The third curve 636 shows Figure 5 IV performance of the 100V ESD protection device. The resistance is only slightly higher than the other two devices and is acceptable for IC protection applications. Crucially, the BV increases to 100V without modifying the size and relative to Figure 2 The first ESD protection does not significantly increase resistance.

[0097] Figure 6B The variation of the breakdown voltage based on the third spacing parameter c defined above is shown. The first curve 638 shows the variation of BV (measured in V) against the value of the third spacing parameter c (in micrometers) for a value of the first spacing parameter a equal to 1 um. The first curve shows the general trend: higher BV is obtained when the third spacing parameter c is less than the first spacing parameter a.

[0098] The second curve 640 shows the change in BV (measured in V) versus the value of the third spacing parameter c (in microns) for a value of the first spacing parameter a equal to 2 um. The second curve 640 includes a plateau in which the BV remains substantially constant as the third parameter spacing varies between 0.5-1.5 um. This plateau can advantageously provide a fixed BV while allowing for errors in the alignment of the blanket mask when defining the NBL portion or the first p-doped region. In some examples, the first parameter spacing a can be 2 um and the third parameter spacing can be 1 um to recognize a mask alignment error tolerance of + / - 0.44 um.

[0099] Figure 7 A method for manufacturing an ESD protection device according to an embodiment of the present disclosure is shown. The drawings include schematic diagrams of the structure after different manufacturing steps.

[0100] The first step 742 includes providing a substrate 702. The substrate may include a p-doped substrate, and may include a silicon-on-insulator substrate.

[0101] The second step 744 includes implanting an n-doped material to form an NBL 704 at the surface of the substrate 702. The NBL extends laterally across the surface of the substrate 702. After implantation, the NBL includes a second n-doping level.

[0102] A third step 746 includes masking the surface of the substrate using photolithography.A mask 760 (eg, photoresist) masks the second NBL portion 704-2 and exposes the first and third NBL portions 704-1, 704-3.

[0103] A fourth step 748 includes implanting additional n-doped material to increase the n-doping level in the first and third NBL portions 704-1, 704-3. The resulting NBL includes: a first NBL portion 704-1 having a first n-doping level; a second NBL portion 704-2 having a second n-doping level less than the first n-doping level; and a third NBL portion 704-3 having the first n-doping level.

[0104] After removing the mask, a fifth step 750 includes forming an epitaxial layer 706 on the surface of the substrate 702, for example by known material deposition techniques. The epitaxial layer may include a p-doped epitaxial layer having a bulk doping level.

[0105] A sixth step 752 includes defining a PNP structure in the epitaxial layer 706. The PNP structure includes a first p-doped region 708, a second p-doped region 710, and an n-doped region 712. The first p-doped region 708 is aligned with the second NBL portion 704-2. The first and second p-doped regions may be formed by masking and implanting p-doped materials. The n-doped region may be formed by masking and implanting n-doped materials. Other steps may include defining STI and DTI features, contacts, and insulators.

[0106] Throughout this specification, descriptors related to relative orientation and position, such as "horizontal", "vertical", "top", "bottom", "lateral", "upright", "above", "below", "lateral edge", and "side", are used in the sense of the orientation of the ESD protection device as presented in the drawings. However, such descriptors are not intended to limit in any way the intended use of the invention described or claimed.

[0107] Unless a particular order is explicitly stated, the instructions and / or flow chart steps in the above figures may be executed in any order. Moreover, those skilled in the art will recognize that although an example instruction set / method has been discussed, the materials in this specification may be combined in a variety of ways to produce other examples, and should be understood within the context provided in this detailed description.

[0108] In some example embodiments, the instruction set / method steps described above are implemented as functions and software instructions embodied as an executable instruction set, which is implemented on a computer or a machine programmed and controlled with the executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor may refer to a single component or multiple components.

[0109] In other examples, the instruction sets / methods shown herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer readable or computer usable storage media. Such computer readable or computer usable storage media are considered to be part of an article (or product). An article or product may refer to any manufactured single component or multiple components. A non-transitory machine or computer usable medium as defined herein does not include signals, but such media may be able to receive and process information from signals and / or other transient media.

[0110] Example embodiments of the materials discussed in this specification may be implemented in whole or in part via a network, computer or data-based device and / or service. These may include the cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, an infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive definitions are provided.

[0111] In one example, one or more instructions or steps discussed herein are automated. The term automation or automatic (and similar variations thereof) means the use of computers and / or mechanical / electrical devices to control the operation of equipment, systems and / or processes without the need for human intervention, observation, effort and / or decision making.

[0112] It should be understood that any components that are said to be coupled may be coupled or connected directly or indirectly. In the case of indirect coupling, additional components may be located between the two components that are said to be coupled.

[0113] In this specification, example embodiments have been presented based on a selected set of details. However, one of ordinary skill in the art will appreciate that many other example embodiments including different selected sets of these details may be practiced. It is intended that the appended claims cover all possible example embodiments.

Claims

1. A semiconductor device including an electrostatic discharge (ESD) protection device, characterized in that: The ESD protection device comprises a first PNP unit, wherein the first PNP unit comprises: a substrate comprising an n-doped buried layer NBL extending laterally at a surface of the substrate, wherein the NBL comprises a first NBL portion, a second NBL portion, and a third NBL portion laterally arranged at the surface of the substrate, wherein the second NBL portion is positioned between the first NBL portion and the third NBL portion, wherein the second NBL portion has a second n-doping level that is less than a first n-doping level of the first NBL portion and less than a third n-doping level of the third NBL portion; an epitaxial layer disposed on the surface of the substrate and comprising a PNP device, the PNP device comprising: a first p-doped region; a second p-doped region; and an n-doped region located between the first p-doped region and the second p-doped region, Wherein the first p-doped region is partially aligned with the second NBL.

2. The semiconductor device according to claim 1, wherein: A top surface of the first p-doped region includes an active opening for a first electrical contact, and wherein the active opening of the first p-doped region is partially aligned with the second NBL.

3. The semiconductor device according to claim 1 or claim 2, characterized in that: The top surface of the first p-doped region comprises: an active opening for a first electrical contact; A first shallow trench isolation (STI) region on a first side of the active opening; and a second STI region on a second side of the active opening, in: At least a portion of the first STI region of the first p-doped region is partially aligned with the first NBL; and At least a portion of the second STI region of the first p-doped region is partially aligned with the third NBL.

4. The semiconductor device according to claim 2 or claim 3, characterized in that: The lateral extent of the second NBL portion is within the lateral extent of the active opening.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that: a distance from a first lateral edge of the first p-doped region to a corresponding first lateral edge of the active opening is greater than a distance from the first lateral edge of the first p-doped region to a corresponding first lateral edge of the second NBL portion; and A distance from a second lateral edge of the first p-doped region to a corresponding second lateral edge of the active opening is greater than a distance from the second lateral edge of the first p-doped region to a corresponding second lateral edge of the second NBL portion.

6. A semiconductor device according to any one of the preceding claims, characterized in that The epitaxial layer includes a p-doped epitaxial layer having a body doping level, and wherein the first p-doped region, the second p-doped region and the n-doped region are arranged in the p-doped epitaxial layer, wherein the first p-doped region is a high voltage p-doped region having a first p-doping level higher than the body doping level, and the second p-doped region is a high voltage p-doped region having a second p-doping level higher than the body doping level.

7. A semiconductor device according to any one of the preceding claims, characterized in that The n-doped region includes a deep n-doped column extending from the top surface of the epitaxial layer to the NBL.

8. A semiconductor device according to any one of the preceding claims, characterized in that The PNP device includes a PNP transistor, wherein the first p-doped region includes a collector of the PNP transistor, the second p-doped region includes an emitter of the PNP transistor, and the n-doped region includes a base of the PNP transistor.

9. A semiconductor device according to any one of the preceding claims, characterized in that: The second p-doped region is used to connect to the IO terminal; and The first p-doped region is used to be connected to a negative terminal.

10. A method for manufacturing a semiconductor device including an electrostatic discharge (ESD) protection device, characterized in that: The method comprises: manufacturing an n-doped buried layer NBL in a substrate, the NBL extending laterally at a surface of the substrate, wherein the NBL comprises a first NBL portion, a second NBL portion and a third NBL portion laterally arranged at the surface of the substrate, wherein the second NBL portion is positioned between the first NBL portion and the third NBL portion, wherein the second NBL portion has a second n-doping level that is less than a first n-doping level of the first NBL portion and less than a third n-doping level of the third NBL portion; and Providing an epitaxial layer on the surface of the substrate, the epitaxial layer comprising a PNP device, the PNP device comprising: a first p-doped region; a second p-doped region; and an n-doped region located between the first p-doped region and the second p-doped region, Wherein providing the epitaxial layer comprises aligning the first p-doped region with the second NBL portion.

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