Image sensor and method of manufacturing image sensor

Abstract

The embodiment of the invention provides an image sensor and a manufacturing method thereof. The image sensor includes a substrate and a gate electrode. The gate electrode is disposed proximate the first side of the substrate. The gate electrode includes a first gate portion, a second gate portion, and a third gate portion. The first gate portion is disposed over a first side of the substrate. The second gate portion is disposed within the substrate and connected to the first gate portion. The third gate portion is disposed under and connected to the second gate portion. A first width of the first gate portion is greater than a second width of the second gate portion, and a third width of the third gate portion is greater than the second width.

Description

Technical Field

[0001] Embodiments of the present application relate to image sensors and methods of manufacturing image sensors. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensors can be designed with buried photodiode regions to increase full well capacity. A more efficient mechanism to transfer charge from the photodiode region is desired. Summary of the invention

[0003] Some embodiments of the present application provide an image sensor, comprising: a substrate; and a gate electrode, arranged near a first side of the substrate, comprising: a first gate portion, arranged on the first side of the substrate; a second gate portion, arranged in the substrate and connected to the first gate portion; and a third gate portion, arranged under the second gate portion and connected to the second gate portion, wherein a first width of the first gate portion is greater than a second width of the second gate portion, and a third width of the third gate portion is greater than the second width.

[0004] Other embodiments of the present application provide an image sensor, comprising: a substrate having a first side; and a gate electrode, comprising a gate portion, the gate portion being buried in the substrate, wherein the gate portion has a first surface and a second surface, the first surface and the second surface facing in opposite directions to each other and both being substantially parallel to the first side of the substrate, and wherein the first surface and the second surface of the gate portion are spaced apart from the first side of the substrate.

[0005] Still other embodiments of the present application provide a method for manufacturing an image sensor, comprising: forming a pixel area in a substrate; forming a sacrificial area between a first side of the substrate and the pixel area; removing a portion of the substrate between the first side and the sacrificial area to form a first hole having a first width; removing the sacrificial area to form a second hole connected to the first hole and having a second width greater than the first width; and forming a gate electrode having a first gate portion located on the first side, a second gate portion located in the first hole, and a third gate portion located in the second hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

[0007] Figure 1 A schematic diagram illustrating a cross-sectional view of an image sensor according to some embodiments.

[0008] Figure 1A Schematic diagram showing a top view of an image sensor according to some embodiments.

[0009] Figure 1B Shows Figure 1 Schematic diagram of an enlarged view of box B1 in FIG.

[0010] Figure 1B-1 A schematic diagram illustrating a three-dimensional view of a gate electrode according to some embodiments.

[0011] Figure 1C Shows Figure 1 Schematic diagram of another enlarged view of box B1 in FIG.

[0012] Figure 2A , Figure 2B , Figure 2C and Figure 2D Each shows a schematic diagram of a portion of an image sensor according to some embodiments.

[0013] Figure 3A , Figure 3B , Figure 3C and Figure 3D Each diagram shows a top view of an image sensor according to some embodiments.

[0014] Figure 4A , Figure 4B , Figure 4C and Figure 4D Each diagram shows a top view of an image sensor according to some embodiments.

[0015] Figure 5 A schematic diagram illustrating a cross-sectional view of an image sensor according to some embodiments.

[0016] Figure 5A Schematic diagram showing a top view of an image sensor according to some embodiments.

[0017] Fig. 6A , Figure 6B and Figure 6C Each diagram shows a top view of an image sensor according to some embodiments.

[0018] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G , Figure 7H , Fig.7I, Figure 7J , Figure 7K , Figure 7L and Figure 7M Shows Figure 1 A series of cross-sectional views of some embodiments of image sensors at various stages of fabrication.

[0019] Fig. 8A , Figure 8B , Figure 8C and Fig.8D Shows Figure 1 A series of cross-sectional views of some embodiments of image sensors at various stages of fabrication.

[0020] Fig. 9 A flow chart illustrating some embodiments of a method of manufacturing an image sensor according to some embodiments is shown. DETAILED DESCRIPTION

[0021] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0022] The embodiments or examples shown in the drawings are disclosed as follows using specific language. However, it should be understood that the embodiments and examples are not intended to be limiting. Any changes or modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are considered to be what would normally occur to a person of ordinary skill in the relevant art.

[0023] Furthermore, it should be understood that only a few processing steps and / or components of a device may be briefly described. Furthermore, additional processing steps and / or components may be added, and some of the following processing steps and / or components may be removed or changed while still implementing the claims. Therefore, it should be understood that the following description represents only examples and is not intended to indicate that one or more steps or components are required.

[0024] In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0025] To improve the full well capacity, the image sensor can be manufactured to have a deep photodiode region away from the front side of the substrate. The image sensor correspondingly has a gate extending into a position between the deep photodiode region and the floating diffusion. The gate can form a channel region that transfers photo-induced carriers from the deep photodiode region to the floating diffusion. However, due to the demand for higher and higher pull-out speeds for image sensors, the design of the deep photodiode region and the gate may no longer be attractive.

[0026] The disclosed embodiments relate to an image sensor, the image sensor comprising a deep photodiode region and a gate electrode, the gate electrode comprising a planar transfer gate, a vertical transfer gate and an embedded transfer gate. The planar transfer gate is located outside a substrate, on the front side of the substrate, and the embedded transfer gate is buried in the substrate. In addition, the vertical transfer gate extends from the planar transfer gate to the embedded transfer gate.

[0027] The embedded transfer gate extends laterally within the substrate and has a width that is relatively greater than the width of the vertical transfer gate. The embedded transfer gate can be formed by etching a sacrificial region and depositing a gate material therein. The embedded transfer gate is at least partially disposed within or adjacent to the deep photodiode region, thereby increasing the interface area between the gate electrode and the deep photodiode region. In other words, the channel region below the embedded transfer gate provides a larger path for photoinduced carrier transfer to the floating node. The embedded transfer gate enhances the ability to extract charge (or carriers) from the deep photodiode region. Therefore, the pull-out speed and full well capacity can be increased.

[0028] Figure 1 A schematic diagram of a cross-sectional view of an image sensor 100 according to some embodiments is shown. The image sensor 100 has a pixel 101. The term "pixel" refers to a unit cell that includes components for converting electromagnetic radiation into electrical signals (e.g., a photodetector and various circuits, which may include various semiconductor devices). Each pixel may include a photodetector, such as a grating-type photodetector, for recording the intensity or brightness of light (radiation). Each pixel may also include various semiconductor devices, such as various transistors including a transfer transistor, a reset transistor, a source follower transistor, a select transistor, another suitable transistor, or a combination thereof. Additional circuits, inputs, and / or outputs may be coupled to the pixel array to provide an operating environment for the pixel and to support external communications with the pixel. For example, the pixel array may be coupled to a readout circuit and / or a control circuit.

[0029] The image sensor 100 (or pixel 101) includes a substrate 10, a shallow trench isolation (STI) structure 11, a pixel region 12, a floating node 14, a spacer 15, a gate electrode 16, a gate oxide 17, an interlayer dielectric (ILD) layer 18, conductive contacts 191 and 192, a deep trench isolation (DTI) structure 21, an anti-reflective layer 22, a dielectric layer 23, a metal grid structure 24, a color filter 25 and a microlens 26.

[0030] The substrate 10 (or semiconductor substrate) has a first side (or front side) 10s1 and a second side (or back side) 10s2 opposite to the first side 10s1. In some embodiments, the substrate 10 may include any type of semiconductor body (e.g., silicon / CMOS block, SiGe, SOI, etc.) such as a semiconductor wafer or one or more dies on a wafer, and any other type of semiconductor and / or epitaxial layer formed thereon and / or otherwise associated therewith. In some embodiments, the substrate 10 may have a depth in a range from about 2 μm to about 10 μm.

[0031] The STI structure 11 is disposed near the first side 10s1 of the substrate 10. The STI structure 11 may surround the pixel region 12 and the floating node 14. In some embodiments, the STI structure 11 may have a width in a range from about 50 nm to about 200 nm. In some embodiments, the STI structure 11 may include, for example, oxides, nitrides, high-k dielectric materials such as aluminum oxide (AlO), tantalum oxide (TaO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO) or hafnium tantalum oxide (HMO) or any combination thereof.

[0032] The pixel region 12 is disposed within the substrate 10. The substrate 10 has a second doping type (e.g., p-type doping) different from the first doping type (e.g., n-type doping) of the pixel region 12, and contacts the pixel region 12 to form a PN junction photodiode 121. The PN junction photodiode 121 is configured to convert radiation entering the substrate 10 from the second side 10s2 into an electrical signal. When incident light (including photons of sufficient energy) strikes the PN junction photodiode 121, electron-hole pairs are generated. If absorption occurs in the depletion region of the junction or in a region at a diffusion length away from it, the carriers (or photo-induced carriers) of the electron-hole pair are swept out of the junction by the built-in electric field of the depletion region. The pixel region 12 can be formed by implanting a first dopant (e.g., n-type dopant) opposite to the second dopant (e.g., p-type dopant of the substrate 10) into the substrate 10.

[0033] A floating node (or floating diffusion region) 14 is disposed near the first side 10s1 of the substrate 10. The floating node 14 is disposed next to the pixel region 12 (or the PN junction photodiode 121). The floating node 14 may be electrically connected to a source follower transistor and / or a select transistor (not shown) of the image sensor 100 via a conductive contact 191. The floating node 14 may be formed as a high injection (e.g., N+ injection) in the substrate 10. The floating node 14 may be configured to store charge transferred and generated from the pixel region 12. The charge stored in the floating node 14 may then be converted into a voltage signal that may be read or processed by a circuit (e.g., a source follower transistor and / or a select transistor) of the image sensor 100.

[0034] A gate electrode (or transfer gate electrode) 16 is disposed proximate to the first side 10s1 of the substrate 10. The gate electrode 16 may be disposed between the floating node 14 and the pixel region 12. The gate electrode 16 is configured to control the transfer of charges generated in the pixel region 12. A gate oxide 17 is disposed along a surface of the gate electrode 16. The gate oxide 17 is disposed between the gate electrode 16 and the substrate 10. When a suitable voltage (e.g., a positive voltage or VDD) is applied to the gate electrode 16 via the conductive contact 192, the gate electrode 16 will be turned on, and a channel region will be generated along a portion of the substrate 10 adjacent to the gate oxide 17. During operation, photo-generated carriers (or electrons) in the pixel region 12 are transferred to the floating node 14 through the channel region under the gate electrode 16. If the potential of the floating node 14 is high enough (e.g., the charge within the floating node 14 is rich enough), the circuit of the image sensor 100 will be activated.

[0035] In some embodiments, gate electrode 16 may be or include, for example, copper, aluminum copper, some other metal, doped polysilicon, doped germanium or III-V material (e.g., GaAs, GaN), some other conductive material, or any combination of the above materials. In some embodiments, gate oxide 17 may be or include, for example, SiO2, HfO2, ZrO2, Al2O3, La2O3, etc. In some embodiments, gate oxide 17 may include a nitride compound or a carbon compound.

[0036] The spacer 15 is disposed on the first side 10s1 of the substrate 10. The spacer 15 surrounds the gate electrode 16. The spacer 15 may partially and vertically overlap the floating node 14. In some embodiments, the spacer 15 may be or include, for example, SiO2, Si3N4, or the like.

[0037] The ILD layer 18 is disposed on the first side 10s1 of the substrate 10. The ILD layer 18 covers the gate electrode 16 and the spacer 15. The ILD layer 18 surrounds the conductive contacts 191 and 192. The ILD layer 18 may include one or more of a low-k dielectric layer (e.g., a dielectric having a dielectric constant of less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide). The conductive contact 191 contacts the floating node 14 to form an ohmic contact therebetween. The conductive contact 192 contacts the gate electrode 16 to form an ohmic contact therebetween. In some embodiments, the conductive contacts 191 and 192 may include, for example, a conductive metal such as copper or tungsten.

[0038] The DTI structure 21 is disposed in the substrate 10. The DTI structure 21 extends from the second side 10s2 of the substrate 10 to a position in the substrate 10. The DTI structure 21 surrounds the pixel region 12. The DTI structure 21 is used to connect the pixel 101 with other adjacent pixels (e.g., Figure 1A The pixels 102, 103 and 104 in the DTI structure 21 are optically isolated. The DTI structure 21 may have a depth in a range from about 2 μm to about 10 μm. In some embodiments, the DTI structure 21 includes a dielectric filling layer (e.g., an oxide layer). In some embodiments, the DTI structure 21 may include, for example, an oxide, a nitride, a high-k dielectric material, such as aluminum oxide (AlO), tantalum oxide (TaO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO) or hafnium tantalum oxide (HMO) or any combination thereof. In some embodiments, the substrate 10 may include a doped region (e.g., a p-type doped region) surrounding the DTI structure 21 to compensate for damage caused during the formation of the DTI structure 21.

[0039] The anti-reflection layer 22 is disposed on the second side 10s2 of the substrate 10. The anti-reflection layer 22 is disposed between the substrate 10 and the color filter 25. The anti-reflection layer 22 can minimize light reflection and thus allow more light to reach the pixel area 12. In some embodiments, the anti-reflection layer 22 may include, for example, oxides, nitrides, high-k dielectric materials such as aluminum oxide (AlO), tantalum oxide (TaO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HMO), or any combination thereof.

[0040] The dielectric layer 23 is disposed on the anti-reflection layer 22. The dielectric layer 23 separates the substrate 10 from the metal grid structure 24. The dielectric layer 23 may be, for example, an oxide such as silicon dioxide.

[0041] The metal gate structure 24 is disposed on a portion of the dielectric layer 23. The metal grid structure 24 is surrounded by the dielectric layer 23. The metal grid structure 24 may be aligned with the DTI structure 21. The metal grid structure 24 is used to separate the pixel 101 from other adjacent pixels (eg, Figure 1A The metal grid structure 24 may be, for example, tungsten, copper or aluminum copper.

[0042] The color filter 25 is disposed on the dielectric layer 23. The color filter 25 is embedded in the dielectric layer 23. The color filter 25 is surrounded by the metal grid structure 24. The color filter 25 is aligned with the pixel area 12. Such a relationship can increase the illumination of the incident light on the pixel area 12. The color filter 25 is configured to transmit incident radiation or incident light of a specific wavelength. For example, the color filter 25 can be configured to transmit incident radiation having a wavelength from 450nm to 495nm (e.g., blue light), from 495nm to 570nm (e.g., green light), from 620nm to 750nm (e.g., red light), or from 800nm ​​to 2500nm (e.g., near infrared light).

[0043] The microlens 26 is disposed on the color filter 25. The microlens 26 is disposed on the dielectric layer 23. The microlens 26 has a curved surface (or convex surface) that promotes the collection of incident light. The microlens 26 is aligned with the pixel region 12 and the color filter 25. Such a relationship can increase the illumination of the incident light on the pixel region 12.

[0044] In backside illumination (BSI), light is incident on the second side 10s2 of the substrate 10 via the microlens 26, the color filter 25, the dielectric layer 23, and the anti-reflection layer 22 in sequence. Then, the incident light passes through the substrate 10 and reaches the pixel area 12. When the incident light hits the PN junction photodiode 121 of the pixel area 12, a plurality of photocarriers (e.g., electrons) are generated. The PN junction photodiode 121 collects the photocarriers, and once the gate electrode 16 is turned on, the photocarriers are transferred from the pixel area 12 to the floating node 14. When the incident light passes through the interface, there may be unwanted refracted light or reflected light. The metal grid structure 24 and the DTI structure 21 are used to reflect the unwanted refracted light or reflected light back to the pixel area 12, and thus the full well capacity of the image sensor 100 can be increased, and the optical isolation between adjacent pixels can be improved (or crosstalk can be reduced).

[0045] Figure 1AA schematic diagram of a top view 100A of an image sensor (e.g., image sensor 100) according to some embodiments is shown. Image sensor 100 also includes pixels 102, 103, 104. Pixels 102, 103, and 104 are adjacent to pixel 101. Pixels 102, 103, and 104 can have a structure similar to that of pixel 101. Pixels 102, 103, and 104 can each include a pixel similar to Figure 1 The gate electrodes and pixel regions of those depicted in FIG. Pixels 101, 102, 103, and 104 may have a size from 0.5 μm to 10 μm. Pixels 101, 102, 103, and 104 may be made of Figure 1 The STI structure 11 shown in FIG. 1 surrounds the pixels 101 , 102 , 103 , and 104 which share a floating node 14 .

[0046] Each gate electrode 16 of the pixels 101, 102, 103, and 104 is disposed close to the floating node 14. The gate electrode 16 includes a first gate portion 161, a second gate portion 162, and a third gate portion 163 that overlap each other in the top view 100A. The layout of the second gate portion 162 and the third gate portion 163 is asymmetric within the pixel; both are located closer to the floating node 14. In order to avoid any influence on the electrical characteristics of the floating node 14, the floating node 14 does not overlap with the third gate portion 163 in the top view 100A. The first gate portion 161 may have a triangular shape in the top view 100A. The second gate portion 162 is depicted with a dotted line to indicate that the second gate portion 162 is disposed below the first gate portion 161. The second portion 162 may have a circular shape in the top view 100A. The third gate portion 163 is depicted with a dotted line to indicate that the third gate portion 163 is disposed below the second gate portion 162. The third gate portion 163 may have a rectangular shape in the top view 100A.

[0047] Figure 1 Can be along Figure 1A Cross-sectional view of line A1-A1' in FIG. Return to reference Figure 1, the first gate portion 161 is connected to the second gate portion 162. The second gate portion 162 is connected to the third gate portion 163. The first gate portion 161 is disposed above the first side 10s1 of the substrate 10. The second gate portion 162 is disposed within the substrate 10. The third gate portion 163 is disposed below the second gate portion 162. The spacer 15 surrounds and / or contacts the first gate portion 161 and is spaced apart from the second gate portion 162 and the third gate portion 163. The second gate portion 162 is vertically located at a position between the first gate portion 161 and the third gate portion 163. The third gate portion 163 is located at a first height different from the second height of the first gate portion 161. In other words, the horizontal level of the third gate portion 163 is different from the horizontal level of the first gate portion 161.

[0048] The STI structure 11 is closer to the first side 10s1 than the third gate portion 163. In other words, the bottom surface of the STI structure 11 is closer to the top surface of the third gate portion 163 (eg, Figure 1B The second surface 163s2 in the first gate portion 161 is closer to the first side 10s1. The gate oxide 17 is disposed under the first gate portion 161. The gate oxide 17 surrounds the second gate portion 162 and the third gate portion 163. There may be no interface between two of the first gate portion 161, the second gate portion 162, and the third gate portion 163. The first gate portion 161 may be continuous with the second gate portion 162. The second gate portion 162 may be continuous with the third gate portion 163.

[0049] Figure 1B Shows Figure 1Schematic diagram of an enlarged view of a frame B1 in FIG. The first gate portion 161 has a bottom surface 161s1 facing the first side 10s1 of the substrate 10. The gate oxide 17 is disposed along the bottom surface 161s1 of the first gate portion 161. The second gate portion 162 has a sidewall surface 162s1. The gate oxide 17 surrounds the sidewall surface 162s1 of the second gate portion 162. The third gate portion 163 has a first surface (or bottom surface) 163s1 and a second surface (or top surface) 163s2 opposite to the first surface 163s1. Both the first surface 163s1 and the second surface 163s2 are substantially parallel to the first side 10s1 of the substrate 10 and are spaced apart from the first side 10s1 of the substrate 10. The third gate portion 163 has a sidewall surface 163s3 connected to the first surface 163s1 and the second surface 163s2 of the third gate portion 163. The gate oxide 17 is disposed along the first surface 163s1, the second surface 163s2, and the sidewall surface 163s3 of the third gate portion 163. The third gate portion 163 has a tip 163t away from the first surface 163s1 and the second surface 163s2 of the third gate portion 163. The tip 163t may be formed by a lower portion of the sidewall surface 163s3 and an upper portion of the sidewall surface 163s3. The lower portion and the upper portion of the sidewall surface 163s3 extend in different directions. The third gate portion 163 may have a diamond profile due to the crystal orientation of the substrate 10 (e.g., (110)) and the lateral etching that forms the hole and then fills (all or part of) the hole to form the third gate portion 163. The lateral etching is selective to the (111) crystal plane (or surface) of the substrate 10. The lateral etching exposes the (111) surface, which is the lower portion and the upper portion of the sidewall surface 163s3.

[0050] In crystalline semiconductor materials, the atoms that make up the solid are arranged in a periodic manner. If the periodic arrangement exists in the entire solid, the material is formed by a crystal. The periodic arrangement of atoms in the crystal is generally referred to as a "lattice". The lattice also contains a volume representing the entire lattice, and is called a unit cell that is regularly repeated throughout the crystal. For example, silicon has a rhombic cubic lattice structure, which can be represented as two interpenetrating face-centered cubic lattices. Therefore, the analysis and visualization of the cubic lattice can be extended to the characterization of silicon crystals. In the description herein, various planes in a semiconductor crystal (e.g., a silicon crystal) will be referenced, especially (100), (110) and (111) planes. These planes show the orientation of the semiconductor atomic plane relative to the main crystal axis. The value (xyz) is called the Miller index and is determined by the inverse of the point where the crystal plane of silicon intersects the main crystal axis. In some embodiments, based on different crystal orientations, for example, (100), (111), etc., the third gate portion 163 can have different profiles.

[0051] The first gate portion 161 has a first width 161w in a direction parallel to the first side 10s1 of the substrate 10. The second gate portion 162 has a second width 162w in a direction parallel to the first side 10s1 of the substrate 10. The second width 162w may be in a range from 50nm to 90nm or around 70nm. The second gate portion 162 may have a tapered profile toward the pixel region 12. The third gate portion 163 has a third width 163w1 formed by the tip 163t in a direction parallel to the first side 10s1 of the substrate 10. The third gate portion 163 also has a fourth width 163w2 formed by the first surface 163s1. The first width 161w of the first gate portion 161 is greater than the second width 162w of the second gate portion 162. In some embodiments, the first width 161w is greater than the third width 163w1. In some embodiments, the first width 161w is less than the third width 163w1. In some embodiments, the first width 161w is substantially the same as the third width 163w1. The third width 163w1 of the third gate portion 163 is greater than the second width 162w. The fourth width 163w2 is less than the third width 163w1. Due to the relatively wide first portion 161 and the third portion 163 and the relatively narrow second portion 162 therebetween, the gate electrode 16 can have an "H"-shaped profile rotated 90 degrees. The height (or thickness) 162h of the second gate portion 162 is higher than the height (or thickness) 163h of the third gate portion 163. The second portion 162 and the third portion 163 can form a hammer-shaped profile. The height 162h of the second gate portion 162 can be from 400nm to 600nm. The height 163h of the third gate portion 163 can be from 60nm to 100nm, or from 10nm to 1μm.

[0052] Because the pixel area 12 is an implanted area, the position of its boundary depends on the thermal budget, doping concentration and dopant of the surrounding area of ​​the pixel area 12 and the substrate 10. The positional relationship between the pixel area 12 and the third gate portion 163 can vary. In some embodiments, the third gate portion 163 can be partially embedded in the pixel area 12. The first surface 163s1 of the third gate portion 163 is located within the pixel area 12. In some embodiments, the third gate portion 163 can be completely embedded in the pixel area 12. The first surface 163s1 and the second surface 163s2 of the third gate portion 163 can be located within the pixel area 12. In some embodiments, the third gate portion 163 can be disposed outside the pixel area 12. The first surface 163s1 and the second surface 163s2 of the third gate portion 163 can be located outside the pixel area 12.

[0053] Each of the first gate portion 161 (e.g., planar transfer gate), the second gate portion 162 (e.g., vertical transfer gate), and the third gate portion 163 (e.g., embedded transfer gate) is configured to transfer photo-induced carriers from the pixel region 12 to the floating node 14. The embedded transfer gate 163 extends laterally within the substrate 10 and has a third width 163w1 that is relatively greater than the second width 162w of the vertical transfer gate 162. The embedded transfer gate 163 may be formed by etching a sacrificial region (e.g., Figure 7B The embedded transfer gate 163 is formed by depositing a gate material in a sacrificial region 13 in the pixel region 12. The embedded transfer gate 163 is disposed close to or at least partially in or adjacent to the pixel region 12, thereby increasing the interface area between the gate electrode 16 and the pixel region 12. When the gate electrode 16 is turned on, the channel region under the embedded transfer gate 163 provides a larger path for photo-induced carriers to transfer from the pixel region 12 to the floating node 14. The embedded transfer gate 163 enhances the extraction of charge (or carriers) from the pixel region 12. Therefore, the pull-out speed and the full well capacity can be increased.

[0054] Figure 1B-1 Schematic diagram showing a three-dimensional view of a gate electrode (eg, gate electrode 16 according to some embodiments). First gate portion 161, second gate portion 162, and third gate portion 163 may have substantially circular shapes with different diameters. Third gate portion 163 may have a diamond-shaped profile. Figure 1B-1 Two sidewall surfaces are shown. In some embodiments, the diamond-shaped profile of the third gate portion 163 may have more than two sidewall surfaces.

[0055] Figure 1C Shows Figure 1 Schematic diagram of another enlarged view of box B1 in FIG. Figure 1C A zoomed-in view similar to Figure 1B Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0056] In some embodiments, the second gate portion has a void (or second void) 201 extending substantially perpendicular to the first side 10s1 of the substrate 10. The third gate portion 163 has a void (or first void) 202 extending substantially parallel to the first side 10s1 of the substrate 10. The first void 202 is connected to the second void 201. The middle portion of the first void 202 may be connected to the end of the second void 201. The first void 202 and the second void 201 may form a "T" shaped profile. In some embodiments, the first void 202 may be spaced apart from the second void 201. The first void 202 and the second void 201 may be filled with air.

[0057] The first void 202 and the second void 201 may be formed during the formation of the gate electrode 16 by, for example, chemical vapor deposition. Due to the flow, step coverage, nucleation, and growth of the deposited gate material's precursors, the first void 202 and the second void 201 may have different sizes and profiles. The first void 202 and the second void 201 may each have an oblate ellipsoid shape. Because the second gate portion 162 has a relatively small width, less precursor may enter the deeper pores (e.g., Figure 7G The second hole 10h2 in the embodiment is then deposited with a gate material to form a third gate portion 163. The diameter of the first gap 202 may be greater than the diameter of the second gap 201.

[0058] The voids may affect the electrical properties of the gate electrode. The size of the voids can be minimized by controlling the deposition of the gate material.

[0059] Figure 2A A schematic diagram of a portion of an image sensor (eg, image sensor 100 ) is shown in accordance with some embodiments. Figure 2A The image sensor part is similar to Figure 1B Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0060] The gate electrode 16 also includes a fourth gate portion 164 disposed between the first gate portion 161 and the third gate portion 163. The fourth gate portion 164 intersects with the second gate portion 162. The fourth gate portion 164 may have a structure similar to that of the third gate portion 163. For example, the fourth gate portion 164 may have a diamond profile. The fourth gate portion 164 (or a further embedded transfer gate) is configured to transfer photo-induced carriers from the pixel region 12 to the floating node 14. The further embedded transfer gate 164 extends laterally within the substrate 10 and has a width that is relatively greater than the width of the vertical transfer gate 162. The further embedded transfer gate 164 may be formed by etching a sacrificial region and depositing a gate material therein. When the gate electrode 16 is turned on, the channel region below the further embedded transfer gate 164 provides a further larger path for photo-induced carriers to transfer from the pixel region 12 to the floating node 14. The further embedded transfer gate 164 enhances the extraction of charge (or carriers) from the pixel region 12. Therefore, the pull-out speed and the full well capacity can be increased. In some embodiments, the gate electrode 16 may include more than two embedded transfer gates.

[0061] Figure 2B A schematic diagram of a portion of an image sensor (eg, image sensor 100 ) is shown in accordance with some embodiments. Figure 2B The image sensor part is similar to Figure 1B Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0062] and Figure 1B The third gate portion 163 is disposed closer to the first side 10s1 of the substrate 10 than the third gate portion 163 in the gate electrode 16. The gate electrode 16 further includes a fifth gate portion 165 disposed under the third gate portion 163. The fifth gate portion 165 may have a tapered profile toward the pixel region 12. The fifth gate portion 165 may be partially embedded in the pixel region 12 or outside the pixel region 12, depending on the boundary of the pixel region 12. Figure 2B The third gate portion 163 in the embodiment is away from the pixel region 12. Damage caused during the formation (eg, etching) of the third gate portion 163 will not affect the optoelectronic characteristics of the pixel region 12.

[0063] Figure 2C A schematic diagram of a portion of an image sensor (eg, image sensor 100 ) is shown in accordance with some embodiments. Figure 2C The image sensor part is similar to Figure 1B Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0064] A centerline 162c of the second gate portion 162 extends substantially perpendicular to the first side 10s1 of the substrate 10, and a centerline 163c of the third gate portion 163 extends substantially perpendicular to the first side 10s1 of the substrate 10. The centerline 162c of the second gate portion 162 is not aligned with the centerline 163c of the third gate portion 163 by an offset os1.

[0065] Figure 2D A schematic diagram of a portion of an image sensor (eg, image sensor 100 ) is shown in accordance with some embodiments. Figure 2D The image sensor part is similar to Figure 1B Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0066] The gate electrode 16 includes a gate portion 163' instead of Figure 1B The gate portion 163 ′ has a substantially rectangular shape due to the crystal orientation of the substrate 10 . The gate portion 163 ′ has a sidewall surface 163 s 3 ′ that is substantially perpendicular to the first side 10 s 1 of the substrate 10 .

[0067] Figure 3ASchematic diagram showing a top view of an image sensor according to some embodiments. Figure 3A The top view is similar to Figure 1A Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0068] The center 162z of the second gate portion 162 is not aligned with the center line 163z of the third gate portion 163, with an offset os2. The second gate portion 162 partially overlaps the third gate portion 163 in the top view. The third gate portion 163 is farther from the floating node 14 than the second gate portion 162 in the top view. Therefore, the potential of the third gate portion 163 will not affect the floating node 14.

[0069] Figure 3B Schematic diagram showing a top view of an image sensor according to some embodiments. Figure 3B The top view is similar to Figure 1A Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0070] like Figure 3B As shown in FIG. 1 , at least a portion of the third gate portion 163 overlaps the floating node 14 in the top view. The width of the third gate portion 163 is greater than Figure 1A The width in .

[0071] Figure 3C Schematic diagram showing a top view of an image sensor according to some embodiments. Figure 3C The top view is similar to Figure 1A Therefore, some detailed descriptions may refer to the corresponding previous paragraphs and are not repeated below for the sake of brevity. The differences between them are as follows. The gate electrode 16 has a gate portion 263 instead of Figure 1A The gate portion 263 may have a circular shape in a top view.

[0072] Figure 3D Schematic diagram showing a top view of an image sensor according to some embodiments. Figure 3D The top view is similar to Figure 1A Therefore, some detailed descriptions can be referred to the corresponding previous paragraphs, and for the sake of brevity, they are not repeated below, and the differences between them are as follows. The gate electrode 16 has a gate portion 262 instead of Figure 1A The second gate portion 162 in the embodiment of the present invention. The gate portion 262 may have an elliptical shape in a top view.

[0073] Figure 4A Schematic diagram showing a top view of an image sensor according to some embodiments. Figure 4A The top view is similar to Figure 1A Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0074] The layout of the second gate portion 162 and the third gate portion 163 is symmetrical within the pixel; both are aligned with the pixel region 12. The gate electrode 16 includes a gate portion 261 instead of Figure 1A The first gate portion 161 in the embodiment of the present invention is shown in FIG. The gate portion 261 may have a substantially rectangular shape in a top view. The gate portion 261 is aligned with the second gate portion 162 and the third gate portion 163.

[0075] Figure 4B Schematic diagram showing a top view of an image sensor according to some embodiments. Figure 4B The top view is similar to Figure 4A Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0076] The second gate portion 162 is not aligned with the third gate portion 163. The second gate portion 162 partially overlaps with the third gate portion 163 in the top view. At least a portion of the third gate portion 163 does not overlap with the gate portion 261 in the top view.

[0077] Figure 4C Schematic diagram showing a top view of an image sensor according to some embodiments. Figure 4C The top view is similar to Figure 4A Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0078] The third gate portion 163 is wider than the gate portion 261. At least a portion of the third gate portion 163 does not overlap with the gate portion 261 in a top view.

[0079] Figure 4D Schematic diagram showing a top view of an image sensor according to some embodiments. Figure 4D The top view is similar to Figure 4A Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0080] The gate electrode 16 includes a gate portion 271 instead of Figure 4AThe gate portion 271 may have a circular shape in a top view. The gate electrode 16 has a gate portion 263 instead of Figure 4A The gate portion 263 may have a circular shape in a top view.

[0081] Figure 5 A schematic diagram illustrating a cross-sectional view of an image sensor 300 according to some embodiments is shown. Figure 5 The image sensor 300 is similar to Figure 1 Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0082] The image sensor 300 has a pixel 301, which is a single pixel with its own dedicated floating node 34. The floating node (or floating diffusion region) 34 is disposed near the first side 10s1 of the substrate 10. The floating node 34 is disposed next to the pixel region 12 (or the PN junction photodiode 121). The floating node 34 can be electrically connected to a source follower transistor and / or a select transistor (not shown) of the image sensor 300 via a conductive contact 191. The floating node 34 can be formed as a high injection (e.g., N+ injection) in the substrate 10. The floating node 34 can be configured to store charge transferred and generated from the pixel region 12. The charge stored in the floating node 34 will then be converted into a voltage signal that can be read or processed by the circuitry (e.g., source follower transistor and / or select transistor) of the image sensor 300.

[0083] Image sensor 300 may include gate electrode 36 instead of gate electrode 16 of image sensor 100. Gate electrode 36 may be disposed between floating node 34 and pixel region 12. Gate electrode 36 is configured to control the transfer of charges generated in pixel region 12. Gate oxide 37 is disposed along the surface of gate electrode 36. Gate oxide 37 is disposed between gate electrode 36 and substrate 10. When a suitable voltage (e.g., a positive voltage or VDD) is applied to gate electrode 36 via conductive contact 192, gate electrode 36 will be turned on, and a channel region will be generated along a portion of substrate 10 adjacent to gate oxide 37. During operation, photo-generated carriers (or electrons) in pixel region 12 are transferred to floating node 34 through the channel region under gate electrode 36. If the potential of floating node 34 is high enough (e.g., the charge within floating node 34 is rich enough), the circuit of image sensor 300 will be activated.

[0084] In some embodiments, gate electrode 36 may be or include, for example, copper, aluminum copper, some other metal, doped polysilicon, doped germanium or III-V material (e.g., GaAs, GaN), some other conductive material, or any combination thereof. In some embodiments, gate oxide 37 may be or include, for example, SiO2, HfO2, ZrO2, Al2O3, La2O3, etc. In some embodiments, gate oxide 37 may include a nitride compound or a carbon compound.

[0085] The spacer 15 is disposed on the first side 10s1 of the substrate 10. The spacer 15 surrounds the gate electrode 36. The spacer 15 may partially and vertically overlap the floating node 34. In some embodiments, the spacer 15 may be or include, for example, SiO2, Si3N4, or the like.

[0086] The conductive contact 191 contacts the floating node 34 to form an ohmic contact therebetween. The conductive contact 192 contacts the gate electrode 36 to form an ohmic contact therebetween.

[0087] Figure 5A A schematic diagram of a top view 300A of an image sensor (e.g., image sensor 300) according to some embodiments is shown. A gate electrode 36 of a pixel 301 is disposed proximate to a floating node 34. The gate electrode 36 includes a first gate portion 361, a second gate portion 362, and a third gate portion 363 that overlap (e.g., partially overlap) each other in the top view 300A. The layout of the second gate portion 362 and the third gate portion 363 is asymmetric within the pixel 301; both are closer to the floating node 34. In order to avoid any effect on the electrical characteristics of the floating node 34, the floating node 34 does not overlap with the third gate portion 363 in the top view 300A. The first gate portion 361 may have a triangular shape in the top view 300A. The second gate portion 362 is depicted with a dotted line to indicate that the second gate portion 362 is disposed below the first gate portion 361. The second gate portion 362 may have a circular shape in the top view 300A. The third gate portion 363 is depicted with a dotted line to indicate that the third gate portion 363 is disposed below the second gate portion 362. The third gate portion 363 may have a rectangular shape in the top view 300A.

[0088] Figure 5 Can be along Figure 5A Cross-sectional view of line B1-B1' in FIG. Return to reference Figure 5, the first gate portion 361 is connected to the second gate portion 362. The second gate portion 362 is connected to the third gate portion 363. The first gate portion 361 is disposed above the first side 10s1 of the substrate 10. The second gate portion 362 is disposed within the substrate 10. The second gate portion 362 may have a tapered profile toward the pixel region 12. The third gate portion 363 is disposed below the second gate portion 362. The spacer 15 surrounds and / or contacts the first gate portion 361 and is spaced apart from the second gate portion 362 and the third gate portion 363. The second gate portion 362 is vertically located at a position between the first gate portion 361 and the third gate portion 363. The third gate portion 363 is located at a first height different from the second height of the first gate portion 361. In other words, the horizontal level of the third gate portion 363 is different from the horizontal level of the first gate portion 361.

[0089] The STI structure 11 is closer to the first side 10s1 than the third gate portion 363. In other words, the bottom surface of the STI structure 11 is closer to the first side 10s1 than the top surface of the third gate portion 363. The gate oxide 37 is disposed under the first gate portion 361. The gate oxide 37 surrounds the second gate portion 362 and the third gate portion 363. There may be no interface between two of the first gate portion 361, the second gate portion 362, and the third gate portion 363. The first gate portion 361 may be continuous with the second gate portion 362. The second gate portion 362 may be continuous with the third gate portion 363.

[0090] The third gate portion 363 may not be aligned with the second gate portion 362. The third gate portion 363 may have a semi-rhombus profile. A sidewall surface 363s3 of the third gate portion 363 away from the second gate portion 362 has two portions extending in different directions and forming a tip 363t. The tip 363t is away from the bottom surface and the top surface of the third gate portion 363. A sidewall surface 363s4 of the third gate portion 363 close to the second gate portion 362 may have a substantially flat shape.

[0091] Because the pixel region 12 is an implanted region, the position of its boundary depends on the thermal budget, doping concentration, and dopant of the surrounding area of ​​the pixel region 12 and the substrate 10. The positional relationship between the pixel region 12 and the third gate portion 363 can vary. In some embodiments, the third gate portion 363 can be partially embedded in the pixel region 12. In some embodiments, the third gate portion 363 can be completely embedded in the pixel region 12. In some embodiments, the third gate portion 363 can be disposed outside the pixel region 12.

[0092] Each of the first gate portion 361 (e.g., planar transfer gate), the second gate portion 362 (e.g., vertical transfer gate), and the third gate portion 363 (e.g., embedded transfer gate) is configured to transfer photo-generated carriers from the pixel region 12 to the floating node 34. The embedded transfer gate 363 extends laterally within the substrate 10 and is wider than the vertical transfer gate 362. The embedded transfer gate 363 can be formed by etching a sacrificial region (e.g., Figure 7B The embedded transfer gate 363 is formed by depositing a gate material in the sacrificial region 13 in the pixel region 12. The embedded transfer gate 363 is disposed close to or at least partially in or adjacent to the pixel region 12, thereby increasing the interface area between the gate electrode 36 and the pixel region 12. When the gate electrode 36 is turned on, the channel region under the embedded transfer gate 363 provides a larger path for photo-induced carriers to transfer from the pixel region 12 to the floating node 34. The embedded transfer gate 363 enhances the extraction of charge (or carriers) from the pixel region 12. Therefore, the pull-out speed and the full well capacity can be increased.

[0093] Fig. 6A Schematic diagram showing a top view of an image sensor according to some embodiments. Fig. 6A The top view is similar to Figure 5A Therefore, some detailed descriptions may refer to the corresponding previous paragraphs, and for the sake of brevity, they will not be repeated below, and the differences between them are as follows.

[0094] The layout of the second gate portion 362 and the third gate portion 363 is symmetrical within the pixel; both are aligned with the pixel region 12. The gate electrode 36 includes a gate portion 461 instead of Figure 5A The first gate portion 361 in the embodiment of the present invention is shown in FIG. The gate portion 461 may have a substantially rectangular shape in a top view. The gate portion 461 is aligned with the second gate portion 362 and the third gate portion 363.

[0095] Figure 6B Schematic diagram showing a top view of an image sensor according to some embodiments. Figure 6B The top view is similar to Figure 5A Therefore, some detailed descriptions may refer to the corresponding previous paragraphs and are not repeated below for the sake of brevity. The differences between them are as follows. The gate electrode 36 has a gate portion 463 instead of Fig. 6A The third gate portion 363 in the embodiment of the present invention. The gate portion 463 may have a circular shape in a top view.

[0096] Figure 6C Schematic diagram showing a top view of an image sensor according to some embodiments. Figure 6C The top view is similar to Figure 5ATherefore, some detailed descriptions may refer to the corresponding previous paragraphs and are not repeated below for the sake of brevity. The differences between them are as follows. The gate electrode 36 includes a gate portion 471 instead of Figure 5A The gate electrode 36 has a gate portion 463 instead of a first gate portion 361 in the embodiment of the present invention. The gate portion 471 may have a circular shape in a top view. Figure 5A The third gate portion 363 in the embodiment of the present invention. The gate portion 463 may have a circular shape in a top view.

[0097] Fig. 7A , Figure 7B , Figure 7C , Fig.7D , Fig. 7E , Figure 7F , Figure 7G , Figure 7H , Fig.7I , Figure 7J , Figure 7K , Figure 7L and Figure 7M Shows Figure 1 A series of cross-sectional views of some embodiments of image sensor 100 at various stages of fabrication.

[0098] exist Fig. 7A In the embodiment, a substrate 10 is provided. A pixel region (or deep photodiode region) 12 is formed in the substrate 10. The pixel region 12 can be formed by implanting a first dopant (e.g., an n-type dopant) opposite to a second dopant (e.g., a p-type dopant of the substrate 10) into the substrate 10.

[0099] exist Figure 7B In the embodiment of the present invention, a sacrificial region 13 is formed in the substrate 10. The sacrificial region 13 may be formed by implanting a doping concentration relatively higher than that of the pixel region 12 and the substrate 10 into the substrate. The dopant of the sacrificial region 13 may be an n-type dopant.

[0100] exist Figure 7C In the embodiment of the present invention, a passivation layer 10p1 is formed over the sacrificial region 13. The passivation layer 10p1 may be an epitaxial layer. The passivation layer 10p1 may be a p-type layer that passivates damage caused by the implantation of the sacrificial region 13. There may be no boundary between the passivation layer 10p1 and the substrate 10. The passivation layer 10p1 may be referred to as a part of the substrate 10, and thus the dotted line therebetween may be an imaginary line.

[0101] exist Fig.7DIn the embodiment, the STI structure 11 is formed near the first side 10s1 of the substrate 10. The STI structure 11 may be formed by removing a portion of the substrate 10 to form a groove and depositing a dielectric material into the groove. The STI structure 11 may be closer to the first side 10s1 of the substrate 10 than the sacrificial region 13.

[0102] exist Fig. 7E In the embodiment of the present invention, a floating node 14 is formed near the first side 10s1 of the substrate 10 . The floating node 14 may be formed as a high implant (eg, an N+ implant) in the substrate 10 . The floating node 14 is far away from the pixel region 12 .

[0103] exist Figure 7F In the embodiment of the present invention, a portion of the substrate 10 between the first side 10s1 and the sacrificial region 13 is removed to form a first hole 10h1 having a first width 10w1. In some embodiments, a portion of the sacrificial region may be removed. The first width 10w1 may be in a range from 50nm to 90nm or about 70nm. The first hole 10h1 may taper toward the pixel region 12.

[0104] exist Figure 7G In the embodiment of the present invention, the sacrificial region 13 is removed to form a second hole 10h2 that is connected to the first hole 10h1 and has a second width 10w2. The second hole 10h2 is located below the first hole 10h1. The second hole 10h2 extends laterally in the substrate 10. The second hole 10h2 can be formed by laterally etching the sacrificial region 13. Because the doping concentration of the sacrificial region 13 is very different from the doping concentration of the substrate 10 and the pixel region 12, the etchant will selectively etch the sacrificial region 13 with minimal damage to the surrounding area. Therefore, the second width 10w2 of the second hole 10h2 is greater than the first width 10w1 of the first hole 10h1. In some embodiments, the etchant may be or include a chlorine-based etchant and / or some other suitable etchant type. The second hole 10h2 may have a diamond profile due to the lateral etching of the substrate 10 having a crystal orientation (110). The lateral etching is selective to the (111) crystal plane (or surface) of the substrate 10. The lateral etching exposes the (111) surface, which is a lateral surface of the second hole 10h2. The second hole 10h2 may have a third width 10w3 formed by a bottom side of the second hole 10h2.

[0105] exist Figure 7H In the embodiment, gate oxide 17 is formed along the sidewalls of first hole 10h1 and second hole 10h2. Gate oxide 17 may be formed along a portion of first side 10s1 of substrate 10. Before forming gate oxide 17, a passivation process may be performed on the sidewalls of first hole 10h1 and second hole 10h2 to mitigate damage caused by removing portions of substrate 10 and sacrificial region 13.

[0106] exist Figure 7H In the embodiment, a gate electrode 16 is formed having a first gate portion 161 located above the first side 10s1 of the substrate 10, a second gate portion 162 located within the first hole 10h1, and a third gate portion 163 located within the second hole 10h2. The third gate portion 163 may have a diamond profile inherited from the second hole 10h2.

[0107] exist Fig.7I In the embodiment, the spacer 15 is formed to surround the first gate portion 161 of the gate electrode 16. The spacer 15 is spaced apart from the second gate portion 162 and the third gate portion 163.

[0108] exist Figure 7J In the embodiment of the present invention, an ILD layer 18 is formed over a first side 10s1 of a substrate 10. A conductive contact 191 is formed over a floating node 14 to make an electrical connection therebetween. A conductive contact 192 is formed over a gate electrode 16 to make an electrical connection therebetween. Conductive contacts 191 and 192 may be formed by etching the ILD layer 18 to form a hole and depositing a conductive material therein. The ILD layer 18 may include one or more of a low-k dielectric layer (e.g., a dielectric having a dielectric constant of less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide). In some embodiments, the conductive contacts 191 and 192 may include, for example, a conductive metal such as copper or tungsten.

[0109] exist Figure 7K In the embodiment of the present invention, a DTI structure 21 is formed in the substrate 10. The DTI structure 21 extends from the second side 10s2 of the substrate 10 to a position in the substrate 10. The DTI structure 21 can be formed by removing a portion of the substrate 10 to form a deep trench and depositing a dielectric material into the deep trench. The DTI structure 21 surrounds the pixel area 12 to prevent crosstalk from adjacent pixels.

[0110] exist Figure 7L In the embodiment, an anti-reflection layer 22 is formed on the second side 10s2 of the substrate 10 to minimize reflection and thus allow more light to reach the pixel area 12. In some embodiments, the anti-reflection layer 22 may include, for example, an oxide, a nitride, a high-k dielectric material such as aluminum oxide (AlO), tantalum oxide (TaO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), or hafnium tantalum oxide (HMO), or any combination thereof.

[0111] exist Figure 7L In the embodiment of the present invention, a dielectric layer 23 is formed on the anti-reflection layer 22. The dielectric layer 23 may be, for example, an oxide such as silicon dioxide.

[0112] exist Figure 7LIn the embodiment, a metal grid structure 24 is formed on a portion of the dielectric layer 23. The metal grid structure 24 is surrounded by the dielectric layer 23. The metal grid structure 24 is formed to be aligned with the DTI structure 21. The metal grid structure 24 is used to optically isolate the pixel 101 from other adjacent pixels. The metal grid structure 24 can be, for example, tungsten, copper, or aluminum copper.

[0113] exist Figure 7M In the embodiment of the present invention, a color filter 25 is formed on the dielectric layer 23. The color filter 25 is embedded in the dielectric layer 23. The color filter 25 can be formed by etching a portion of the dielectric layer 23 to form a groove and depositing an organic dye or a pigment-based material into the groove. Thereafter, a microlens 26 can be formed on the color filter 25 and the dielectric layer 23 to form a Figure 1 The image sensor 100 is provided.

[0114] Fig. 8A , Figure 8B , Figure 8C and Fig.8D Shows Figure 1 A series of cross-sectional views of some embodiments of image sensor 100 at various stages of fabrication.

[0115] exist Fig. 8A In the present invention, a substrate 10 is provided. A pixel region (or deep photodiode region) 12 is formed in the substrate 10. The pixel region 12 can be formed by implanting a first dopant (e.g., an n-type dopant) opposite to a second dopant (e.g., a p-type dopant of the substrate 10) into the substrate 10. An STI structure 11 is formed near a first side 10s1 of the substrate 10. The STI structure 11 can be formed by removing a portion of the substrate 10 to form a groove and depositing a dielectric material into the groove.

[0116] exist Figure 8B In the embodiment of the present invention, a floating node 14 is formed near the first side 10s1 of the substrate 10 . The floating node 14 may be formed as a high implant (eg, an N+ implant) in the substrate 10 . The floating node 14 is far away from the pixel region 12 .

[0117] exist Figure 8C In the embodiment, a sacrificial region 13 is formed between the first side 10s1 of the substrate 10 and the pixel region 12. The sacrificial region 13 may be formed by implanting a doping concentration relatively higher than the doping concentrations of the pixel region 12 and the substrate 10 into the substrate. The dopant of the sacrificial region 13 may be an n-type dopant. The STI structure 11 may be closer to the first side 10s1 of the substrate 10 than the sacrificial region 13.

[0118] exist Fig.8DIn the embodiment of the present invention, a passivation layer 10p2 is formed over the sacrificial region 13 by implanting with a p-type dopant. The passivation layer 10p2 passivates the damage caused by the implantation of the sacrificial region 13. There may be no boundary between the passivation layer 10p2 and the substrate 10. The passivation layer 10p2 may be referred to as a part of the substrate 10, and thus the line therebetween may be an imaginary line.

[0119] FIG. 7F to FIG. 7M The stage can be Fig. 8A , Figure 8B , Figure 8C and Fig.8D After the stage of Figure 1 The image sensor 100 is provided.

[0120] Fig. 9 1 is a flow chart showing a method 500 of manufacturing an image sensor (e.g., image sensor 100, 300) according to some embodiments. Method 500 includes operations S501, S503, S505, S507, S509, S511, and S513. The order of operations S501, S503, S505, S507, S509, S511, and S513 may be exemplary and will not limit the disclosed embodiments.

[0121] Method 500 begins with operation S501, which includes forming a pixel region (eg, pixel region 12) within a substrate (eg, substrate 10). Operation S501 may include implanting the substrate with a first dopant to form the pixel region, wherein the first dopant is different from a second dopant of substrate 10.

[0122] In operation S503, method 500 includes forming a sacrificial region (eg, sacrificial region 13) between a first side of the substrate (eg, first side 10s1) and the pixel region. Operation 503 may include implanting the substrate with a high doping concentration (eg, N+ implant) to form the sacrificial region.

[0123] In operation S505, method 500 includes forming a passivation layer (e.g., passivation layers 10p1, 10p2) over the sacrificial region. Operation 503 may include depositing an epitaxial layer over the sacrificial region to form the passivation layer. In some embodiments, operation 503 may include implanting a portion of the substrate proximate to the first side 10s1 to form the passivation layer. The passivation layer may be a p-type layer.

[0124] In operation S507 , the method 500 includes removing a portion of the substrate between the first side and the sacrificial region to form a first hole (eg, first hole 10 h 1 ) having a first width (eg, first width 10 w 1 ).

[0125] In operation S509, method 500 includes removing the sacrificial region to form a second hole (e.g., second hole 10h2) that is connected to the first hole and has a second width (e.g., second width 10w2) greater than the first width. Operation S509 may include laterally etching the sacrificial region to form the second hole. Because the doping concentration of the sacrificial region 13 is very different from the doping concentration of the substrate 10 and the pixel region 12, the etchant will selectively etch the sacrificial region 13 with minimal damage to the surrounding area.

[0126] In operation S511, method 500 includes forming a gate oxide (eg, gate oxide 17) along sidewalls of the first and second holes. Operation S511 may include performing a passivation process along the sidewalls of the first and second holes to mitigate damage caused by removing portions of the substrate and the sacrificial region.

[0127] In operation S513, method 500 includes forming a gate electrode (e.g., gate electrode 16, 36), the gate electrode having a first gate portion (e.g., first gate portion or planar transfer gate 161, 361) located above the first side, a second gate portion (e.g., second gate portion or vertical transfer gate 162, 362) located within the first hole, and a third gate portion (e.g., third gate portion or embedded transfer gate 163, 363) located within the second hole.

[0128] The embedded transfer gate extends laterally within the substrate and has a width that is relatively greater than the width of the vertical transfer gate. The embedded transfer gate is at least partially disposed within or adjacent to the pixel region, thereby increasing the interface area between the gate electrode and the pixel region. In other words, the channel region below the embedded transfer gate provides a larger path for photoinduced carrier transfer to the floating node. The embedded transfer gate enhances the extraction of charge (or carriers) from the pixel region. Therefore, the pull-out speed and full well capacity can be increased.

[0129] Method 500 is merely an example and is not intended to limit the disclosed embodiments beyond what is explicitly recited in the claims. Additional operations may be provided before, during, or after each operation of method 500, and some of the operations described may be replaced, eliminated, or reordered for additional embodiments of the method. In some embodiments, method 500 may include Fig. 9 In some embodiments, method 500 may include: Fig. 9 One or more operations depicted in .

[0130] According to other embodiments, an image sensor is provided. The image sensor includes a substrate and a gate electrode. The gate electrode is disposed near a first side of the substrate. The gate electrode includes a first gate portion, a second gate portion, and a third gate portion. The first gate portion is disposed on the first side of the substrate. The second gate portion is disposed in the substrate and connected to the first gate portion. The third gate portion is disposed under the second gate portion and connected to the second gate portion. The first width of the first gate portion is greater than the second width of the second gate portion, and the third width of the third gate portion is greater than the second width.

[0131] According to other embodiments, an image sensor is provided. The image sensor includes a substrate and a gate portion. The substrate has a first side. The gate portion is disposed within the substrate and has a first surface and a second surface, both of which are substantially parallel to the first side of the substrate. The first surface and the second surface of the gate portion are spaced apart from the first side of the substrate.

[0132] According to other embodiments, a method for manufacturing an image sensor is provided, including: forming a pixel area in a substrate; forming a sacrificial area between a first side of the substrate and the pixel area; removing a portion of the substrate located between the first side and the sacrificial area to form a first hole having a first width; removing the sacrificial area to form a second hole connected to the first hole and having a second width greater than the first width; and forming a gate electrode having a first gate portion located on the first side, a second gate portion located in the first hole, and a third gate portion located in the second hole.

[0133] Some embodiments of the present application provide an image sensor, comprising: a substrate; and a gate electrode, arranged near a first side of the substrate, comprising: a first gate portion, arranged on the first side of the substrate; a second gate portion, arranged in the substrate and connected to the first gate portion; and a third gate portion, arranged under the second gate portion and connected to the second gate portion, wherein a first width of the first gate portion is greater than a second width of the second gate portion, and a third width of the third gate portion is greater than the second width.

[0134] In some embodiments, the image sensor further comprises: a pixel region disposed within the substrate, wherein the third gate portion has a first surface located within the pixel region. In some embodiments, the third gate portion is partially embedded in the pixel region. In some embodiments, the third gate portion is located at a first height different from the second height of the first gate portion. In some embodiments, the image sensor further comprises: a spacer surrounding the first gate portion and spaced apart from the second gate portion and the third gate portion. In some embodiments, the third gate portion has a first surface, the first surface has a fourth width, and the fourth width is less than the third width of the third gate portion. In some embodiments, the third gate portion has a diamond profile. In some embodiments, the image sensor further comprises: a gate oxide disposed along a sidewall surface of the third gate portion and the first surface. In some embodiments, the third gate portion has a first void extending substantially parallel to the first side of the substrate. In some embodiments, the second gate portion has a second void extending substantially perpendicular to the first side of the substrate and communicating with the first void. In some embodiments, the first gate portion, the second gate portion, and the third gate portion overlap each other in a top view. In some embodiments, a centerline of the second gate portion extends substantially perpendicular to the first side of the substrate, and a centerline of the third gate portion extends substantially perpendicular to the first side of the substrate, and wherein the centerline of the second gate portion is not aligned with the centerline of the third gate portion, having an offset. In some embodiments, the image sensor further comprises: a floating node proximate to the first side of the substrate, wherein the floating node does not overlap with the third gate portion in a top view.

[0135] Other embodiments of the present application provide an image sensor, comprising: a substrate having a first side; and a gate electrode, comprising a gate portion, the gate portion being buried in the substrate, wherein the gate portion has a first surface and a second surface, the first surface and the second surface facing in opposite directions to each other and both being substantially parallel to the first side of the substrate, and wherein the first surface and the second surface of the gate portion are spaced apart from the first side of the substrate.

[0136] In some embodiments, the gate portion has a tip that is away from the first surface and the second surface. In some embodiments, the image sensor further comprises: a pixel region located within the substrate; and a floating node proximate to the first side of the substrate, wherein the gate portion is configured to transfer photon-induced carriers from the pixel region to the floating node. In some embodiments, the image sensor further comprises: a shallow trench isolation (STI) structure proximate to the first side of the substrate, wherein the shallow trench isolation structure is closer to the first side than the gate portion.

[0137] Still other embodiments of the present application provide a method for manufacturing an image sensor, comprising: forming a pixel area in a substrate; forming a sacrificial area between a first side of the substrate and the pixel area; removing a portion of the substrate between the first side and the sacrificial area to form a first hole having a first width; removing the sacrificial area to form a second hole connected to the first hole and having a second width greater than the first width; and forming a gate electrode having a first gate portion located on the first side, a second gate portion located in the first hole, and a third gate portion located in the second hole.

[0138] In some embodiments, the method further comprises: forming a passivation layer over the sacrificial region. In some embodiments, the method further comprises: forming a gate oxide along sidewalls of the first hole and the second hole.

[0139] The methods and components of the embodiments of the present disclosure have been fully described in the above examples and descriptions. It should be understood that any modification or change without departing from the spirit of the embodiments of the present disclosure is intended to be included in the protection scope of the embodiments of the present disclosure.

[0140] In addition, the scope of the present application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, and material compositions, modes, methods, and steps described in the specification. As will be readily understood by those skilled in the art from the embodiments disclosed herein, according to the embodiments disclosed herein, processes, machines, manufactures, material compositions, modes, methods, or steps currently existing or to be developed in the future that implement substantially the same functions as the corresponding embodiments described herein or achieve substantially the same results may be utilized.

[0141] Therefore, the appended claims are intended to include within their scope the process, machine, manufacture, composition of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and any combination of various claims and embodiments is within the scope of the disclosed embodiments.

Claims

1. An image sensor, comprising: substrate; as well as A gate electrode, disposed near the first side of the substrate, comprises: a first gate portion disposed on the first side of the substrate; a second gate portion disposed in the substrate and connected to the first gate portion; and a third gate portion disposed below and connected to the second gate portion, The first width of the first gate portion is greater than the second width of the second gate portion, and the third width of the third gate portion is greater than the second width.

2. The image sensor according to claim 1, further comprising: A pixel region is disposed in the substrate, wherein the third gate portion has a first surface located in the pixel region.

3. The image sensor according to claim 2, wherein: The third gate portion is partially embedded in the pixel region.

4. The image sensor according to claim 1, wherein: The third gate portion is located at a first height different from a second height of the first gate portion.

5. The image sensor according to claim 1, further comprising: A spacer surrounds the first gate portion and is spaced apart from the second gate portion and the third gate portion.

6. The image sensor according to claim 1, wherein: The third gate portion has a first surface, the first surface has a fourth width, and the fourth width is smaller than the third width of the third gate portion.

7. The image sensor according to claim 6, wherein: The third gate portion has a diamond-shaped profile.

8. The image sensor according to claim 6, further comprising: A gate oxide is disposed along sidewall surfaces of the third gate portion and the first surface.

9. An image sensor, comprising: a substrate having a first side; as well as a gate electrode including a gate portion, wherein the gate portion is buried in the substrate, wherein the gate portion has a first surface and a second surface, the first surface and the second surface face opposite directions to each other and are both substantially parallel to the first side of the substrate, and The first surface and the second surface of the gate portion are spaced apart from the first side of the substrate.

10. A method for manufacturing an image sensor, comprising: forming a pixel region in a substrate; forming a sacrificial region between the first side of the substrate and the pixel region; removing a portion of the substrate between the first side and the sacrificial region to form a first hole having a first width; removing the sacrificial area to form a second hole communicating with the first hole and having a second width greater than the first width; as well as A gate electrode is formed having a first gate portion located on the first side, a second gate portion located in the first hole, and a third gate portion located in the second hole.

Images