Preparation method of back structure layer of passivation contact cell and passivation contact cell

Abstract

The invention relates to a preparation method for a back structure layer of a passivation contact cell and the passivation contact cell, and the method comprises the steps: firstly, selecting a monocrystalline silicon wafer, removing a BSG layer at the back and the edge, and sequentially growing a tunneling oxide layer and an intrinsic polycrystalline silicon layer at the back of the silicon wafer; secondly, forming a selective polycrystalline silicon layer based on the intrinsic polycrystalline silicon layer; and finally, forming a passivation anti-reflection film layer on the outer doping structure layer. On one hand, parasitic absorption of heavy doping on light is reduced by the polycrystalline silicon layer in the non-metal region, the light utilization rate is improved, and the photoelectric conversion efficiency is improved; the heavy doping is more favorable for forming better ohmic contact with a metal electrode, so that the contact resistivity is reduced; on the other hand, carbon or oxygen or nitrogen elements are doped, the activity of phosphorus atoms is reduced, Auger recombination and SRH recombination are reduced, meanwhile, H escape can be inhibited by forming C-H chemical bonds, and surface passivation can be promoted.

Description

[0001] This application is a divisional application with an application date of August 22, 2024, application number 2024111542695, and name: A passivated contact cell with a selective polysilicon layer and a preparation method. Technical Field

[0002] The invention belongs to the technical field of solar cells, and in particular relates to a method for preparing a back structural layer of a passivation contact cell, and also relates to a passivation contact cell. Background Art

[0003] The emergence of tunneling oxide passivated contact (TOPCon) solar cells has attracted great attention to high-efficiency crystalline silicon solar cell technology. In 2013, the Frauhofer Institute in Germany introduced the concept of TOPCon technology. The cell uses N-type silicon as the substrate material and consists of an ultra-thin silicon oxide layer and a highly doped polysilicon layer. Since the tunneling potential of the tunneling oxide layer (4.5eV) is higher than the tunneling potential of electrons (3.1eV), this can reduce the carrier recombination between the metal electrode and silicon, so electrons are more likely to tunnel and be collected; another function of the tunneling oxide layer is full-area passivation. The excellent passivation ability further improves the efficiency of TOPCon solar cells. At present, the photoelectric conversion efficiency record of TOPCon cells has exceeded 26.5%.

[0004] At present, the efficiency of PERC cells has reached its theoretical limit. HJT cells, TOPCon cells and BC cells are expected to replace PERC cells and become the mainstream solar cell structures. Compared with the other two types of cells, TOPCon cells have unique advantages in manufacturing process and are highly compatible with PERC cells. They only need to add additional boron diffusion equipment, tunneling layers and polysilicon deposition equipment, which greatly reduces the cost of solar cell iterations. In addition, with the continuous development of various processing techniques and equipment, the commercialization of TOPCon cells has made great progress, making this technology the current leader in the global photovoltaic market.

[0005] TOPCon cells use a tunneling oxide layer + doped polysilicon layer passivation contact structure. Since the doped polysilicon layer itself has serious parasitic absorption, this tunneling layer + passivation layer structure is only used on the back of the TOPCon cell. The current industrialized tunneling oxide layer thickness is 1-2nm, and the doped polysilicon layer thickness is 100-150nm. That is, the selective polysilicon layer structure reduces the free carrier absorption and direct bandgap absorption on the back of the cell. Compared with the conventional cell structure, the short-circuit current density (Jsc) is increased by about 1.2mA / cm 2At the same time, in order to further reduce the negative impact of the parasitic absorption of the doped polysilicon layer itself on the electrical performance of the battery, some processing technologies that can form selectively doped polysilicon layers have emerged in recent years. At present, the mainstream of this type of technology is mainly divided into two categories: one is to use an ultraviolet picosecond laser to oxidize the surface of the phosphorus-doped polysilicon layer using laser to form a SiOx mask layer, and then use tetramethylammonium hydroxide (TMAH) solution to etch away the polysilicon layer without mask blocking, and finally use hydrofluoric acid (HF) solution to etch away the SiOx mask layer to form phosphorus-doped polysilicon layers of different thicknesses; the second is to use a picosecond laser to directly use laser to thin and ablate the doped polysilicon layer, thereby forming phosphorus-doped polysilicon layers of different thicknesses.

[0006] Therefore, the formation of the selective polysilicon layer structure has the following technical defects:

[0007] (1) Heavily doped polysilicon covers the entire back surface of the TOPCon cell. This part of the structure has a large light absorption coefficient for long-wave light. This type of absorption is called free carrier absorption (FCA), which is invalid absorption. The greater the thickness of the doped polysilicon or the higher the doping concentration, the more severe the FCA absorption and the lower the photoelectric conversion efficiency.

[0008] (2) Using ultraviolet laser to oxidize the polysilicon layer to form a local mask, and then using a wet process to remove the polysilicon layer without mask coverage to form a selective polysilicon layer (the polysilicon layer in the metal area is thick, and the polysilicon layer in the non-metal area is thin). This technology uses laser to generate an oxide layer that is not dense enough. In the process of removing polysilicon with alkaline solution, polysilicon in some areas below the oxide layer will also be removed. At the same time, the greater the power used in laser oxidation, the greater the thickness of the oxide layer formed to a certain extent. In this process, the laser will cause greater damage to the phosphorus-doped polysilicon layer at the bottom of the oxide layer, resulting in a decrease in the original passivation effect.

[0009] (3) Using laser to directly thin polysilicon to form a selective polysilicon layer. This method has relatively simple process steps, but has high requirements for laser equipment. At the same time, this method requires the removal of nearly 95% of the polysilicon layer on the back surface of the battery cell. The single-chip processing time is long and the production capacity is low, which is not suitable for industrial promotion. Summary of the invention

[0010] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a new method for preparing the back structure layer of a passivated contact battery.

[0011] Meanwhile, the invention also relates to a passivation contact battery.

[0012] In order to solve the above technical problems, the technical solution adopted by the present invention is as follows:

[0013] A method for preparing a back structure layer of a passivated contact battery comprises the following steps:

[0014] First, a single-crystal silicon wafer is selected to remove the BSG layer on the back and edge, and a tunnel oxide layer and an intrinsic polysilicon layer are grown on the back of the silicon wafer in sequence;

[0015] Secondly, a selective polysilicon layer is formed based on the intrinsic polysilicon layer, which includes a first doped polysilicon layer, a second doped polysilicon layer and a third doped polysilicon layer, wherein the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer constitute inner and outer doped structural layers with different concentrations of phosphorus atoms, and the doped polysilicon layer with the highest concentration of phosphorus atoms corresponds to the metal region, and carbon, oxygen or nitrogen elements are doped only in the doped polysilicon layer with the second highest concentration of phosphorus atoms, and the non-metallic region corresponding to the outer doped structural layer, the doped polysilicon layer with the highest concentration of phosphorus atoms and the doped polysilicon layer with the second highest concentration of phosphorus atoms constitute the outer doped structural layer, and the doped polysilicon layer with the lowest concentration of phosphorus atoms constitutes the inner doped structural layer;

[0016] Finally, a passivation anti-reflection film layer is formed on the external doping structure layer.

[0017] According to a specific implementation and preferred aspect of the present invention, the selective polysilicon layer forming step includes: first, growing a carbon-doped polysilicon layer on the back of the intrinsic polysilicon layer; second, slotting the carbon-doped polysilicon layer corresponding to the metal region; finally, phosphorus diffusion treatment, atoms enter the intrinsic polysilicon layer to form a first doped polysilicon layer and a second doped polysilicon layer, phosphorus atoms enter the carbon-doped polysilicon layer to form a third doped polysilicon layer, wherein the first doped polysilicon layer and the third doped polysilicon layer correspond to the metal region and the non-metal region respectively, and the concentration of phosphorus atoms in the selective polysilicon layer is ranked as the first doped polysilicon layer> the third doped polysilicon layer> the second doped polysilicon layer. Laser slotting is used for processing and forming, that is, the laser needs to open and remove only the polysilicon layer of the outer carbon-doped part of the subsequent metallization area, and the inner intrinsic polysilicon is not damaged, and there is no need to use a wet process to etch the surface structure, so there is no problem of damaging the polysilicon in the metallization area, and the original passivation performance is not affected. At the same time, carbon has an excellent ability to capture hydrogen atoms, which helps to passivate defects and improve passivation performance.

[0018] Preferably, a UV picosecond or nanosecond laser with a wavelength of 200 to 600 nm is used, a laser frequency of 50 to 300 KHz, a laser scanning speed of 5 to 25 m / s, and an energy density of 0.1 to 5 J / cm 2 , remove the carbon-doped polysilicon layer in the back metal area, and the width of the removal is 60-100 μm, corresponding to the metal gate line area. In some specific embodiments, a 355 nm violet laser or a 532 nm green laser is preferred.

[0019] Alternatively, the selective polysilicon layer forming step includes: first, placing the back side of the silicon wafer on a graphite carrier with a mask pattern; second, using ion implantation equipment, depositing carbon atoms onto the surface of the intrinsic polysilicon of the silicon wafer, and under the mask, making the polysilicon in the non-metallic area all carbon-doped polysilicon layers, and the metal area all intrinsic polysilicon layers; finally, performing phosphorus diffusion treatment, wherein the atoms enter the intrinsic polysilicon layer to form a first doped polysilicon layer and a second doped polysilicon layer, and the phosphorus atoms enter the carbon-doped polysilicon layer to form a third doped polysilicon layer; wherein the first doped polysilicon layer and the third doped polysilicon layer correspond to the metal area and the non-metallic area respectively, the second doped polysilicon layer covers the entire back side of the tunneling oxide layer, and the concentration of phosphorus atoms in the selective polysilicon layer is arranged as the first doped polysilicon layer> the third doped polysilicon layer> the second doped polysilicon layer. The process is carried out by masking to deposit carbon atoms on the surface of intrinsic polysilicon of silicon wafer, so that the surface structure of intrinsic polysilicon forms carbon-doped polysilicon due to the doping of carbon atoms. At this time, because the graphite carrier acts as a mask, the polysilicon in the non-metallic area is all carbon-doped polysilicon, and the metal area is all intrinsic polysilicon. Due to the doping of carbon on the polysilicon in the selected area, a passivation contact of the selective polysilicon layer is formed. After phosphorus diffusion treatment, the phosphorus doping concentration of the polysilicon in the non-metallized area is low, and the phosphorus doping concentration of the polysilicon in the metallized area is high. This can reduce the parasitic absorption coefficient of the polysilicon layer in the non-metallized area due to the reduction of doping concentration, improve the utilization rate of light, and thus improve the photoelectric conversion efficiency of the battery. The heavily doped structure of the metallized area helps to form a better ohmic contact with the metal electrode and reduce the contact resistivity; due to the doping of carbon elements, it is beneficial to suppress the escape of H by forming a CH chemical bond, which is more conducive to promoting surface passivation and increasing the passivation performance of the battery.

[0020] Alternatively, the selective polysilicon layer forming steps include: first, placing the back side of the silicon wafer on a graphite carrier with a mask pattern, and then transferring the graphite carrier into a plate chamber of a physical vapor deposition device; second, magnetron sputtering a carbon-doped silicon target, the carbon-doped silicon target is located below the graphite carrier, and the magnetron sputtering process allows silicon atoms to desorb from the target and move upward to deposit on the back side of the silicon wafer, forming a deposition on the silicon wafer in the graphite hollow area, forming a carbon-doped polysilicon layer on the surface of the non-metallic area, and the surface of the metal area is bare The exposed intrinsic polysilicon layer; finally, phosphorus diffusion treatment is performed, and atoms enter the intrinsic polysilicon layer to form a first doped polysilicon layer and a second doped polysilicon layer, and phosphorus atoms enter the carbon-doped polysilicon layer to form a third doped polysilicon layer, wherein the first doped polysilicon layer and the third doped polysilicon layer correspond to the metal region and the non-metal region respectively, and the second doped polysilicon layer covers the entire back side of the tunneling oxide layer, and the concentration of phosphorus atoms in the selective polysilicon layer is ranked as the first doped polysilicon layer>the third doped polysilicon layer>the second doped polysilicon layer.

[0021] Preferably, under the condition of oxygen, phosphorus oxychloride decomposes at high temperature to generate phosphorus pentachloride and phosphorus pentoxide, and the generated phosphorus pentoxide reacts with silicon at the diffusion temperature to generate silicon dioxide and phosphorus atoms. In short, phosphorus diffuses to form polysilicon structures with different phosphorus doping concentrations, that is, under the condition of oxygen, phosphorus oxychloride (POCl3) decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5), and the generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms (P), and the phosphorus atoms enter the carbon-doped polysilicon layer to form a carbon / phosphorus-doped polysilicon layer, and the phosphorus atoms enter the intrinsic polysilicon layer to form a phosphorus-heavy doped polysilicon layer. Due to the role of carbon atoms in inhibiting the activity of phosphorus atoms, the phosphorus doping concentration of the carbon / phosphorus-doped polysilicon layer is lower than that of the phosphorus-heavy doped polysilicon layer, so there is a difference in phosphorus atom doping concentration between the two.

[0022] In some specific embodiments, the concentration of the first doped polysilicon layer is 4.0 to 8.0E+20 cm -3 ; The concentration of the third doped polysilicon layer is 0.8~1.0E+20cm -3 ; The concentration of the second doped polysilicon layer is 1.0~4.0E+19cm -3 .

[0023] In addition, 3% to 10% HF is used to remove the BSG layer on the back and edge of the silicon wafer after boron diffusion; then the back of the silicon wafer is polished by a wet method to form a flat surface, and the reaction temperature is 60±10°C; low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition is used to make silane react on the back of the silicon wafer and deposit and grow an ultra-thin tunneling oxide layer and a polysilicon layer.

[0024] Furthermore, the structural material of the tunnel oxide layer is SiO2, the deposition reaction temperature is 400-600°C, the thickness is selected to be 0.5nm-2.5nm, and the deposition reaction temperature of the intrinsic polysilicon is 500-650°C, and the thickness is selected to be 60-200nm.

[0025] Preferably, silane is used as the silicon source and methane is used as the carbon source, and the flow rate ratio of silane:methane is maintained at 100:100-300 to obtain a carbon-doped polysilicon layer; the carbon-doped polysilicon layer is a nitrogen-doped polysilicon layer or an oxygen-doped polysilicon layer, and the thickness is 20-100 nm, wherein silane is used as the silicon source and carbon dioxide is used as the oxygen source, and the flow rate ratio of silane:carbon dioxide is maintained at 100:20-100 to form oxygen doping; silane is used as the silicon source and ammonia is used as the nitrogen source, and the flow rate ratio of silicon source:ammonia is maintained at 100:20-100 to form nitrogen doping.

[0026] According to another specific embodiment and preferred aspect of the present invention, 3% to 10% HF is used to remove the BSG layer on the back and edge of the silicon wafer after boron expansion, and then the back of the silicon wafer is polished by wet method to form a plane, and the reaction temperature is 60±10°C. In short, the back of the battery is wet polished, which uses 3% to 10% HF to remove the BSG layer on the back and edge of the silicon wafer after boron expansion, and then the back of the silicon wafer is polished by a wet additive + KOH&NaOH + water solution (ratio 1:5:90), and the reaction temperature is 60±10°C.

[0027] Preferably, low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) is used to make silane react on the back side (i.e., the plane) of the silicon wafer and deposit and grow an ultra-thin tunnel oxide layer and a polysilicon layer. Preferably, the structural material of the tunnel oxide layer is SiO2, the deposition reaction temperature is 400-600°C, the thickness is selected to be 0.5nm-2.5nm, and the deposition reaction temperature of intrinsic polysilicon is 500-650°C, and the thickness is selected to be 60-200nm. In short, low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) is used to make silane (SiH4) react on the back side of the silicon wafer and deposit and grow an ultra-thin tunnel oxide layer and a polysilicon layer under low pressure conditions. The structural material of the ultra-thin tunneling oxide layer is SiO2, the deposition reaction temperature is 400-600°C, the thickness is selected to be 0.5nm-2.5nm, the deposition reaction temperature of intrinsic polysilicon is 500-650°C, and the thickness is selected to be 60-200nm.

[0028] In addition, a carbon-doped polysilicon layer is obtained by low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition, with silane as the silicon source and methane as the carbon source, and the flow rate ratio of silane:methane is maintained at 100:100-300. Preferably, the carbon-doped polysilicon layer can be a nitrogen-doped polysilicon layer or an oxygen-doped polysilicon layer, and the thickness is 20-100 nm, wherein silane is used as the silicon source, carbon dioxide is used as the oxygen source, and the flow rate ratio of silane:carbon dioxide is maintained at 100:20-100 to form oxygen doping; silane is used as the silicon source, ammonia is used as the nitrogen source, and the flow rate ratio of silicon source:ammonia is maintained at 100:20-100 to form nitrogen doping.

[0029] Preferably, the passivation anti-reflection film layer is at least one of an aluminum oxide layer, a silicon nitride layer, a silicon dioxide layer, and a silicon oxynitride layer. Preferably, an aluminum oxide + silicon carbide passivation anti-reflection film stack design is adopted, wherein the preferred thickness of aluminum oxide is 2 to 10 nm, the preferred thickness of silicon nitride is 20 to 50 nm, and the refractive index of silicon nitride is 2.1 to 2.2.

[0030] Another technical solution of the present invention is: a passivated contact cell, which includes a single crystal silicon wafer, a back structure layer and a front structure layer, a front metal electrode and a back metal electrode, in particular, the back structure layer is made by the above-mentioned preparation method. At the same time, based on the preparation of the back structure layer of the passivated contact cell, this step is then combined with the preparation method of the passivated contact cell, specifically referring to the following steps:

[0031] 1) Select a single crystal silicon wafer for surface treatment and then form a velvet surface;

[0032] 2) forming a boron-doped emitter on the surface of the textured silicon wafer;

[0033] 3) Remove the BSG layer on the back and edges;

[0034] 4) Growing a tunnel oxide layer and an intrinsic polysilicon layer in sequence on the back of the silicon wafer;

[0035] 5) forming a selective polysilicon layer based on the intrinsic polysilicon layer, which includes a first doped polysilicon layer, a second doped polysilicon layer and a third doped polysilicon layer, wherein the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer constitute inner and outer doped structural layers with different concentrations of phosphorus atoms, and the doped polysilicon layer with the highest concentration of phosphorus atoms corresponds to the metal region, the doped polysilicon layer with the second highest concentration of phosphorus atoms is doped with carbon, oxygen or nitrogen elements and corresponds to the non-metallic region of the outer doped structural layer and is located in the outer doped structural layer, and the doped polysilicon layer with the lowest concentration of phosphorus atoms constitutes the inner doped structural layer;

[0036] 6) Passivation anti-reflection layer is formed on the front and back surfaces;

[0037] 7) Printing and sintering of metal electrodes on the front and back surfaces, wherein the metal electrodes correspond to the metal areas and are formed on the doped polysilicon layer with the highest phosphorus atom concentration.

[0038] In short, ①, the structure of the multi-layer polysilicon stack in the non-metallic area, from the inside to the outside, is a phosphorus lightly doped polysilicon layer, a phosphorus heavily doped polysilicon layer, and a carbon / phosphorus medium doped polysilicon layer. Different from the single-layer polysilicon structure on the back of the commercial TOPCon battery, the outer layer of polysilicon is more conducive to increasing the passivation performance of the battery due to the carbon doping. ②, the TOPCon battery in the present invention is doped with C element in the non-metallic outer layer of polysilicon, which helps to suppress the activity of P element, thereby forming phosphorus light doping in the non-metallic area. Since there is no carbon-doped polysilicon in the metal area, the deposition and diffusion of P element is not affected, forming phosphorus heavy doping, which can reduce the parasitic absorption of light by heavy doping in the polysilicon layer in the non-metallic area, improve the utilization rate of light, and thus improve the photoelectric conversion efficiency of the battery. ③, the doping of carbon element is conducive to the formation of CH chemical bonds to suppress the escape of H, which is conducive to promoting surface passivation. ④, because the metal area adopts a heavy doping method, it is more conducive to forming a better ohmic contact with the metal electrode and reducing the contact resistivity.

[0039] Due to the implementation of the above technical solution, the present invention has the following advantages compared with the prior art:

[0040] The formation of the existing selective polysilicon layer structure, due to the heavy doped polysilicon covering the entire area on the back of the TOPCon cell, this part of the structure has a large light absorption coefficient for long-wave light. This type of absorption is called free carrier absorption (FCA), which is invalid absorption. In addition, the greater the thickness of the doped polysilicon or the higher the doping concentration, the more severe the FCA absorption, the lower the photoelectric conversion efficiency, and so on. The present invention cleverly solves the various existing deficiencies by overall designing the preparation method of the selective polysilicon layer structure and the passivated contact cell structure. After adopting the preparation method, a double-layer polysilicon stacking method is sequentially adopted to form a selective polysilicon layer based on the intrinsic polysilicon layer, which includes a first doped polysilicon layer, a second doped polysilicon layer and a third doped polysilicon layer, wherein the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer constitute inner and outer doped structural layers with different concentrations of phosphorus atoms, and the doped polysilicon layer with the highest concentration of phosphorus atoms corresponds to the metal region, the doped polysilicon layer with the second highest concentration of phosphorus atoms is doped with carbon, oxygen or nitrogen elements, and corresponds to the non-metallic region of the outer doped structural layer and is located in the outer doped structural layer, and the doped polysilicon layer with the lowest concentration of phosphorus atoms constitutes the inner doped structural layer. Therefore, on the one hand, the present invention forms inner and outer doped layers in the phosphorus diffusion process, and corresponds to the metal region The different phosphorus atom contents in the polysilicon layer and the non-metallic region not only reduce the parasitic absorption of light by heavy doping in the polysilicon layer in the non-metallic region, improve the utilization rate of light, and thus improve the photoelectric conversion efficiency of the battery; and because the metal region adopts the heavy doping method, it is more conducive to forming a better ohmic contact with the metal electrode, reducing the contact resistivity, and also beneficial to increasing the passivation performance of the battery; on the other hand, doping carbon, oxygen or nitrogen elements in the polysilicon layer can reduce the activity of phosphorus atoms, reduce Auger recombination and SRH recombination, and thus inhibit the advancement of phosphorus atoms in the non-metallic region during the phosphorus diffusion process. At the same time, doping with carbon, oxygen or nitrogen elements is also beneficial to inhibit the escape of H by forming CH chemical bonds, which is more conducive to promoting surface passivation and increasing the passivation performance of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagram of a passivation contact cell structure with a selective polysilicon layer of Example 1 (i.e., step 7 of the passivation contact cell structure preparation method); Schematic diagram of a passivation contact cell structure with a selective polysilicon layer of Example 3);

[0042] Figure 2 This is a schematic diagram of step 1) of the method for preparing a passivated contact battery structure of Example 1;

[0043] Figure 3 This is a schematic diagram of step 2) of the method for preparing a passivated contact battery structure in Example 1;

[0044] Figure 4This is a schematic diagram of step 3) of the method for preparing the passivated contact battery structure of Example 1;

[0045] Figure 5 This is a schematic diagram of step 4) of the method for preparing a passivated contact battery structure in Example 1;

[0046] Figure 6 It is a schematic diagram of state 5.1 in step 5) of the method for preparing a passivated contact battery structure in Example 1;

[0047] Figure 7 It is a schematic diagram of state 5.2 in step 5) of the method for preparing the passivated contact battery structure of Example 1;

[0048] Figure 8 It is a schematic diagram of state 5.3 in step 5) of the method for preparing a passivated contact battery structure in Example 1;

[0049] Fig. 9 This is a schematic diagram of step 6) of the method for preparing a passivated contact battery structure in Example 1;

[0050] Fig.10 is a schematic diagram of a passivation contact cell structure with a selective polysilicon layer according to Example 2;

[0051] Fig.11 It is the schematic diagram of 5.2 in step 5) of the method for preparing the passivated contact battery structure of Example 2;

[0052] Fig.12 It is the schematic diagram of 5.3 in step 5) of the method for preparing the passivated contact battery structure of Example 2;

[0053] Fig.13 It is the schematic diagram of 5.2 in step 5) of the method for preparing the passivated contact battery structure of Example 3;

[0054] Fig.14 A schematic diagram of a passivated contact battery structure of a comparative example;

[0055] Among them: 1. N-type single crystal silicon wafer; 2. Boron-doped emitter; 3. Tunneling oxide layer; 4. Intrinsic polysilicon layer; 5. Carbon-doped polysilicon layer; 6. Carbon / phosphorus-doped polysilicon layer; 7. Phosphorus-heavy doped polysilicon layer; 8. Phosphorus-lightly doped polysilicon layer; 91, 92, passivation layer; 101, 102, anti-reflection layer; 111, 112, metal electrode; 12, graphite carrier; 121, mask covering layer; 122, hollow layer; 13, phosphorus-doped polysilicon layer; 14, back passivation layer; 15, front passivation layer; 16, back anti-reflection layer; 17, front anti-reflection layer; 18, back metal electrode; 19, front metal electrode. DETAILED DESCRIPTION

[0056] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present invention, so the present invention is not limited by the specific embodiments disclosed below.

[0057] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0058] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0059] In the present invention, unless otherwise clearly defined and specified, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] In the invention, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being “above”, “above”, or “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below”, or “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0061] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation method.

[0062] Example 1

[0063] like Figure 1 As shown, the passivation contact cell structure involved in this embodiment includes an N-type single crystal silicon wafer 1, a front structure layer formed on the front side of the N-type single crystal silicon wafer 1, and a back structure layer formed on the back side of the N-type single crystal silicon wafer 1.

[0064] Combination Figures 2 to 9 , a method for preparing a passivation contact cell structure with a selective polysilicon layer (laser grooving method), comprising the following steps:

[0065] 1) Wet-clean the N-type monocrystalline silicon wafer 1 to remove the damaged layer on the surface of the silicon wafer, clean the metal impurities and oil on the surface and make a velvet surface. Specifically, at a reaction temperature of 70±10°C, use a 10% volume fraction of sodium hydroxide solution to corrode the damaged layer on the surface of the silicon wafer caused by wire cutting, and the etching thickness on both sides is about 10μm. Then, use an alkaline solution + velvet additive wet chemical process to produce a random pyramid surface texture, and perform standard RCA wet cleaning. The height of the obtained random pyramid is about 0.5~2μm;

[0066] 2) Performing a double-sided boron diffusion process on the textured silicon wafer to form a surface boron-doped emitter 2, wherein the boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak temperature of the diffusion is 1000-1100°C. After the boron diffusion process, the boron emitter square resistance obtained by the four-probe test method is 100Ω / sq-250Ω / sq;

[0067] 3) 3% to 10% HF is used to remove the BSG layer on the back and edge of the silicon wafer after boron diffusion, and then the back of the silicon wafer is polished to form a flat surface with a wet additive + (KOH & NaOH) + water solution (ratio 1:5:90), and the reaction temperature is 60±10℃;

[0068] 4) using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) to react silane (SiH4) on the back side (plane) of the silicon wafer under low pressure conditions and deposit and grow an ultra-thin tunneling oxide layer 3 and an intrinsic polysilicon layer 4, wherein the structural material of the ultra-thin tunneling oxide layer 2 is SiO2, the deposition reaction temperature is 400-600°C, the thickness is selected to be 0.5nm-2.5nm, and the deposition reaction temperature of the intrinsic polysilicon layer 4 is 500-650°C, and the thickness is selected to be 60-200nm;

[0069] 5) includes: 5.1. On the intrinsic polysilicon layer 4, low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) is used, silane (SiH4) is used as a silicon source, methane (CH4) is used as a carbon source, and the flow rate ratio of silane: methane is maintained at 100:100-300, and then annealing is performed at a reaction temperature of 800-900°C for 30 minutes to obtain a carbon-doped polysilicon layer 5; when a specification is required, in this process, in addition to carbon doping to meet the design requirements, doping with elements such as oxygen and nitrogen can also meet the design requirements. In the process of oxygen doping, silane is used as a silicon source, carbon dioxide is used as an oxygen source, and the flow rate ratio of silane: methane is maintained at 100:20-100; in the process of nitrogen doping, silane is used as a silicon source, ammonia is used as a nitrogen source, and the flow rate ratio of silicon source: ammonia is maintained at 100:20-100. After annealing, the thickness of the carbon (nitrogen, oxygen) doped polysilicon is selected to be 20-100nm; 5.2, using a violet laser with a wavelength of 355nm or a green laser with a wavelength of 532nm, a laser frequency of 50-300KHz, a laser scanning speed of 5-25m / s, and an energy density of the laser treatment of 0.1-5J / cm 2, remove the carbon-doped polysilicon layer 5 in the back metal area, and the width of a single gate line etched by laser is 60 to 100 μm; 5.3. Under the condition of oxygen, phosphorus oxychloride decomposes at high temperature to generate phosphorus pentachloride and phosphorus pentoxide. The generated phosphorus pentoxide reacts with silicon at the diffusion temperature to generate silicon dioxide and phosphorus atoms. In short, phosphorus diffuses to form polysilicon structures with different phosphorus doping concentrations, that is, under the condition of oxygen, phosphorus oxychloride (POCl3) decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5). The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms (P). The phosphorus atoms enter the carbon-doped polysilicon layer to form a carbon / phosphorus medium-doped polysilicon layer 6 (the third doped polysilicon layer), and the phosphorus atoms enter the intrinsic polysilicon layer to form a phosphorus heavily doped polysilicon layer 7 (the first doped polysilicon layer). Due to the presence of carbon atoms, the activity of phosphorus atoms is inhibited. The phosphorus doping concentration of the carbon / phosphorus medium-doped polysilicon layer 6 is lower than that of the phosphorus heavily-doped polysilicon layer 7, so there is a difference in the phosphorus atom doping concentration between the two. At the same time, the phosphorus lightly-doped polysilicon layer 8 is formed on the back of the tunneling oxide layer 3, wherein the carbon / phosphorus medium-doped polysilicon layer 6 and the phosphorus heavily-doped polysilicon layer 7 constitute an outer doping layer structure, and corresponding to the non-metallic region and the metal region, the phosphorus lightly-doped polysilicon layer 8 constitutes an inner doping layer structure, and the concentration of phosphorus atoms in the selective polysilicon layer is ranked as the first doped polysilicon layer> the third doped polysilicon layer> the second doped polysilicon layer, and the concentration of the first doped polysilicon layer is 6.2E+20cm -3 ; The concentration of the third doped polysilicon layer is 0.9E+20cm -3 ; The concentration of the second doped polysilicon layer is 2.5E+19cm -3 ;

[0070] 6) forming a passivation anti-reflection layer on the front and back surfaces, preferably, the passivation anti-reflection layer adopts a laminated design of a passivation layer (91, 92) of aluminum oxide + silicon carbide and an anti-reflection layer (101, 102), wherein the preferred thickness of aluminum oxide is 2 to 10 nm, the preferred thickness of silicon nitride is 20 to 50 nm, and the refractive index of silicon nitride is 2.1 to 2.2;

[0071] 7) Printing and sintering of the metal electrodes (111, 112) on the front and back surfaces, wherein the printing is performed by screen printing or laser transfer, and the width of the metal grid lines on the front and back surfaces is 10-60 μm, the height is 3-10 μm, and the sintering temperature is 700-850°C. Printing metallization patterns on the front and back surfaces (printing is performed by screen printing or laser transfer, etc.), the metal grid lines can be made of silver paste, silver aluminum paste or other metal materials (aluminum, copper, titanium, nickel, etc.), the width of the metal grid lines on the front and back surfaces is 10-60 μm, the height is 3-10 μm, and the sintering temperature is 700-850°C; or laser-assisted enhanced sintering process is used to enhance contact and reduce contact resistivity.

[0072] Example 2

[0073] like Figures 10 to 12 As shown, the passivation contact cell structure involved in this embodiment includes an N-type single crystal silicon wafer 1, a front structure layer formed on the front side of the N-type single crystal silicon wafer 1, and a back structure layer formed on the back side of the N-type single crystal silicon wafer 1, wherein the back structure layer is different from that in Example 1, and the preparation method is also different.

[0074] Specifically, the method for preparing the passivation contact cell structure with a selective polysilicon layer (mask + ion implantation method) of this embodiment includes the following steps:

[0075] 1) Wet-clean the N-type monocrystalline silicon wafer 1 to remove the damaged layer on the surface of the silicon wafer, clean the metal impurities and oil on the surface and make a velvet surface. Specifically, at a reaction temperature of 70±10°C, use a 10% volume fraction of sodium hydroxide solution to corrode the damaged layer on the surface of the silicon wafer caused by wire cutting, and the etching thickness on both sides is about 10μm. Then, use an alkaline solution + velvet additive wet chemical process to produce a random pyramid surface texture, and perform standard RCA wet cleaning. The height of the obtained random pyramid is about 0.5~2μm;

[0076] 2) Performing a double-sided boron diffusion process on the textured silicon wafer to form a surface boron-doped emitter 2, wherein the boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak temperature of the diffusion is 1000-1100°C. After the boron diffusion process, the boron emitter square resistance obtained by the four-probe test method is 100Ω / sq-250Ω / sq;

[0077] 3) Use 3% to 10% HF to remove the BSG layer on the back and edge of the silicon wafer after boron expansion, and then polish the back of the silicon wafer with a wet additive + (KOH & NaOH) + water solution (ratio 1:5:90), and the reaction temperature is 60±10℃;

[0078] 4) using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) to react silane (SiH4) on the back of the silicon wafer under low pressure conditions and deposit and grow an ultra-thin tunneling oxide layer 3 and an intrinsic polysilicon layer 4, wherein the structural material of the ultra-thin tunneling oxide layer 2 is SiO2, the deposition reaction temperature is 400-600°C, the thickness is selected to be 0.5nm-2.5nm, and the deposition reaction temperature of the intrinsic polysilicon layer 4 is 500-650°C, and the thickness is selected to be 60-200nm;

[0079] 5) includes: 5.1, placing the back side of the silicon wafer on a graphite carrier 12 with a mask pattern, wherein the structure of the graphite carrier 12 includes a mask covering layer 121 and a hollow layer 122, wherein the mask covering layer 121 corresponds to the metal area, and the width of the mask is 60 to 100 μm, and the hollow layer 122 corresponds to the non-metal area; 5.2, through ion implantation equipment, carbon atoms are deposited on the surface of the intrinsic polysilicon layer of the silicon wafer, so that the surface structure of the intrinsic polysilicon forms a carbon-doped polysilicon layer 5 because of the doping of carbon atoms. At this time, because the graphite carrier 12 acts as a mask, the polysilicon in the non-metallized domain is all carbon-doped polysilicon, and the metal area is all intrinsic polysilicon; 5.3, a phosphorus diffusion process is performed to form a selective polysilicon layer. At this time, the surface The carbon-doped polysilicon layer and the intrinsic polysilicon layer both have phosphorus atoms, which are converted into a carbon / phosphorus medium-doped polysilicon layer 6 (the third doped polysilicon layer) and a phosphorus heavily-doped polysilicon layer 7 (the first doped polysilicon layer), respectively. The phosphorus lightly-doped polysilicon layer 8 (the second doped polysilicon layer) covers the entire back side of the tunneling oxide layer 3, and the concentration of phosphorus atoms in the selective polysilicon layer is ranked as the first doped polysilicon layer>the third doped polysilicon layer>the second doped polysilicon layer (in short, the phosphorus lightly-doped polysilicon layer corresponds to the inner doping layer formed on the back side of the tunneling oxide layer, and the carbon / phosphorus medium-doped polysilicon layer and the phosphorus heavily-doped polysilicon layer are distributed in the non-metallic region and the metal region, and constitute an outer doping layer), wherein the concentration of the first doped polysilicon layer is 7.6E+20cm -3 ; The concentration of the third doped polysilicon layer is 0.88E+20cm -3 ; The concentration of the second doped polysilicon layer is 1.5E+19cm -3 ;

[0080] 6) forming a passivation anti-reflection layer on the front and back surfaces, preferably, the passivation anti-reflection layer adopts a laminated design of a passivation layer (91, 92) of aluminum oxide + silicon carbide and an anti-reflection layer (101, 102), wherein the preferred thickness of aluminum oxide is 2 to 10 nm, the preferred thickness of silicon nitride is 20 to 50 nm, and the refractive index of silicon nitride is 2.1 to 2.2;

[0081] 7) Printing and sintering of the metal electrodes (111, 112) on the front and back surfaces, wherein the printing is performed by screen printing or laser transfer, and the width of the metal grid lines on the front and back surfaces is 10-60 μm, the height is 3-10 μm, and the sintering temperature is 700-850°C. Printing metallization patterns on the front and back surfaces (printing is performed by screen printing or laser transfer, etc.), the metal grid lines can be made of silver paste, silver aluminum paste or other metal materials (aluminum, copper, titanium, nickel, etc.), the width of the metal grid lines on the front and back surfaces is 10-60 μm, the height is 3-10 μm, and the sintering temperature is 700-850°C; or laser-assisted enhanced sintering process is used to enhance contact and reduce contact resistivity.

[0082] Example 3

[0083] See also Figure 1 and Fig.13 As shown, the passivation contact cell structure involved in this embodiment includes an N-type single crystal silicon wafer 1, a front structure layer formed on the front side of the N-type single crystal silicon wafer 1, and a back structure layer formed on the back side of the N-type single crystal silicon wafer, wherein the structure is the same as that of Embodiment 1, and the difference lies in the preparation method.

[0084] Specifically, the preparation method of the passivation contact cell structure with a selective polysilicon layer (mask + physical vapor deposition method) of this embodiment includes the following steps:

[0085] 1) Wet-clean the N-type monocrystalline silicon wafer to remove the damaged layer on the surface of the silicon wafer, clean the metal impurities and oil on the surface and make a velvet surface. Specifically, at a reaction temperature of 70±10°C, use a 10% volume fraction of sodium hydroxide solution to corrode the damaged layer on the surface of the silicon wafer caused by wire cutting. The etching thickness on both sides is about 10μm. Then, a wet chemical process of alkaline solution + velvet additive is used to produce a random pyramid surface texture, and a standard RCA wet cleaning is performed. The height of the obtained random pyramid is about 0.5~2μm;

[0086] 2) Performing a double-sided boron diffusion process on the textured silicon wafer to form a boron-doped emitter, wherein the boron source used in the boron diffusion process is boron tribromide (BBr3) or boron trichloride (BCl3), and the peak temperature of the diffusion is 1000-1100°C. After the boron diffusion process, the boron emitter square resistance obtained by the four-probe test method is 100Ω / sq-250Ω / sq;

[0087] 3) Use 3% to 10% HF to remove the BSG layer on the back and edge of the silicon wafer after boron expansion, and then polish the back of the silicon wafer with a wet additive + (KOH & NaOH) + water solution (ratio 1:5:90), and the reaction temperature is 60±10℃;

[0088] 4) Using low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), silane (SiH4) is reacted on the back of the silicon wafer under low pressure conditions to deposit and grow an ultra-thin tunneling oxide layer and a polysilicon layer, wherein the structural material of the ultra-thin tunneling oxide layer is SiO2, the deposition reaction temperature is 400-600°C, the thickness is 0.5nm-2.5nm, and the deposition reaction temperature of intrinsic polysilicon is 500-650°C, and the thickness is selected to be 60-200nm;

[0089] 5) includes: 5.1. Placing the back of a silicon wafer on a graphite carrier with a mask pattern, and then transferring the graphite carrier into a plate chamber of a physical vapor deposition (PVD) device; 5.2. Magnetron sputtering a carbon-doped silicon target, the carbon-doped silicon target is located below the graphite carrier, and the magnetron sputtering process allows silicon atoms to desorb from the target and move upward to deposit on the back of the silicon wafer, forming a deposition on the silicon wafer in the graphite hollow area, and forming a carbon-doped polysilicon layer on the surface of the non-metallic area, so that the surface of the metal area is an exposed intrinsic polysilicon layer; 5.3. Under the condition of oxygen, phosphorus oxychloride decomposes at high temperature to generate phosphorus pentachloride and phosphorus pentoxide, and the generated phosphorus pentoxide reacts with silicon at the diffusion temperature to generate silicon dioxide and phosphorus atoms. In short, phosphorus diffuses to form polysilicon structures with different phosphorus doping concentrations, that is, under the condition of oxygen, phosphorus oxychloride (POCl3) decomposes at high temperature to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5), and the generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms (P), and the phosphorus atoms enter the carbon-doped polysilicon layer to form a carbon / phosphorus medium-doped polysilicon layer 6 (the third doped polysilicon layer), and the phosphorus atoms enter the intrinsic polysilicon layer to form a phosphorus heavily doped polysilicon layer. The carbon / phosphorus doped polysilicon layer 7 (the first doped polysilicon layer) has a phosphorus doping concentration lower than that of the heavily phosphorus doped polysilicon layer 7 due to the effect of carbon atoms inhibiting the activity of phosphorus atoms. Thus, there is a difference in phosphorus doping concentration between the two. At the same time, the portion corresponding to the non-metallic region constitutes a phosphorus lightly doped polysilicon layer 8, and the concentration of phosphorus atoms in the selective polysilicon layer is ranked as follows: the first doped polysilicon layer> the third doped polysilicon layer> the second doped polysilicon layer, wherein the concentration of the first doped polysilicon layer is 8.0E+20cm -3 ; The concentration of the third doped polysilicon layer is 1.0E+20cm -3 ; The concentration of the second doped polysilicon layer is 1.0E+19cm -3 ;

[0090] 6) forming a passivation anti-reflection layer on the front and back surfaces, preferably, the passivation anti-reflection layer adopts a laminated design of a passivation layer (91, 92) of aluminum oxide + silicon carbide and an anti-reflection layer (101, 102), wherein the preferred thickness of aluminum oxide is 2 to 10 nm, the preferred thickness of silicon nitride is 20 to 50 nm, and the refractive index of silicon nitride is 2.1 to 2.2;

[0091] 7) Printing and sintering of the metal electrodes (111, 112) on the front and back surfaces, wherein the printing is performed by screen printing or laser transfer, and the width of the metal grid lines on the front and back surfaces is 10-60 μm, the height is 3-10 μm, and the sintering temperature is 700-850°C. Printing metallization patterns on the front and back surfaces (printing is performed by screen printing or laser transfer, etc.), the metal grid lines can be made of silver paste, silver aluminum paste or other metal materials (aluminum, copper, titanium, nickel, etc.), the width of the metal grid lines on the front and back surfaces is 10-60 μm, the height is 3-10 μm, and the sintering temperature is 700-850°C; or laser-assisted enhanced sintering process is used to enhance contact and reduce contact resistivity.

[0092] Comparative Example 1

[0093] like Fig.14 As shown, the passivation contact cell structure involved in this comparative example 1 includes an N-type single crystal silicon wafer 1, a front structural layer formed on the front side of the N-type single crystal silicon wafer, a back structural layer formed on the back side of the N-type single crystal silicon wafer, a front metal electrode 19 and a back metal electrode 18, wherein the back structural layer is a single layer of polycrystalline silicon deposited and covers the entire area of ​​the back side of the cell, that is, the back structural layer includes a tunneling oxide layer 3, a phosphorus-doped polycrystalline silicon layer 13, a back passivation layer 14, and a back anti-reflection layer arranged in sequence from the inside to the outside, and the front structural layer includes a boron-doped emitter 2, a front passivation layer 15 and a front anti-reflection layer 17 arranged in sequence from the inside to the outside.

[0094] In short, the preparation scheme of the comparative example is basically the same as the steps of Example 1, with the difference being step 5). In this comparative example, double-layer polysilicon deposition (intrinsic polysilicon layer + carbon-doped polysilicon layer) is used before the phosphorus diffusion process, and the outer carbon-doped polysilicon is selective, while a single-layer polysilicon deposition is used to cover the entire area of ​​the back of the battery, i.e., to form a corresponding phosphorus-doped polysilicon layer.

[0095] Performance test: The batteries obtained in the above-mentioned Examples 1-3 and Comparative Example 1 were subjected to the following performance test, and the test method was: using an IV tester to test the battery photoelectric conversion efficiency and related electrical performance parameters under standard light power under a simulated solar light source (and the electrical performance data is the average value data of 100Pcs batteries of various samples). Specific test results are shown in Table 1 (Eta: conversion efficiency, Voc: open circuit voltage, Jsc: short circuit current density, FF: fill factor).

[0096] Table 1

[0097] sample Eta(%) Voc(mV) <![CDATA[Jsc(mA / cm 2 )]]> FF(%) Example 1 25.03 725 40.84 84.52 Example 2 25.00 724 40.85 84.53 Example 3 24.96 723 40.84 84.52 Comparative Example 1 24.77 722 40.60 84.50

[0098] Based on the data in Table 1, it can be seen that compared with Comparative Example 1, Examples 1 to 3 have the following advantages:

[0099] 1. Due to the doping of carbon elements, it is beneficial to suppress the escape of H by forming CH chemical bonds, which is more conducive to promoting surface passivation, and the open circuit voltage Voc is improved compared with the comparative example;

[0100] 2. Due to the decrease in doping concentration, the parasitic absorption coefficient of the polysilicon layer in the non-metallized area decreases, which improves the utilization rate of light. Therefore, the short-circuit current density Jsc will be 0.2+mA / cm 2 Advantages of left and right;

[0101] 3. The heavily doped structure of the metallized area helps to form a better ohmic contact with the metal electrode and reduce the contact resistivity. The filling factor FF of this structure has a certain advantage over the comparative example.

[0102] 4. The photoelectric conversion efficiency Eta formed by this structure is also improved by 0.19-0.26%.

[0103] In summary, after adopting the preparation method of the passivated contact cell structure, a double-layer polysilicon stacking method is adopted in turn, the thickness of the inner intrinsic polysilicon layer is maintained at 30-60nm, and the outer polysilicon is doped with carbon elements, and the thickness is maintained at 30-60nm. This technology is beneficial to inhibit the escape of H by forming CH chemical bonds, which is beneficial to promote surface passivation; in addition, doping carbon elements in the polysilicon layer can reduce the activity of phosphorus atoms, reduce Auger recombination and SRH recombination, and thus inhibit the advancement of phosphorus atoms in non-metallic areas during the phosphorus diffusion process. In the metal area, due to the absence of carbon-doped polysilicon, phosphorus atoms can be doped to the maximum extent, and higher The doping concentration will form a better ohmic contact. This is because the resistivity of the high-concentration doped area is greatly reduced, reducing the resistance of the contact interface between the semiconductor and the metal electrode. The parasitic absorption of the low-concentration area doped with carbon in the non-metallic area will also be lower than that of the traditional cell. Therefore, the specific advantages of this application are: ① Due to the carbon doping of polysilicon in the selected area, a passivation contact of the selective polysilicon layer is formed. The polysilicon phosphorus doping concentration in the non-metallic area is low, and the polysilicon phosphorus doping concentration in the metal area is high. This can reduce the parasitic absorption coefficient of the polysilicon layer in the non-metallic area due to the reduction in doping concentration, improve the utilization rate of light, and thus improve the photoelectric conversion efficiency of the battery. ② Because the metal area adopts a heavily doped structure, it helps to form a better ohmic contact with the metal electrode and reduce the contact resistivity. ③ Due to the doping of carbon elements, it is beneficial to suppress the escape of H by forming a CH chemical bond, and it is more conducive to promoting surface passivation and increasing the passivation performance of the battery. The key points of this application are as follows: ① The TOPCon cell in the present invention adopts a structure of multi-layer polysilicon stacking in a non-metallic region, which, from the inside to the outside, are a phosphorus lightly doped polysilicon layer, a phosphorus heavily doped polysilicon layer, and a carbon / phosphorus medium doped polysilicon layer. Different from the single-layer polysilicon structure on the back of the commercial TOPCon cell, the outer layer of polysilicon is more conducive to increasing the passivation performance of the cell due to the doping of carbon. ② In the present invention, the TOPCon cell is doped with C element in the non-metallic outer layer of polysilicon, which helps to suppress the activity of P element, thereby forming a phosphorus light doping in the non-metallic region. Since there is no carbon-doped polysilicon in the metal region, the deposition and diffusion of P element is not affected, forming a phosphorus heavy doping, which can reduce the parasitic absorption of light by the heavy doping of the polysilicon layer in the non-metallic region, improve the utilization rate of light, and thus improve the photoelectric conversion efficiency of the cell. ③ The doping of carbon element is conducive to the formation of CH chemical bonds to suppress the escape of H, which is conducive to promoting the passivation of the surface. ④ Because the metal region adopts a heavy doping method, it is more conducive to forming a better ohmic contact with the metal electrode and reducing the contact resistivity.The characteristics of the present application are as follows: ① The polysilicon in the present invention (including metal areas and non-metal areas) can be divided into three layers from the inside to the outside, namely, lightly phosphorus-doped polysilicon, heavily phosphorus-doped polysilicon, and carbon / phosphorus-medium-doped polysilicon; ② Carbon-doped polysilicon has an inhibitory effect on the activity of phosphorus atoms; ③ Heavily phosphorus-doped polysilicon is distributed in the metal area, and carbon / phosphorus-medium-doped polysilicon is distributed in the non-metal area; ④ The concentration of phosphorus atoms in polysilicon: heavily phosphorus-doped polysilicon>carbon / phosphorus-medium-doped polysilicon>lightly phosphorus-doped polysilicon; ⑤ The preparation steps of the battery and two different alternative schemes; ⑥ The selective polysilicon layer formed by doping carbon elements in the present invention can be replaced by doping with elements such as oxygen and nitrogen.

[0104] The above detailed description of the present invention is intended to enable persons familiar with the art to understand the contents of the present invention and implement them. It does not limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing a back structure layer of a passivated contact battery, characterized in that: It includes the following steps: First, a single-crystal silicon wafer is selected to remove the BSG layer on the back and edge, and a tunnel oxide layer and an intrinsic polysilicon layer are grown on the back of the silicon wafer in sequence; Secondly, a selective polysilicon layer is formed based on the intrinsic polysilicon layer, which includes a first doped polysilicon layer, a second doped polysilicon layer and a third doped polysilicon layer, wherein the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer constitute inner and outer doped structural layers with different concentrations of phosphorus atoms, and the doped polysilicon layer with the highest concentration of phosphorus atoms corresponds to the metal region, and carbon, oxygen or nitrogen elements are doped only in the doped polysilicon layer with the second highest concentration of phosphorus atoms, and the non-metallic region corresponding to the outer doped structural layer, the doped polysilicon layer with the highest concentration of phosphorus atoms and the doped polysilicon layer with the second highest concentration of phosphorus atoms constitute the outer doped structural layer, and the doped polysilicon layer with the lowest concentration of phosphorus atoms constitutes the inner doped structural layer; Finally, a passivation anti-reflection film layer is formed on the external doping structure layer.

2. The method for preparing the back structure layer of the passivation contact battery according to claim 1, characterized in that: The selective polysilicon layer forming step includes: first, growing a carbon-doped polysilicon layer on the back side of the intrinsic polysilicon layer; second, making grooves on the carbon-doped polysilicon layer corresponding to the metal region; finally, performing phosphorus diffusion treatment, wherein atoms enter the intrinsic polysilicon layer to form a first doped polysilicon layer and a second doped polysilicon layer, and phosphorus atoms enter the carbon-doped polysilicon layer to form a third doped polysilicon layer, wherein the first doped polysilicon layer and the third doped polysilicon layer correspond to the metal region and the non-metal region respectively, and the concentration of phosphorus atoms in the selective polysilicon layer is arranged as follows: first doped polysilicon layer>third doped polysilicon layer>second doped polysilicon layer.

3. The method for preparing the back structure layer of the passivation contact battery according to claim 2, characterized in that: It uses ultraviolet picosecond or nanosecond laser with a wavelength of 200-600nm, a laser frequency of 50-300KHz, a laser scanning speed of 5-25m / s, and an energy density of 0.1-5J / cm 2 , remove the carbon-doped polysilicon layer in the back metal area, and the removal width is 60 to 100 μm, corresponding to the metal gate line area.

4. The method for preparing the back structure layer of the passivation contact battery according to claim 1, characterized in that: The selective polysilicon layer forming step includes: first, placing the back side of the silicon wafer on a graphite carrier with a mask pattern; second, depositing carbon atoms on the surface of the intrinsic polysilicon of the silicon wafer through ion implantation equipment, and making the polysilicon in the non-metallic area all carbon-doped polysilicon layers, and the metal area all intrinsic polysilicon layers under the mask; finally, phosphorus diffusion treatment, atoms enter the intrinsic polysilicon layer to form a first doped polysilicon layer and a second doped polysilicon layer, and phosphorus atoms enter the carbon-doped polysilicon layer to form a third doped polysilicon layer; wherein the first doped polysilicon layer and the third doped polysilicon layer correspond to the metal area and the non-metallic area respectively, the second doped polysilicon layer covers the entire back side of the tunneling oxide layer, and the concentration of phosphorus atoms in the selective polysilicon layer is arranged as the first doped polysilicon layer> the third doped polysilicon layer> the second doped polysilicon layer.

5. The method for preparing the back structure layer of the passivation contact battery according to claim 1, characterized in that: The selective polysilicon layer forming step comprises: first, placing the back side of the silicon wafer on a graphite carrier with a mask pattern, and then transferring the graphite carrier into a plate chamber of a physical vapor deposition device; second, magnetron sputtering a carbon-doped silicon target material, the carbon-doped silicon target material is located below the graphite carrier, and the magnetron sputtering process allows silicon atoms to desorb from the target material and move upward to deposit on the back side of the silicon wafer, forming a deposition on the silicon wafer in the graphite hollow area, forming a carbon-doped polysilicon layer on the surface of the non-metallic area, and the surface of the metal area is bare intrinsic polysilicon layer; finally, phosphorus diffusion treatment is performed, and atoms enter the intrinsic polysilicon layer to form a first doped polysilicon layer and a second doped polysilicon layer, and phosphorus atoms enter the carbon-doped polysilicon layer to form a third doped polysilicon layer, wherein the first doped polysilicon layer and the third doped polysilicon layer correspond to the metal region and the non-metal region, respectively, and the second doped polysilicon layer covers the entire back side of the tunneling oxide layer, and the concentration of phosphorus atoms in the selective polysilicon layer is ranked as the first doped polysilicon layer>the third doped polysilicon layer>the second doped polysilicon layer.

6. The method for preparing the back structure layer of a passivated contact cell according to claim 2, 4 or 5, characterized in that: Under the condition of oxygen, phosphorus oxychloride decomposes at high temperature to generate phosphorus pentachloride and phosphorus pentoxide. The generated phosphorus pentoxide reacts with silicon at the diffusion temperature to generate silicon dioxide and phosphorus atoms.

7. The method for preparing the back structure layer of a passivated contact cell according to claim 1, 2, 3, 4 or 5, characterized in that: The concentration of the first doped polysilicon layer is 4.0 to 8.0E+20cm -3 ; The concentration of the third doped polysilicon layer is 0.8~1.0E+20cm -3 ; The concentration of the second doped polysilicon layer is 1.0~4.0E+19cm -3 .

8. The method for preparing the back structure layer of a passivated contact cell according to claim 1, characterized in that: 3% to 10% HF is used to remove the BSG layer on the back and edge of the silicon wafer after boron diffusion; then the back of the silicon wafer is polished by a wet method to form a flat surface, and the reaction temperature is 60±10°C; low-pressure chemical vapor deposition or plasma enhanced chemical vapor deposition is used to make silane react on the back of the silicon wafer and deposit and grow an ultra-thin tunneling oxide layer and a polysilicon layer.

9. The method for preparing the back structure layer of a passivation contact battery according to claim 1, characterized in that: The structural material of the tunneling oxide layer is SiO2, the deposition reaction temperature is 400-600°C, the thickness is selected to be 0.5nm~2.5nm, the deposition reaction temperature of intrinsic polysilicon is 500-650°C, and the thickness is selected to be 60~200nm; and / or, silane is used as a silicon source, methane is used as a carbon source, and the flow ratio of silane: methane is maintained at 100:100~300 to obtain a carbon-doped polysilicon layer; the carbon-doped polysilicon layer is a nitrogen-doped polysilicon layer or an oxygen-doped polysilicon layer, and the thickness is 20~100nm, wherein silane is used as a silicon source, carbon dioxide is used as an oxygen source, and the flow rate ratio of silane: carbon dioxide is maintained at 100:20~100 to form oxygen doping; silane is used as a silicon source, ammonia is used as a nitrogen source, and the flow rate ratio of silicon source: ammonia is maintained at 100:20~100 to form nitrogen doping.

10. A passivation contact cell, comprising a single crystal silicon wafer, a back structure layer and a front structure layer, a front metal electrode and a back metal electrode, characterized in that: the back structure layer is made by the preparation method of the back structure layer of the passivation contact cell according to any one of claims 1 to 9.

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