Infrared LED element

Abstract

Provided is an infrared LED element in which a concave-convex shape can be efficiently formed on a light emission surface, and in which the luminous efficiency is less likely to decrease even when driven by a large current. The present invention is provided with: a conductive support substrate; and a semiconductor laminate disposed on an upper layer of the support substrate and made of a material capable of lattice matching with InP, the semiconductor laminate having: a first semiconductor layer disposed on a side closest to the support substrate and exhibiting a first conductivity type, and a second semiconductor layer disposed on a side closest to the support substrate and exhibiting a second conductivity type; an active layer disposed above the first semiconductor layer; a second semiconductor layer disposed on the upper layer of the active layer and exhibiting a second conductivity type different from the first conductivity type; and a third semiconductor layer that is disposed above the second semiconductor layer and is composed of AlaGabIncAs exhibiting the second conductivity type, the third semiconductor layer having a concavo-convex portion on a surface on the opposite side from the side on which the second semiconductor layer is located, the band gap energy of the third semiconductor layer being lower than the band gap energy of the second semiconductor layer, and the band gap energy of the third semiconductor layer being lower than the band gap energy of the second semiconductor layer. And the band gap energy is higher than that of the active layer.

Description

Technical Field

[0001] The present invention relates to an infrared LED element, and in particular to an infrared LED element with a light emission wavelength of more than 1,000 nm. Background Art

[0002] In recent years, semiconductor light-emitting devices that emit light in the infrared region with a wavelength of 1,000 nm or more have been widely used in security / surveillance cameras, gas detectors, medical sensors, industrial equipment, and the like.

[0003] Semiconductor light-emitting elements with a light emission wavelength of 1,000 nm or more are generally manufactured by the following steps. On an InP substrate as a growth substrate, a semiconductor layer of the first conductivity type, an active layer (sometimes also called a "light-emitting layer"), and a semiconductor layer of the second conductivity type are epitaxially grown in sequence, and then electrodes for injecting current are formed on the semiconductor wafer. Afterwards, it is cut into chips.

[0004] In the past, semiconductor laser elements were the first to be developed as semiconductor light-emitting elements with a light emission wavelength of 1,000 nm or more. On the other hand, LED elements have not been developed ahead of laser elements because they have few uses.

[0005] However, in recent years, as the application expands, the requirement for high efficiency of infrared LED elements has also increased. As a structure that meets this requirement, for example, Patent Document 1 discloses an infrared LED element, which forms electrodes on the upper and lower surfaces of a wafer having an LED structure crystal-grown on an InP substrate, applies a voltage between the two electrodes, and thus injects current into the active layer to make it emit light.

[0006] Furthermore, due to the expansion of the use of this wavelength band, LEDs with higher luminous efficiency and smaller size and lower height are required. As a structure that meets this requirement, Patent Document 2 discloses the following structure: for a light emitting diode wafer having an epitaxial semiconductor film of an LED structure crystal-grown on a growth substrate, after being bonded to a supporting substrate via a high-reflection film and a metal layer, the growth substrate is thinned or completely removed.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Laid-Open No. 4-282875

[0010] Patent Document 2: Japanese Patent Application Publication No. 2012-129357

[0011] Patent Document 3: Japanese Patent Application Publication No. 2023-018332

[0012] Patent Document 4: Japanese Patent Application Publication No. 2012-074489 Summary of the invention

[0013] Problems that the invention will solve

[0014] The growth substrate and semiconductor layer of the infrared LED element with a light emission wavelength of more than 1,000nm are composed of a material composed of a combination of multiple elements among Al, Ga, In, As, and P. It is known that most of these materials have a high refractive index. For example, the refractive index of InP for light with a wavelength of more than 1,000nm and less than 2,000nm is about 3.1 to 3.3. Therefore, when light is taken out from the InP substrate side, if the InP substrate is not processed in any way, most of the light generated in the semiconductor layer will be totally reflected at the boundary between the InP substrate and the air. It is assumed that the light reflected at the interface with the InP substrate and returned to the active layer side is taken out to the outside after further repeated reflection, but in the process of traveling in the InP substrate and the semiconductor layer, part of the light is absorbed, resulting in a decrease in the extraction efficiency.

[0015] In addition, in order to extract more light in the infrared LED element, etching based on a liquid medicine is performed to form a concave-convex shape on the light extraction surface. However, as mentioned in the above-mentioned patent document 3, a method for setting a concave-convex shape with the same degree of randomness as GaN-based and GaAs-based LED elements on the surface of an InP substrate by a simple etching process under a liquid medicine has not yet been established. Therefore, if an infrared LED element with the main surface of the InP substrate as the light extraction surface forms a concave-convex shape on the light extraction surface by etching based on a liquid medicine, the randomness becomes insufficient, and there is a problem of multiple peaks (multi-peaks) appearing in the spectrum of the emitted light.

[0016] In addition, in infrared LED elements using InP as a growth substrate, InP is generally used as a semiconductor layer that matches the substrate lattice, and InP is also used to form a rough light extraction surface. Therefore, as a method for forming a concave-convex shape, there is a known method of immersing the light extraction surface in an acid etching solution without using a patterned mask as shown in the above-mentioned patent document 4 (wet etching), but as mentioned above, the problem of multiple peaks cannot be eliminated.

[0017] Here, the phenomenon of multi-peak emission spectrum is caused by the propagation of light in a thin area sandwiched by a pair of reflective interfaces. In view of this, it is believed that multi-peak emission can be suppressed by reducing the reflectivity of the light extraction surface. In the above-mentioned GaN-based and GaAs-based LED elements, the main surface of the semiconductor layer constituting the light extraction surface is etched to randomly roughen the surface. As a result, the multi-peak emission spectrum of the GaN-based and GaAs-based LED elements is suppressed.

[0018] The above method can be used in GaN and GaAs LED elements because a method has been established that can etch the main surface of the semiconductor layer with high reproducibility. In the case of GaN, the nitrogen polar surface ([000-1] surface) has relatively low chemical stability and relatively high defect density, so it is relatively easy to form a rough surface by etching based on KOH and other liquids. In addition, in the case of GaAs, since As is an element that is relatively easy to oxidize, it is easy to form a rough surface by etching while forming a micromask on the surface using an etchant to which an oxidant is added.

[0019] However, at the time of the present invention, a method for randomly roughening the surface with good reproducibility has not yet been established in InP-based LED components. As reasons for this, it can be cited that InP has higher stability and lower defect density than the nitrogen polar surface of GaN, and it is also difficult to properly form an oxide micromask. Moreover, as mentioned above, compared with GaN-based and GaAs-based LED components, the demand for InP-based LED components has been relatively low in the past, and there is also a situation where the research and development of an etchant that can randomly roughen the surface has not yet progressed. In addition, even if such an etchant is developed, in view of the above situation, it can be imagined that its cost becomes extremely high.

[0020] Moreover, in the infrared LED element of the vertical structure, an electrode is arranged on the upper surface of the light extraction surface. When the light extraction surface is roughened, it is necessary to consciously avoid the area where the electrode is formed. Due to this situation, high reproducibility is required when roughening the upper surface.

[0021] In view of the above circumstances, a method capable of randomly roughening the surface of an InP-based infrared LED element with good reproducibility has not yet been put to practical use.

[0022] Therefore, as a method for forming projections and depressions, attention is paid to As-containing materials that are generally subjected to an immersion treatment method. It is known that in GaAs and AlGaAs, which are generally used in red LED elements, relatively random projections and depressions can be formed by immersing them in an etching solution containing nitric acid, even without forming a patterned mask. However, in infrared LED elements using an InP substrate as a growth substrate, if GaAs or AlGaAs is used, crystal defects will be introduced due to lattice mismatch. In particular, in a structure such as patent document 2 in which the growth substrate is peeled off and attached to a supporting substrate, since the layer forming the projections and depressions is grown in the early stage of crystal growth, the crystal defects introduced due to lattice mismatch pass through the active layer and become the main cause of reduced luminous efficiency and reliability. Therefore, the inventors of the present invention, based on Figure 1The correlation diagram related to the band gap energy of the semiconductor material shown focuses on AlGaInAs, which is an As-containing material considered to be easy to form a concavo-convex shape and is lattice-matched with InP.

[0023] When the n-InP layer serving as the light extraction surface was changed to n-AlGaInAs, it was confirmed that the concavo-convex shape could be easily formed. In addition, it was confirmed that it was effective in suppressing multiple peaks, which is one of the purposes of forming the concavo-convex shape on the light extraction surface.

[0024] However, the inventors of the present invention have noticed that if the entire n-type layer is changed from InP to AlGaInAs, the luminous efficiency of the infrared LED element decreases when driven with a particularly large current, compared with the element having the structure before the change.

[0025] The present invention has been made in view of the above problems, and an object of the present invention is to provide an infrared LED element in which a concavo-convex shape can be efficiently formed on a light emitting surface and in which the light emitting efficiency is unlikely to decrease even when driven with a large current.

[0026] Means for solving problems

[0027] The semiconductor light emitting device of the present invention is characterized in that

[0028] It is an infrared LED element capable of emitting infrared light with a peak wavelength of 1,000nm to 2,000nm, having:

[0029] a conductive support substrate; and

[0030] The semiconductor stack is disposed on the upper layer of the support substrate and is composed of a material that can be lattice matched to InP.

[0031] The semiconductor stack has:

[0032] A first semiconductor layer, disposed on a side closest to the support substrate and exhibiting a first conductivity type;

[0033] an active layer disposed on the upper layer of the first semiconductor layer;

[0034] A second semiconductor layer, disposed on an upper layer of the active layer and exhibiting a second conductivity type different from the first conductivity type; and

[0035] The third semiconductor layer is disposed on the upper layer of the second semiconductor layer and is composed of Al a Ga b In c As (0≤a<1, 0<b<1, 0<c<1, a+b+c=1),

[0036] The third semiconductor layer has a concavo-convex portion on a surface opposite to a surface on which the second semiconductor layer is located.

[0037] The band gap energy of the third semiconductor layer is lower than the band gap energy of the second semiconductor layer, and is higher than the band gap energy of the active layer.

[0038] The inventors of the present invention have speculated through in-depth research that in the previous infrared LED elements, when the n-type layer is changed from InP to AlGaInAs as a whole, the band gap energy difference between the active layer and the n-type layer becomes smaller, resulting in a decrease in luminous efficiency. Generally speaking, the active layer adopts a structure sandwiched by P-type and N-type semiconductors with larger band gap energy. This is to help the luminous electrons and holes to be confined in the active layer and to allow them to recombine efficiently. However, if the band gap energy difference between the active layer and the n-type layer, or the active layer and the p-type layer is small, the electrons and holes are likely to leak from the active layer before recombination. That is, it is believed that the above-mentioned reduction in luminous efficiency is caused by the reduction in the band gap energy difference between the active layer and the n-type layer.

[0039] Based on the above speculation, the inventors of the present invention considered forming a roughened layer in the semiconductor stack that is an As-containing material that is believed to easily form a concave-convex shape and is lattice-matched with InP, and a capping layer (second semiconductor layer) that has a large band gap energy and is less likely to cause a decrease in luminous efficiency.

[0040] The infrared LED element of the above structure is the same as the previous structure. Since the second semiconductor layer is formed on the upper layer of the active layer, the band gap energy difference between the active layer and the second semiconductor layer is maintained at the same level as before. Moreover, the third semiconductor layer constituting the light emitting surface is easier to form a concave-convex portion for improving the light extraction efficiency than InP.

[0041] Therefore, the infrared LED element having the above-described structure can efficiently form a concavo-convex shape on the light emitting surface and is an element in which the light emission efficiency is unlikely to decrease even when driven with a large current.

[0042] The above infrared LED element can also be,

[0043] The second semiconductor layer is InP.

[0044] InP has the largest band gap energy among the types of materials that are lattice-matched with the InP substrate, and therefore, InP is suitable as a material for the second semiconductor layer (cap layer).

[0045] The above-mentioned LED element may also be,

[0046] The thickness of the third semiconductor layer is 1 μm to 5 μm.

[0047] If the third semiconductor layer is too thin, it is very difficult to form a rough surface, and if it is too thick, the resistance value increases. Therefore, the third semiconductor layer preferably has a thickness that allows the formation of a rough surface and does not cause a problem with the resistance value, and specifically, preferably within the range of 1 μm to 5 μm.

[0048] The above infrared LED element can also be,

[0049] having a first electrode arranged to be in contact with a portion of the upper surface of the third semiconductor layer,

[0050] The doping concentration of the third semiconductor layer is higher than that of the second semiconductor layer and is 5×10 17 / cm 3 above.

[0051] Furthermore, the infrared LED element may also be,

[0052] The doping concentration of the second semiconductor layer is 5×10 17 / cm 3 above,

[0053] The doping concentration of the third semiconductor layer is 1×10 18 / cm 3 above.

[0054] In the configuration in which the first electrode is formed on a portion of the upper surface of the third semiconductor layer, the third semiconductor layer functions as a contact layer that electrically connects the first electrode to the second semiconductor layer. Therefore, it is more important that the third semiconductor layer has a lower resistance value than the second semiconductor layer. In addition, when the doping concentration of the third semiconductor layer is less than 5×10 17 / cm 3 In this case, the resistance value becomes large, which may cause problems such as temperature rise during operation.

[0055] In the above configuration, the doping concentrations of the second semiconductor layer and the third semiconductor layer are adjusted as described above, so that the third semiconductor layer functions as a contact layer with a sufficiently small resistance value between the first electrode and the second semiconductor layer. In addition, considering that the second semiconductor layer functions as a capping layer, it is more preferable that the doping concentration of the second semiconductor layer is 5×10 17 / cm 3 The doping concentration of the third semiconductor layer is 1×10 18 / cm 3 above.

[0056] In addition, the infrared LED element may also include:

[0057] a second electrode disposed on a surface of the support substrate on a side opposite to a side on which the semiconductor stack is disposed; and

[0058] The reflective layer is disposed between the support substrate and the semiconductor stack and is made of a conductive material.

[0059] According to the above configuration, the reflective layer reflects light generated by the active layer and traveling toward the first conductor layer side, that is, the opposite side of the light emitting surface formed on the main surface of the third semiconductor layer, toward the light emitting surface side. Therefore, the infrared LED element of the above configuration can extract more light generated in the active layer from the light emitting surface.

[0060] The above infrared LED element can also be,

[0061] The band gap energy of the second semiconductor layer is 1.1 times or more relative to the band gap energy of the active layer.

[0062] By setting the relationship between the band gap energy of the second semiconductor layer and the band gap energy of the active layer to the above relationship, a decrease in efficiency can be further suppressed.

[0063] The above infrared LED element can also be,

[0064] The surface roughness (Ra) of the concavo-convex portion formed on the surface of the third semiconductor layer is 0.25 to 1.00.

[0065] Effects of the Invention

[0066] According to the present invention, it is possible to realize an infrared LED element in which a concavo-convex shape can be efficiently formed on a light emitting surface and in which the light emitting efficiency is unlikely to decrease even when driven with a large current. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1 is a correlation diagram related to the band gap energy of semiconductor materials.

[0068] Figure 2 This is a cross-sectional view schematically showing the structure of an infrared LED element according to one embodiment.

[0069] Figure 3A It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0070] Figure 3B It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0071] Figure 3C It is used to illustrate Figure 2A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0072] Figure 3D It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0073] Figure 3E It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0074] Figure 3F It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0075] Figure 3G It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0076] Figure 3H It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0077] Fig. 3I It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0078] Figure 3J It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0079] Figure 3K It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown.

[0080] Figure 3L It is used to illustrate Figure 2 A cross-sectional view showing one process step of a method for manufacturing an infrared LED element shown. DETAILED DESCRIPTION

[0081] The infrared LED element of the present invention is described below with reference to the accompanying drawings. In addition, the following drawings related to the infrared LED element are schematically illustrated, and the size ratios and numbers in the drawings are not necessarily consistent with the actual size ratios and numbers.

[0082] In this specification, the expression "layer B is formed on layer A" includes, of course, the case where layer B is directly formed on the surface of layer A, and also includes the case where layer B is formed on the surface of layer A via a thin film. In addition, the "thin film" mentioned here may refer to a layer with a film thickness of 50 nm or less, preferably a layer with a film thickness of 10 nm or less.

[0083] Figure 2 It is a cross-sectional view schematically showing the structure of the infrared LED element of this embodiment. Figure 2 The infrared LED element 1 shown includes a semiconductor stacked body 20 arranged on the upper layer (+Y side) of a supporting substrate 11 . Figure 2 The infrared LED element 1 shown corresponds to a schematic cross-sectional view when cut along the XY plane at a predetermined position. Figure 2 The attached XYZ coordinate system.

[0084] In the following description, when expressing a direction, when distinguishing between positive and negative directions, it is recorded with positive and negative signs such as "+X direction" and "-X direction". In addition, when expressing a direction without distinguishing between positive and negative directions, it is simply recorded as "X direction". That is, in this specification, when it is simply recorded as "X direction", both "+X direction" and "-X direction" are included. The same applies to the Y direction and the Z direction.

[0085] The infrared LED element 1 generates infrared light L in the semiconductor stack 20 (more specifically, in the active layer 25 described later). More specifically, Figure 2 As shown, infrared light L (L1, L2) is extracted in the +Y direction with reference to the active layer 25. The peak wavelength of the infrared light L is 1,000 nm to 2,000 nm.

[0086] [Component structure]

[0087] Hereinafter, the structure of the infrared LED element 1 will be described in detail.

[0088] (Support substrate 11)

[0089] The support substrate 11 is made of, for example, a semiconductor such as Si or Ge, or a metal material such as Cu or CuW. When the support substrate 11 is made of a semiconductor, a dopant may be doped at a high concentration to exhibit conductivity. As an example, the support substrate 11 is made of a semiconductor containing boron (B) at a concentration of 1×10 19 / cm 3The above doping concentration is a Si substrate with a resistivity of 10 mΩ·cm or less. As a dopant, in addition to boron (B), phosphorus (P), arsenic (As), antimony (Sb), etc. can also be used. From the perspective of balancing high heat dissipation and low manufacturing cost, the support substrate 11 is preferably a Si substrate.

[0090] The thickness (length in the Y direction) of the support substrate 11 is not particularly limited, but is, for example, 50 μm to 500 μm, and preferably 100 μm to 300 μm.

[0091] (Metal Bonding Layer 13)

[0092] The infrared LED element 1 includes a metal bonding layer 13 disposed on an upper layer of the support substrate 11. The metal bonding layer 13 is composed of a low melting point solder material, such as Au, Au-Zn, Au-Sn, Au-In, Au-Cu-Sn, Cu-Sn, Pd-Sn, or Sn. Figure 3G As described above, the metal bonding layer 13 is used to bond the growth substrate 3 having the semiconductor stack 20 formed thereon to the support substrate 11. The thickness of the metal bonding layer 13 is not particularly limited, but is, for example, 0.5 μm to 5.0 μm, preferably 1.0 μm to 3.0 μm.

[0093] In addition, a barrier layer may be formed on the upper layer and the lower layer of the metal bonding layer 13. Sometimes, a barrier layer is provided for the purpose of suppressing the diffusion of the solder material constituting the metal bonding layer 13. The material is not limited as long as the relevant function is achieved, but the barrier layer may be implemented by a material including Ti, Pt, W, Mo, or Ni, for example. As a more specific example, it is a stack of Ti / Pt / Au.

[0094] (Reflective layer 15)

[0095] The infrared LED element 1 of the present embodiment includes a reflective layer 15 disposed on the upper layer of the metal bonding layer 13 .

[0096] The reflective layer 15 has the function of reflecting the infrared light L2 traveling toward the support substrate 11 side (-Y direction) among the infrared light L generated in the active layer 25 and guiding it toward the +Y direction. The reflective layer 15 is made of a conductive material and is a material that exhibits a high reflectivity for the infrared light L. The reflectivity of the reflective layer 15 for the infrared light L is 50% or more, preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

[0097] When the peak wavelength of the infrared light L is 1,000 nm to 2,000 nm, Ag, Ag alloy, Au, Al, Cu, etc. can be used as the material of the reflective layer 15. The material can be appropriately selected according to the wavelength of the infrared light L.

[0098] The thickness of the reflective layer 15 is not particularly limited, but is, for example, 0.1 μm to 2.0 μm or less, and preferably 0.3 μm to 1.0 μm or less.

[0099] Furthermore, when the barrier layer as described above is formed between the reflective layer 15 and the metal bonding layer 13 , it is possible to suppress the material constituting the metal bonding layer 13 from diffusing toward the reflective layer 15 and reducing the reflectivity of the reflective layer 15 .

[0100] From the perspective of improving light extraction efficiency, Figure 2 As shown, it is preferable that the infrared LED element 1 includes the reflective layer 15 . However, in the present invention, whether the infrared LED element 1 includes the reflective layer 15 is optional.

[0101] In addition, although not shown in the figure, from the viewpoint of improving light extraction efficiency, the infrared LED element 1 preferably has an anti-reflection film covering the upper surface, the side surface, or both of the semiconductor stack 23. However, whether the infrared LED element 1 has the anti-reflection film is optional. In addition, the anti-reflection film is made of, for example, SiO 2 , SiN, etc. are used as materials, and the film thickness is appropriately determined according to the refractive index and the emission wavelength to become an optical film thickness that reduces the reflectivity. It is formed on the upper surface, side surface, or both sides of the semiconductor stack 23 by plasma CVD method.

[0102] (Insulation layer 17)

[0103] Figure 2 The infrared LED element 1 shown has an insulating layer 17 disposed on the upper layer of the reflective layer 15. The insulating layer 17 is made of a material that exhibits electrical insulation and has high transmittance to infrared light L. The transmittance of the insulating layer 17 to infrared light L is preferably 70% or more, more preferably 80% or more, and particularly preferably 90% or more.

[0104] When the peak wavelength of the infrared light L is 1,000 nm to 2,000 nm, SiO can be used as the material of the insulating layer 17. 2 、SiN,Al 2 O 3 , ZrO, HfO, or MgO, etc. The material can be appropriately selected according to the wavelength of light generated in the active layer 25 .

[0105] (Semiconductor stack 20)

[0106] Figure 2 The infrared LED element 1 shown has a semiconductor stack 20 disposed on an upper layer of an insulating layer 17. The semiconductor stack 20 is a stack of multiple semiconductor layers, and includes, for example, a first contact layer 21, a first cover layer 23, an active layer 25, and a second cover layer 27. Each semiconductor layer (21, 23, 25, 27) constituting the semiconductor stack 20 is composed of a material that can be epitaxially grown in a lattice-matched manner with a growth substrate 3 described later.

[0107] The overall thickness of the semiconductor stack 20 is 30 μm (30,000 nm) or less, preferably 5 μm to 20 μm.

[0108] <<First contact layer 21, first covering layer 23>>

[0109] In this embodiment, the first contact layer 21 is composed of, for example, p-type GaInAsP. The thickness of the first contact layer 21 is not limited, but is, for example, 10 nm to 1000 nm, preferably 50 nm to 500 nm. In addition, the p-type doping concentration of the first contact layer 21 is preferably 5×10 17 / cm 3 ~3×10 19 / cm 3 , more preferably 1×10 18 / cm 3 ~2×10 19 / cm 3 .

[0110] In this embodiment, the first cover layer 23 is disposed on the upper layer of the first contact layer 21, and is composed of, for example, p-type InP. The thickness of the first cover layer 23 is not limited, but is, for example, 1,000 nm to 10,000 nm, preferably 2,000 nm to 5,000 nm. The p-type doping concentration of the first cover layer 23 is preferably 1×10 17 / cm 3 ~3×10 18 / cm 3 Below, more preferably 5×10 17 / cm 3 ~3×10 18 / cm 3 the following.

[0111] As the p-type dopant contained in the first contact layer 21 and the first cap layer 23, Zn, Mg, or Be can be used, preferably Zn or Mg, and particularly preferably Zn. In this embodiment, the first contact layer 21 and the first cap layer 23 correspond to the "first semiconductor layer".

[0112] 《Active Layer 25》

[0113] In this embodiment, the active layer 25 is disposed on the upper layer of the first cover layer 23. The material of the active layer 25 can be selected from a material that can generate light of a target wavelength and can be used as described later. Figure 3B It is appropriately selected from the materials that can be epitaxially grown to be lattice-matched with the growth substrate 3 as described above.

[0114] When one wants to manufacture an infrared LED element 1 that emits infrared light L with a peak wavelength of 1,000nm to 2,000nm, the active layer 25 can be either a single-layer structure of GaInAsP, AlGaInAs or InGaAs, or an MQW (Multiple Quantum Well) structure that includes a well layer composed of GaInAsP, AlGaInAs or InGaAs and a barrier layer composed of GaInAsP, AlGaInAs, InGaAs or InP having a band gap energy larger than that of the well layer.

[0115] The thickness of the active layer 25 is 50 nm to 2,000 nm, preferably 100 nm to 300 nm, when the active layer 25 has a single layer structure. When the active layer 25 has an MQW structure, well layers and barrier layers with a thickness of 5 nm to 20 nm are stacked in a range of 2 to 50 cycles.

[0116] The active layer 25 may be n-type doped or p-type doped, or may be undoped. When n-type doping is performed, Si, for example, can be used as a dopant.

[0117] 《Second Covering Layer 27》

[0118] In this embodiment, the second cover layer 27 is disposed on the upper layer of the active layer 25 and is composed of, for example, n-type InP. The second cover layer 27 is used for current dispersion, and therefore requires a certain degree of film thickness and impurity concentration. The thickness of the second cover layer 27 is not limited, but is, for example, 2,000 nm to 15,000 nm, preferably 5,000 nm to 10,000 nm. The n-type doping concentration of the second cover layer 27 is preferably 5×10 17 / cm 3 Above, more preferably 1×1018 / cm 3 In addition, when current dispersion and the like are also taken into consideration, the range of the n-type doping concentration of the second cladding layer 27 is preferably 5×10 17 / cm 3 ~1×10 19 / cm 3 , more preferably 1×10 18 / cm 3 ~5×10 18 / cm 3.

[0119] The materials of the first cover layer 23 and the second cover layer 27 can be materials that do not absorb the infrared light L generated in the active layer 25 and can be bonded to the growth substrate 3 (see Figure 3B ) is appropriately selected from the materials that can be epitaxially grown in a lattice-matched manner. When an InP substrate is used as the growth substrate 3, the materials of the first cladding layer 23 and the second cladding layer 27 can be InP, GaInAsP, or AlGaInAs, but InP is preferred.

[0120] Although optional, from the viewpoint of suppressing a decrease in efficiency, the band gap energy of the second cladding layer 27 is preferably 1.1 times or more the band gap energy of the active layer 25 .

[0121] 《Second contact layer 28》

[0122] In this embodiment, the material of the second contact layer 28 is disposed on the upper layer of the second cover layer 27 and can be selected from the materials satisfying Al a Ga b In c It is appropriately selected from materials such as As (0≤a<1, 0<b<1, 0<c<1, a+b+c=1). More specifically, for example, AlGaInAs or InGaAs can be used.

[0123] The second contact layer 28 may be made of a material having a band gap energy lower than that of the second cover layer 27 and higher than that of the active layer 25 .

[0124] In this embodiment, the second contact layer 28 is composed of, for example, n-type AlGaInAs. The thickness of the second contact layer 28 is not limited, but is preferably 1 μm to 5 μm, and more preferably 2 μm to 4 μm. In addition, the n-type doping concentration of the second contact layer 28 is preferably 5×10 17 / cm 3 More preferably, 1×10 18 / cm 3 above.

[0125] In addition, when current dispersion and the like are also taken into consideration, the range of the n-type doping concentration of the second contact layer 28 is, for example, 5×10 17 / cm 3 ~3×10 19 / cm 3 , more preferably 1×10 18 / cm 3 ~2×10 19 / cm 3In addition, although it is arbitrary, from the viewpoint of relatively reducing the resistance value, the doping concentration of the second contact layer 28 is preferably configured to be higher than the doping concentration of the second cladding layer.

[0126] As the n-type impurity material doped in the second cladding layer 27 and the second contact layer 28, Sn, Si, S, Ge, or Se can be used, and Si is particularly preferred. The second cladding layer 27 corresponds to the "second semiconductor layer", and the second contact layer 28 corresponds to the "third semiconductor layer".

[0127] like Figure 2 As shown, in the infrared LED element 1 of this embodiment, a concavo-convex portion 40 is formed on the surface of the +Y side of the second contact layer 28 (hereinafter referred to as the "first surface 28a"). Figure 2 Although it is schematically shown as a periodic shape, it is actually a random concave-convex shape formed by immersion treatment using an etching solution. Here, although it is arbitrary, from the perspective of improving light extraction efficiency and the perspective of ease of formation, the surface roughness (Ra) of the concave-convex portion 40 is preferably 0.25 to 1.00.

[0128] (Internal electrode 31)

[0129] Figure 2 The infrared LED element 1 shown has internal electrodes 31 formed to penetrate in the Y direction at multiple locations in the insulating layer 17. The internal electrodes 31 electrically connect the first semiconductor layer (21, 23) and the support substrate 11. The internal electrodes 31 are preferably provided at multiple locations dispersed in a direction parallel to the XZ plane (i.e., a direction parallel to the main surface of the support substrate 11).

[0130] The internal electrode 31 is made of a material that can form an ohmic connection with the first contact layer 21. As an example, the internal electrode 31 is made of AuZn, AuBe, or a stacked structure containing at least Au and Zn (e.g., Au / Zn / Au, etc.). In addition, these materials have a lower reflectivity to infrared light L than the material constituting the reflective layer 15.

[0131] The pattern shape of the internal electrode 31 when viewed along the Y direction is arbitrary. However, from the perspective of allowing current to flow over a wider range in the active layer 25 in a direction parallel to the main surface (XZ plane) of the support substrate 11 (hereinafter referred to as the "surface direction"), it is preferred that a plurality of internal electrodes 31 are dispersedly arranged along the surface direction.

[0132] The total area of ​​all the internal electrodes 31 when viewed in the Y direction is preferably 30% or less, more preferably 20% or less, and particularly preferably 15% or less relative to the surface area of ​​the semiconductor stack 20 (e.g., the active layer 25). If the total area of ​​the internal electrodes 31 becomes relatively large, the amount of infrared light L2 traveling from the active layer 25 to the support substrate 11 side (-Y direction) absorbed by the internal electrodes 31 increases, resulting in a decrease in light extraction efficiency. On the other hand, if the total area of ​​the internal electrodes 31 is too small, the resistance value becomes high, resulting in an increase in the forward voltage.

[0133] (Upper surface electrode 32)

[0134] Figure 2 The infrared LED element 1 shown has an upper surface electrode 32 disposed on the surface of the semiconductor stack 20. The upper surface electrode 32 is typically formed in a plurality of ways extending in a predetermined direction. As an example, the plurality of upper surface electrodes 32 extend in the X direction and the Z direction along the side of the semiconductor stack 20, and are in a comb shape. However, the configuration pattern shape of the upper surface electrode 32 is arbitrary, for example, it can also be a grid shape or a spiral shape.

[0135] The upper surface electrode 32 exposes the surface of the second contact layer 28 located in the lower layer (-Y side) (directly or by removing a part of the dielectric layer formed on the same surface), and is formed over a wide range on the XZ plane. As a result, the current flowing in the active layer 25 can be diffused in a direction parallel to the XZ plane, and light can be emitted over a wide range in the active layer 25.

[0136] As an example, the upper surface electrode 32 is made of a material such as AuGe / Ni / Au or AuGe, and may include a plurality of these materials. The upper surface electrode 32 corresponds to a "first electrode".

[0137] (Pad electrode 34)

[0138] like Figure 2 As shown in FIG. 1 , the infrared LED element 1 has a pad electrode 34 disposed on the upper surface of a portion of the upper surface electrode 32. Figure 2 In the figure, the pad electrode 34 is shown to be formed on the entire surface of the upper surface electrode 32, but this is for the convenience of illustration. In fact, the pad electrode 34 may be formed on a part of the surface of the upper surface electrode 32 extending in the surface direction.

[0139] The pad electrode 34 is made of, for example, Ti / Au or Ti / Pt / Au, etc. The pad electrode 34 is provided for the purpose of securing a region for contacting a bonding wire for power supply, but in the present invention, whether or not to provide the pad electrode 34 is optional.

[0140] (Back electrode 33)

[0141] Figure 2 The infrared LED element 1 shown has a back electrode 33 disposed on the surface of the support substrate 11 on the side opposite to the semiconductor stack 20 (-Y side). The back electrode 33 realizes ohmic contact with the support substrate 11. As an example, the back electrode 33 is composed of materials such as Ti / Au or Ti / Pt / Au, and may also have multiple materials among these materials. In addition, the back electrode 33 corresponds to the "second electrode".

[0142] [Manufacturing method]

[0143] Reference Figure 3A to Figure 3L The drawings illustrate an example of a method for manufacturing the infrared LED element 1 described above. Figure 3A to Figure 3L In addition, as far as the following steps are concerned, their order can be appropriately advanced or postponed as long as it does not affect the manufacturing of the infrared LED element 1.

[0144] (Step S1)

[0145] like Figure 3A As shown, a growth substrate 3 is prepared. In this embodiment, an InP substrate having a (001) plane as one main surface is preferably used as the growth substrate 3. An example of the thickness is 370 μm, and the diameter of the main surface is 2 inches. However, the thickness and size of the growth substrate 3 can be appropriately set.

[0146] (Step S2)

[0147] The growth substrate 3 is transported to a MOCVD (Metal Organic Chemical Vapor Deposition) device, for example, and a buffer layer 22, an etching stop layer (ES layer) 24, a second contact layer 28, a second cover layer 27, an active layer 25, a first cover layer 23, and a first contact layer 21 are epitaxially grown on the growth substrate 3 in sequence to form a semiconductor stack 20 (see Figure 3B ). In this step S2, the type and flow rate of the raw material gas, the processing time, the ambient temperature, etc. are appropriately adjusted according to the material of the layer to be grown or the film thickness.

[0148] An example of forming the semiconductor stack 20 is as follows. First, n-type InP doped with Si is stacked on the growth substrate 3 with a predetermined film thickness (for example, about 500 nm) to obtain a buffer layer 22. Next, a layer of a material different from the buffer layer 22 (here, an InGaAs layer) is stacked with a predetermined film thickness (for example, about 200 nm) to obtain an ES layer 24a. Next, a layer of a material different from the ES layer 24a (here, an InP layer) is stacked with a predetermined film thickness (for example, about 300 nm) to obtain an ES layer 24b. Thereafter, under the state where the growth conditions are set to the above-mentioned film thickness and composition, a second contact layer 28, a second covering layer 27, an active layer 25, a first covering layer 23, and a first contact layer 21 are formed in sequence. In addition, in the case where the second semiconductor layer has the function of an ES layer, the ES layer 24 may not be formed.

[0149] As a detailed example, AlGaInAs is stacked to a film thickness of 5,000 nm to obtain the second contact layer 28. Next, n-type InP doped with Si is stacked to a film thickness of 3,000 nm to obtain the second cladding layer 27. Next, InGaAsP is stacked to a film thickness of 900 nm to obtain the active layer 25. Here, it is assumed that the peak wavelength of the infrared light L emitted from the infrared LED element 1 is 1,300 nm. However, as described above, by adjusting the composition ratio of the materials constituting the active layer 25 or adopting the MQW structure, the peak wavelength of the infrared light L can be adjusted within the range of 1,000 nm to 2,000 nm.

[0150] Thereafter, p-type InP doped with Zn was stacked to a thickness of 3,000 nm to form the first cladding layer 23 , and then p-type InGaAsP doped with Zn was stacked to a thickness of 200 nm to form the first contact layer 21 .

[0151] (Step S3)

[0152] After the wafer having the semiconductor stack 20 formed on the growth substrate 3 is taken out from the MOCVD device, a film of, for example, SiO is formed by plasma CVD. 2 The insulating layer 17 (see Figure 3C ). An example of the film thickness is 200nm. Next, a resist mask patterned by photolithography is formed on the surface of the insulating layer 17. After the insulating layer 17 formed in the resist opening is removed by an etching method using a predetermined agent such as buffered hydrofluoric acid, an EB evaporation device is used to form a material film of the internal electrode 31, for example, composed of Au / Zn / Au. An example of the film thickness of the material film of the internal electrode 31 is Au / Zn / Au=25nm / 25nm / 150nm.

[0153] Next, the resist mask is removed, and then the material film formed in the unnecessary region is peeled off to form the internal electrode 31 (see Figure 3C ). Thereafter, an annealing treatment is performed by, for example, heating at 450° C. for 10 minutes to achieve ohmic contact between the first contact layer 21 and the internal electrode 31 .

[0154] (Step S4)

[0155] like Figure 3D As shown, a reflective layer 15 and a metal bonding layer 13a are sequentially formed on the upper surface of the insulating layer 17. For example, the reflective layer 15 is formed by forming Al / Au with a predetermined film thickness by an EB evaporation device, and then the metal bonding layer 13a is formed by forming Ti / Au with a predetermined film thickness. The metal bonding layer 13a may also be made of the same material as the above-mentioned metal bonding layer 13.

[0156] An example of the material film of the reflective layer 15 is Al / Au=5nm / 200nm. An example of the film thickness of the metal bonding layer 13a is Ti / Au=150nm / 1500nm. In addition, as described above, a barrier layer may be formed between the reflective layer 15 and the metal bonding layer 13a. An example of the material film of the barrier layer is Ti / Pt / Au=150nm / 300nm / 200nm.

[0157] (Step S5)

[0158] like Figure 3E As shown, a support substrate 11 different from the growth substrate 3 is prepared. In this embodiment, a Si substrate having a (001) plane as a main surface, doped with boron (B) at a high concentration and showing conductivity is used. The resistivity of the support substrate 11 is preferably less than 10 mΩ·cm (= 0.1 mΩ·m). In addition, as described above, a barrier layer may be formed between the support substrate 11 and the metal bonding layer 13b.

[0159] (Step S6)

[0160] like Figure 3F As shown, a metal bonding layer 13b is formed on the main surface of the support substrate 11. The metal bonding layer 13b can be formed by the same method as the metal bonding layer 13a described in step S4.

[0161] (Step S7)

[0162] like Figure 3GAs shown, the growth substrate 3 and the support substrate 11 are bonded together while being pressurized via the metal bonding layer 13 (13a, 13b), for example, using a wafer bonding device. Preferably, the bonding is performed in a state where the surfaces of the metal bonding layers 13 (13a, 13b) are cleaned. The bonding process is performed, for example, at 300°C and 1MPa. Through this process, the metal bonding layer 13a on the growth substrate 3 and the metal bonding layer 13b on the support substrate 11 are melted and integrated (metal bonding layer 13).

[0163] (Step S8)

[0164] like Figure 3H As shown, the growth substrate 3 is removed. As an example, the growth substrate 3 is removed by immersing the bonded wafer in a hydrochloric acid-based etchant. At this time, the ES layer 24 formed of a material different from the growth substrate 3 and the buffer layer 22 is insoluble in the hydrochloric acid-based etchant, so the etching process stops when the ES layer 24a is exposed.

[0165] (Step S9)

[0166] like Fig. 3I As shown, the ES layer 24a and the ES layer 24b are removed to expose the second contact layer 28. For example, after washing with pure water as needed, the ES layer 24a is removed by immersing in a predetermined chemical solution that is soluble in the ES layer 24a and insoluble in the ES layer 24b. As an example, the chemical solution for removing the ES layer 24a can be a mixed solution of sulfuric acid and hydrogen peroxide (SPM). Thereafter, the ES layer 24b is removed by immersing in a predetermined chemical solution that is soluble in the ES layer 24b and insoluble in the second contact layer 28. As an example, the chemical solution for removing the ES layer 24b can be a hydrochloric acid-based etchant.

[0167] (Step S10)

[0168] like Figure 3J As shown, the upper surface electrode 32 is formed on the exposed surface of the second contact layer 28. Specifically, the process is performed in the following steps.

[0169] A resist mask patterned by photolithography is formed on the surface of the second contact layer 28. Next, a material for forming the upper surface electrode 32 (for example, Au / Ge / Au) is formed into a film by an EB evaporation device, and then peeled off to form the upper surface electrode 32. An example of the film thickness of the upper surface electrode 32 is Au / Ge / Au=10nm / 30nm / 150nm.

[0170] Thereafter, in order to realize the ohmic property of the upper surface electrode 32 , an annealing treatment is performed by, for example, a heating treatment at 450° C. for 10 minutes.

[0171] Next, a pad electrode 34 is formed on the upper surface of the upper surface electrode 32 at a predetermined position. In this case, it can be realized by a film forming process and a peeling process using an EB evaporation device, as in the case of the upper surface electrode 32. As the pad electrode 34, for example, Ti / Pt / Au is formed into a film, and an example of its thickness is Ti / Pt / Au=150nm / 300nm / 1500nm.

[0172] (Step S11)

[0173] like Figure 3K As shown, the concavo-convex portion 40 is formed on the first surface 28 a of the second contact layer 28 .

[0174] As an example of a specific method, first, a resist patterned by photolithography is formed on the first surface 28a of the second contact layer 28. The resist is formed so as to cover the upper portion of the region where the upper surface electrode 32 is formed.

[0175] The first surface 28a of the second contact layer 28 is etched using an etchant such as a sulfuric acid-nitric acid mixture through the patterned resist. In this way, a concavoconvex portion 40 having a random concavoconvex shape is formed on the first surface 28a of the second contact layer 28. As the etchant, for example, a nitric acid-water mixture is used.

[0176] Thereafter, the resist is removed with a cleaning solution such as acetone. As an example of an etchant, for example, a resist stripping solution sold by various resist manufacturers is used.

[0177] (Step S12)

[0178] like Figure 3L As shown, mesa etching for separation into individual elements is performed. Specifically, wet etching is performed using a predetermined etchant in a state where the non-etched area on the surface of the second contact layer 28 is masked with a resist patterned by photolithography. As a result, a portion of the semiconductor stack 20 located in the unmasked area is removed.

[0179] As an example of a specific method, first, the second contact layer 28 and the second covering layer 27 are removed by etching using a hydrochloric acid-phosphoric acid mixture. The reaction stops when the active layer 25 is exposed. Next, the active layer 25 is removed by etching using a mixed solution of sulfuric acid and hydrogen peroxide (SPM). The reaction stops at the first covering layer 23. Next, the first covering layer 23 is removed halfway by etching using a hydrochloric acid-phosphoric acid mixture. Thereafter, the resist is removed using a cleaning solution such as acetone. In addition, the first covering layer 23 and the first contact layer 21 may be removed to expose the insulating layer 17.

[0180] (Step S13)

[0181] After adjusting the thickness of the back side of the support substrate 11, a back electrode 33 is formed on the back side of the support substrate 11 (see Figure 2 As a specific method for forming the back electrode 33, similar to the upper surface electrode 32, the back electrode 33 can be formed by forming a film of a material (e.g., Ti / Pt / Au) for forming the back electrode 33 using a vacuum evaporation device. An example of the film thickness of the back electrode 33 is Ti / Pt / Au=150nm / 300nm / 1500nm.

[0182] The thickness of the support substrate 11 can be adjusted by any method, but as an example, a method of grinding the semiconductor stack 20 side with a back grinding tape by a back grinding machine can be adopted. The thickness after grinding is adjusted within a range of 50 μm to 250 μm, for example, and is appropriately selected according to the purpose of the infrared LED element 1 and the subsequent process. As a specific example, the thickness of the support substrate 11 after grinding is 150 μm. After the grinding process is completed, it is peeled off from the tape and washed.

[0183] In addition, the thickness of the back surface side of the support substrate 11 may be adjusted as needed, and is not an essential step.

[0184] (Step S14)

[0185] Next, the entire support substrate 11 is cut into chips. For example, with the back electrode 33 side adhered with a dicing tape, the support substrate 11 is cut from the upper surface electrode 32 side using a diamond blade or the like along the dicing line formed by the mesa etching in step S13.

[0186] Thereafter, the infrared LED element 1 formed into a chip is mounted on a stem or the like using a conductive adhesive such as Ag paste. The pad electrode 34 is connected to the column portion of the stem by wire bonding.

[0187] The infrared LED element 1 of the above-mentioned structure is the same as the conventional structure, and the second covering layer 27 equivalent to the second semiconductor layer is formed on the upper layer of the active layer 25, so that the band gap energy difference between the active layer and the second semiconductor layer is maintained at the same level as before. Moreover, the second contact layer 28 composed of the light emitting surface (first surface 28a) is easier to form the concave-convex portion 40 for improving the light extraction efficiency than InP. Therefore, the infrared LED element 1 becomes an element that can efficiently form a concave-convex shape for the light emitting surface (first surface 28a), and the luminous efficiency is difficult to decrease even when driven with a large current.

[0188] In the above embodiment, the first semiconductor layer (first contact layer 21 and first cladding layer 23 ) is a p-type semiconductor and the second semiconductor layer (second contact layer 28 and second cladding layer 27 ) is an n-type semiconductor, but the conductivity types of the two may be reversed.

[0189] Description of Reference Numerals

[0190] 1: Infrared LED components

[0191] 3: Growth substrate

[0192] 11: Support base plate

[0193] 13, 13a, 13b: Metal bonding layer

[0194] 15: Reflection layer

[0195] 17: Insulation layer

[0196] 20: Semiconductor stack

[0197] 21: First contact layer

[0198] 22: Buffer layer

[0199] 23: First covering layer

[0200] 24: ES layer

[0201] 25: Active layer

[0202] 27: Second covering layer

[0203] 28: Second contact layer

[0204] 28a: Side 1

[0205] 31: Internal electrode

[0206] 32: Upper surface electrode

[0207] 33: Back electrode

[0208] 34: Pad electrode

[0209] 36: Dielectric layer

[0210] 40: Concavoconvex part

[0211] L: Infrared light

Claims

1. An infrared LED element capable of emitting infrared light with a peak wavelength of 1,000 nm to 2,000 nm, characterized in that: The infrared LED element has: a conductive support substrate; and The semiconductor stack is disposed on the upper layer of the support substrate and is composed of a material that can be lattice matched to InP. The semiconductor stack has: A first semiconductor layer, disposed on a side closest to the support substrate and exhibiting a first conductivity type; an active layer disposed on the upper layer of the first semiconductor layer; A second semiconductor layer, disposed on an upper layer of the active layer and exhibiting a second conductivity type different from the first conductivity type; as well as The third semiconductor layer is disposed on the upper layer of the second semiconductor layer and is composed of Al a Ga b In c As, where 0≤a<1, 0<b<1, 0<c<1, a+b+c=1, The third semiconductor layer has a concavo-convex portion on a surface opposite to a surface on which the second semiconductor layer is located. The band gap energy of the third semiconductor layer is lower than the band gap energy of the second semiconductor layer, and is higher than the band gap energy of the active layer.

2. The infrared LED element according to claim 1, characterized in that: The second semiconductor layer is InP.

3. The infrared LED element according to claim 1 or 2, characterized in that: The thickness of the third semiconductor layer is 1 μm to 5 μm.

4. The infrared LED element according to claim 1 or 2, characterized in that: having a first electrode arranged to be in contact with a portion of the upper surface of the third semiconductor layer, The doping concentration of the third semiconductor layer is higher than that of the second semiconductor layer and is 5×10 17 / cm 3 above.

5. The infrared LED element according to claim 4, characterized in that: The doping concentration of the second semiconductor layer is 5×10 17 / cm 3 above, The doping concentration of the third semiconductor layer is 1×10 18 / cm 3 above.

6. The infrared LED element according to claim 4, characterized in that: have: a second electrode disposed on a surface of the support substrate on a side opposite to a side on which the semiconductor stack is disposed; and The reflective layer is disposed between the support substrate and the semiconductor stack and is made of a conductive material.

7. The infrared LED element according to claim 1 or 2, characterized in that: The band gap energy of the second semiconductor layer is 1.1 times or more relative to the band gap energy of the active layer.

8. The infrared LED element according to claim 1 or 2, characterized in that: The surface roughness (Ra) of the concavo-convex portion formed on the surface of the third semiconductor layer is 0.25 to 1.00.

Images