A buried electrode deep ultraviolet led device and a method of fabricating the same

Abstract

A deep ultraviolet LED device with buried electrodes and its fabrication method, comprising: a substrate, an AlN template, and a first n-Al x1 Ga 1‑x1 N-layer, quantum well layer, electron blocking layer, p-Al y1 Ga 1‑y1 N layer, p‑Al y Ga 1‑ y N-type contact layer, n-type electrode contact layer, n-type electrode pad layer, p-type electrode contact layer, p-type electrode pad layer, passivation layer, buried metal electrode, and second n-Al x1 Ga 1‑x1 N layers. This device is achieved through the first n-Al layer. x1 Ga 1‑x1 N layer and second n-Al x1 Ga 1‑x1 The metal electrodes buried in the N-layer act as a high-speed current transmission channel between the n-type electrode contact layer and the mesa, increasing the uniformity of current distribution, improving luminous efficiency, and enhancing the performance of polycrystalline n-Al. x1 Ga 1‑x1 The N is processed to form a porous structure as a DBR reflector, which increases light extraction and further improves light efficiency.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a deep ultraviolet LED device with a buried electrode and a preparation method thereof. BACKGROUND

[0002] In recent years, the deep ultraviolet (UVC) LED prepared based on AlGaN material has the advantages of energy saving, environmental protection, small size and long service life compared with mercury lamp. Especially for the deep ultraviolet LED with a wavelength shorter than 280 nm, it has great application prospects in the fields of sterilization and disinfection, air / water purification, photocuring, medical treatment and non-line-of-sight (NLOS) communication due to its characteristics which are not possessed by traditional light sources.

[0003] The AlGaN-based material deep ultraviolet LED with a wavelength shorter than 280 nm needs AlGaN material with a high Al component. However, the doping efficiency of the AlGaN material with a high Al component is low, which leads to a high resistivity of the AlGaN material and limits the lateral transmission of the carriers. The conventional deep ultraviolet LED chip generally adopts a flip chip structure, as shown in FIG. 1, which comprises a substrate 1, an AlN template 2 fixed on one side of the substrate 1, an n-AlGaN layer 3 fixed on one side of the AlN template 2 away from the substrate 1, a quantum well layer 4 fixed on one step surface of the n-AlGaN layer 3 away from the substrate 1, an electron blocking layer 5 fixed on one side of the quantum well layer 4 away from the substrate 1, a p-AlGaN layer 6 fixed on one side of the electron blocking layer 5 away from the substrate 1, a p-AlGaN contact layer 7 fixed on one side of the p-AlGaN layer 6 away from the substrate 1, an n-type electrode contact layer 8 fixed on the other step surface of the n-AlGaN layer 3 away from the substrate 1, an n-type electrode pad layer 9 fixed on one side of the n-type electrode contact layer 8 away from the substrate 1, a p-type electrode contact layer 10 fixed on one side of the p-AlGaN contact layer 7 away from the substrate 1, a p-type electrode pad layer 11 fixed on one side of the p-type electrode contact layer 10 away from the substrate 1, and a p-type electrode 12 fixed on one side of the p-type electrode pad layer 11 away from the substrate 1. Figure 1 x1 Ga 1-x1 N layer 3, the quantum well layer 4, the electron blocking layer 5, the p-Al x1 Ga 1-x1 N layer 6, the p-Al y1 Ga 1-y1 N contact layer 7, the p-type electrode contact layer 10, the p-type electrode pad layer 11 and the p-type electrode 12 are sequentially arranged on one side of the p-Al y1 Ga 1-y1 N layer 6 away from the substrate 1. y2 Ga 1-y2 N contact layer 7, the p-type electrode contact layer 10, the p-type electrode pad layer 11 and the p-type electrode 12 are sequentially arranged on one side of the p-Al x1 Ga 1-x1 N layer 3, the quantum well layer 4, the electron blocking layer 5, the p-Al y3 Ga 1-y3 N contact layer 7, the p-type electrode contact layer 10, the p-type electrode pad layer 11 and the p-type electrode 12 are sequentially arranged on one side of the p-Al x1 Ga 1-x1 N layer 3, the quantum well layer 4, the electron blocking layer 5, the p-Al y1 Ga 1-y1 N layer 6, the p-Al y2 Ga​1-y2 N contact layer 7, p-type electrode contact layer 10 and n-type electrode contact layer 8 contact the surface of the passivation layer 12. In such an inverted structure, the p-side uses electrode to cover the light-emitting mesa, and the problem of lateral expansion of p-AlGaN is effectively solved, but the conductivity of n-AlGaN is much smaller than that of metal, which leads to current aggregation on the light-emitting mesa near the n-electrode side, aggravation of sidewall leakage current, and a large amount of localized self-heating, thereby affecting the performance of the deep ultraviolet LED chip.

[0004] In addition, the deep ultraviolet LED with a vertical structure can well solve the problem of current aggregation, but the substrate peeling technology for high Al component AlGaN-based deep ultraviolet LED is not mature, the development process is complex, the yield is low, and the cost is high. SUMMARY

[0005] The present application provides a deep ultraviolet LED device with a buried electrode and a preparation method thereof, which is used to solve the problems of current aggregation, serious leakage current and reduced light-emitting efficiency caused by self-heating of the existing deep ultraviolet LED.

[0006] The technical scheme adopted by the present application to solve the above technical problems is as follows.

[0007] In a first aspect, the present application provides a deep ultraviolet LED device with a buried electrode, comprising:

[0008] a substrate;

[0009] an AlN template fixed on one side of the substrate;

[0010] a first n-Al x1 Ga 1-x1 N layer fixed on the side of the AlN template away from the substrate;

[0011] a buried metal electrode fixed on the side of the first n-Al x1 Ga 1-x1 N layer away from the substrate;

[0012] a second n-Al x1 Ga 1-x1 N layer fixed on the side of the buried metal electrode away from the substrate, and the side of the second n-Al x1 Ga 1-x1 N layer in contact with the buried metal electrode is polycrystalline and has a plurality of holes;

[0013] a quantum well layer fixed on the side of the second n-Al x1 Ga 1-x1 N layer away from the substrate;

[0014] an electron blocking layer fixed to a side of the quantum well layer distal from the substrate;

[0015] p-Al y1 Ga 1-y1 N layer fixed to a side of the electron blocking layer distal from the substrate;

[0016] p-Al y2 Ga 1-y2 N contact layer fixed to a side of the p-Al y1 Ga 1-y1 N layer distal from the substrate, the electron blocking layer, p-Al y1 Ga 1-y1 N layer, p-Al y2 Ga 1-y2 N contact layer decreasing in Al composition;

[0017] an n-type electrode contact layer fixed to a side of the buried metal electrode distal from the substrate and spaced apart from the second n-Al x1 Ga 1-x1 N layer;

[0018] an n-type electrode pad layer fixed to a side of the n-type electrode contact layer distal from the substrate;

[0019] a p-type electrode contact layer fixed to a side of the p-Al y2 Ga 1-y2 N contact layer distal from the substrate;

[0020] a p-type electrode pad layer fixed to a side of the p-type electrode contact layer distal from the substrate;

[0021] a passivation layer fixed to surfaces of the buried metal electrode, second n-Al x1 Ga 1-x1 N layer, quantum well layer, electron blocking layer, p-Al y1 Ga 1-y1 N layer, p-Al y2 Ga 1-y2 N contact layer, n-type electrode contact layer, and p-type electrode contact layer that contact air.

[0022] Preferably, the substrate is of a hetero-substrate material or a homo-substrate material, the hetero-substrate material being any one of sapphire, silicon carbide, silicon, and the homo-substrate material being GaN or AlN.

[0023] Preferably, the first n-Al x1 Ga 1-x1 N layer and the second n-Al x1 Ga 1-x1In the n-Alx1Ga1-x1N layer, 0.5 < x1 < 1, the first n-Al x1 Ga 1-x1 N layer and the second n-Al x1 Ga 1-x1 N layer have a total thickness of 100-5000 nm, the first n-Al x1 Ga 1-x1 N layer and the second n-Al x1 Ga 1-x1 N layer has a doping concentration ≥ 5 x 10 17 cm -3 .

[0024] Preferably, the material of the buried metal electrode is at least one of Ti, V, and TiN, and the thickness of the buried metal electrode is 50-500 nm.

[0025] Preferably, the quantum well layer is a multiple quantum well containing 3-5 periods of Al m Ga 1-m N well layers and Al n Ga 1-n N barrier layers, wherein the Al m Ga 1-m N well layers have a thickness of 2-5 nm, and the Al n Ga 1-n N barrier layers have a thickness of 4-10 nm, and n and m are both between 0 and 1 and n > m.

[0026] Preferably, the material of the electron blocking layer is p-Al y3 Ga 1-y3 N, 0.8 ≤ y3 ≤ 1, the thickness of the electron blocking layer is 5-30 nm, and the doping concentration of the electron blocking layer is ≥ 1 x 10 17 cm -3 .

[0027] Preferably, in the p-Al y1 Ga 1-y1 N layer, y1 < y3, the thickness of the p-Al y1 Ga 1-y1 N layer is 10-100 nm, and the doping concentration of the p-Al y1 Ga 1-y1 N layer is ≥ 1 x 10 17 cm -3 .

[0028] Preferably, in the p-Al y2 Ga 1-y2 N contact layer, y2 < y1, and the thickness of the p-Al y2 Ga 1-y2The thickness of the n-contact layer is 10-30 nm, and the p-Al y2 Ga 1-y2 The doping concentration of the n-contact layer is ≥1x10 17 cm -3 ;

[0029] More preferably, y2 is 0.

[0030] Preferably, the material of the n-type electrode contact layer comprises at least one of Pt, Ti, Al, Ni, Au, V, and the thickness of the n-type electrode contact layer is 20-200 nm.

[0031] Preferably, the material of the p-type electrode contact layer comprises at least one of Ni, Al, Au, ITO, Ti, Pt, Pd, Mg, Rh, and the thickness of the p-type electrode contact layer is 20-200 nm.

[0032] Preferably, the material of the n-type electrode pad layer and the p-type electrode pad layer respectively independently comprises at least one of Ti, Al, Ni, Au, Pt, Pd, V, and the thickness of the n-type electrode pad layer and the p-type electrode pad layer respectively independently is 500-2000 nm.

[0033] Preferably, the passivation layer is a non-conductive material; more preferably, the non-conductive material comprises at least one of SiO2, AlN, AlScN, AlGaN.

[0034] In a second aspect, the present application further provides a method for preparing the deep ultraviolet LED with the buried electrode, comprising the following steps:

[0035] Step 1: providing a substrate;

[0036] Step 2: growing an AlN template on the substrate;

[0037] Step 3: growing a first n-Al x1 Ga 1-x1 N layer on the AlN template;

[0038] Step 4: etching a pattern on the first n-Al x1 Ga 1-x1 N layer;

[0039] Step 5: preparing a pattern electrode on the n-Al x1 Ga 1-x1 N layer with the pattern to form a buried metal electrode;

[0040] Step 6: growing a second n-Al x1 Ga 1-x1Continuing epitaxy of a second n-Al x1 Ga 1-x1 N layer on the N layer

[0041] Step 7: solution treatment is performed on the second n-Al x1 Ga 1-x1 N layer which is in contact with the buried metal electrode x1 Ga 1-x1 N layer, and a plurality of holes are formed on one side of the second n-Al

[0042] Step 8: quantum well layers, electron blocking layers, p-Al x1 Ga 1-x1 N layers and p-Al y1 Ga 1-y1 N contact layers are epitaxially grown on the second n-Al y2 Ga 1-y2 N layer

[0043] Step 9: etching is performed on the epitaxial wafer in which the quantum well layers, electron blocking layers, p-Al y1 Ga 1-y1 N layers and p-Al y2 Ga 1-y2 N contact layers are grown, and the etching is performed to the buried metal electrode to form a mesa

[0044] Step 10: an n-type electrode contact layer is prepared on the side of the mesa formed by the etching and away from the substrate

[0045] Step 11: a p-type electrode contact layer is prepared on the side of the p-Al y2 Ga 1-y2 N contact layer of the mesa formed by the etching and away from the substrate

[0046] Step 12: an n-type electrode pad layer and a p-type electrode pad layer are respectively prepared on the sides of the n-type electrode contact layer and the p-type electrode contact layer and away from the substrate

[0047] Step 13: a passivation layer is prepared on the surfaces of the buried metal electrode, the second n-Al x1 Ga 1-x1 N layer, the quantum well layers, the electron blocking layers, the p-Al y1 Ga 1-y1 N layer, the p-Al y2 Ga 1-y2 N contact layer, the n-type electrode contact layer and the p-type electrode contact layer which are in contact with air

[0048] The principle of the present application is that, on the basis of the existing flip-chip structure of the deep ultraviolet LED, the first n-Al x1 Ga 1-x1 N layer and the second n-Alx1 Ga 1-x1 N layer, and the buried metal electrode is arranged on the second n-Al x1 Ga 1-x1 N layer. The structure of the buried metal electrode in the n-Al x1 Ga 1-x1 N layer and the second n-Al x1 Ga 1-x1 N layer. The current can be rapidly transmitted along the buried metal electrode, and the electrical performance of the device is improved. Meanwhile, the second n-Al x1 Ga 1-x1 N layer grown on the buried metal electrode is polycrystalline, and after etching, a DBR with a plurality of small holes can be formed to increase light extraction.

[0049] Compared with the prior art, the beneficial effects of the present application are as follows:

[0050] The buried electrode deep ultraviolet LED device has the buried metal electrode buried into the first n-Al x1 Ga 1-x1 N layer and the second n-Al x1 Ga 1-x1 N layer on the side of the mesa, and directly contacts the n-type electrode contact layer on the side of the n-type electrode contact layer. The metal has the advantages of good electrical conductivity and good thermal conductivity compared with the AlGaN material, and is used as a high-speed current transmission channel between the n-type electrode contact layer and the mesa, thereby increasing the uniformity of current distribution, relieving the problem of spontaneous heat aggregation, and improving the light efficiency.

[0051] Meanwhile, the second n-Al x1 Ga 1-x1 N layer grown on the metal is polycrystalline, and for this purpose, the polycrystal is treated by a solution to form a plurality of small holes, which can be used as a DBR mirror to increase light extraction and further improve the light efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments of the present application or the prior art will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0053] Figure 1 is a schematic diagram of a flip-chip structure deep ultraviolet LED in the prior art;

[0054] Figure 2 A schematic diagram of a deep ultraviolet LED of the buried electrode of the present application;

[0055] Figure 3 A process flow diagram of a manufacturing method of a deep ultraviolet LED of the buried electrode of the present application;

[0056] Figure 4 A buried metal electrode and an n-Al x1 Ga 1-x1 N layer of the deep ultraviolet LED of the present application;

[0057] In the figure, 1, a substrate, 2, an AlN template, 3, a first n-Al x1 Ga 1-x1 N layer, 4, a quantum well layer, 5, an electron blocking layer, 6, a p-Al y1 Ga 1-y1 N layer, 7, a p-Al y2 Ga 1-y2 N contact layer, 8, an n-type electrode contact layer, 9, an n-type electrode pad layer, 10, a p-type electrode contact layer, 11, a p-type electrode pad layer, 12, a passivation layer, 13, a current, 14, a buried metal electrode, 15, a second n-Al x1 Ga 1-x1 N layer. DETAILED DESCRIPTION

[0058] Embodiments of the present application are described below in detail, examples of which are shown in the accompanying drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the accompanying drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application.

[0059] In the description of the present application, it is to be understood that the terms "upper", "lower", "horizontal", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0060] As Figure 2 and Figure 4 shown, the deep ultraviolet LED device of the buried electrode of the present application comprises:

[0061] a substrate 1;

[0062] an AlN template 2 fixed to one side of the substrate 1;

[0063] a first n-Alx1 Ga 1-x1 N layer 3, fixed on the side of the AlN template 2 away from the substrate 1;

[0064] Buried metal electrode 14, fixed on the side of the first n-Al x1 Ga 1-x1 N layer 3 away from the substrate 1;

[0065] Second n-Al x1 Ga 1-x1 N layer 15, fixed on the side of the buried metal electrode 14 away from the substrate 1, and in contact with the second n-Al x1 Ga 1-x1 N layer 15 presents polycrystalline on one side and has several holes;

[0066] Quantum well layer 4, fixed on the side of the n-Al x1 Ga 1-x1 N layer 3 away from the substrate 1;

[0067] Electron blocking layer 5, fixed on the side of the quantum well layer 4 away from the substrate 1;

[0068] p-Al y1 Ga 1-y1 N layer 6, fixed on the side of the electron blocking layer 5 away from the substrate 1;

[0069] p-Al y2 Ga 1-y2 N contact layer 7, fixed on the side of the p-Al y1 Ga 1-y1 N layer 6 away from the substrate 1, the electron blocking layer 5, p-Al y1 Ga 1-y1 N layer 6, p-Al y2 Ga 1-y2 N contact layer 7 decreases in Al composition;

[0070] n-type electrode contact layer 8, fixed on the side of the buried metal electrode 14 away from the substrate 1, and in contact with the second n-Al x1 Ga 1-x1 N layer 15 is spaced apart (i.e. the n-type electrode contact layer 8 and the second n-Al x1 Ga 1-x1 N layer 15 is not in contact);

[0071] n-type electrode pad layer 9, fixed on the side of the n-type electrode contact layer 8 away from the substrate 1;

[0072] p-type electrode contact layer 10, fixed on the side of the p-Al y2Ga 1-y2 N contact layer 7 is away from one side of the substrate 1;

[0073] p-type electrode pad layer 11, fixed to one side of the p-type electrode contact layer 10 away from the substrate 1;

[0074] passivation layer 12, fixed to the buried metal electrode 14, second n-Al x1 Ga 1-x1 N layer 15, quantum well layer 4, electron blocking layer 5, p-Al y1 Ga 1-y1 N layer 6, p-Al y2 Ga 1-y2 N contact layer 7, n-type electrode contact layer 8 and p-type electrode contact layer 10 contact the air surface.

[0075] In the above technical solution, the material of the substrate 1 is a heterogeneous substrate material or a homogeneous substrate material, the heterogeneous substrate material is any one of sapphire, silicon carbide and silicon, and the homogeneous substrate material is GaN or AlN.

[0076] In the above technical solution, the first n-Al x1 Ga 1-x1 N layer 3 and the second n-Al x1 Ga 1-x1 N layer 15, 0.5 < x1 < 1, the first n-Al x1 Ga 1-x1 N layer 3 and the second n-Al x1 Ga 1-x1 N layer 15, the total thickness is 100-5000nm, the first n-Al x1 Ga 1-x1 N layer 3 and the second n-Al x1 Ga 1-x1 N layer 15, the doping concentration is ≥5×10 17 cm -3 .

[0077] In the above technical solution, the material of the buried metal electrode 14 is at least one of Ti, V and TiN, and the thickness of the buried metal electrode 14 is 50-500nm.

[0078] In the above technical solution, the quantum well layer 4 is a multi-quantum well, containing 3-5 periods of Al m Ga 1-m N well layer and Al n Ga 1-n N barrier layer, wherein the Al m Ga 1-m N well layer is 2-5nm thick, and the Al n Ga1-n The thickness of the n-type GaN layer is 4-10 nm, and n>m.

[0079] In the technical solution, the material of the electron blocking layer 5 is p-Al y3 Ga 1-y3 N, 0.8≤y3≤1, the thickness of the electron blocking layer 5 is 5-30 nm, and the doping concentration of the electron blocking layer 5 is ≥1×10 17 cm -3 .

[0080] In the technical solution, in the p-Al y1 Ga 1-y1 N layer 6, y1<y3, the thickness of the p-Al y1 Ga 1-y1 N layer 6 is 10-100 nm, and the doping concentration of the p-Al y1 Ga 1-y1 N layer 6 is ≥1×10 17 cm -3 .

[0081] In the technical solution, in the p-Al y2 Ga 1-y2 N contact layer 7, y2<y1, the thickness of the p-Al y2 Ga 1-y2 N contact layer 7 is 10-30 nm, and the doping concentration of the p-Al y2 Ga 1-y2 N contact layer 7 is ≥1×10 17 cm -3 ; preferably y2 is 0.

[0082] In the technical solution, the material of the n-type electrode contact layer 8 includes at least one of Pt, Ti, Al, Ni, Au, V, and the thickness of the n-type electrode contact layer 8 is 20-200 nm.

[0083] In the technical solution, the material of the p-type electrode contact layer 10 includes at least one of Ni, Al, Au, ITO, Ti, Pt, Pd, Mg, Rh, and the thickness of the p-type electrode contact layer 10 is 20-200 nm.

[0084] In the technical solution, the materials of the n-type electrode pad layer 9 and the p-type electrode pad layer 11 respectively independently include at least one of Ti, Al, Ni, Au, Pt, Pd, and V, and the thicknesses of the n-type electrode pad layer 9 and the p-type electrode pad layer 11 respectively independently are 500-2000 nm.

[0085] In the technical solution, the passivation layer 12 is made of non-conductive material; preferably, the non-conductive material comprises at least one of SiO2, AlN, AlScN and AlGaN.

[0086] As shown in Figure 3 , the method for manufacturing the deep ultraviolet LED with buried electrode comprises the following steps:

[0087] Step 1: providing a substrate 1;

[0088] Step 2: growing an AlN template 2 on the substrate 1;

[0089] Step 3: growing an n-Al x1 Ga 1-x1 N layer 3 on the AlN template 2;

[0090] Step 4: etching a pattern on the first n-Al x1 Ga 1-x1 N layer 3;

[0091] Step 5: manufacturing a pattern electrode on the first n-Al x1 Ga 1-x1 N layer 3 with the pattern to form a buried metal electrode 14;

[0092] Step 6: continuing to epitaxially grow a second n-Al x1 Ga 1-x1 N layer 15 on the first n-Al x1 Ga 1-x1 N layer 3 with the buried metal electrode 14;

[0093] Step 7: performing solution treatment on the second n-Al x1 Ga 1-x1 N layer 15 that is continuously epitaxially grown, forming a plurality of holes on one side of the second n-Al x1 Ga 1-x1 N layer 15 that is in contact with the buried metal electrode 14;

[0094] Step 8: continuing to epitaxially grow a quantum well layer 4, an electron blocking layer 5, a p-Al x1 Ga 1-x1 N layer 6 and a p-Al y1 Ga 1- y1 N contact layer 7 on the second n-Al y2 Ga 1-y2 N layer 15;

[0095] Step 9: performing solution treatment on the growth of the quantum well layer 4, the electron blocking layer 5, the p-Al y1 Ga 1-y1 N layer 6 and the p-Aly2 Ga 1-y2 The epitaxial wafer of N contact layer 7 is etched down to the buried metal electrode 14 to form a mesa.

[0096] Step 10: Prepare an n-type electrode contact layer 8 on the side of the metal electrode 14 away from the substrate on the mesa formed by the etching;

[0097] Step 11: On the etched mesa p-Al y2 Ga 1-y2 A p-type electrode contact layer 10 is prepared on the side of the N-contact layer 7 away from the substrate;

[0098] Step 12: Prepare an n-type electrode pad layer 9 and a p-type electrode pad layer 11 on the side of the n-type electrode contact layer 8 and the p-type electrode contact layer 10 away from the substrate, respectively;

[0099] Step 13: In the buried metal electrode 14, the second n-Al x1 Ga 1-x1 N-layer 15, quantum well layer 4, electron blocking layer 5, p-Al y1 Ga 1-y1 N layer 6, p-Al y2 Ga 1-y2 A passivation layer 12 is prepared on the surface of the N-type contact layer 7, the n-type electrode contact layer 8, and the p-type electrode contact layer 10 that are in contact with air.

[0100] This invention, based on existing flip-chip deep ultraviolet LEDs, focuses on the first n-Al... x1 Ga 1-x1 N layer 3 and the second n-Al x1 Ga 1-x1 Buried metal electrodes are placed between layers N and 15, presenting an n-Al layer. x1 Ga 1-x1 The structure of the embedded metal electrode in N. Current 13 can be applied in the first n-Al... x1 Ga 1-x1 N layer 3 and the second n-Al x1 Ga 1-x1 Within the N-layer 15, rapid transport occurs along the buried metal electrode 14, improving the device's electrical performance. Simultaneously, due to the disordered crystal orientation of the metal and the high migration barrier of Al atoms, a second n-Al atom continues to grow on the buried metal electrode 14. x1 Ga 1-x1 The N-layer 15 exhibits a polycrystalline structure, which, after etching, can form a porous DBR structure, increasing light extraction.

[0101] The above merely describes exemplary embodiments of the present application, and only specific examples of the structure of the present application are described, which are merely intended to explain the principles of the present application and cannot be interpreted as limiting the protection scope of the present application in any way. Based on the explanations herein, any modifications, equivalent replacements and improvements made within the spirit and principle of the present application, and other specific embodiments of the present application that can be conceived by those skilled in the art without creative labor, should be included in the protection scope of the present application.

Claims

1. A deep ultraviolet LED device with a buried electrode, characterized in that, The application relates to a quantum well structure, which comprises: a substrate (1); an AlN template (2) fixed to one side of the substrate (1); first n-Al x1 Ga 1-x1 a layer of N (3) fixed on the side of the AlN template (2) facing away from the substrate (1) a buried metal electrode (14) fixed to the first n-Al x1 Ga 1-x1 N layer (3) on the side facing away from the substrate (1); second n-Al x1 Ga 1-x1 N layer (15) fixed to the side of the buried metal electrode (14) away from the substrate (1) and in contact with the buried metal electrode (14) second n-Al x1 Ga 1-x1 The side of the N layer (15) presents a polycrystalline form and has several holes; a quantum well layer (4) fixed to the second n-Al x1 Ga 1-x1 N layer (15) remote from the side of the substrate (1) an electron blocking layer (5) fixed to the side of the quantum well layer (4) away from the substrate (1); p-Al y1 Ga 1-y1 a layer (6) of GaN, fixed to the side of the electron-blocking layer (5) far from the substrate (1); p-Al y2 Ga 1-y2 N contact layer (7) fixed to the p-Al y1 Ga 1-y1 N layer (6) away from the side of the substrate (1), the electron blocking layer (5), p-Al y1 Ga 1-y1 N layer (6), p-Al y2 Ga 1-y2 N contact layer (7) decreases in Al composition; n-type electrode contact layer (8) fixed to the side of the buried metal electrode (14) facing away from the substrate (1) and spaced from the second n-Al x1 Ga 1-x1 N layer (15) an n-type electrode pad layer (9) fixed to the side of the n-type electrode contact layer (8) away from the substrate (1); a p-type electrode contact layer (10) fixed to the p-Al y2 Ga 1-y2 N contact layer (7) on the side remote from the substrate (1); a p-type electrode pad layer (11) fixed to the side of the p-type electrode contact layer (10) away from the substrate (1); a passivation layer (12) fixed to the buried metal electrode (14), a second n-Al x1 Ga 1-x1 N layer (15), a quantum well layer (4), an electron blocking layer (5), a p-Al y1 Ga 1-y1 N layer (6), a p-Al y2 Ga 1-y2 N contact layer (7), an n-type electrode contact layer (8) and a p-type electrode contact layer (10) contact the air surface.

2. The DUV LED device of claim 1, wherein, the material of the substrate (1) is a hetero-substrate material or a homo-substrate material, the hetero-substrate material is any one of sapphire, silicon carbide and silicon, and the homo-substrate material is GaN or AlN.

3. The buried electrode DUV LED device of claim 1, wherein, said first n-Al x1 Ga 1-x1 N layer (3) and second n-Al x1 Ga 1-x1 N layer (15), 0.5 < x1 < 1, said first n-Al x1 Ga 1-x1 N layer (3) and second n-Al x1 Ga 1-x1 N layer (15), the total thickness of 100 ~ 5000 nm, first n-Al x1 Ga 1-x1 N layer (3) and second n-Al x1 Ga 1- x1 N layer (15), the doping concentration ≥ 5 × 10 17 cm -3 .

4. The buried electrode DUV LED device of claim 1, wherein, The material of the buried metal electrode (14) is at least one of Ti, V and TiN, and the thickness of the buried metal electrode (14) is 50-500 nm.

5. The buried electrode DUV LED device of claim 1, wherein, The quantum well layer (4) is a multi-quantum well, containing 3-5 periods of Al m Ga 1-m N well layer and Al n Ga 1-n N barrier layer, wherein the Al m Ga 1-m N well layer is 2-5 nm thick, and the Al n Ga 1-n N barrier layer is 4-10 nm thick, and n>m.

6. The buried electrode DUV LED device of claim 1, wherein, The material of the electron blocking layer (5) is p-Al y3 Ga 1-y3 N, 0.8≤y3≤1, the thickness of the electron blocking layer (5) is 5-30 nm, the doping concentration of the electron blocking layer (5) is ≥1x10 17 cm -3 ; The p-Al y1 Ga 1-y1 N layer (6) has a thickness of 10 to 100 nm, and the p-Al y1 Ga 1-y1 N layer (6) has a doping concentration of > 1 x 10 y1 cm 1-y1 -2. 17 cm -3 -2. The p-Al y2 Ga 1-y2 In the N contact layer (7), y2 < y1, the p-Al y2 Ga 1-y2 The thickness of the N contact layer (7) is 10-30 nm, the p-Al y2 Ga 1-y2 The doping concentration of the N contact layer (7) is ≥ 1 x 10 17 cm -3 .

7. The buried electrode DUV LED device of claim 1, wherein, The material of the n-type electrode contact layer (8) comprises at least one of Pt, Ti, Al, Ni, Au and V, and the thickness of the n-type electrode contact layer (8) is 20-200 nm. The material of the p-type electrode contact layer (10) comprises at least one of Ni, Al, Au, ITO, Ti, Pt, Pd, Mg and Rh, and the thickness of the p-type electrode contact layer (10) is 20-200 nm.

8. The buried electrode DUV LED device of claim 1, wherein, The materials of the n-type electrode pad layer (9) and the p-type electrode pad layer (11) independently comprise at least one of Ti, Al, Ni, Au, Pt, Pd and V, and the thicknesses of the n-type electrode pad layer (9) and the p-type electrode pad layer (11) are independently 500-2000 nm.

9. The buried electrode DUV LED device of claim 1, wherein, The passivation layer (12) is a non-conductive material, and the non-conductive material comprises at least one of SiO2, AlN, AlScN and AlGaN.

10. The method of producing a buried electrode deep ultraviolet LED according to any one of claims 1 to 9, wherein The application further discloses a preparation method of the quantum well structure, which comprises the following steps: Step 1: providing a substrate (1); Step 2: growing an AlN template (2) on the substrate (1); Step 3: growing a first n-Al x1 Ga 1-x1 N layer (3) on the AlN template (2); Step 4: etching a pattern on the first n-Al x1 Ga 1-x1 N layer (3) Step 5: A patterned first n-Al x1 Ga 1-x1 N layer (3) is prepared on the patterned first n-Al N layer (3) to form a buried metal electrode (14); Step 6: Continue epitaxy of a second n-Al x1 Ga 1-x1 N layer (15) on the first n-Al x1 Ga 1-x1 N layer (3) with buried metal electrodes (14) Step 7: Solution treatment of the second n-Al x1 Ga 1-x1 N layer (15) in contact with the buried metal electrode (14) x1 Ga 1-x1 holes are formed on one side of the second n-Al Step 8: On the second n-Al x1 Ga 1-x1 N layer (15) epitaxial quantum well layer (4), electron barrier layer (5), p-Al y1 Ga 1-y1 N layer (6) and p-Al y2 Ga 1-y2 N contact layer (7); Step 9: Etching of the epitaxial wafer grown with the quantum well layer (4), electron blocking layer (5), p-Al y1 Ga 1-y1 N layer (6) and p-Al y2 Ga 1-y2 N contact layer (7) to the buried metal electrode (14) to form a mesa; Step 10: preparing an n-type electrode contact layer (8) on the side of the mesa buried metal electrode (14) away from the substrate; Step 11: A mesa p-Al y2 Ga 1-y2 N contact layer (7) is prepared away from the substrate side of the p-type electrode contact layer (10); Step 12: preparing an n-type electrode pad layer (9) and a p-type electrode pad layer (11) on the sides of the n-type electrode contact layer (8) and the p-type electrode contact layer (10) away from the substrate respectively; Step 12: preparing an n-type electrode pad layer (9) and a p-type electrode pad layer (11) on the sides of the n-type electrode contact layer (8) and the p-type electrode contact layer (10) away from the substrate respectively; Step 13: A passivation layer (12) is prepared on the surface of the buried metal electrode (14), the second n-Al x1 Ga 1-x1 N layer (15), the quantum well layer (4), the electron blocking layer (5), the p-Al y1 Ga 1-y1 N layer (6), the p-Al y2 Ga 1-y2 N contact layer (7), the n-type electrode contact layer (8), and the p-type electrode contact layer (10) which are exposed to air.

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