Display device

Abstract

The invention provides a display device. A display device according to an embodiment includes: a substrate; a first electrode and a second electrode disposed on the substrate and extending in a first direction and spaced apart from each other; a first insulating layer disposed on the first electrode and the second electrode; a light emitting element disposed on the first insulating layer and disposed between the first electrode and the second electrode; and a first connection electrode and a second connection electrode, the first connection electrode being connected to one end of the light-emitting element, the second connection electrode being connected to the other end of the light-emitting element, in which the first insulation layer includes a trench portion overlapping the light-emitting element and including a plurality of trenches.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] As multimedia develops, the importance of display devices is increasing. In response to this, various types of display devices such as organic light emitting display devices (OLED: Organic Light Emitting Display) and liquid crystal display devices (LCD: Liquid Crystal Display) are being used.

[0003] As a device for displaying an image, there is a self-luminous display device including a light-emitting element. Self-luminous display devices include organic light-emitting display devices including a light-emitting element using organic substances as light-emitting materials, and inorganic light-emitting display devices including a light-emitting element using inorganic substances as light-emitting materials. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a display device which can prevent a seam from being generated in a first insulating layer due to a step difference of an electrode and improve the neat arrangement of light emitting elements.

[0005] The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those skilled in the art through the following description.

[0006] A display device according to one embodiment for solving the above technical problems may include: a substrate; a first electrode and a second electrode, which are arranged on the substrate, extend along a first direction and are separated from each other; a first insulating layer, which is arranged on the first electrode and the second electrode; a light-emitting element, which is arranged on the first insulating layer and between the first electrode and the second electrode; and a first connecting electrode and a second connecting electrode, the first connecting electrode being connected to one end of the light-emitting element, and the second connecting electrode being connected to the other end of the light-emitting element, wherein the first insulating layer may include a groove portion overlapping the light-emitting element and including a plurality of grooves.

[0007] The groove portion may include: a first groove portion overlapping one end portion of the light emitting element; and a second groove portion overlapping the other end portion of the light emitting element.

[0008] The first groove portion may overlap with the first electrode and extend side by side, and the second groove portion may overlap with the second electrode and extend side by side.

[0009] The side of the first groove portion can be aligned neatly with the side of one end portion of the light-emitting element, and the side of the second groove portion can be aligned neatly with the side of the other end portion of the light-emitting element.

[0010] The groove portion can be in contact with the lower surface of the light-emitting element.

[0011] The depth of the groove portion can be configured to be 1% to 30% of the thickness of the first insulating layer.

[0012] The first insulating layer can include a silicon oxynitride represented by Chemical Formula 1 below.

[0013] [Chemical Formula 1] Si x O y N z (wherein x, y, and z respectively satisfy 34.6 < x < 42.9, 24.2 < y < 63.8, 1.5 < z < 32.9, and x, y, and z are atomic ratios.) The thickness of the first insulating layer can be 2000 to 3000 .

[0014] The refractive index of the first insulating layer can be greater than 1.4 and less than 1.63.

[0015] The display device may further include: a second insulating layer disposed on the light-emitting element, wherein the etching selectivity between the first insulating layer and the second insulating layer can be 4.1 or more.

[0016] Moreover, a display device according to an embodiment may include: a substrate; a first electrode and a second electrode disposed on the substrate and extending along a first direction and spaced apart from each other; a first insulating layer disposed on the first electrode and the second electrode; a light-emitting element disposed on the first insulating layer and disposed between the first electrode and the second electrode; and a first connection electrode and a second connection electrode, the first connection electrode being connected to one end portion of the light-emitting element, the second connection electrode being connected to the other end portion of the light-emitting element, wherein the first insulating layer may include a protruding portion overlapping with the light-emitting element and including a plurality of protruding structures.

[0017] The protruding portion may include: a first protruding portion overlapping with one end portion of the light-emitting element; and a second protruding portion overlapping with the other end portion of the light-emitting element.

[0018] The first protruding portion may overlap with the first electrode and extend side by side, and the second protruding portion may overlap with the second electrode and extend side by side.

[0019] The side of the first protrusion can be aligned neatly with the side of one end of the light-emitting element, and the side of the second protrusion can be aligned neatly with the side of the other end of the light-emitting element.

[0020] The protrusion can be in contact with the lower surface of the light-emitting element.

[0021] The height of the protruding structure can be configured to be 1% to 30% of the thickness of the first insulating layer.

[0022] The first insulating layer can include a silicon oxynitride represented by the following Chemical Formula 1.

[0023] [Chemical Formula 1] Si x O y N z (Wherein, x, y, and z respectively satisfy 34.6 < x < 42.9, 24.2 < y < 63.8, 1.5 < z < 32.9, and x, y, and z are atomic ratios.) The thickness of the first insulating layer can be 2000 to 3000 .

[0024] The refractive index of the first insulating layer can be greater than 1.4 and less than 1.63.

[0025] The display device may further include: a second insulating layer disposed on the light-emitting element, wherein the etching selectivity between the first insulating layer and the second insulating layer can be 4.1 or more.

[0026] Specific matters of other embodiments are included in the detailed description and the drawings.

[0027] According to an embodiment of the display device, by forming a first insulating layer including a silicon oxynitride having a composition ratio of Chemical Formula 1, it is possible to prevent seams from occurring on the side surface of the electrode, and it is possible to facilitate the neat alignment of the light-emitting elements and improve the light extraction efficiency.

[0028] Moreover, the degree of neat alignment of the light-emitting elements can be improved by forming a groove portion or a protrusion portion in the first insulating layer.

[0029] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0031] Figure 2 is a plan view showing the arrangement of a plurality of wirings included in a display device according to an embodiment.

[0032] Figure 3 is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0033] Figure 4 is a plan view showing one pixel of a display device according to an embodiment.

[0034] Figure 5 is along Figure 4 Cross-sectional view taken along line E1-E1'.

[0035] Figure 6 is along Figure 4 Cross-sectional view taken along line E2-E2'.

[0036] Figure 7 Is magnification Figure 5 Figure 1 shows the A region of the graph.

[0037] Figure 8 Is magnification Figure 5 Floor plan of area A.

[0038] Fig. 9 is a cross-sectional view showing a first insulating layer of a display device according to an embodiment.

[0039] Fig.10 is a schematic diagram of a light emitting element according to an embodiment.

[0040] Fig.11 is a cross-sectional view showing a display device according to another embodiment.

[0041] Fig.12 Is magnification Fig.11 A diagram of a portion of an area.

[0042] Fig.13 2 is a diagram showing a protruding portion of the first insulating layer.

[0043] Fig.14 is a cross-sectional view showing a display device according to still another embodiment.

[0044] Fig.15 is a transmission electron microscope image according to Comparative Example 1.

[0045] Fig.16 is a transmission electron microscope image according to Comparative Example 2.

[0046] Fig.17 is a transmission electron microscope image according to Comparative Example 3.

[0047] Fig.18 is a transmission electron microscope image according to an embodiment.

[0048] Description of Reference Numerals 10: Display device RME1: First electrode RME2: Second electrode PAS1: First insulation layer PAS2: Second insulation layer ED: Light Emitting Element CNE1: First connection electrode CNE2: Second connection electrode TRP: Groove TRP1: First groove part TRP2: Second groove part PRU: Protrusion PRU1: First protrusion PRU2: Second protrusion DETAILED DESCRIPTION

[0049] The advantages and features of the present invention and the methods for achieving the advantages and features of the present invention as well as the methods for achieving the advantages and features of the present invention can be clearly seen by referring to the embodiments described in detail below in conjunction with the accompanying drawings. However, the present invention can be implemented in a variety of different forms and is not limited to the embodiments disclosed below. The purpose of providing the embodiments is only to make the disclosure of the present invention complete and to fully inform the scope of the invention to those with ordinary knowledge in the technical field to which the present invention belongs. The present invention is only defined by the scope of the claims.

[0050] When an element or layer is mentioned as being "on" another element or layer, it includes being immediately above the other element or layer or having another layer or other element in between. Similarly, when it is referred to as "below", "left" and "right", it includes all cases where it is arranged directly adjacent to another element or having another layer or other element in between. Throughout the specification, the same reference numerals refer to the same constituent elements.

[0051] Although the terms "first" and "second" are used to describe various components, these components are obviously not limited to these terms. These terms are only used to distinguish one component from another component. Therefore, the first component mentioned below can obviously also be the second component within the technical concept of the present invention.

[0052] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0053] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0054] Reference Figure 1 , the display device 10 displays a video or a still image. The display device 10 may refer to all electronic devices that provide a display screen. For example, the display device 10 may include a television, a notebook computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC: Personal Computer), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP: Portable Multimedia Player), a navigator, a game console, a digital camera, a video camera, etc. that provide a display screen.

[0055] The display device 10 includes a display panel that provides a display screen. Examples of the display panel may include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, etc. Below, as an example of a display panel, an inorganic light emitting diode display panel is illustrated, but it is not limited thereto, and as long as the same technical concept can be applied, it can also be applied to other display panels.

[0056] The shape of the display device 10 can be variously deformed. For example, the display device 10 can have a horizontally long rectangle, a vertically long rectangle, a square, a quadrilateral with rounded corners (vertex), other polygons, a circle, and the like. The shape of the display area DPA of the display device 10 can also be similar to the overall shape of the display device 10. Figure 1 , a display device 10 having a rectangular shape whose length in the second direction DR2 is long is shown.

[0057] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA is an area where a picture can be displayed, and the non-display area NDA is an area where a picture is not displayed. The display area DPA may also be referred to as an active area, and the non-display area NDA may also be referred to as a non-active area. The display area DPA may occupy approximately the center of the display device 10.

[0058] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in rows and columns. The shape of each pixel PX may be a rectangle or a square on a plane, but is not limited thereto, and may also be a rhombus shape with each side inclined relative to one direction. Each pixel PX may be arranged in a stripe type or an island type. Furthermore, each of the pixels PX may include one or more light-emitting elements that emit light of a specific wavelength band to display a specific color.

[0059] A non-display area NDA may be arranged around the display area DPA. The non-display area NDA may surround the display area DPA in whole or in part. The display area DPA may be in a rectangular shape, and the non-display area NDA may be arranged to be adjacent to four sides of the display area DPA. The non-display area NDA may constitute a frame of the display device 10. In each non-display area NDA, a wiring or circuit driving unit included in the display device 10 may be arranged, or an external device may be mounted.

[0060] Figure 2 is a plan view showing the arrangement of a plurality of wirings included in a display device according to an embodiment.

[0061] Reference Figure 2 , the display device 10 may include a plurality of wirings. The display device 10 may include a plurality of scan lines SL (SL1, SL2, SL3), a plurality of data lines DTL (DTL1, DTL2, DTL3), an initialization voltage wiring VIL, and a plurality of voltage wirings VL (VL1, VL2, VL3, VL4), etc. Although not shown in the drawings, the display device 10 may also be arranged with other wirings.

[0062] The first scan line SL1 and the second scan line SL2 may be arranged to extend along the first direction DR1. The first scan line SL1 and the second scan line SL2 may be arranged to be adjacent to each other, and may be arranged to be spaced apart from other first scan lines SL1 and second scan lines SL2 along the second direction DR2. The first scan line SL1 and the second scan line SL2 may be connected to a scan wiring pad WPD_SC connected to a scan driving part (not shown). The first scan line SL1 and the second scan line SL2 may be arranged to extend from a pad area PDA arranged in the non-display area NDA to the display area DPA.

[0063] The third scan line SL3 may be arranged to extend along the second direction DR2 and be arranged spaced apart from other third scan lines SL3 along the first direction DR1. One third scan line SL3 may be connected to more than one first scan line SL1 or more than one second scan line SL2. In one embodiment, the first scan line SL1 and the second scan line SL2 may be formed by a conductive layer arranged at a different layer from the third scan line SL3. The plurality of scan lines SL may have a mesh structure on the entire surface of the display area DPA, but is not limited thereto.

[0064] In addition, in this specification, the meaning of "connection" can not only mean that one component is connected to another component by physical contact with each other, but also that it is connected through other components. And it can be understood that as an integrated component, one part and another part are connected to each other due to the integrated component. Further, the connection between one component and another component can be interpreted as including the meaning of electrical connection through another component in addition to direct contact connection.

[0065] The data lines DTL may be arranged to extend along the first direction DR1. The data lines DTL include a first data line DTL1, a second data line DTL2, and a third data line DTL3, and one first data line DTL1, one second data line DTL2, and one third data line DTL3 form a pair and are arranged adjacent to each other. Each of the data lines DTL1, DTL2, and DTL3 may be arranged to extend from a pad area PDA arranged in a non-display area NDA to a display area DPA. However, this is not limited thereto, and a plurality of data lines DTL may also be arranged at equal intervals between a first voltage wiring VL1 and a second voltage wiring VL2 described later.

[0066] The initialization voltage wiring VIL may be arranged to extend along the first direction DR1. The initialization voltage wiring VIL may be arranged between the data line DTL and the first and second scan lines SL1 and SL2. The initialization voltage wiring VIL may be arranged to extend from the pad area PDA arranged in the non-display area NDA to the display area DPA.

[0067] The first voltage wiring VL1 and the second voltage wiring VL2 are arranged to extend along the first direction DR1, and the third voltage wiring VL3 and the fourth voltage wiring VL4 are arranged to extend along the second direction DR2. The first voltage wiring VL1 and the second voltage wiring VL2 may be arranged alternately along the second direction DR2, and the third voltage wiring VL3 and the fourth voltage wiring VL4 may be arranged alternately along the first direction DR1. The first voltage wiring VL1 and the second voltage wiring VL2 may extend along the first direction DR1 and be arranged across the display area DPA, and a portion of the third voltage wiring VL3 and the fourth voltage wiring VL4 may be arranged in the display area DPA, and the other wiring may be arranged in the non-display area NDA located on both sides of the display area DPA in the first direction DR1. The first voltage wiring VL1 and the second voltage wiring VL2 may be formed using a conductive layer arranged at a different layer from the third voltage wiring VL3 and the fourth voltage wiring VL4. The first voltage wiring VL1 may be connected to at least one third voltage wiring VL3 , the second voltage wiring VL2 may be connected to at least one fourth voltage wiring VL4 , and the plurality of voltage wirings VL may have a mesh structure on the entire surface of the display area DPA.

[0068] The first scan line SL1, the second scan line SL2, the data line DTL, the initialization voltage wiring VIL, the first voltage wiring VL1, and the second voltage wiring VL2 may be electrically connected to at least one wiring pad WPD. Each wiring pad WPD may be arranged in the non-display area NDA. In one embodiment, each wiring pad WPD may be arranged in the pad area PDA located at the lower side of the display area DPA as the other side of the first direction DR1. The first scan line SL1 and the second scan line SL2 are connected to the scan wiring pad WPD_SC arranged in the pad area PDA, and each of the plurality of data lines DTL is connected to a different data wiring pad WPD_DT. The initialization voltage wiring VIL is connected to the initialization wiring pad WPD_Vint, the first voltage wiring VL1 is connected to the first voltage wiring pad WPD_VL1, and the second voltage wiring VL2 is connected to the second voltage wiring pad WPD_VL2. An external device may be mounted on the wiring pad WPD. The external device may be mounted on the wiring pad WPD by an anisotropic conductive film, ultrasonic bonding, or the like. In the drawings, the wiring pads WPD are arranged in the pad area PDA arranged below the display area DPA, but the present invention is not limited thereto. Some of the wiring pads WPD may also be arranged in any area above or on the left or right sides of the display area DPA.

[0069] Each pixel PX or sub-pixel SPXn (n is an integer from 1 to 3) of the display device 10 includes a pixel driving circuit. The above-mentioned wiring can apply a driving signal to each pixel driving circuit while passing through each pixel PX or its surroundings. The pixel driving circuit may include transistors and capacitors. The number of transistors and capacitors of each pixel driving circuit may be variously deformed. According to one embodiment, each sub-pixel SPXn of the display device 10 may be a 3T1C structure in which the pixel driving circuit includes three transistors and one capacitor. The 3T1C structure is used as an example to illustrate the pixel driving circuit below, but it is not limited to this, and other various deformation structures such as 2T1C structure, 7T1C structure, 6T1C structure, etc. may also be applied.

[0070] Figure 3 is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0071] Reference Figure 3 According to an embodiment, each sub-pixel SPXn of the display device 10 includes three transistors T1, T2, and T3 and a storage capacitor Cst in addition to the light emitting diode EL.

[0072] The light emitting diode EL emits light according to the current supplied by the first transistor T1. The light emitting diode EL may include a first electrode, a second electrode, and at least one light emitting element arranged therebetween. The light emitting element may emit light of a specific wavelength band by means of an electrical signal transmitted from the first electrode and the second electrode.

[0073] One end of the light emitting diode EL can be connected to the source electrode of the first transistor T1, and the other end can be connected to the second voltage wiring VL2 that supplies a low potential voltage (hereinafter referred to as the second power supply voltage) lower than the high potential voltage (hereinafter referred to as the first power supply voltage) of the first voltage wiring VL1.

[0074] The first transistor T1 adjusts the current flowing from the first voltage wiring VL1 supplying the first power supply voltage to the light emitting diode EL according to the voltage difference between the gate electrode and the source electrode. As an example, the first transistor T1 may be a driving transistor for driving the light emitting diode EL. The gate electrode of the first transistor T1 may be connected to the source electrode of the second transistor T2, the source electrode may be connected to the first electrode of the light emitting diode EL, and the drain electrode may be connected to the first voltage wiring VL1 to which the first power supply voltage is applied.

[0075] The second transistor T2 is turned on by the scan signal of the first scan line SL1 to connect the data line DTL to the gate electrode of the first transistor T1. The gate electrode of the second transistor T2 may be connected to the first scan line SL1, the source electrode may be connected to the gate electrode of the first transistor T1, and the drain electrode may be connected to the data line DTL.

[0076] The third transistor T3 is turned on by the scan signal of the second scan line SL2 and connects the initialization voltage wiring VIL to one end of the light emitting diode EL. The gate electrode of the third transistor T3 may be connected to the second scan line SL2, the drain electrode may be connected to the initialization voltage wiring VIL, and the source electrode may be connected to one end of the light emitting diode EL or the source electrode of the first transistor T1.

[0077] In one embodiment, the source electrode and the drain electrode of each transistor T1, T2, and T3 are not limited to the above-mentioned ones, but may be the opposite. Moreover, each of the transistors T1, T2, and T3 may be formed by a thin film transistor. Figure 3In the description, the case where each transistor T1, T2, and T3 is formed using an N-type metal oxide semiconductor field effect transistor (MOSFET) is mainly described, but the present invention is not limited to this. That is, each transistor T1, T2, and T3 can be formed using a P-type MOSFET, or a part of the transistor T1, T2, and T3 can be formed using an N-type MOSFET and the other part of the transistor T1, T2, and T3 can be formed using a P-type MOSFET.

[0078] The storage capacitor Cst is formed between the gate electrode and the source electrode of the first transistor T1. The storage capacitor Cst stores a voltage difference between the gate voltage and the source voltage of the first transistor T1.

[0079] Hereinafter, the structure of a pixel PX of the display device 10 according to an embodiment will be described in detail with reference to other drawings.

[0080] Figure 4 is a plan view showing one pixel of a display device according to an embodiment. Figure 4 The planar arrangement of electrodes RME ( RME1 , RME2 ), bank patterns BP1 , BP2 and a bank layer BNL, a plurality of light emitting elements ED, and connection electrodes CNE ( CNE1 , CNE2 ) arranged in one pixel PX of the display device 10 is shown.

[0081] Reference Figure 4 , each of the pixels PX of the display device 10 may include a plurality of sub-pixels SPXn. For example, one pixel PX may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 may emit light of a first color, the second sub-pixel SPX2 may emit light of a second color, and the third sub-pixel SPX3 may emit light of a third color. As an example, the first color may be blue, the second color may be green, and the third color may be red. However, this is not limited to this, and each sub-pixel SPXn may also emit light of the same color. In one embodiment, each sub-pixel SPXn may emit blue light. The accompanying drawings show a situation in which one pixel PX includes three sub-pixels SPXn, but this is not limited to this, and the pixel PX may include a greater number of sub-pixels SPXn.

[0082] Each sub-pixel SPXn of the display device 10 may include a light-emitting area EMA and a non-light-emitting area. The light-emitting area EMA may be an area where a light-emitting element ED is arranged and emits light of a specific wavelength band. The non-light-emitting area may be an area where no light-emitting element ED is arranged and where light emitted from the light-emitting element ED does not reach and does not emit light.

[0083] The light emitting area EMA may include an area where the light emitting element ED is arranged and an area where the light emitted from the light emitting element ED is emitted as an area adjacent to the light emitting element ED. For example, the light emitting area EMA may also include an area where the light emitted from the light emitting element ED is reflected or refracted by another component and emitted. A plurality of light emitting elements ED may be arranged in each sub-pixel SPXn, and the light emitting area EMA may be formed by including the area where they are arranged and the area adjacent to them.

[0084] The drawings show that the light emitting areas EMA of the respective sub-pixels SPXn have the same area, but the present invention is not limited thereto. In some embodiments, the light emitting areas EMA of the respective sub-pixels SPXn may also have different areas according to the color or wavelength band of the light emitted from the light emitting element ED arranged in the corresponding sub-pixel.

[0085] Each sub-pixel SPXn may further include a sub-region SA arranged in a non-luminous region. The sub-region SA of the corresponding sub-pixel SPXn may be arranged on the lower side of the luminous region EMA which is the other side of the first direction DR1. The luminous region EMA and the sub-region SA may be alternately arranged along the first direction DR1, and the sub-region SA may be arranged between the luminous regions EMA of different sub-pixels SPXn spaced apart from each other along the first direction DR1. For example, the luminous region EMA and the sub-region SA may be alternately arranged with each other in the first direction DR1, and each of the luminous region EMA and the sub-region SA may be repeatedly arranged in the second direction DR2. However, this is not limited to this, and in a plurality of pixels PX, the luminous region EMA and the sub-region SA may also have the same Figure 4 Different arrangements.

[0086] The subregion SA does not have a light emitting element ED disposed therein so that no light is emitted, but may have a portion of the electrode RME disposed therein. The electrodes RME disposed in different subpixels SPXn may be disposed to be separated from each other at the separation portion ROP of the subregion SA.

[0087] The wiring and circuit elements of the circuit layer arranged in each pixel PX and connected to the light emitting element ED may be connected to the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, respectively. However, the wiring and circuit elements may not be arranged corresponding to the areas occupied by the sub-pixels SPXn or the light emitting areas EMA, but may be arranged in one pixel PX regardless of the position of the light emitting area EMA.

[0088] The bank layer BNL may be arranged to surround a plurality of sub-pixels SPXn and the emission area EMA and the sub-region SA. The bank layer BNL may be arranged at the boundary of the sub-pixels SPXn adjacent to each other in the first direction DR1 and the second direction DR2, and may also be arranged at the boundary of the emission area EMA and the sub-region SA. The sub-pixels SPXn, the emission area EMA, and the sub-region SA of the display device 10 may be regions divided by the arrangement of the bank layer BNL. The intervals between the plurality of sub-pixels SPXn and the emission area EMA and the sub-region SA may be different according to the width of the bank layer BNL.

[0089] The bank layer BNL may include a portion extending in the first direction DR1 and the second direction DR2 on a plane, so as to be arranged in a lattice pattern on the entire surface of the display area DPA. The bank layer BNL may be arranged across the boundaries of each sub-pixel SPXn, so as to divide adjacent sub-pixels SPXn. Furthermore, the bank layer BNL may be arranged to surround the emission area EMA and the sub-area SA arranged in each sub-pixel SPXn, so as to divide them.

[0090] Figure 5 is along Figure 4 Cross-sectional view taken along line E1-E1'. Figure 6 is along Figure 4 Cross-sectional view taken along line E2-E2'. Figure 7 Is magnification Figure 5 Figure 1 shows the A region of the graph. Figure 8 It is shown Figure 5 Floor plan of area A. Fig. 9 is a cross-sectional view showing a first insulating layer of a display device according to an embodiment.

[0091] Figure 5 The cross section of both ends of the light emitting element ED arranged in the first sub-pixel SPX1 and across the electrode contact holes CTD and CTS is shown. Figure 6 The cross section across both ends of the light emitting element ED arranged in the first sub-pixel SPX1 and the contact portions CT1 and CT2 is shown. Figure 7 The via layer VIA, the electrodes RME1 , RME2 , the first insulating layer PAS1 , the light emitting element ED, and the connecting electrodes CNE1 , CNE2 are shown. Figure 8 The electrodes RME1, RME2, the trench portion TRP and the light emitting element ED are shown. Fig. 9 A trench portion TRP of the first insulating layer PAS1 is shown.

[0092] Combination Figure 4 And refer to Figures 5 to 9The display device 10 may include a first substrate SUB, a semiconductor layer disposed on the first substrate SUB, a plurality of conductive layers, and a plurality of insulating layers. Furthermore, the display device 10 may include a plurality of electrodes RME (RME1, RME2), a light emitting element ED, and a connecting electrode CNE (CNE1, CNE2) disposed on the first substrate SUB. The semiconductor layer, the conductive layer, and the insulating layer may respectively constitute a circuit layer of the display device 10.

[0093] The first substrate SUB may be an insulating substrate. The first substrate SUB may be formed of an insulating material such as glass, quartz or polymer resin. Furthermore, the first substrate SUB may be a rigid substrate, but may also be a flexible substrate capable of bending, folding, rolling, etc. The first substrate SUB may include a display area DPA and a non-display area NDA surrounding the display area DPA, and the display area DPA may include a light-emitting area EMA and a sub-area SA as a part of the non-light-emitting area.

[0094] The first conductive layer may be disposed on the first substrate SUB. The first conductive layer includes a lower metal layer BML, and the lower metal layer BML is disposed to overlap with the first active layer ACT1 of the first transistor T1. The lower metal layer BML may prevent light from being incident on the first active layer ACT1 of the first transistor T1, or may be electrically connected to the first active layer ACT1 to perform a function of stabilizing the electrical characteristics of the first transistor T1. However, the lower metal layer BML may be omitted.

[0095] The buffer layer BL may be disposed on the lower metal layer BML and the first substrate SUB. The buffer layer BL is formed on the first substrate SUB to protect the transistors of the pixels PX from moisture penetrating through the moisture-permeable first substrate SUB and may perform a surface planarization function.

[0096] The semiconductor layer is disposed on the buffer layer BL. The semiconductor layer may include a first active layer ACT1 of the first transistor T1 and a second active layer ACT2 of the second transistor T2. The first active layer ACT1 and the second active layer ACT2 may be disposed to partially overlap first and second gate electrodes G1 and G2 of a second conductive layer described later, respectively.

[0097] The semiconductor layer may include polycrystalline silicon, single crystal silicon, oxide semiconductor, etc. In another embodiment, the semiconductor layer may also include polycrystalline silicon. The oxide semiconductor may be an oxide semiconductor containing indium (In). For example, the oxide semiconductor may be at least one of indium tin oxide (ITO: Indium Tin Oxide), indium zinc oxide (IZO: Indium Zinc Oxide), indium gallium oxide (IGO: Indium Gallium Oxide), indium zinc tin oxide (IZTO: Indium Zinc Tin Oxide), indium gallium tin oxide (IGTO: Indium Gallium Tin Oxide), indium gallium zinc oxide (IGZO: IndiumGallium Zinc Oxide), and indium gallium zinc tin oxide (IGZTO: Indium Gallium Zinc Tin Oxide).

[0098] In the drawings, a case where one first transistor T1 is disposed in the sub-pixel SPXn of the display device 10 is illustrated, but the present invention is not limited thereto, and the display device 10 may include a greater number of transistors.

[0099] The first gate insulating layer GI is arranged on the semiconductor layer and the buffer layer BL in the display area DPA. The first gate insulating layer GI is not arranged in the pad area PDA, and can play the role of a gate insulating film of each transistor T1, T2. In the accompanying drawings, the case where the first gate insulating layer GI is arranged on the entire surface of the buffer layer BL is illustrated, but it is not limited to this. In some embodiments, the first gate insulating layer GI can also be patterned together with the gate electrodes G1, G2 of the second conductive layer described later, so as to be locally arranged between the second conductive layer and the active layers ACT1, ACT2 of the semiconductor layer.

[0100] The second conductive layer is arranged on the first gate insulating layer GI. The second conductive layer may include a first gate electrode G1 of the first transistor T1 and a second gate electrode G2 of the second transistor T2. The first gate electrode G1 may be arranged to overlap with the channel region of the first active layer ACT1 in the third direction DR3 as the thickness direction, and the second gate electrode G2 may be arranged to overlap with the channel region of the second active layer ACT2 in the third direction DR3 as the thickness direction. Although not shown in the drawings, the second conductive layer may further include an electrode of a storage capacitor.

[0101] The first interlayer insulating layer IL1 is disposed on the second conductive layer. The first interlayer insulating layer IL1 may function as an insulating film between the second conductive layer and other layers disposed on the second conductive layer, and protect the second conductive layer.

[0102] The third conductive layer may be disposed on the first interlayer insulating layer IL1. The third conductive layer may include first and second voltage wirings VL1 and VL2 disposed in the display area DPA, a first conductive pattern CDP1, source electrodes S1, S2, and drain electrodes D1, D2 of the respective transistors T1, T2. Although not shown in the drawings, the third conductive layer may further include another electrode of the storage capacitor.

[0103] The first voltage wiring VL1 may be applied with a high potential voltage (or a first power supply voltage) transmitted to the first electrode RME1, and the second voltage wiring VL2 may be applied with a low potential voltage (or a second power supply voltage) transmitted to the second electrode RME2. A portion of the first voltage wiring VL1 may contact the first active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. The first voltage wiring VL1 may function as a first drain electrode D1 of the first transistor T1. The second voltage wiring VL2 may be directly connected to the second electrode RME2 described later.

[0104] The first conductive pattern CDP1 may contact the first active layer ACT1 of the first transistor T1 through a contact hole penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. The first conductive pattern CDP1 may contact the lower metal layer BML through another contact hole. The first conductive pattern CDP1 may function as a first source electrode S1 of the first transistor T1. Furthermore, the first conductive pattern CDP1 may be electrically connected to a first electrode RME1 or a first connection electrode CNE1 described later. The first transistor T1 may transmit a first power supply voltage applied from a first voltage wiring VL1 to the first electrode RME1 or the first connection electrode CNE1.

[0105] The second source electrode S2 and the second drain electrode D2 may respectively contact the second active layer ACT2 of the second transistor T2 through the contact holes penetrating the first interlayer insulating layer IL1 and the first gate insulating layer GI. Figure 3 Any of the switch transistors described above. The second transistor T2 can Figure 3 The signal applied by the data line DTL is transmitted to the first transistor T1, or from Figure 3 A signal applied by the initialization voltage wiring VIL is transmitted to the other electrode of the storage capacitor.

[0106] The first protective layer PV1 is disposed on the third conductive layer. The first protective layer PV1 may perform a function of an insulating film between the third conductive layer and other layers, and may protect the third conductive layer.

[0107] The buffer layer BL, the first gate insulating layer GI, the first interlayer insulating layer IL1, and the first protective layer PV1 may be formed by alternately stacking a plurality of inorganic layers. For example, the buffer layer BL, the first gate insulating layer GI, the first interlayer insulating layer IL1, and the first protective layer PV1 may be formed to include silicon oxide (SiO x :Silicon Oxide)、Silicon Nitride(SiN x :Silicon Nitride)、Silicon Nitride Oxygen(SiO x N y : Silicon Oxynitride) or a plurality of layers alternately stacked therefrom. However, it is not limited thereto, and the buffer layer BL, the first gate insulating layer GI, the first interlayer insulating layer IL1, and the first protective layer PV1 may also be formed using an inorganic layer including the above-mentioned insulating material. Moreover, in some embodiments, the first interlayer insulating layer IL1 may also be formed using an organic insulating material such as polyimide (PI:Polyimide).

[0108] The via layer VIA is arranged on the third conductive layer in the display area DPA. The via layer VIA includes an organic insulating material (e.g., an organic insulating material such as polyimide (PI)) to compensate for the step difference formed by the lower conductive layer and to form the upper surface flat. However, in some embodiments, the via layer VIA may be omitted.

[0109] The display device 10 may include bank patterns BP1, BP2, a plurality of electrodes RME (RME1, RME2), a bank layer BNL, a plurality of light emitting elements ED, and a plurality of connection electrodes CNE (CNE1, CNE2) as display element layers disposed on the via layer VIA. Also, the display device 10 may include a plurality of insulating layers PAS1, PAS2 disposed on the via layer VIA.

[0110] A plurality of bank patterns BP1 and BP2 may be arranged at the emission area EMA of each sub-pixel SPXn. The bank patterns BP1 and BP2 may have a predetermined width in the second direction DR2 and may have a shape extending in the first direction DR1.

[0111] For example, the bank patterns BP1 and BP2 may include a first bank pattern BP1 and a second bank pattern BP2 spaced apart from each other along the second direction DR2 in the light emitting area EMA of each sub-pixel SPXn. The first bank pattern BP1 may be arranged on the left side of the center of the light emitting area EMA as one side in the second direction DR2, and the second bank pattern BP2 may be spaced apart from the first bank pattern BP1 and arranged on the right side of the center of the light emitting area EMA as the other side in the second direction DR2. The first bank pattern BP1 and the second bank pattern BP2 may be alternately arranged with each other along the second direction DR2, and may be arranged in an island-type pattern in the display area DPA. A plurality of light emitting elements ED may be arranged between the first bank pattern BP1 and the second bank pattern BP2.

[0112] The lengths of the first embankment pattern BP1 and the second embankment pattern BP2 in the first direction DR1 may be the same as each other, and may be smaller than the length of the light emitting area EMA surrounded by the embankment layer BNL in the first direction DR1. The first embankment pattern BP1 and the second embankment pattern BP2 may be separated from the portion of the embankment layer BNL extending in the second direction DR2. However, this is not limited to the above, and the embankment patterns BP1 and BP2 may be integrated with the embankment layer BNL, or partially overlap with the portion of the embankment layer BNL extending in the second direction DR2. In this case, the lengths of the embankment patterns BP1 and BP2 in the first direction DR1 may be the same as or greater than the length of the light emitting area EMA surrounded by the embankment layer BNL in the first direction DR1.

[0113] The widths of the first embankment pattern BP1 and the second embankment pattern BP2 in the second direction DR2 may be the same as each other. However, this is not limited to the above, and they may also have different widths from each other. For example, one embankment pattern may have a larger width than another embankment pattern, and the embankment pattern with a larger width may be arranged across the light emitting area EMA of another sub-pixel SPXn adjacent to each other in the second direction DR2. In this case, in the embankment pattern arranged across a plurality of light emitting areas EMA, the portion of the embankment layer BNL extending along the first direction DR1 may overlap with the second embankment pattern BP2 in the thickness direction. In the accompanying drawings, the case where two embankment patterns BP1 and BP2 are arranged with the same width in each sub-pixel SPXn is illustrated, but this is not limited to the above. The number and shape of the embankment patterns BP1 and BP2 may be different depending on the number or arrangement structure of the electrodes RME.

[0114] A plurality of dam patterns BP1 and BP2 may be arranged on the via layer VIA. For example, the dam patterns BP1 and BP2 may be arranged directly on the via layer VIA, and may have a structure in which at least a portion protrudes with respect to the upper surface of the via layer VIA. The protruding portion of the dam patterns BP1 and BP2 may have an inclined or curvatured side surface, and the light emitted from the light-emitting element ED may be reflected by the electrode RME arranged on the dam patterns BP1 and BP2 and emitted toward the upper direction of the via layer VIA. Different from the case illustrated in the accompanying drawings, the dam patterns BP1 and BP2 may also have a semicircular or semi-elliptical shape with a curvature on the outer surface in the cross-sectional view. The dam patterns BP1 and BP2 may include organic insulating materials such as polyimide (PI), but are not limited thereto.

[0115] A plurality of electrodes RME (RME1, RME2) are arranged in each sub-pixel SPXn in a shape extending in one direction. The plurality of electrodes RME1, RME2 may extend in the first direction DR1 and be arranged in the light emitting area EMA and the sub-area SA of the sub-pixel SPXn, and they may be arranged spaced apart from each other in the second direction DR2. The plurality of electrodes RME may be electrically connected to the light emitting element ED described later, but are not limited thereto and may not be electrically connected to the light emitting element ED.

[0116] The display device 10 may include a first electrode RME1 and a second electrode RME2 arranged in each sub-pixel SPXn. The first electrode RME1 is arranged on the left side of the center of the light emitting area EMA, and the second electrode RME2 is spaced apart from the first electrode RME1 in the second direction DR2 and is arranged on the right side of the center of the light emitting area EMA. The first electrode RME1 may be arranged on the first bank pattern BP1, and the second electrode RME2 may be arranged on the second bank pattern BP2. The first electrode RME1 and the second electrode RME2 may be locally arranged in the sub-region SA of the corresponding sub-pixel SPXn across the bank layer BNL. The first electrode RME1 and the second electrode RME2 of the sub-pixels SPXn different from each other may be spaced apart from each other based on the separation portion ROP located in the sub-region SA of one sub-pixel SPXn.

[0117] In the drawings, the two electrodes RME in each subpixel SPXn have a shape extending in the first direction DR1, but are not limited thereto. The electrodes RME may be arranged obliquely to each other, or the electrodes RME may be partially bent and have a shape having different widths depending on positions.

[0118] The first electrode RME1 and the second electrode RME2 may be arranged at least on the inclined side surfaces of the bank patterns BP1 and BP2. In one embodiment, the width of the plurality of electrodes RME measured in the second direction DR2 may be smaller than the width of the bank patterns BP1 and BP2 measured in the second direction DR2, and the interval between the first electrode RME1 and the second electrode RME2 in the second direction DR2 may be smaller than the interval between the bank patterns BP1 and BP2. At least a portion of the first electrode RME1 and the second electrode RME2 may be directly arranged on the via layer VIA so that they may be arranged on the same plane.

[0119] The light emitting element ED disposed between the bank patterns BP1 and BP2 emits light toward both ends, and the emitted light may be toward the electrode RME disposed on the bank patterns BP1 and BP2. Each electrode RME may have a structure in which a portion disposed on the bank patterns BP1 and BP2 can reflect light emitted from the light emitting element ED. The first electrode RME1 and the second electrode RME2 may be disposed to cover at least one side surface of the bank patterns BP1 and BP2, thereby reflecting light emitted from the light emitting element ED.

[0120] Between the light emitting area EMA and the sub-area SA, each electrode RME may be in direct contact with the third conductive layer through the electrode contact holes CTD and CTS in the portion overlapping the bank layer BNL. The first electrode contact hole CTD may be formed in the region where the bank layer BNL overlaps the first electrode RME1, and the second electrode contact hole CTS may be formed in the region where the bank layer BNL overlaps the second electrode RME2. The first electrode RME1 may be in contact with the first conductive pattern CDP1 through the first electrode contact hole CTD that passes through the via layer VIA and the first protective layer PV1. The second electrode RME2 may be in contact with the second voltage wiring VL2 through the second electrode contact hole CTS that passes through the via layer VIA and the first protective layer PV1. The first electrode RME1 may be electrically connected to the first transistor T1 through the first conductive pattern CDP1 and a first power supply voltage may be applied thereto, and the second electrode RME2 may be electrically connected to the second voltage wiring VL2 and a second power supply voltage may be applied thereto. However, this is not limited thereto. In another embodiment, the electrodes RME1 and RME2 may not be electrically connected to the voltage wirings VL1 and VL2 of the third conductive layer, and the connection electrode CNE described later may be directly connected to the third conductive layer.

[0121] The plurality of electrodes RME may include a conductive material with high reflectivity. For example, the electrode RME may include a metal such as silver (Ag), copper (Cu), aluminum (Al), etc., or may be formed as an alloy including aluminum (Al), nickel (Ni), lanthanum (La), etc., or may have a structure in which a metal layer including titanium (Ti), molybdenum (Mo), and niobium (Nb) and the alloy are stacked. In some embodiments, the electrode RME may be formed as a double layer or a multilayer, wherein the double layer or the multilayer is formed by stacking one or more metal layers including an alloy including aluminum (Al) and titanium (Ti), molybdenum (Mo), and / or niobium (Nb).

[0122] Without being limited thereto, each electrode RME may further include a transparent conductive material. For example, each electrode RME may include materials such as ITO, IZO, ITZO, and the like. In some embodiments, each electrode RME may form a structure in which more than one layer of a transparent conductive material and a metal layer with high reflectivity are stacked, or may include them and form one layer. For example, each electrode RME may have a stacking structure of ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO, and the like. The electrode RME may be electrically connected to the light emitting element ED, and reflect a portion of the light emitted from the light emitting element ED toward the upper direction of the first substrate SUB.

[0123] The first insulating layer PAS1 may be arranged on the entire surface of the display area DPA, and may be arranged on the via layer VIA and the plurality of electrodes RME. The first insulating layer PAS1 may insulate different electrodes RME from each other while protecting the plurality of electrodes RME. In particular, the first insulating layer PAS1 is arranged to cover the electrodes RME before forming the bank layer BNL, thereby preventing the electrodes RME from being damaged in the process of forming the bank layer BNL. Furthermore, the first insulating layer PAS1 may also prevent the light emitting element ED arranged on the upper portion thereof from being damaged by direct contact with other components.

[0124] In an exemplary embodiment, the first insulating layer PAS1 may form a step difference between the electrodes RME spaced apart along the second direction DR2 in a manner in which a portion of the upper surface is recessed. A light emitting element ED is arranged on the upper surface of the first insulating layer PAS1 where the step difference is formed, and a space may be formed between the light emitting element ED and the first insulating layer PAS1.

[0125] As described above, the first insulating layer PAS1 can cover the electrode RME to insulate and protect the electrode RME. The first insulating layer PAS1 can generate a seam on the side surface of the lower electrode RME through the taper angle, double taper, or inverted taper of the side surface of the lower electrode RME. Here, the seam can refer to a crack in the first insulating layer PAS1. If a seam is generated in the first insulating layer PAS1, the etching solution or moisture in the subsequent process will penetrate through the seam, thereby damaging the electrode RME.

[0126] According to an embodiment, the first insulating layer PAS1 includes silicon oxynitride (SiON), so that seams can be prevented from being generated and the electrode RME can be prevented from being damaged.

[0127] The material of the first insulating layer PAS1 should meet various conditions. The conditions are as follows: First, it should be a material that can be formed into a film at a temperature below 200°C; second, it should have excellent step coverage to prevent seams from being generated; third, it should be easy to etch with the second insulating layer PAS2; fourth, it should have a thickness of 3000 or less to easily form an electric field during the alignment process of the light-emitting elements ED.

[0128] In one embodiment, the first insulating layer PAS1 can include silicon oxynitride (SiON) that meets the above conditions. Silicon oxynitride can be formed into a film at a low temperature below 200°C.

[0129] The silicon oxynitride included in the above-mentioned first insulating layer PAS1 can be represented by the following Chemical Formula 1.

[0130] [Chemical Formula 1] Si x O y N z Wherein, x, y, and z respectively satisfy 34.6 < x < 42.9, 24.2 < y < 63.8, 1.5 < z < 32.9, and x, y, and z are atomic ratios.

[0131] The silicon oxynitride can be configured to have a composition ratio in which Si, O, and N have atomic ratios within the above ranges. That is, it can include Si in the range greater than 4.6 at% and less than 42.9 at%, O in the range greater than 24.2 at% and less than 63.8 at%, and N in the range greater than 1.5 at% and less than 32.9 at%.

[0132] In order to have excellent step coverage, the lower the sticking coefficient of the first insulating layer PAS1, the more advantageous it is. In one embodiment, the first insulating layer PAS1 may include N greater than 1.5 at % to reduce the sticking coefficient, and may include N less than 32.9 at % to prevent the dielectric constant from increasing. The first insulating layer PAS1 forms step coverage by including N, thereby improving the phenomenon of the non-filmed portion or seam generated on the side surface of the electrode RME.

[0133] Furthermore, the etching selectivity ratio of the first insulating layer PAS1 to the second insulating layer PAS2 may be greater than 4.1. x ) may have an etching selectivity of 4.1 or more. The connection electrode CNE may be connected to the electrodes RME1 and RME2 through the contact portions CT1 and CT2 penetrating the first insulating layer PAS1 and the second insulating layer PAS2. In this case, the contact portions CT1 and CT2 may be formed by simultaneously dry-etching the first insulating layer PAS1 and the second insulating layer PAS2. In this embodiment, since the etching selectivity of the first insulating layer PAS1 including silicon oxynitride and the second insulating layer PAS2 including silicon nitride is 4.1 or more, the contact portions CT1 and CT2 may be easily formed.

[0134] Furthermore, the first insulating layer PAS1 may be 2000 Up to 3000 The light emitting elements ED can be aligned by an electric field formed on the first insulating layer PAS1 through the electrode RME. In this embodiment, the first insulating layer PAS1 including silicon nitride is formed to have a thickness of 2000. The above configuration can prevent the generation of seams on the side surfaces of the electrode RME. Hereinafter, the dielectric constant of the first insulating layer PAS1 can be prevented from increasing, and an electric field that can easily align the light emitting elements ED can be formed.

[0135] Furthermore, the first insulating layer PAS1 may have a predetermined refractive index so that light emitted from the light emitting element ED is reflected by the electrode RME and emits light. For example, the first insulating layer PAS1 may have a refractive index greater than 1.4 and less than 1.63. In this case, the wavelength of the light may be 633 nm. As described above, the first insulating layer PAS1 includes O and N, but if the atomic ratio of N is increased, the refractive index may increase, and if the atomic ratio of O is increased, the refractive index may decrease. Since the first insulating layer PAS1 is formed in the above-mentioned range of the atomic ratio of O and N, it may have a refractive index greater than 1.4 and less than 1.63, thereby improving the light extraction efficiency of the light of the light emitting element ED.

[0136] As described above, the first insulating layer PAS1 according to an embodiment includes silicon oxynitride having the composition ratio of Chemical Formula 1, thereby preventing seams from being generated on the side surfaces of the electrode RME, facilitating the orderly arrangement of the light emitting elements ED, and improving light extraction efficiency.

[0137] In addition, in order to improve the regular arrangement of the light emitting elements ED, the first insulating layer PAS1 may include a plurality of trench portions TRP.

[0138] Reference Figures 7 to 9 , the first insulating layer PAS1 may include a groove portion TRP. The groove portion TRP may be a groove recessed from the surface of the first insulating layer PAS1 toward the via layer VIA. The groove portion TRP may be formed as one body with the first insulating layer PAS1 and may be a part of the first insulating layer PAS1. The groove portion TRP may overlap with the light emitting element ED on a plane to induce physical surface friction with the light emitting element ED, thereby playing a role in improving the adhesion of the light emitting element ED.

[0139] The groove portion TRP may include a first groove portion TRP1 and a second groove portion TRP2. The first groove portion TRP1 may overlap and extend side by side with the first electrode RME1, and may overlap with one end portion of the light emitting element ED. The second groove portion TRP2 may overlap and extend side by side with the second electrode RME2, and may overlap with the other end portion of the light emitting element ED. The first groove portion TRP1 and the second groove portion TRP2 may extend along the first direction DR1, and may be arranged spaced apart from each other in the second direction DR2. The first groove portion TRP1 and the second groove portion TRP2 may be arranged side by side with each other.

[0140] The first groove portion TRP1 and the second groove portion TRP2 may be in contact with the light emitting element ED, respectively. For example, the first groove portion TRP1 may be in contact with the lower surface of one end of the light emitting element ED, and the second groove portion TRP2 may be in contact with the lower surface of the other end of the light emitting element ED. The first groove portion TRP1 and the second groove portion TRP2 may be arranged along the length direction of the light emitting element ED in the area overlapping with the light emitting element ED. For example, the width of the first groove portion TRP1 in the second direction DR2 may be smaller than the length of the light emitting element ED. Similarly, the width of the second groove portion TRP2 in the second direction DR2 may also be smaller than the length of the light emitting element ED. The sum of the widths of each of the first groove portion TRP1 and the second groove portion TRP2 may be smaller than the length of the light emitting element ED.

[0141] Furthermore, the side of the first groove portion TRP1 and the side of one end of the light emitting element ED can be arranged and aligned with each other. If the first groove portion TRP1 is arranged outside the side of one end of the light emitting element ED, the light reflected by the electrode RME may be reflected and diffused in the groove TP of the first groove portion TRP1, thereby reducing the light extraction efficiency.

[0142] The first trench portion TRP1 and the second trench portion TRP2 may include a plurality of trenches TP, respectively. The plurality of trenches TP may extend along the first direction DR1 and be arranged spaced apart from each other in the second direction DR2. The trench TP may be formed with a depth DH of 1% to 30% of the thickness of the first insulating layer PAS1. The trench TP may have a predetermined width W1, and the width W1 is not particularly limited as long as a plurality of trenches TP may be arranged in an area in contact with the lower surface of the light emitting element ED. Furthermore, a predetermined spacing interval SD1 may be provided between the trench TP and adjacent trenches TP. The spacing interval SD1 of the trench TP may be greater than or equal to the width W1 of the trench TP. However, it is not limited thereto, and the spacing interval SD1 of the trench TP may also be less than the width W1 of the trench TP.

[0143] After the light emitting element ED is coated on the first insulating layer PAS1 together with the solvent, the light emitting element ED can be moved by the electric field formed on the first insulating layer PAS1, so that it can be placed and neatly arranged on the electrode RME. In one embodiment, since a groove portion TRP is formed on the first insulating layer PAS1, after the light emitting element ED is placed on the electrode RME, it will not move to other places due to friction with the groove portion TRP, but will be fixed. That is, by forming the groove portion TRP on the first insulating layer PAS1, the light emitting element ED can be well and neatly arranged on the electrode RME.

[0144] In addition, the bank layer BNL may be arranged on the first insulating layer PAS1. The bank layer BNL may include portions extending in the first direction DR1 and the second direction DR2, and may surround each sub-pixel SPXn. The bank layer BNL may surround the light emitting area EMA and the sub-area SA of each sub-pixel SPXn to divide them, and may surround the outermost contour of the display area DPA to divide the display area DPA and the non-display area NDA. The bank layer BNL is fully arranged in the display area DPA to form a lattice pattern, and the area opened by the bank layer BNL in the display area DPA may be the light emitting area EMA and the sub-area SA.

[0145] The bank layer BNL may have a predetermined height similar to the bank patterns BP1 and BP2. In some embodiments, the height of the upper surface of the bank layer BNL may be higher than the bank patterns BP1 and BP2, and its thickness may be equal to or greater than the bank patterns BP1 and BP2. The bank layer BNL may prevent ink from overflowing to adjacent sub-pixels SPXn during the inkjet printing process in the manufacturing process of the display device 10. Similar to the bank patterns BP1 and BP2, the bank layer BNL may include an organic insulating material such as polyimide.

[0146] A plurality of light emitting elements ED may be arranged in the light emitting area EMA. The light emitting elements ED are arranged between the embankment patterns BP1 and BP2, and may be arranged spaced apart from each other in the first direction DR1. In one embodiment, the plurality of light emitting elements ED may have a shape extending in one direction, and both ends may be arranged on electrodes RME different from each other, respectively. The length of the light emitting element ED may be longer than the interval between the electrodes RME spaced apart in the second direction DR2. The light emitting elements ED may be arranged roughly so that the direction in which they extend is perpendicular to the first direction DR1 in which the electrodes RME extend. However, this is not limited thereto, and the extending direction of the light emitting elements ED may be arranged toward the second direction DR2 or in a direction inclined thereto.

[0147] A plurality of light emitting elements ED may be arranged on the first insulating layer PAS1. The light emitting elements ED may be arranged in contact with the groove portion TRP formed on the first insulating layer PAS1. The light emitting element ED may have a shape extending in one direction, and may be arranged so that the one direction of extension is parallel to the upper surface of the first substrate SUB. As described below, the light emitting element ED may include a plurality of semiconductor layers arranged along the one direction of extension, and the plurality of semiconductor layers may be arranged in sequence along a direction parallel to the upper surface of the first substrate SUB. However, this is not limited to this, and in the case where the light emitting element ED has other structures, the plurality of semiconductor layers may also be arranged in a direction perpendicular to the first substrate SUB.

[0148] The light emitting elements ED arranged in each sub-pixel SPXn may emit light of different wavelength bands according to the materials of the semiconductor layers. However, the light emitting elements ED arranged in each sub-pixel SPXn may include semiconductor layers of the same material and emit light of the same color.

[0149] The light emitting element ED may be in contact with the connection electrode CNE ( CNE1 , CNE2 ) to be electrically connected to the electrode RME and the conductive layer below the via layer VIA, and may emit light of a specific wavelength band when an electrical signal is applied thereto.

[0150] The second insulating layer PAS2 may be arranged on the plurality of light emitting elements ED and the first insulating layer PAS1. The second insulating layer PAS2 includes a pattern portion extending along the first direction DR1 between the embankment patterns BP1 and BP2 and arranged on the plurality of light emitting elements ED. The pattern portion may be arranged to partially surround the outer surface of the light emitting element ED and may not cover both sides or both ends of the light emitting element ED. In a plan view, the pattern portion may form a linear or island pattern within each sub-pixel SPXn. The pattern portion of the second insulating layer PAS2 may fix the light emitting element ED in the manufacturing process of the display device 10 while protecting the light emitting element ED.

[0151] A plurality of connection electrodes CNE (CNE1, CNE2) may be disposed on the plurality of electrodes RME and the bank patterns BP1, BP2. The plurality of connection electrodes CNE may each have a shape extending in one direction and may be disposed spaced apart from each other. Each connection electrode CNE may contact the light emitting element ED and may be electrically connected to the third conductive layer.

[0152] The plurality of connection electrodes CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 arranged in each sub-pixel SPXn. The first connection electrode CNE1 may have a shape extending in the first direction DR1, and may be arranged on the first electrode RME1 or the first embankment pattern BP1. The first connection electrode CNE1 may partially overlap with the first electrode RME1, and may be arranged from the light emitting area EMA to the sub-area SA across the embankment layer BNL. The second connection electrode CNE2 may have a shape extending in the first direction DR1, and may be arranged on the second electrode RME2 or the second embankment pattern BP2. The second connection electrode CNE2 may partially overlap with the second electrode RME2, and may be arranged from the light emitting area EMA to the sub-area SA across the embankment layer BNL. The first connection electrode CNE1 and the second connection electrode CNE2 may be in contact with the light emitting element ED, respectively, and electrically connected to the electrode RME or a conductive layer thereunder.

[0153] For example, the first connection electrode CNE1 and the second connection electrode CNE2 may be respectively arranged on the side surface of the second insulating layer PAS2 and may contact the light emitting element ED. The first connection electrode CNE1 may partially overlap with the first electrode RME1 and may contact one end of the light emitting element ED. The second connection electrode CNE2 may partially overlap with the second electrode RME2 to contact the other end of the light emitting element ED. The plurality of connection electrodes CNE are arranged across the light emitting area EMA and the sub-area SA. The connection electrode CNE may contact the light emitting element ED in a portion arranged in the light emitting area EMA and be electrically connected to the third conductive layer in a portion arranged in the sub-area SA.

[0154] According to an embodiment, in the display device 10, each connection electrode CNE may contact the electrode RME through the contact portions CT1 and CT2 arranged in the sub-region SA. The first connection electrode CNE1 may contact the first electrode RME1 in the sub-region SA through the first contact portion CT1 penetrating the first insulating layer PAS1 and the second insulating layer PAS2. The second connection electrode CNE2 may contact the second electrode RME2 in the sub-region SA through the second contact portion CT2 penetrating the first insulating layer PAS1 and the second insulating layer PAS2. As described above, the contact portions CT1 and CT2 may be formed by etching the first insulating layer PAS1 and the second insulating layer PAS2 at the same time. In the present embodiment, the first insulating layer PAS1 includes silicon oxynitride having an etching selectivity ratio of 4.1 or more with the second insulating layer PAS2, so that the contact portions CT1 and CT2 may be easily formed.

[0155] Each connection electrode CNE may be electrically connected to the third conductive layer through each electrode RME. The first connection electrode CNE1 may be electrically connected to the first transistor T1 to be applied with a first power supply voltage, and the second connection electrode CNE2 may be electrically connected to the second voltage wiring VL2 to be applied with a second power supply voltage. Each connection electrode CNE may contact the light emitting element ED in the light emitting area EMA and transmit the power supply voltage to the light emitting element ED.

[0156] However, the present invention is not limited thereto. In some embodiments, the plurality of connection electrodes CNE may be in direct contact with the third conductive layer, or may be electrically connected to the third conductive layer through other patterns other than the electrodes RME.

[0157] The connection electrode CNE may include a conductive material, such as ITO, IZO, ITZO, aluminum (Al), etc. As an example, the connection electrode CNE may include a transparent conductive material, and light emitted from the light emitting element ED may be emitted through the connection electrode CNE.

[0158] Although not shown in the drawings, another insulating layer may be disposed on the first connection electrode CNE1, the second connection electrode CNE2 and the second insulating layer PAS2. The insulating layer may protect components disposed on the first substrate SUB from the external environment.

[0159] Each of the first insulating layer PAS1 and the second insulating layer PAS2 may include an inorganic insulating material or an organic insulating material. As an example, each of the first insulating layer PAS1 and the second insulating layer PAS2 may include an inorganic insulating material, or the first insulating layer PAS1 may include an inorganic insulating material and the second insulating layer PAS2 may include an organic insulating material. Each or at least one layer of the first insulating layer PAS1 and the second insulating layer PAS2 may also be formed into a structure in which a plurality of insulating layers are alternately or repeatedly stacked. In an exemplary embodiment, each of the first insulating layer PAS1 and the second insulating layer PAS2 may be silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y The first insulating layer PAS1 and the second insulating layer PAS2 may be formed of the same material, or may be formed of a material that is partly the same and partly different from each other, or may be formed of materials that are different from each other.

[0160] Fig.10 is a schematic diagram of a light emitting element according to an embodiment.

[0161] Reference Fig.10 The light emitting element ED may be a light emitting diode (LED), and specifically, the light emitting element ED may be an inorganic light emitting diode having a size of nanometer to micrometer and made of inorganic matter. If an electric field is formed along a specific direction between two electrodes facing each other, the light emitting elements ED may be neatly arranged between the two electrodes forming polarity.

[0162] According to an embodiment, the light emitting element ED may have a shape extending in one direction. The light emitting element ED may have a shape such as a cylinder, a rod, a wire, a tube, etc. However, the form of the light emitting element ED is not limited thereto, and may have a multi-prism shape such as a cube, a rectangular parallelepiped, a hexagonal prism, or a shape extending in one direction with an outer surface partially inclined, etc.

[0163] The light emitting element ED may include a semiconductor layer doped with a dopant of any conductivity type (e.g., p-type or n-type). The semiconductor layer may emit light of a specific wavelength band by receiving an electrical signal applied from an external power source. The light emitting element ED may include a first semiconductor layer 31, a second semiconductor layer 32, a light emitting layer 36, an electrode layer 37, and an insulating film 38.

[0164] The first semiconductor layer 31 may be an n-type semiconductor. The first semiconductor layer 31 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) semiconductor material. For example, the first semiconductor layer 31 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with an n-type dopant. The n-type dopant doped in the first semiconductor layer 31 may be Si, Ge, Se, Sn, etc.

[0165] The second semiconductor layer 32 is disposed on the first semiconductor layer 31 and interposes the light emitting layer 36 therebetween. The second semiconductor layer 32 may be a p-type semiconductor, and the second semiconductor layer 32 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, 0≤x+y≤1) semiconductor material. For example, the second semiconductor layer 32 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with a p-type dopant. The p-type dopant doped in the second semiconductor layer 32 may be Mg, Zn, Ca, Ba, etc.

[0166] In addition, although the first semiconductor layer 31 and the second semiconductor layer 32 are shown in the drawings as being formed into one layer, this is not limited thereto. Depending on the material of the light emitting layer 36, the first semiconductor layer 31 and the second semiconductor layer 32 may also include a greater number of layers, for example, a clad layer or a tensile strain barrier reducing (TSBR: Tensile strain barrier reducing) layer. For example, the light emitting element ED may also include other semiconductor layers arranged between the first semiconductor layer 31 and the light emitting layer 36 or between the second semiconductor layer 32 and the light emitting layer 36. The semiconductor layer arranged between the first semiconductor layer 31 and the light emitting layer 36 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with an n-type dopant, and the semiconductor layer arranged between the second semiconductor layer 32 and the light emitting layer 36 may be one or more of AlGaInN, GaN, AlGaN, InGaN, AlN and InN doped with a p-type dopant.

[0167] The light emitting layer 36 is arranged between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material of a single quantum well structure or a multi-quantum well structure. In the case where the light emitting layer 36 includes a material of a multi-quantum well structure, it may also be a structure in which a plurality of quantum layers (Quantum layer) and a well layer (Well layer) are alternately stacked with each other. The light emitting layer 36 may emit light by combining electron-hole pairs according to an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include materials such as AlGaN, AlGaInN, InGaN, etc. In particular, in the case where the light emitting layer 36 is a structure in which quantum layers and well layers are alternately stacked as a multi-quantum well structure, the quantum layer may include AlGaN or AlGaInN, and the well layer may include materials such as GaN or AlInN.

[0168] The light emitting layer 36 may be a structure in which semiconductor materials of a type with a large energy band gap and semiconductor materials of a type with a small energy band gap are alternately stacked, or may include different semiconductor materials of group III to group V according to the wavelength band of the emitted light. The light emitted by the light emitting layer 36 is not limited to the light of the blue wavelength band, and may also emit light of the red and green wavelength bands according to the circumstances.

[0169] The electrode layer 37 may be an Ohmic connection electrode. However, it is not limited thereto, and it may also be a Schottky connection electrode. The light emitting element ED may include at least one electrode layer 37. The light emitting element ED may include more than one electrode layer 37, but it is not limited thereto, and the electrode layer 37 may also be omitted.

[0170] When the light emitting element ED is electrically connected to an electrode or a connection electrode in the display device 10, the resistance between the light emitting element ED and the electrode or the connection electrode can be reduced in the electrode layer 37. The electrode layer 37 may include a metal having conductivity. For example, the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), ITO, IZO, and ITZO.

[0171] The insulating film 38 is arranged in a manner surrounding the outer surfaces of the plurality of semiconductor layers and the electrode layer. For example, the insulating film 38 may be arranged to surround at least the outer surface of the light emitting layer 36, and may be formed to expose both ends of the light emitting element ED in the length direction. Furthermore, the upper surface of the insulating film 38 in the region adjacent to at least one end of the light emitting element ED may also be formed to be smoothly rounded in cross section.

[0172] The insulating film 38 may include a substance having insulating properties, for example, silicon oxide (SiO x), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x In the drawings, the insulating film 38 is shown as a single layer, but the present invention is not limited thereto. In some embodiments, the insulating film 38 may be a multilayer structure in which a plurality of layers are stacked.

[0173] The insulating film 38 can perform the function of protecting the semiconductor layer and the electrode layer of the light emitting element ED. In the case where the insulating film 38 is in direct contact with the electrode that transmits an electrical signal to the light emitting element ED, an electrical short circuit that may occur in the light emitting layer 36 can be prevented. In addition, the insulating film 38 can prevent the light emitting efficiency of the light emitting element ED from being reduced.

[0174] Furthermore, the outer surface of the insulating film 38 may be subjected to surface treatment. The light emitting elements ED may be sprayed onto the electrode in a state of being dispersed in a predetermined ink and arranged in a regular manner. In order to prevent the light emitting elements ED from agglomerating with other adjacent light emitting elements ED in the ink and maintain a dispersed state, the surface of the insulating film 38 may be subjected to hydrophobic or hydrophilic treatment.

[0175] Fig.11 is a cross-sectional view showing a display device according to another embodiment. Fig.12 Is magnification Fig.11 A diagram of a portion of an area. Fig.13 2 is a diagram showing a protruding portion of the first insulating layer.

[0176] Reference Figures 11 to 13 , and the above Figures 5 to 10 The embodiment is different from the embodiment in that the first insulating layer PAS1 according to an embodiment includes a protrusion PRU. Hereinafter, the description repeated with the above-mentioned embodiment will be omitted, and the difference will be described.

[0177] The first insulating layer PAS1 may include a protrusion PRU. The protrusion PRU may be a portion protruding from the surface of the first insulating layer PAS1 toward the light emitting element ED. The protrusion PRU may be formed as one body with the first insulating layer PAS1 and may be a part of the first insulating layer PAS1. However, it is not limited thereto, and the protrusion PRU may also be formed separately from the first insulating layer PAS1. The protrusion PRU may overlap with the light emitting element ED on a plane to induce physical surface friction with the light emitting element ED, thereby playing a role in improving the adhesion of the light emitting element ED.

[0178] The protrusion PRU may include a first protrusion PRU1 and a second protrusion PRU2. The first protrusion PRU1 may overlap with the first electrode RME1 and may overlap with one end of the light emitting element ED. The second protrusion PRU2 may overlap with the second electrode RME2 and may overlap with the other end of the light emitting element ED. The first protrusion PRU1 and the second protrusion PRU2 may be arranged to extend along the first direction DR1 and may be arranged to be spaced apart from each other in the second direction DR2. The first protrusion PRU1 and the second protrusion PRU2 may be arranged side by side with each other.

[0179] The first protrusion PRU1 and the second protrusion PRU2 may be in contact with the light emitting element ED, respectively. For example, the first protrusion PRU1 may be in contact with the lower surface of one end of the light emitting element ED, and the second protrusion PRU2 may be in contact with the lower surface of the other end of the light emitting element ED. The first protrusion PRU1 and the second protrusion PRU2 may be arranged along the length direction of the light emitting element ED in the area overlapping with the light emitting element ED. For example, the width of the first protrusion PRU1 in the second direction DR2 may be smaller than the length of the light emitting element ED. Similarly, the width of the second protrusion PRU2 in the second direction DR2 may also be smaller than the length of the light emitting element ED. The sum of the widths of each of the first protrusion PRU1 and the second protrusion PRU2 may be smaller than the length of the light emitting element ED.

[0180] Furthermore, the side of the first protrusion PRU1 and the side of one end of the light emitting element ED can be neatly arranged and aligned with each other. If the first protrusion PRU1 is arranged further outward than the side of one end of the light emitting element ED, the light reflected by the electrode RME may be reflected and diffused between the protruding structures PR of the first protrusion PRU1, thereby reducing the light extraction efficiency.

[0181] The first protrusion PRU1 and the second protrusion PRU2 may include a plurality of protruding structures PR, respectively. The plurality of protruding structures PR may extend along the first direction DR1 and be arranged spaced apart from each other in the second direction DR2. The protruding structures PR may be formed with a height HH of 1% to 30% of the thickness of the first insulating layer PAS1. The protruding structures PR may have a predetermined width W2, and the width W2 is not particularly limited as long as a plurality of protruding structures PR may be arranged in an area in contact with the lower surface of the light emitting element ED. In addition, the protruding structures PR may have a predetermined spacing interval SD2 with adjacent protruding structures PR. The spacing interval SD2 of the protruding structures PR may be greater than or equal to the width W2 of the protruding structures PR. However, it is not limited thereto, and the spacing interval SD2 of the protruding structures PR may also be less than the width W2 of the protruding structures PR.

[0182] As described above, after the light emitting element ED is coated on the first insulating layer PAS1 together with the solvent, the light emitting element ED can be moved by the electric field formed on the first insulating layer PAS1, so that it can be placed and neatly arranged on the electrode RME. In one embodiment, since a protrusion PRU is formed on the first insulating layer PAS1, after the light emitting element ED is placed on the electrode RME, it will not move to other places due to friction with the protrusion PRU, but will be fixed. That is, by forming the protrusion PRU on the first insulating layer PAS1, the light emitting element ED can be well and neatly arranged on the electrode RME.

[0183] Fig.14 is a cross-sectional view showing a display device according to still another embodiment.

[0184] Reference Fig.14 In this embodiment, Figures 5 to 13 The embodiment of FIG. 1 is different in that a flat layer GP is included between RMEs. Hereinafter, repeated contents will be omitted and the differences will be described.

[0185] A flat layer GP may be arranged between the RMEs. For example, a flat layer GP may be arranged between the first electrode RME1 and the second electrode RME2. The flat layer GP may be arranged on the upper surface of the via layer VIA, and may be arranged in contact with the side surface of each of the first electrode RME1 and the second electrode RME2. The flat layer GP may fill the space between the first electrode RME1 and the second electrode RME2. The upper surface of the flat layer GP may be aligned with the upper surface of the first electrode RME1 and the upper surface of the second electrode RME2 so as to be aligned with each other.

[0186] The planar layer GP may be formed of an organic insulating material such as polyimide, etc. For example, the planar layer GP may be formed of the same material as the via layer VIA, the bank patterns BP1 and BP2 , or the bank layer BNL.

[0187] A first insulating layer PAS1 may be arranged on the flat layer GP and may be arranged overlapping with the light emitting element ED. The flat layer GP may flatten the step difference of the lower portion of the first insulating layer PAS1, thereby playing a role in forming the first insulating layer PAS1 flatly in the region overlapping with the light emitting element ED. The side of each of the first electrode RME1 and the second electrode RME2 may be tapered, or the side of the first electrode RME1 and the second electrode RME2 may be filled with the flat layer GP to remove the step difference. Accordingly, by forming the first insulating layer PAS1 formed on the first electrode RME1 and the second electrode RME2 flatly, it is possible to prevent the generation of a seam in the first insulating layer PAS1.

[0188] Hereinafter, an experimental example on the first insulating layer according to the present embodiment is disclosed.

[0189] <Experimental Example: Whether a Seam Occurs Depending on the Composition of the First Insulating Layer> Manufacturing example Electrodes are formed on the substrate, and a first insulating layer covering the electrodes is formed on the substrate. Then, a first connecting electrode is formed on the first insulating layer. Aluminum alloy is used as the electrode, and ITO is used as the first connecting electrode and stacked.

[0190] Comparative Example 1 As the first insulating layer, SiO x The thickness is 3000 The film was formed in the manner of.

[0191] Comparative Example 2 As the first insulating layer, the thickness of SiON is 3000 At this time, the film was formed to have a composition ratio of 34.6 at% Si, 63.8 at% O, and 1.5 at% N.

[0192] Comparative Example 3 As the first insulating layer, the thickness of SiON is 3000 At this time, the film was formed to have a composition ratio of Si at 42.9 at%, O at 24.2 at%, and N at 32.9 at%.

[0193] Example As the first insulating layer, the thickness of SiON is 3000 At this time, the film was formed to have a composition ratio of Si of 41.8 at%, O of 29.0 at%, and N of 29.3 at%.

[0194] The structures manufactured according to Comparative Examples 1 to 3 and the Example were observed using a transmission electron microscope (TEM) to obtain images.

[0195] Fig.15 is a transmission electron microscope image according to Comparative Example 1, Fig.16 is a transmission electron microscope image according to Comparative Example 2, Fig.17 is a transmission electron microscope image according to Comparative Example 3, Fig.18 is a transmission electron microscope image according to an embodiment.

[0196] Reference Figures 15 to 18 , seams were generated in all the first insulating layers according to Comparative Examples 1 to 3. In contrast, it was confirmed that no seams were generated in the first insulating layer according to the embodiment.

[0197] From this result, it can be confirmed that the first insulating layer according to the present embodiment prevents the generation of seams on the side surfaces of the electrodes by including silicon oxynitride in which the composition ratio of Si, O, and N is adjusted.

[0198] The embodiments of the present invention are described above with reference to the accompanying drawings, but it is understood by those with ordinary knowledge in the technical field to which the present invention belongs that the present invention can be implemented in other specific forms without changing the technical ideas or essential features of the present invention. Therefore, the embodiments described above should be understood to be exemplary in all aspects, rather than restrictive.

Claims

1. A display device, comprising: a substrate; a first electrode and a second electrode, disposed on the substrate, extending in a first direction and spaced apart from each other; a first insulating layer, disposed on the first electrode and the second electrode; a light-emitting element, disposed on the first insulating layer and disposed between the first electrode and the second electrode; and a first connection electrode and a second connection electrode, the first connection electrode being connected to one end of the light-emitting element, and the second connection electrode being connected to the other end of the light-emitting element, wherein the first insulating layer includes a trench portion overlapping with the light-emitting element and including a plurality of trenches.

2. The display device according to claim 1, wherein the trench portion includes: a first trench portion overlapping with one end of the light-emitting element; and a second trench portion overlapping with the other end of the light-emitting element.

3. The display device according to claim 2, wherein the first trench portion overlaps with the first electrode and extends side by side, and the second trench portion overlaps with the second electrode and extends side by side.

4. The display device according to claim 2, wherein the side of the first trench portion is aligned with the side of one end of the light-emitting element, and the side of the second trench portion is aligned with the side of the other end of the light-emitting element.

5. The display device according to claim 1, wherein the trench portion is in contact with the lower surface of the light-emitting element.

6. The display device according to claim 1, wherein the depth of the trench portion is configured to be 1% to 30% of the thickness of the first insulating layer.

7. The display device according to claim 1, wherein the first insulating layer includes a silicon oxynitride represented by Chemical Formula 1 below: [Chemical Formula 1] You x About y N z , wherein x, y, and z respectively satisfy 34.6 < x < 42.9, 24.2 < y < 63.8, 1.5 < z < 32.9, and x, y, and z are atomic ratios.

8. The display device according to claim 1, wherein The thickness of the first insulating layer is 2000 Up to 3000 .

9. The display device according to claim 1, wherein the refractive index of the first insulating layer is greater than 1.4 and less than 1.

63.

10. The display device according to claim 1, further comprising: a second insulating layer, disposed on the light-emitting element, wherein the etching selectivity between the first insulating layer and the second insulating layer is 4.1 or more.

11. A display device, comprising: a substrate; a first electrode and a second electrode, disposed on the substrate, extending in a first direction and spaced apart from each other; a first insulating layer, disposed on the first electrode and the second electrode; a light-emitting element, disposed on the first insulating layer and disposed between the first electrode and the second electrode; and a first connection electrode and a second connection electrode, the first connection electrode being connected to one end of the light-emitting element, and the second connection electrode being connected to the other end of the light-emitting element, wherein the first insulating layer includes a protruding portion overlapping with the light-emitting element and including a plurality of protruding structures.

12. The display device according to claim 11, wherein The protruding portion includes: a first protruding portion overlapping with one end portion of the light-emitting element; and a second protruding portion overlapping with the other end portion of the light-emitting element.

13. The display device according to claim 12, wherein, The first protruding portion overlaps with the first electrode and extends side by side, and the second protruding portion overlaps with the second electrode and extends side by side.

14. The display device according to claim 12, wherein, The side edge of the first protruding portion is aligned with the side edge of one end portion of the light-emitting element, and the side edge of the second protruding portion is aligned with the side edge of the other end portion of the light-emitting element.

15. The display device according to claim 11, wherein, The protruding portion is in contact with the lower surface of the light-emitting element.

16. The display device according to claim 11, wherein, The height of the protruding structure is configured to be 1% to 30% of the thickness of the first insulating layer.

17. The display device according to claim 11, wherein, The first insulating layer includes a silicon oxynitride represented by the following Chemical Formula 1: [Chemical Formula 1] You x About y N z , Wherein, x, y, and z respectively satisfy 34.6 < x < 42.9, 24.2 < y < 63.8, 1.5 < z < 32.9, and x, y, and z are atomic ratios.

18. The display device according to claim 11, wherein, The thickness of the first insulating layer is 2000 Up to 3000 .

19. The display device according to claim 11, wherein, The refractive index of the first insulating layer is greater than 1.4 and less than 1.

63.

20. The display device according to claim 11, further comprising: A second insulating layer disposed on the light-emitting element, Wherein, the etching selectivity between the first insulating layer and the second insulating layer is 4.1 or more.

Images