Display panel, preparation method thereof and display device
By opening a first via on the anode layer, the flat layer is exposed and an isolation groove is formed, the crosstalk between low gray-grade pixels in series OLED devices is solved, reducing production costs and improving product yield.
Patent Information
- Application Number
- CN202411651992.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-02-25
AI Technical Summary
When solving the crosstalk problem between low grayscale pixels, existing series OLED devices have complex processes, high production costs, and are prone to abnormal overlap between the anode and auxiliary electrodes.
A first via is opened on the anode layer to expose the flat layer, thereby forming an isolation groove in this area of the flat layer, reducing processing steps and reducing production costs while avoiding contact abnormalities between the anode and the auxiliary electrode.
By reducing processing processes and reducing production costs, the problem of low grayscale pixel crosstalk is solved, and the product yield and product competitiveness of the display panel are improved.
Smart Images
Figure CN119521956A_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art
[0002] With the development of display technology, compared with ordinary OLED (organic light emitting diode) devices, Tandem (tandem) OLED devices have the characteristics of long life, narrow half-peak width (to achieve high color gamut), and low power consumption. In TandemOLED devices, the light-emitting material layers are connected by CGL (charge generation layer). Under the action of the electric field, the CGL layer undergoes charge separation, and electrons and holes are transmitted to different light-emitting material layers respectively. Under the same current density, the luminous efficiency is several times that of single-stack OLED devices.
[0003] However, in the process of solving the problem of crosstalk between low grayscale pixels, the tandem OLED device in the related art has problems such as complex process, high production cost, and easy to cause abnormal overlap between the anode and the auxiliary electrode. Summary of the invention
[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a display panel and a method for preparing the same, and a display device, wherein a first via hole is formed in the anode layer to expose the flat layer, thereby facilitating the formation of an isolation groove in the area where the flat layer is exposed from the first via hole, which is beneficial to reducing the processing steps and reducing the production and processing costs, while reliably avoiding the problem of abnormal contact between the anode and the auxiliary electrode in the overlapping holes of the flat layer, thereby reliably solving the problem of crosstalk between low grayscale pixels of the display panel, ensuring that the display panel has a good display effect, and improving the product yield and product competitiveness of the display panel.
[0005] In a first aspect, the present invention provides a display panel, comprising:
[0006] Flat layer;
[0007] an anode layer, the anode layer being disposed on one side of the flat layer, and having a first via hole formed on the anode layer, the first via hole penetrating the anode layer from a surface of the anode layer away from the flat layer toward the flat layer, so that the flat layer is exposed at the first via hole;
[0008] The planar layer is provided with an isolation groove, and the isolation groove is extended from the surface of the planar layer exposed from the first via hole toward the inside of the planar layer.
[0009] As an optional solution, the display panel includes a substrate, the substrate includes a plurality of pixel areas, and an orthographic projection of the first via hole on the substrate is located in a region between orthographic projections of two adjacent pixel areas on the substrate.
[0010] As an optional solution, in the isolation trench region, the planar layer is recessed relative to the anode layer along a direction parallel to the planar layer.
[0011] As an optional solution, the indentation amount of the planar layer relative to the anode layer is greater than or equal to 0.1 μm and less than or equal to 0.5 μm.
[0012] As an optional solution, the width of the isolation trench gradually decreases in the extension direction of the isolation trench.
[0013] As an optional solution, the anode layer is also provided with a second via hole, which penetrates the anode layer from the surface of the anode layer facing away from the flat layer toward the flat layer, and the second via hole is spaced apart from the first via hole, and the orthographic projection of the second via hole on the substrate does not overlap with the orthographic projection of the pixel area on the substrate.
[0014] As an optional solution, the display panel also includes a pixel definition layer, which is arranged on the side of the anode layer away from the flat layer, and a third via is opened on the pixel definition layer, and the third via penetrates the pixel definition layer from the surface of the pixel definition layer away from the flat layer toward the flat layer, and the position of the third via corresponds to the first via, so that the flat layer is exposed to the third via.
[0015] As an optional solution, the pixel definition layer is further provided with a pixel opening area, the pixel opening area is arranged corresponding to the pixel area, and the opening area is arranged at an interval with the third via hole.
[0016] As an optional solution, the substrate further includes an auxiliary electrode, the flat layer is provided with a lap hole, and the anode layer is in electrical contact with the auxiliary electrode through the lap hole.
[0017] In a second aspect, the present invention provides a method for preparing a display panel, the method comprising the following steps:
[0018] preparing a flat layer;
[0019] An anode layer is formed on one side of the flat layer, and a first via hole is opened in the anode layer. The first via hole penetrates the anode layer from a surface of the anode layer away from the flat layer toward the flat layer, so that the flat layer is exposed at the first via hole;
[0020] An isolation groove is formed in the flat layer, and the isolation groove extends from the surface of the flat layer exposed from the first via hole toward the inside of the flat layer.
[0021] As an optional solution, an isolation trench is formed in the planar layer, including:
[0022] forming a pixel definition layer on a side of the anode layer facing away from the planar layer;
[0023] A third via hole is formed on the pixel definition layer, the third via hole penetrates the pixel definition layer from the surface of the pixel definition layer away from the flat layer toward the flat layer, and the position of the third via hole corresponds to the first via hole, so that the flat layer is exposed at the third via hole;
[0024] The area of the planar layer exposed from the third via hole is etched to obtain an isolation groove.
[0025] As an optional solution, after forming the anode layer on one side of the planar layer, the method further includes:
[0026] A second via hole is opened in the anode layer, and the second via hole penetrates the anode layer from the surface of the anode layer away from the flat layer toward the flat layer, and the second via hole is spaced apart from the first via hole, and the orthographic projection of the second via hole on the substrate does not overlap with the orthographic projection of the pixel area on the substrate.
[0027] As an optional solution, before forming the anode layer on one side of the planar layer, the method further includes:
[0028] An exposure process is used to form overlapping holes in the flat layer.
[0029] In a third aspect, the present invention provides a display device, comprising the display panel of the first aspect or the display panel obtained according to the preparation method of the second aspect.
[0030] The display panel of the present invention directly sets an anode layer on one side of the flat layer, and a first via hole is opened on the anode layer. The first via hole penetrates the anode layer from the surface of the anode layer away from the flat layer toward the flat layer, so that the flat layer is exposed to the first via hole. The flat layer is provided with an isolation groove, and the isolation groove extends from the surface of the flat layer exposed to the first via hole toward the inside of the flat layer. In this way, by opening a hole in the anode layer to expose the flat layer, it is convenient to form an isolation groove in the area where the flat layer is exposed to the first via hole, and there is no need to set a passivation layer, which is conducive to reducing the processing steps and reducing the production and processing costs. At the same time, the problem of abnormal contact between the anode and the auxiliary electrode in the overlapping hole of the flat layer is reliably avoided, and the problem of low grayscale pixel crosstalk in the display panel is further reliably solved, and the display panel is guaranteed to have a good display effect, and the product yield and product competitiveness of the display panel are improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0032] Figure 1 is a schematic diagram of the structure of a display panel in the prior art;
[0033] Figure 2 This is a rendering of the isolation groove of the passivation layer B and the planar layer in the display panel in the prior art;
[0034] Figure 3 A schematic diagram of a foreign body in a flat layer overlap hole of a display panel in the prior art;
[0035] Figure 4 A schematic diagram of abnormal overlap of an anode layer in an overlap hole in a display panel in the prior art;
[0036] Figure 5 A schematic diagram of the structure of a display panel according to an embodiment of the present application;
[0037] Figure 6 A schematic diagram of a structure for preparing a flat layer in a display panel according to an embodiment of the present application;
[0038] Figure 7 A schematic diagram of a structure for preparing an anode layer on a flat layer in a display panel of an embodiment of the present application;
[0039] Figure 8 A schematic diagram of a structure for preparing a pixel definition layer on an anode layer in a display panel of an embodiment of the present application;
[0040] Fig. 9 A schematic diagram of the structure of preparing isolation grooves in a flat layer of a display panel according to an embodiment of the present application.
[0041] In the figure,
[0042] 100. Display panel;
[0043] 10. substrate, 11. passivation layer A, 12. auxiliary electrode, 13. passivation layer B;
[0044] 20. flat layer, 21. overlap hole, 22. isolation groove;
[0045] 30. anode layer, 31. first via hole, 32. second via hole;
[0046] 40. pixel definition layer, 41. pixel opening area, 42. third via hole. DETAILED DESCRIPTION
[0047] The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are shown in the accompanying drawings.
[0048] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0049] Tandem OLED has the problem of crosstalk between low grayscale pixels. In the related art, isolation grooves 22 are set between pixel areas to isolate the light-emitting layer and the metal connection layer between each light-emitting layer to improve the problem of crosstalk between low grayscale pixels. Figure 1 and 2 As shown, in the related art, a passivation layer B13 (PVX) is usually stacked on one side of the flat layer 20 (PLN), and an anode layer 30 is set on the layer of the passivation layer away from the flat layer 20. In this way, the passivation layer needs to be prepared through deposition, masking, evaporation, and etching processes to expose the flat layer 20, and the flat layer 20 is etched to form an isolation groove 22. In the process of etching the passivation layer B13, in addition to etching the passivation layer B13 in the area corresponding to the isolation groove 22, it is also necessary to etch the passivation layer B13 in the area of the overlapping hole 21. The above process increases production costs and reduces production efficiency. In addition, the etching morphology of the overlapping hole 21 has high requirements and the process is difficult. At present, there are problems such as residual foreign matter at the edge of the hole and abnormal morphology of the hole edge (such as Figure 3 and 4 As shown in the figure, the anode layer 30 (AND) is deposited abnormally at the hole edge, resulting in the risk of breakage and ET dark spots.
[0050] Based on the above problems, Figure 5 As shown, in a first aspect, the present invention provides a display panel 100, comprising:
[0051] Flat layer 20;
[0052] an anode layer 30, the anode layer 30 being disposed on one side of the flat layer 20, and having a first via hole 31 formed therein, the first via hole 31 penetrating the anode layer 30 from a surface of the anode layer 30 away from the flat layer 20 toward the flat layer 20, so that the flat layer 20 is exposed at the first via hole 31;
[0053] The planar layer 20 is provided with an isolation trench 22 , and the isolation trench 22 is extended from the surface of the planar layer 20 exposed from the first via hole 31 toward the inside of the planar layer 20 .
[0054] It can be understood that the display panel 100 includes a driving layer, which includes an active layer, a gate insulation layer, a gate layer, an interlayer dielectric layer, and a source-drain metal layer; wherein the source-drain metal layer is covered with a passivation layer A11, and the passivation layer A11 is used to protect and isolate the source-drain metal layer. The passivation layer A11 is usually made of inorganic materials, such as but not limited to silicon nitride, silicon oxynitride, etc.; the surface of the passivation layer A11 facing away from the source-drain metal layer is covered with a flat layer 20 (PLN), and the flat layer 20 is mainly used to provide a flat and stable surface for the deposition of subsequent layers (such as electron injection layer, cathode layer, etc.), and can also protect the underlying metal structure. The flat layer 20 is usually made of organic materials.
[0055] In the embodiment of the present application, the anode layer 30 (AND) on one side of the flat layer 20 does not need to be provided with a passivation layer B13 between the anode layer 30 and the flat layer 20, which is conducive to simplifying the processing technology, saving processing steps, and reducing production costs; wherein, a first via hole 31 is opened on the anode layer 30, and the first via hole 31 can be obtained by graphically designing the anode layer 30 using a mask and dry etching; the first via hole 31 can be of any shape, such as but not limited to a circular hole, a rectangular hole, etc., and the first via hole 31 is mainly used to expose the flat layer 20 area corresponding to the isolation groove 22. It should be noted that in the process of etching the anode layer 30, at least the anode layer 30 area corresponding to the pixel area of the display panel needs to be retained, as long as the area of the anode layer 30 located between two adjacent pixel areas is partially etched to form the first via hole 31.
[0056] The anode layer 30 may be a composite structure composed of a transparent conductive oxide film / metal film / transparent conductive oxide film stacked in sequence. The material of the transparent conductive oxide film may be any one of ITO (Indium tin oxide) and IZO (Indium zinc oxide), and the material of the metal film may be any one of gold (Au), silver (Ag), nickel (Ni) and platinum (Pt). For another example, the structure of the anode layer 30 may also be a single-layer structure, and the material of the single-layer structure may be any one of ITO, IZO, Au, Ag, Ni, and Pt.
[0057] It can also be understood that the flat layer 20 is provided with an isolation groove 22, and the isolation groove 22 extends from the surface of the flat layer 20 exposed in the first via hole 31 toward the inside of the flat layer 20, that is, the isolation groove 22 is connected to the first via hole 31, so that an undercut structure is formed between the anode layer 30 and the flat layer 20, which can ensure that the light-emitting layer and the metal connection layer between each light-emitting layer are separated, thereby improving the problem of low grayscale pixel crosstalk. Among them, the shape and size of the isolation groove 22 are the same as the shape and size of the isolation groove 22 in the related art. For example, the depth of the isolation groove 22 of the embodiment of the present application along its extension direction can be 0.2μm-1μm, as long as it is ensured that the isolation groove 22 does not penetrate the flat layer 20 in its extension direction.
[0058] The display panel of the embodiment of the present application solves the problem of complicated process of preparing isolation groove 22 in the prior art and abnormal overlap between anode layer 30 and auxiliary electrode 12. The embodiment of the present application opens a first via hole 31 in anode layer 30 to expose flat layer 20, thereby facilitating the formation of isolation groove 22 in the area where flat layer 20 is exposed to first via hole 31, and does not need to set passivation layer B13, which is conducive to reducing processing procedures and production and processing costs; and since passivation layer B13 is not set between flat layer 20 and anode layer 30, there is no problem of etching foreign matter in overlap hole 21 due to etching passivation layer B13, thereby reliably avoiding the problem of abnormal contact between anode and auxiliary electrode 12 in overlap hole 21 of flat layer 20, further reliably solving the problem of crosstalk of low grayscale pixels of display panel, while ensuring that the display panel has good display effect, improving product yield and product competitiveness of display panel.
[0059] In some embodiments, the display panel 100 includes a substrate 10 , the substrate 10 includes a plurality of pixel regions, and an orthographic projection of the first via hole 31 on the substrate 10 is located in a region between orthographic projections of two adjacent pixel regions on the substrate 10 .
[0060] The substrate 10 may be, but is not limited to, glass, PI (Polyimide), PET (Polyethyleneglycol terephthalate), PEN (Polyethylene naphthalate twoformic acid glycol ester) substrate or silicon (single crystal silicon or polycrystalline silicon), etc. For example, in the embodiment of the present application, the substrate 10 may be a silicon base, such as single crystal silicon, and the corresponding display panel is a silicon-based display panel.
[0061] It can be understood that the substrate 10 is sequentially provided with a driving layer, a passivation layer, a flat layer 20, a pixel definition layer 40 and a plurality of light-emitting units in a direction away from the substrate 10; wherein, a plurality of pixel opening regions 41 are provided on the pixel definition layer 40, and each light-emitting unit is correspondingly located in each pixel opening region 41, and the light-emitting unit includes an anode layer 30, a light-emitting layer and a cathode layer which are sequentially stacked. Each pixel opening region 41 exposes a portion of the anode of the corresponding light-emitting unit, and at least a portion of the light-emitting layer is located in the corresponding pixel opening region 41 and is electrically connected to the corresponding anode. In this way, a plurality of pixel regions are formed on the substrate 10.
[0062] In the embodiment of the present application, the orthographic projection of the first via hole 31 on the substrate 10 is located in the area between the orthographic projections of two adjacent pixel areas on the substrate 10, which means that the orthographic projection of the first via hole 31 on the substrate 10 does not overlap with the orthographic projection of the pixel area on the substrate 10. This is conducive to ensuring that the isolation groove 22 is reliably formed to separate the light-emitting layer and the metal connection layer, avoiding the problem of crosstalk between low grayscale pixel components, and at the same time, it can ensure that the light-emitting layer is reliably driven to emit light.
[0063] In some embodiments, Figure 5 As shown, in the region of the isolation groove 22 , along a direction parallel to the planar layer 20 , the planar layer 20 is retracted relative to the anode layer 30 .
[0064] In practical applications, the isolation groove 22 is formed by sequentially dry-etching the anode layer 30 and the flat layer 20, and the isolation groove 22 is formed along a direction parallel to the flat layer 20 (eg Figure 5 In the X direction), the etching amount of the flat layer 20 is greater than the etching amount of the anode layer 30, so that the notch of the isolation groove 22 is smaller, and the anode layer 30 protrudes part of the area relative to the notch of the isolation groove 22, which is conducive to forming an "undercut" isolation groove 22 morphology, ensuring the isolation effect, while helping to improve the adhesion effect of other film layers (such as the encapsulation layer) in the isolation groove 22, thereby ensuring the processing quality of the display panel.
[0065] In a preferred embodiment, Figure 5 As shown, the amount of indentation d of the planar layer 20 relative to the anode layer 30 is greater than or equal to 0.1 μm and less than or equal to 0.5 μm.
[0066] Specifically, the indentation amount of the flat layer 20 relative to the anode layer 30 may be, but is not limited to, 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm or 0.5 μm, etc.;
[0067] In this embodiment, the indentation of the flat layer 20 relative to the anode layer 30 is beneficial to ensuring the morphology of the isolation groove 22, while facilitating processing and reducing the requirements of the processing technology.
[0068] In some embodiments, the width of the isolation trench 22 gradually decreases in the extending direction of the isolation trench 22 .
[0069] The width of the isolation trench 22 refers to the width of the isolation trench 22 in a direction parallel to the planar layer 20 (eg Figure 5 The distance between the two opposite sides in the X direction.
[0070] In this embodiment, the width of the isolation groove 22 along its extension direction gradually decreases to form an inverted trapezoidal isolation groove 22, which ensures reliable isolation of the light-emitting layer and the metal connection layer while facilitating better bonding with other film layers and facilitating processing.
[0071] As a feasible method, the anode layer 30 is further provided with a second via hole 32, which penetrates the anode layer 30 from the surface of the anode layer 30 away from the flat layer 20 toward the flat layer 20, and the second via hole 32 is spaced apart from the first via hole 31, and the orthographic projection of the second via hole 32 on the substrate 10 does not overlap with the orthographic projection of the pixel area on the substrate 10.
[0072] In the actual processing process, the first via hole 31 and the second via hole 32 of the anode layer 30 are formed at one time through graphic design. The shape and size of the second via hole 32 can be the same as the shape and size of the first via hole 31. Of course, the shape and size of the second via hole 32 can also be different from the shape and size of the first via hole 31, as long as the second via hole 32 passes through the anode layer 30, the anode layer 30 of the pixel area is disconnected from the anode layer 30 of other areas (between two pixel areas or the anode layer 30 area corresponding to the isolation groove 22), thereby avoiding the inability to reliably achieve the isolation effect.
[0073] The second via hole 32 in this embodiment is helpful to ensure that the isolation groove 22 can reliably isolate the light-emitting layer and the metal connection layer, thereby solving the problem of crosstalk between low grayscale pixels.
[0074] As a feasible method, the display panel also includes a pixel definition layer 40, which is arranged on the side of the anode layer 30 away from the flat layer 20, and a third via hole 42 is opened on the pixel definition layer 40, and the third via hole 42 penetrates the pixel definition layer 40 from the surface of the pixel definition layer 40 away from the flat layer 20 toward the flat layer 20, and the position of the third via hole 42 corresponds to the first via hole 31, so that the flat layer 20 is exposed to the third via hole 42.
[0075] It can be understood that the pixel definition layer 40 (PDL) is used to define and limit the shape and size of the pixel area to ensure that each pixel area can work. Specifically, the pixel definition layer 40 can ensure isolation between pixel areas to prevent crosstalk of current or light.
[0076] In actual processing, the pixel definition layer 40 is generally made of inorganic materials, formed into a film by plasma enhanced chemical vapor deposition, and then formed into a specific PDL structure (forming an opening area 41 and a third via 42 in the pixel definition layer 40) through processes such as photoresist coating, exposure, development, curing, dry etching and wet stripping.
[0077] In this embodiment, a third via hole 42 is formed in the pixel definition layer 40 , and the third via hole 42 is arranged corresponding to the first via hole 31 of the anode layer 30 , which is beneficial to expose the planar layer 20 , thereby facilitating the formation of the isolation groove 22 between the pixel regions.
[0078] Among them, the shape of the third via hole 42 can be the same as the shape of the first via hole 31. Of course, the shape of the third via hole 42 can also be different from the shape of the first via hole 31, as long as the third via hole 42 passes through the pixel definition layer 40 so that the third via hole 42 is connected to the first via hole 31.
[0079] In some embodiments, the pixel definition layer 40 further defines a pixel opening region 41 , the pixel opening region 41 is disposed corresponding to the pixel region, and the pixel opening region 41 is spaced apart from the third via hole 42 .
[0080] The pixel opening area 41 of the pixel definition layer 40 in this embodiment is stacked with a light emitting layer and a cathode layer to define the pixel area. The third via hole 42 is spaced apart from the pixel opening area 41 to reliably define the pixel area while exposing the planar layer 20, thereby reliably forming the isolation groove 22.
[0081] It can be understood that, in actual processing, the pixel opening area 41 and the third via hole 42 of the pixel definition layer 40 are formed simultaneously, which saves process and improves processing efficiency.
[0082] In some embodiments, the substrate 10 further includes an auxiliary electrode 12 , the planar layer 20 is provided with a lap hole 21 , and the anode layer 30 is in electrical contact with the auxiliary electrode 12 through the lap hole 21 .
[0083] The auxiliary electrode 12 is generally made of titanium, aluminum and titanium. The auxiliary electrode 12 is in electrical contact with the source and drain electrodes, and is used to reliably drive the light-emitting layer to emit light.
[0084] In this embodiment, a lap hole 21 is opened in the flat layer 20, and the anode layer 30 can be directly deposited in the lap hole 21, so that the anode layer 30 is directly in electrical contact with the auxiliary electrode 12, ensuring good ohmic contact, thereby reliably driving the light-emitting layer to emit light under the drive of the driving layer.
[0085] In summary, the display panel of the present application, by opening the first via hole in the anode layer 30 to expose the flat layer 20, facilitates the formation of the isolation groove 22 in the area where the flat layer 20 is exposed in the first via hole 31, and does not need to set the passivation layer B13, which is conducive to reducing the processing steps and reducing the production and processing costs. At the same time, it reliably avoids the problem of abnormal contact between the anode and the auxiliary electrode 12 in the overlapping hole 21 of the flat layer 20, further reliably solves the problem of low grayscale pixel crosstalk in the display panel, and ensures that the display panel has a good display effect, thereby improving the product yield and product competitiveness of the display panel;
[0086] Furthermore, the second via hole 32 of the anode layer 30 can reliably isolate the anode layer 30 in the pixel area from the anode layer 30 in the isolation groove 22 area, further ensuring that the isolation groove 22 reliably isolates the light-emitting layer and the metal connection layer, thereby solving the problem of crosstalk between low grayscale pixels.
[0087] In a second aspect, an embodiment of the present application provides a method for preparing a display panel, such as Figure 6-9 As shown, the preparation method comprises the following steps:
[0088] Step S10, preparing a flat layer 20;
[0089] It is understandable that before preparing the flat layer 20, a passivation layer A11 is first prepared on the substrate 10 to protect the driving layer; the flat layer 20 is prepared using an existing flat layer 20 process. For example, a flat material layer can be formed on one side of the substrate 10 using a film forming process, and the flat material layer is dry-etched to obtain the overlapping hole 21.
[0090] Step 20, forming an anode layer 30 on one side of the flat layer 20, and opening a first via hole 31 in the anode layer 30, wherein the first via hole 31 penetrates the anode layer 30 from a surface of the anode layer 30 away from the flat layer 20 toward the flat layer 20, so that the flat layer 20 is exposed in the first via hole 31;
[0091] Among them, the anode layer 30 is generally a single-layer or multi-layer structure of metal or metal oxide, which can be prepared by processes such as sputtering or thin film deposition; the first via hole 31 is obtained by graphically designing the anode layer 30 and etching the exposed anode layer 30 with an etching solution, so that the flat layer 20 exposes the first via hole 31.
[0092] In this embodiment, the anode layer 30 is graphically designed in advance according to the position of the pixel region and the target position of the isolation groove 22 , and it should be ensured that the exposed area of the anode layer 30 (that is, the position of the first via hole 31 ) corresponds to the position of the isolation groove 22 .
[0093] Step 30 , forming an isolation trench 22 in the planar layer 20 . The isolation trench 22 extends from the surface of the planar layer 20 exposed from the first via hole 31 toward the inside of the planar layer 20 .
[0094] It should be noted that since the isolation groove 22 is used to isolate the light-emitting layer and the metal connection layer between the light-emitting layers to prevent the problem of crosstalk between pixels at low grayscale, before the isolation groove 22 is formed in the flat layer 20, the pixel area should be determined first, that is, it is necessary to first prepare the pixel definition layer 40 on the surface of the anode layer 30 away from the flat layer 20, and perform graphic design on the pixel definition layer 40, and etch the exposed area of the pixel definition layer 40 to expose the flat layer 20, and etch the exposed area of the flat layer 20 to obtain the isolation groove 22.
[0095] The method for preparing the display panel of the embodiment of the present application directly opens the first via hole 31 in the anode layer 30 so that the flat layer 20 is exposed in the first via hole 31, thereby etching the area of the flat layer 20 where the first via hole 31 is exposed to obtain the isolation groove 22. There is no need to set a passivation layer B13 on the flat layer 20. On the one hand, it simplifies the processing technology and is conducive to reducing production costs. On the other hand, it reliably avoids the problem of abnormal contact between the anode and the auxiliary electrode 12 in the overlapping hole 21 of the flat layer 20, further reliably solves the problem of low grayscale pixel crosstalk in the display panel, ensures that the display panel has a good display effect, and improves the product yield and product competitiveness of the display panel.
[0096] In some embodiments, step 30, forming an isolation trench 22 in the planar layer 20, includes:
[0097] A pixel definition layer 40 is formed on a side of the anode layer 30 away from the planar layer 20;
[0098] A third via hole 42 is formed on the pixel definition layer 40. The third via hole 42 penetrates the pixel definition layer 40 from the surface of the pixel definition layer 40 away from the planar layer 20 toward the planar layer 20. The third via hole 42 corresponds to the position of the first via hole 31, so that the planar layer 20 is exposed at the third via hole 42.
[0099] The area of the planar layer 20 exposed by the third via hole 42 is etched to obtain the isolation groove 22 .
[0100] It can be understood that the pixel definition layer 40 is formed on the side of the anode layer 30 away from the flat layer 20 by evaporation to ensure that the pixel definition layer 40 covers the entire flat layer 20; then the pixel definition layer 40 is patterned and the exposed pixel definition layer 40 is etched to form a third via 42.
[0101] Among them, the pixel definition layer 40 is graphically designed according to the position of the first via hole 31 and the position of the pixel area, ensuring that the exposed area of the pixel definition layer 40 corresponds to the first via hole 31 and the pixel area respectively, so as to facilitate the opening of the third via hole 42 and the pixel opening area 41, ensuring that the third via hole 42 and the first via hole 31 are connected to expose the flat layer 20, and the third via hole 42 is located between two adjacent pixel areas.
[0102] In some embodiments, after forming the anode layer 30 on one side of the planar layer 20, the method further includes:
[0103] A second via hole 32 is opened in the anode layer 30, and the second via hole 32 penetrates the anode layer 30 from the surface of the anode layer 30 away from the flat layer 20 toward the flat layer 20, and the second via hole 32 is spaced apart from the first via hole 31, and the orthographic projection of the second via hole 32 on the substrate 10 does not overlap with the orthographic projection of the pixel area on the substrate 10.
[0104] The second via hole 32 and the first via hole 31 can be formed simultaneously, which simplifies the process and saves processing cost.
[0105] In this embodiment, the existence of the second via hole 32 is conducive to ensuring that the anode layer 30 corresponding to the isolation groove 22 area is disconnected from the anode layer 30 corresponding to the pixel area, which is further conducive to reliably ensuring low grayscale inter-pixel crosstalk.
[0106] In some embodiments, in actual processing, before forming the anode layer 30 on one side of the planar layer 20, the method further includes:
[0107] The overlapping holes 21 are formed in the planar layer 20 by using an exposure process.
[0108] The overlapping hole 21 in this embodiment is conducive to reliable electrical contact between the anode layer 30 and the auxiliary electrode 12, thereby ensuring reliable driving of the light-emitting layer to emit light.
[0109] For example, the manufacturing method of the display panel 100 is as follows:
[0110] like Figure 6 As shown, a flat layer 20 is prepared, and a lap hole 21 is formed in the flat layer 20 by using a film forming process;
[0111] like Figure 7 As shown, an anode layer 30 is formed on the flat layer 20, ensuring that the anode layer 30 forms an ohmic contact with the auxiliary electrode 12 through the overlapping hole 21, and the anode layer 30 is patterned according to the isolation groove 22 area, and a first via hole 31 and a second via hole 32 are etched on the anode, so that the flat layer 20 is exposed in the first via hole 31 and the second via hole 32;
[0112] like Figure 8 As shown, a pixel definition layer 40 is evaporated on the anode layer 30, and the pixel definition layer 40 is graphically designed, the pixel definition layer 40 covers the second via hole 32, and the exposed pixel definition layer 40 is etched to form a pixel opening area 41 and a third via hole 42, the third via hole 42 corresponds to the position of the first via hole 31, and the third via hole 42 is connected to the first via hole 31;
[0113] like Fig. 9 As shown, the planar layer 20 exposed in the third via hole 42 is etched to form an isolation trench 22 .
[0114] To sum up, the preparation method of the display panel of the present application does not need to add an additional passivation layer between the flat layer 20 and the anode layer 30. On the one hand, it simplifies the processing technology, facilitates processing, controls production costs, and is beneficial to improving production and processing efficiency; on the other hand, the overlapping hole 21 is directly formed in the exposure process of the flat layer 20, and there is no need to etch the passivation layer, thereby avoiding the generation of etching foreign matter in the overlapping hole 21, which is beneficial for the anode layer 30 to directly electrically contact the auxiliary electrode 12 through the overlapping hole 21, thereby ensuring the display effect, improving the display effect of the display panel, and thus improving the yield rate and product competitiveness of the display panel.
[0115] In a third aspect, the present invention provides a display device, comprising the display panel 100 of the first aspect or the display panel prepared according to the method of the second aspect. It is understandable that the display device has all the features and advantages of the above-mentioned display module, which will not be repeated here. In short, the display device has high quality and yield rate and good display effect.
[0116] The display device is a product with an image display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (PDA), a digital camera, a camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, a home appliance, an information query device (such as business query equipment of e-government, banks, hospitals, power and other departments), a monitor, etc. The display device may also be a microdisplay or a product containing a microdisplay. The product containing a microdisplay may be a smart watch, a smart bracelet, a helmet display, a stereo display mirror, and any of AR devices (such as AR glasses), VR devices (such as VR glasses), etc. For example, a microdisplay may be a display with a display size ranging from about 0.2 inches to about 2.5 inches, but is not limited thereto. It can be understood that the microdisplay may also be a display with a smaller display size, such as a display size less than or equal to 0.2 inches.
[0117] It should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like used above to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the panel or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "multiple" means two or more.
[0118] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in the present application.
Claims
1. A display panel, characterized in that: include: Flat layer; an anode layer, the anode layer being disposed on one side of the flat layer, and having a first via hole formed on the anode layer, the first via hole penetrating the anode layer from a surface of the anode layer away from the flat layer toward the flat layer, so that the flat layer is exposed at the first via hole; The planar layer is provided with an isolation groove, and the isolation groove is extended from the surface of the planar layer exposed from the first via hole toward the inside of the planar layer.
2. The display panel according to claim 1, characterized in that: The display panel includes a substrate, the substrate includes a plurality of pixel areas, and an orthographic projection of the first via hole on the substrate is located in a region between orthographic projections of two adjacent pixel areas on the substrate.
3. The display panel according to claim 1, characterized in that: In the isolation trench region, the planar layer is retracted relative to the anode layer along a direction parallel to the planar layer.
4. The display panel according to claim 3, characterized in that: The planar layer is recessed relative to the anode layer by more than or equal to 0.1 μm and less than or equal to 0.5 μm.
5. The display panel according to claim 1, characterized in that: In the extending direction of the isolation trench, the width of the isolation trench gradually decreases.
6. The display panel according to any one of claims 2 to 5, characterized in that: The anode layer is also provided with a second via hole, which penetrates the anode layer from the surface of the anode layer away from the flat layer toward the flat layer, and the second via hole is spaced apart from the first via hole, and the orthographic projection of the second via hole on the substrate does not overlap with the orthographic projection of the pixel area on the substrate.
7. The display panel according to any one of claims 2 to 5, characterized in that: The display panel also includes a pixel definition layer, which is arranged on the side of the anode layer away from the flat layer, and a third via hole is opened on the pixel definition layer, and the third via hole penetrates the pixel definition layer from the surface of the pixel definition layer away from the flat layer toward the flat layer, and the position of the third via hole corresponds to that of the first via hole, so that the flat layer is exposed to the third via hole.
8. The display panel according to claim 7, characterized in that: The pixel definition layer is further provided with a pixel opening area, the pixel opening area is arranged corresponding to the pixel area, and the opening area is arranged at an interval with the third via hole.
9. The display panel according to any one of claims 1 to 5, characterized in that: The substrate also includes an auxiliary electrode, the flat layer is provided with a lap hole, and the anode layer is in electrical contact with the auxiliary electrode through the lap hole.
10. A method for preparing a display panel, characterized in that: The method comprises the following steps: preparing a flat layer; An anode layer is formed on one side of the flat layer, and a first via hole is opened in the anode layer, wherein the first via hole penetrates the anode layer from a surface of the anode layer away from the flat layer toward the flat layer, so that the flat layer is exposed in the first via hole; An isolation groove is formed in the planar layer, and the isolation groove extends from a surface of the planar layer exposed from the first via hole toward the inside of the planar layer.
11. The method according to claim 10, characterized in that An isolation trench is formed in the planar layer, comprising: forming a pixel definition layer on a side of the anode layer facing away from the planar layer; A third via hole is formed on the pixel definition layer, wherein the third via hole penetrates the pixel definition layer from a surface of the pixel definition layer away from the planar layer toward the planar layer, and the position of the third via hole corresponds to that of the first via hole, so that the planar layer is exposed at the third via hole; The area of the planar layer exposed from the third via hole is etched to obtain the isolation groove.
12. The method according to claim 10, characterized in that After forming an anode layer on one side of the planar layer, the method further comprises: A second via hole is opened in the anode layer, and the second via hole penetrates the anode layer from the surface of the anode layer away from the flat layer toward the flat layer, and the second via hole is spaced apart from the first via hole, and the orthographic projection of the second via hole on the substrate does not overlap with the orthographic projection of the pixel area on the substrate.
13. The method according to claim 10, characterized in that Before forming an anode layer on one side of the planar layer, the method further includes: An exposure process is used to form overlapping holes in the flat layer.
14. A display device, characterized in that A display panel comprising the display panel according to any one of claims 1 to 9 or a display panel obtained according to the preparation method according to any one of claims 10 to 13.