Display panel and method for manufacturing display panel

Abstract

The invention provides a display panel and a method for manufacturing the same. The display panel includes: a base layer; a first electrode disposed on the base layer; a pixel defining film in which a light emitting opening partially exposing the first electrode is defined, and which is disposed on the base layer; a first conductive partition wall in which a first partition wall opening overlapping the light emitting opening in plan view is defined, the first conductive partition wall being disposed on the pixel defining film; a second conductive partition wall in which a second partition wall opening overlapping the first partition wall opening in plan view and a dummy opening overlapping the first conductive partition wall are defined, the second conductive partition wall being disposed on the first conductive partition wall; a second electrode disposed on the first electrode; and a light emitting pattern disposed between the first electrode and the second electrode.

Description

[0001] This application claims priority to and all benefits derived therefrom from Korean Patent Application No. 10-2023-0112149, filed on August 25, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure herein relates to a display panel and a method for manufacturing the same, and more particularly, to a display panel having improved processability and reliability and a method for manufacturing the same. Background Art

[0003] Multimedia electronic devices such as televisions, mobile phones, tablet computers, computers, navigation systems, and game consoles are provided with display panels for displaying images.

[0004] The display panel includes a light emitting element and a pixel circuit for driving the light emitting element. The light emitting element included in the display panel emits light according to a voltage applied by the pixel circuit and generates an image.

[0005] In order to improve the reliability of display panels, research is being conducted on methods for patterning light-emitting elements, and recently, research is also being conducted on methods for patterning light-emitting materials that are generally supplied using an opening mask as pixel units. Summary of the invention

[0006] The present disclosure provides a display panel with improved reliability.

[0007] The present disclosure also provides a method for manufacturing a display panel having improved processability and reliability.

[0008] An embodiment of the invention provides a display panel, which includes: a base layer; a first electrode, which is arranged on the base layer; a pixel defining film, in which a light-emitting opening partially exposing the first electrode is defined, and the pixel defining film is arranged on the base layer; a first conductive partition wall, in which a first partition wall opening overlapping with the light-emitting opening in a plan view is defined, and the first conductive partition wall is arranged on the pixel defining film; a second conductive partition wall, in which a second partition wall opening overlapping with the first partition wall opening in a plan view and a dummy opening overlapping with the first conductive partition wall are defined, and the second conductive partition wall is arranged on the first conductive partition wall; a second electrode, which is arranged on the first electrode; and a light-emitting pattern, which is arranged between the first electrode and the second electrode.

[0009] In an embodiment, the display panel may further include an inorganic lower encapsulation pattern disposed on the second electrode and covering the light emitting opening, the first partition wall opening, and the second partition wall opening.

[0010] In an embodiment, the display panel may further include an inorganic intermediate encapsulation film covering the upper surface of the dummy opening and the second conductive partition wall.

[0011] In an embodiment, an upper surface of the first conductive partition wall exposed by the dummy opening may be in contact with the inorganic intermediate encapsulation film.

[0012] In an embodiment, a side surface of the second conductive partition wall defining the second partition wall opening may contact the inorganic lower encapsulation pattern, and a side surface of the second conductive partition wall defining the dummy opening may contact the inorganic intermediate encapsulation film.

[0013] In an embodiment, a plurality of dummy openings may be provided.

[0014] In an embodiment, the first conductive partition wall may include a first lower layer disposed on the pixel defining film and a second lower layer disposed on the first lower layer, and a side surface of the second lower layer may protrude more than a side surface of the first lower layer in a plan view.

[0015] In an embodiment, the second conductive partition wall may include a first upper layer disposed on the first conductive partition wall and a second upper layer disposed on the first upper layer, and a side surface of the second upper layer may protrude more than a side surface of the first upper layer in a plan view.

[0016] In an embodiment, the second electrode may contact a side surface of the first conductive partition wall to be electrically connected to each other.

[0017] In an embodiment, a bias voltage may be applied to the first conductive partition wall.

[0018] In an embodiment, the display panel may further include an inorganic dummy encapsulation film covering the dummy opening.

[0019] In an embodiment, the display panel may further include a dummy pattern disposed on the first conductive partition wall in the dummy opening.

[0020] In embodiments, the dummy pattern may not contact the second conductive partition wall.

[0021] In an embodiment, a side surface of the second conductive partition wall defining the second partition wall opening may contact the inorganic lower encapsulation pattern, and a side surface of the second conductive partition wall defining the dummy opening may contact the inorganic dummy encapsulation film.

[0022] In an embodiment of the invention, a method for manufacturing a display panel includes: preparing a preliminary display panel, the preliminary display panel including a substrate layer, a first electrode disposed on the substrate layer, a preliminary pixel defining film covering the first electrode and disposed on the substrate layer, a first conductive layer disposed on the preliminary pixel defining film, and a second conductive layer disposed on the first conductive layer; patterning a photoresist on the preliminary display panel; forming a second preliminary partition wall opening in the second conductive layer; forming a first preliminary conductive partition wall by forming a first preliminary partition wall opening overlapping the second preliminary partition wall opening in a plan view in the first conductive layer; forming a first preliminary conductive partition wall by forming a first preliminary partition wall opening overlapping the second preliminary partition wall opening in the second conductive layer; A second preliminary conductive partition wall is formed by forming a preliminary dummy opening separated by a partition opening; a light-emitting pattern is formed on the first electrode; and a second electrode is formed on the light-emitting pattern, wherein, in the step of patterning the photoresist, the photoresist is patterned to have a first thickness in the first region, the first region neither overlaps with the second preliminary partition wall opening nor the preliminary dummy opening in a plan view, the photoresist is patterned to have a second thickness smaller than the first thickness in the second region, the second region overlaps with the preliminary dummy opening in a plan view, and the photoresist is patterned to not be arranged in a third region, the third region overlaps with the second preliminary partition wall opening in a plan view.

[0023] In an embodiment, the step of forming a second preliminary partition wall opening may include forming a second conductive layer corresponding to the third region by dry etching, the step of forming a second preliminary conductive partition wall may include removing the photoresist corresponding to the second region by ashing the photoresist, and dry etching the second conductive layer corresponding to the second region, and the step of forming a first preliminary conductive partition wall may include dry etching the first conductive layer corresponding to the third region.

[0024] In an embodiment, the method may further include forming a first conductive partition wall defining a first partition wall opening and a second conductive partition wall defining a second partition wall opening by wet etching side surfaces of the first preliminary conductive partition wall and the second preliminary conductive partition wall, wherein the first preliminary conductive partition wall may include a first preliminary lower layer disposed on a preliminary pixel defining film and a second preliminary lower layer disposed on the first preliminary lower layer, the second preliminary conductive partition wall may include a first preliminary upper layer and a second preliminary upper layer disposed on the first preliminary upper layer, the etching rate of the first preliminary lower layer may be greater than the etching rate of the second preliminary lower layer, and the etching rate of the first preliminary upper layer may be greater than the etching rate of the second preliminary upper layer.

[0025] In an embodiment, the method may further include forming a pixel defining film having a light emitting opening defined therein by dry etching the preliminary pixel defining film corresponding to the first partition wall opening.

[0026] In an embodiment, the method may further include forming an inorganic lower encapsulation pattern on the second electrode covering the light emitting opening, the first partition wall opening, and the second partition wall opening.

[0027] In an embodiment, the method may further include forming an inorganic intermediate encapsulation film covering upper surfaces of the dummy opening and the second conductive partition wall. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings: Figure 1A is a combined perspective view of a display device according to an embodiment of the invention; Figure 1B is an exploded perspective view of a display device according to an embodiment of the invention; Figure 2 is a cross-sectional view of a display module according to an embodiment of the invention; Figure 3 is a plan view of a display panel according to an embodiment of the invention; Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment of the invention; Figure 5 is a cross-sectional view of a display panel according to an embodiment of the invention; Figure 6 is a cross-sectional view of a display panel according to an embodiment of the invention; Figure 7 is a flow chart of a method for manufacturing a display panel according to an embodiment of the invention; and FIG. 8A to FIG. 16B are cross-sectional views respectively illustrating operations of a method for manufacturing a display panel according to an embodiment of the invention. DETAILED DESCRIPTION

[0029] In the invention, various modifications can be made and various forms can be applied, and specific embodiments will be shown in the drawings and described in detail in the text. However, it should be understood that this is not intended to limit the invention to a specific disclosed form, but is intended to cover all modifications, equivalents and substitutes included in the spirit and scope of the invention.

[0030] In this specification, when a component (or region, layer, part, etc.) is referred to as being "on" another component, "connected to" or "coupled to" another component, it means that the component (or region, layer, part, etc.) can be directly placed / directly connected / directly coupled to the other component, or a third component can be set between the component (or region, layer, part, etc.) and the other component.

[0031] Meanwhile, in the present application, “directly disposed” may mean that a layer, film, region, plate, etc. is not added between a part such as a layer, film, region, or plate and another part. For example, “directly disposed” may mean placing two layers or two members without using an additional member such as an adhesive member therebetween.

[0032] The same reference numerals or symbols refer to the same elements. In addition, in the drawings, the thickness, proportion and size of components are exaggerated for effective description of technical contents.

[0033] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, "one", "one (kind / person)", "the (said)" and "at least one (kind / person)" do not represent quantitative limitations and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" is not interpreted as being limited to "one" or "one (kind / person)". "Or" means "and / or". "And / or" includes all combinations of one or more that can be limited by the relevant elements.

[0034] Terms such as "first" and "second" can be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component. Unless the context clearly indicates otherwise, a singular form includes a plural form.

[0035] In addition, terms such as “below,” “under,” “above,” and “on” are used to describe the relationship between components shown in the drawings. The terms are relative concepts and are described based on the directions indicated in the drawings.

[0036] It should be understood that terms such as “include” or “have” are intended to indicate the presence of the features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, and do not exclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof.

[0037] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those generally understood by ordinary technicians in the field to which the present invention belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having the same meaning as that in the context of the relevant technology, and should not be interpreted as being too idealistic or too formal.

[0038] Hereinafter, embodiments of the invention will be described with reference to the accompanying drawings.

[0039] Figure 1A is an assembled perspective view of a display device DD according to an embodiment of the invention. Figure 1B is an exploded perspective view of a display device DD according to an embodiment of the invention. Figure 2 is a cross-sectional view of a display module DM according to an embodiment of the invention.

[0040] The display device DD according to the embodiment may be a large electronic device such as a television, a monitor, and a billboard. In addition, the display device DD may be a small or medium-sized electronic device such as a personal computer, a notebook computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet computer, and a camera. These are only proposed as embodiments, and other display devices may be adopted as embodiments as long as they do not deviate from the concept of the invention. In this embodiment, a smart phone is shown as an example of the display device DD.

[0041] Reference Figure 1A , the display device DD may display an image IM toward a third direction DR3 on a display surface FS parallel to each of the first direction DR1 and the second direction DR2. The image IM may include a static image and a dynamic image. Figure 1A , showing an example of an image IM in FIG. 4 , a clock window and an icon are shown. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0042] In the present embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each member are defined relative to the direction in which the image IM is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. Meanwhile, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be changed to other directions. In the present disclosure, the term "on a plane" may mean when viewed in the third direction DR3 (i.e., in a plan view).

[0043] Reference Figure 1B , the display device DD according to the embodiment may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be combined with each other to constitute the exterior of the display device DD.

[0044] The window WP may include an optically transparent insulating material. In an embodiment, for example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD.

[0045] The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. In an embodiment, for example, the transmission area TA may have a visible light transmittance of about 90% or more. The frame area BZA may have a relatively lower light transmittance than the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and may surround the transmission area TA. At the same time, this is shown as an example, and in the window WP according to an embodiment of the invention, the frame area BZA may be omitted. The window WP may also include at least any one functional layer among an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to any one embodiment.

[0046] The display module DM may be disposed below the window WP. The display module DM may be a substantially image generating module IM (see Figure 1A ) is constructed. The image IM generated by the display module DM (see Figure 1A ) may be displayed on the display surface IS of the display module DM and may be viewed by an external user through the transmissive area TA.

[0047] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be activated in response to an electrical signal. The non-display area NDA is adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be covered by the frame area BZA and cannot be viewed from the outside.

[0048] Reference Figure 2 The display module DM according to the present embodiment may include a display panel DP and an input sensor INS. Although not shown separately, the display module DM according to the embodiment of the invention may further include a protection member disposed under the display panel DP or an anti-reflection member disposed on the input sensor INS.

[0049] The display panel DP may be a light-emitting display panel, but is not particularly limited thereto. In an embodiment, for example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0050] The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be directly disposed on the thin film encapsulation layer TFE.

[0051] The base layer BL may be a member that provides a base surface on which the circuit element layer DP-CL is disposed. The base layer BL may be a rigid base or a flexible base that is bendable, foldable, or rollable. The base layer BL may be a glass base, a metal base, a polymer base, etc. However, the embodiments of the invention are not limited thereto, and the base layer BL may be an inorganic layer, an organic layer, or a composite material layer.

[0052] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, etc. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base layer BL in a manner such as coating or deposition, and then the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by performing a photolithography process and an etching process multiple times. Then, the semiconductor pattern, the conductive pattern, and the signal line included in the circuit element layer DP-CL may be formed.

[0053] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element. In an embodiment, for example, the light emitting element may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro LED, or a nano LED.

[0054] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the display element layer DP-OLED from foreign matter such as moisture, oxygen, and dust particles.

[0055] The input sensor INS may be provided on the display panel DP. The input sensor INS may sense an external input applied from the outside. The external input may be an input of a user. The user's input may include various forms of external inputs such as a part of the user's body, light, heat, a pen, or pressure. In an embodiment, for example, the input sensor INS may sense the external input in a capacitive manner. The operation mode of the input sensor INS according to the invention is not particularly limited thereto, and the input sensor INS may sense the external input in an electromagnetic induction manner or a pressure sensing manner.

[0056] The input sensor INS may be formed on the display panel DP by a continuous process. In this case, the input sensor INS may be directly disposed on the display panel DP. That is, a separate adhesive member may not be disposed between the input sensor INS and the display panel DP. In an embodiment, for example, the input sensor INS may be directly disposed on the thin film encapsulation layer TFE of the display panel DP. Alternatively, the input sensor INS may be bonded to the display panel DP by an adhesive member. The adhesive member may include a typical adhesive or bonding agent.

[0057] The input sensor INS may have a multi-layer structure. The input sensor INS may include a single layer or multiple layers of conductive layers. The input sensor INS may include a single layer or multiple layers of insulating layers.

[0058] An optical layer (not shown) may be further provided on the input sensor INS. The optical layer may be directly provided on the input sensor INS. The optical layer may be formed on the input sensor INS by a continuous process. The optical layer may reduce the reflectivity of external light incident from the outside. The optical layer may include a polarizing layer or a color filter layer.

[0059] In an embodiment, the input sensor INS may be omitted, and the optical layer may be directly disposed on the display panel DP. In an embodiment, a position of the input sensor INS and a position of the optical layer may be changed from each other.

[0060] Refer again Figure 1B The housing HAU may be coupled to the window WP to provide a predetermined inner space. The display module DM may be accommodated in the inner space.

[0061] The housing HAU may include a relatively rigid material. In an embodiment, for example, the housing HAU may include a plurality of frames and / or plates including glass, plastic, or metal or a combination thereof. The housing HAU may stably protect the structure of the display device DD accommodated in the internal space from external impact.

[0062] Figure 3 is a plan view of a display panel DP according to an embodiment of the invention.

[0063] Reference Figure 3 The display panel DP may include a base layer BL, the base layer BL is divided into reference Figure 2 Described is a display area DA and a non-display area NDA.

[0064] The display panel DP may include pixels PX disposed in the display area DA and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a driving circuit GDC and a pad portion PLD disposed in the non-display area NDA.

[0065] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0066] The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. The gate line GL may be connected to corresponding pixels among the pixels PX, respectively, and the data line DL may be connected to corresponding pixels among the pixels PX, respectively. The power line PL may be electrically connected to the pixel PX. The control signal line CSL may be connected to the drive circuit GDC to supply a control signal to the drive circuit GDC.

[0067] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and may sequentially output the generated signal to the gate lines GL. The gate driving circuit may also output another control signal to the pixel driving circuit.

[0068] The pad part PLD may be a part for connecting a flexible circuit board. The pad part PLD may include a pixel pad D-PD, and the pixel pad D-PD may connect the flexible circuit board to the display panel DP. Each of the pixel pads D-PD may be connected to a corresponding signal line SGL among the signal lines SGL. The pixel pads D-PD may be connected to corresponding pixels PX through the signal lines SGL, respectively. In addition, one of the pixel pads D-PD may be connected to the drive circuit GDC.

[0069] In addition, the pad part PLD may further include an input pad. The input pad may connect the flexible circuit board to the input sensor INS (see Figure 2 However, the embodiment of the invention is not limited thereto, and the input pad may be provided on the input sensor INS (see Figure 2 ) to be connected to a circuit board separate from the pixel pad D-PD. Optionally, the input sensor INS can be omitted (see Figure 2 ), and may not further include an input pad.

[0070] Figure 4 is an enlarged plan view of a portion of a display area DA of a display panel DP according to an embodiment of the invention.

[0071] Figure 4 shows the display surface IS (see Figure 1B ) on the display module DM (see Figure 1B ) plane and the arrangement of the light-emitting areas PXA-R, PXA-G and PXA-B.

[0072] Reference Figure 4, the display area DA may include a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B and a peripheral area NPXA surrounding the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B. The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may be connected to the light emitting elements ED1, ED2, and ED3 (see FIG. Figure 5 ) corresponds to the area of ​​light supplied. The first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B can be directed toward the display module DM (see Figure 1B ) is divided by the color of the externally emitted light.

[0073] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may respectively provide first color light, second color light, and third color light having different colors. In an embodiment, for example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the examples of the first color light, the second color light, and the third color light are not necessarily limited to this example.

[0074] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be defined as regions in which the first electrodes AE1, AE2, and AE3 (see FIG. Figure 5 ) through the upper surface of the light-emitting openings OP1-E, OP2-E and OP3-E (see Figure 5 The peripheral area NPXA may set the boundaries of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B, and may prevent color mixing between the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B.

[0075] Each of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B is provided in plural and repeatedly provided in the display area DA in a predetermined arrangement manner. In an embodiment, for example, the first light emitting region PXA-R and the third light emitting region PXA-B may be alternately arranged along the first direction DR1 to constitute a "first group". The second light emitting region PXA-G may be arranged along the first direction DR1 to constitute a "second group". Each of the "first group" and the "second group" may be provided in plural, and the "first group" and the "second group" may be alternately arranged along the second direction DR2.

[0076] One second light emitting region PXA-G may be disposed to be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0077] at the same time, Figure 4 The arrangement form of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B is exemplarily shown, but the embodiments of the invention are not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be arranged in various forms. In an embodiment, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a configuration as follows: Figure 4 PENTILE shown in ® Optionally, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a stripe arrangement or a diamond pixel arrangement. ® Layout form.

[0078] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have various shapes on a plane. In an embodiment, for example, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have a shape such as a polygon, a circle, or an ellipse. Figure 4 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a rhombus shape) on a plane and the second light emitting region PXA-G having an octagonal shape are exemplarily illustrated.

[0079] The first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same shape as each other on a plane, or at least a portion of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have shapes different from each other on a plane. Figure 4 The first and third light emitting regions PXA-R and PXA-B having the same shape as each other and the second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-R and PXA-B are exemplarily shown.

[0080] At least a portion of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have different areas on a plane. In an embodiment, the area of ​​the first light emitting region PXA-R emitting red light may be larger than the area of ​​the second light emitting region PXA-G emitting green light, and may be smaller than the area of ​​the third light emitting region PXA-B emitting blue light. However, the size relationship between the areas of the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B according to the color of the light emitted therefrom is not limited thereto, and may be selected according to the display module DM (see Figure 1B In addition, the embodiment of the invention is not limited thereto, and the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same area as each other on a plane.

[0081] According to the display module DM (see Figure 1B The shapes, areas, arrangements, etc. of the first light emitting regions PXA-R, the second light emitting regions PXA-G, and the third light emitting regions PXA-B may be determined according to the color of the emitted light or the display module DM (see Figure 1B ) are designed differently in size and configuration and are not limited to Figure 4 The embodiment shown in .

[0082] According to the invention, the dummy opening OP-DM may be disposed between the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B. The dummy opening OP-DM may refer to a portion of the conductive partition wall PW1 (see FIG. 1 ) described later. Figure 5 ) is formed by a second conductive partition wall PW2 (see Figure 5 The dummy opening OP-DM may be disposed in the peripheral area NPXA between the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B.

[0083] Figure 4 The dummy openings OP-DM are shown to have an integral shape connected to each other on a plane, but the embodiments of the invention are not limited thereto. Figure 4 Unlike that shown in , the dummy openings OP-DM may be provided in a plurality of shapes independent of each other to be spaced apart from each other. In an embodiment, for example, a plurality of dummy openings OP-DM may be provided between the first light emitting region PXA-R and the second light emitting region PXA-G and between the second light emitting region PXA-G and the third light emitting region PXA-B, respectively.

[0084] in addition, Figure 4 It is shown that one dummy opening OP-DM is disposed between adjacent light emitting regions PXA-R, PXA-G, and PXA-B, but the embodiments of the invention are not limited thereto. Figure 4 Unlike what is shown in FIG. 2 , two or more dummy openings OP-DM may be disposed between adjacent light emitting regions PXA-R, PXA-G, and PXA-B.

[0085] Figure 5 is a cross-sectional view of a display panel DP according to an embodiment of the invention. Figure 5 It is along Figure 4 An embodiment of a cross section taken along line II' in FIG.

[0086] Reference Figure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0087] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed in a manner such as coating or deposition. Then, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. In this manner, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0088] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer, a transistor, a signal transmission region, a plurality of insulating layers, and a plurality of connection electrodes.

[0089] The buffer layer may be disposed on the base layer BL. The buffer layer may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0090] The semiconductor pattern may be disposed on the buffer layer. The semiconductor pattern may include polycrystalline silicon. However, the embodiments of the invention are not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. The semiconductor pattern may be arranged for a plurality of light emitting regions in a specific rule. The semiconductor pattern may have different electrical properties depending on whether it is doped. The semiconductor pattern may include a first region having a large doping concentration and a second region having a small doping concentration. The first region may be doped with an n-type dopant or a p-type dopant. The p-type transistor may include a first region doped with a p-type dopant.

[0091] The first region has a greater conductive property than the second region and is basically used as an electrode or a signal line. The second region can basically correspond to the active electrode (or channel) of the transistor. In other words, a part of the semiconductor pattern can be the active electrode of the transistor, another part of the semiconductor pattern can be the source or drain, and another part of the semiconductor pattern can be a conductive region. The source, active electrode and drain of the transistor can be formed by the semiconductor pattern.

[0092] A plurality of insulating layers may be disposed on the buffer layer. The plurality of insulating layers may each be an inorganic layer or an organic layer.

[0093] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include light emitting elements ED1, ED2, and ED3, a pixel defining layer PDL, a first conductive partition wall PW1, and a second conductive partition wall PW2.

[0094] The light emitting elements ED1 , ED2 , and ED3 may include first electrodes AE1 , AE2 , and AE3 , light emitting patterns EP1 , EP2 , and EP3 , and second electrodes CE1 , CE2 , and CE3 , respectively.

[0095] The light emitting element ED1 disposed in the first light emitting region PXA-R may be referred to as a first light emitting element. The light emitting element ED2 disposed in the second light emitting region PXA-G may be referred to as a second light emitting element. The light emitting element ED3 disposed in the third light emitting region PXA-B may be referred to as a third light emitting element.

[0096] The first electrodes AE1, AE2, and AE3 may be disposed on the circuit element layer DP-CL. The first electrodes AE1, AE2, and AE3 may be anodes. The first electrodes AE1, AE2, and AE3 may be transmissive electrodes, semi-transmissive electrodes, or reflective electrodes. The first electrodes AE1, AE2, and AE3 may have conductive properties. In an embodiment, for example, the first electrodes AE1, AE2, and AE3 may be formed of various materials having conductive properties such as metal, transparent conductive oxide (TCO), or conductive polymer materials.

[0097] The first electrodes AE1 , AE2 , and AE3 may be electrically connected to the signal transmission region through connection electrodes (not shown), respectively, and thus may be electrically connected to corresponding circuit elements.

[0098] The display panel DP may further include sacrificial patterns SP1, SP2, and SP3. The sacrificial patterns SP1, SP2, and SP3 may be disposed on upper surfaces of the first electrodes AE1, AE2, and AE3, respectively. Sacrificial openings OP1-S, OP2-S, and OP3-S partially exposing upper surfaces of the first electrodes AE1, AE2, and AE3 may be defined in the sacrificial patterns SP1, SP2, and SP3. The sacrificial patterns SP1, SP2, and SP3 may include an amorphous transparent conductive oxide.

[0099] The pixel defining film PDL may be disposed on the circuit element layer DP-CL. Light emitting openings OP1-E, OP2-E, and OP3-E may be defined in the pixel defining film PDL. In a plan view, the light emitting openings OP1-E, OP2-E, and OP3-E may overlap with the first electrodes AE1, AE2, and AE3, respectively, and the pixel defining film PDL may expose at least a portion of the first electrodes AE1, AE2, and AE3 through the light emitting openings OP1-E, OP2-E, and OP3-E.

[0100] In a plan view, the light emitting openings OP1-E, OP2-E, and OP3-E may overlap the sacrificial openings OP1-S, OP2-S, and OP3-S defined by the sacrificial patterns SP1, SP2, and SP3, respectively. The upper surfaces of the first electrodes AE1, AE2, and AE3 may be spaced apart from the pixel defining film PDL in cross section, and the sacrificial patterns SP1, SP2, and SP3 are between the upper surfaces of the first electrodes AE1, AE2, and AE3 and the pixel defining film PDL, and thus the first electrodes AE1, AE2, and AE3 may be protected from damage in the process of forming the light emitting openings OP1-E, OP2-E, and OP3-E.

[0101] In a plane, the areas of the light-emitting openings OP1-E, OP2-E, and OP3-E may be smaller than the areas of the sacrificial openings OP1-S, OP2-S, and OP3-S, respectively. That is, the inner side surfaces of the pixel defining film PDL defining the light-emitting openings OP1-E, OP2-E, and OP3-E may be respectively adjacent to the centers of the first electrodes AE1, AE2, and AE3 than the inner side surfaces of the sacrificial patterns SP1, SP2, and SP3 defining the sacrificial openings OP1-S, OP2-S, and OP3-S. However, the embodiments of the invention are not limited thereto, and the inner side surfaces of the sacrificial patterns SP1, SP2, and SP3 defining the sacrificial openings OP1-S, OP2-S, and OP3-S may be substantially aligned with the inner side surfaces of the pixel defining film PDL defining the light-emitting openings OP1-E, OP2-E, and OP3-E, respectively. In this case, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may be regions of the first electrodes AE1, AE2, and AE3 exposed from the sacrificial openings OP1-S, OP2-S, and OP3-S corresponding to the first electrodes AE1, AE2, and AE3. The sacrificial patterns SP1, SP2, and SP3 may be omitted.

[0102] The pixel definition film PDL may include an inorganic insulating material. In an embodiment, for example, the pixel definition film PDL may include silicon nitride (SiN x ). The pixel defining film PDL may be disposed between the first electrodes AE1, AE2, and AE3 and the first conductive partition wall PW1, and thus may block the first electrodes AE1, AE2, and AE3 and the first conductive partition wall PW1 from being electrically connected to each other.

[0103] The first conductive partition wall PW1 may be disposed on the pixel definition film PDL. The first partition wall openings OP1-P1, OP2-P1, and OP3-P1 may be defined in the first conductive partition wall PW1. In a plan view, the first partition wall openings OP1-P1, OP2-P1, and OP3-P1 may overlap with the light emitting openings OP1-E, OP2-E, and OP3-E, respectively, and may expose at least a portion of the first electrodes AE1, AE2, and AE3.

[0104] The first conductive partition wall PW1 may have an undercut shape in cross section. The first conductive partition wall PW1 may include a plurality of layers stacked sequentially, and at least one of the plurality of layers may be relatively recessed than an adjacent stacked layer. Therefore, the first conductive partition wall PW1 may include a tip portion. The tip portion of the first conductive partition wall PW1 may be defined as a first tip portion.

[0105] The first conductive partition wall PW1 may include a first lower layer L1a and a second lower layer L2a. The first lower layer L1a may be disposed on the pixel definition film PDL, and the second lower layer L2a may be disposed on the first lower layer L1a. The first lower layer L1a may have a first conductive property, and the second lower layer L2a may have a second conductive property that is smaller than the first conductive property. The thickness of the first lower layer L1a may be greater than the thickness of the second lower layer L2a.

[0106] In the light emitting regions PXA-R, PXA-G, and PXA-B, the first lower layer L1a may be relatively recessed than the second lower layer L2a. In the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B, the second lower layer L2a may be relatively protruding than the first lower layer L1a. That is, the first lower layer L1a may be formed to have an undercut shape relative to the second lower layer L2a. A portion of the second lower layer L2a protruding from the first lower layer L1a toward the light emitting regions PXA-R, PXA-G, and PXA-B may correspond to the above-mentioned first tip portion.

[0107] The first partition wall opening OP1-P1 defined in the first conductive partition wall PW1 may include a first lower inner surface S1-Pa and a second lower inner surface S2-Pa sequentially arranged in the third direction DR3. The first lower inner surface S1-Pa may be an inner surface of the first lower layer L1a, and the second lower inner surface S2-Pa may be an inner surface of the second lower layer L2a. The first lower inner surface S1-Pa and the second lower inner surface S2-Pa may be equally included in the first partition wall openings OP2-P1 and OP3-P1 corresponding to the second light emitting region PXA-G and the third light emitting region PXA-B.

[0108] The first lower inner surface S1-Pa of the first lower layer L1a may be disposed to be concave in a direction farther from the first light emitting region PXA-R than the second lower inner surface S2-Pa of the second lower layer L2a. That is, the first lower inner surface S1-Pa may be formed to have an undercut shape relative to the second lower inner surface S2-Pa.

[0109] The first lower layer L1a and the second lower layer L2a may each include a conductive material. The first lower layer L1a may include a metal. In an embodiment, for example, the first lower layer L1a may include aluminum (Al). However, the material of the first lower layer L1a is not limited thereto. The second lower layer L2a may include a metal. In an embodiment, for example, the second lower layer L2a may include titanium (Ti).

[0110] Figure 5It is exemplarily shown that the first lower inner surface S1 -Pa and the second lower inner surface S2 -Pa are each orthogonal to the upper surface of the pixel defining film PDL, but the embodiments of the invention are not limited thereto. The first conductive partition wall PW1 may have a tapered shape or an inverse tapered shape.

[0111] The light emitting patterns EP1, EP2 and EP3 may be disposed on the first electrodes AE1, AE2 and AE3. The light emitting patterns EP1, EP2 and EP3 may be patterned by a first tip portion defined in the first conductive partition wall PW1. The light emitting patterns EP1, EP2 and EP3 may be disposed in the light emitting openings OP1-E, OP2-E and OP3-E and the first partition wall openings OP1-P1, OP2-P1 and OP3-P1. In an embodiment including sacrificial patterns SP1, SP2 and SP3, the light emitting patterns EP1, EP2 and EP3 may also be disposed in the sacrificial openings OP1-S, OP2-S and OP3-S. The light emitting patterns EP1, EP2 and EP3 may partially cover the upper surface of the pixel defining film PDL exposed from the first partition wall openings OP1-P1, OP2-P1 and OP3-P1.

[0112] The light emitting patterns EP1, EP2, and EP3 may each include a light emitting layer including a light emitting material. The light emitting patterns EP1, EP2, and EP3 may each include a hole injection layer (HIL) and / or a hole transport layer (HTL) disposed between the first electrodes AE1, AE2, and AE3 and the light emitting layer, and may each include an electron transport layer (ETL) and / or an electron injection layer (EIL) disposed on the light emitting layer. The light emitting patterns EP1, EP2, and EP3 may each be referred to as an “organic layer” or an “intermediate layer”.

[0113] The second electrodes CE1, CE2, and CE3 may be disposed on the light emitting patterns EP1, EP2, and EP3, respectively. The second electrodes CE1, CE2, and CE3 may be cathodes. The second electrodes CE1, CE2, and CE3 may be patterned by a first tip portion defined in the first conductive partition wall PW1. The second electrodes CE1, CE2, and CE3 may be disposed in the first partition wall openings OP1-P1, OP2-P1, and OP3-P1, respectively. Figure 5 Differently, the second electrodes CE1, CE2, and CE3 may also be partially disposed in the light emitting openings OP1-E, OP2-E, and OP3-E according to the thickness of the light emitting patterns EP1, EP2, and EP3 or the thickness of the pixel defining film PDL.

[0114] The second electrodes CE1, CE2 and CE3 may be in contact with the first lower inner surface S1-Pa of the first lower layer L1a. The second electrodes CE1, CE2 and CE3 may have conductive properties. In an embodiment, for example, the second electrodes CE1, CE2 and CE3 may be formed of various materials having conductive properties such as metal, transparent conductive oxide (TCO) or conductive polymer material.

[0115] In the present embodiment, the first conductive partition wall PW1 may receive a bias voltage. The second electrodes CE1, CE2, and CE3 may each be electrically connected to the first conductive partition wall PW1, and thus may be supplied with a bias voltage.

[0116] Figure 5 The light emitting patterns EP1, EP2, and EP3 are exemplarily shown not to contact the first lower inner surface S1-Pa of the first lower layer L1a, but the embodiments of the invention are not limited thereto. Not only the second electrodes CE1, CE2, and CE3 but also the light emitting patterns EP1, EP2, and EP3 may be formed to contact the first lower inner surface S1-Pa of the first lower layer L1a.

[0117] The display panel DP may further include cover patterns CP1, CP2, and CP3. The cover patterns CP1, CP2, and CP3 may be disposed on the second electrodes CE1, CE2, and CE3 and in the first partition wall openings OP1-P1, OP2-P1, and OP3-P1, respectively. The cover patterns CP1, CP2, and CP3 may be patterned by a first tip portion formed in the first conductive partition wall PW1.

[0118] Figure 5 It is exemplarily shown that the covering patterns CP1, CP2 and CP3 do not contact the first lower inner surface S1-Pa of the first lower layer L1a, but the embodiments of the invention are not limited thereto. The covering patterns CP1, CP2 and CP3 may be formed to contact the first lower inner surface S1-Pa of the first lower layer L1a. In an embodiment, the covering patterns CP1, CP2 and CP3 may be omitted.

[0119] The second conductive partition wall PW2 may be disposed on the first conductive partition wall PW1. The second partition wall openings OP1-P2, OP2-P2, and OP3-P2 and the dummy openings OP-DM may be defined in the second conductive partition wall PW2.

[0120] In a plan view, the second partition wall openings OP1-P2, OP2-P2, and OP3-P2 may overlap the light emitting openings OP1-E, OP2-E, and OP3-E and the first partition wall openings OP1-P1, OP2-P1, and OP3-P1, respectively, and may expose at least a portion of the first electrodes AE1, AE2, and AE3.

[0121] The second conductive partition wall PW2 may have an undercut shape in cross section. The second conductive partition wall PW2 may include a plurality of layers stacked in sequence, and at least one of the plurality of layers may be relatively recessed than an adjacent stacked layer. Therefore, the second conductive partition wall PW2 may include a tip portion. The tip portion of the second conductive partition wall PW2 may be defined as a second tip portion.

[0122] The second conductive partition wall PW2 may include a first upper layer L1b and a second upper layer L2b. The first upper layer L1b may be disposed on the first conductive partition wall PW1, and the second upper layer L2b may be disposed on the first upper layer L1b. The thickness of the first upper layer L1b may be greater than that of the second upper layer L2b.

[0123] In the present embodiment, the first upper layer L1b may be relatively recessed relative to the light emitting regions PXA-R, PXA-G, and PXA-B than the second upper layer L2b. The second upper layer L2b may be relatively protruding relative to the light emitting regions PXA-R, PXA-G, and PXA-B than the first upper layer L1b. That is, the first upper layer L1b may be formed to have an undercut shape relative to the second upper layer L2b. A portion of the second upper layer L2b protruding from the first upper layer L1b toward the light emitting regions PXA-R, PXA-G, and PXA-B may correspond to the above-mentioned second tip portion.

[0124] The second partition wall opening OP1-P2 defined in the second conductive partition wall PW2 may include a first upper inner surface S1-Pb and a second upper inner surface S2-Pb sequentially arranged in the third direction DR3. The first upper inner surface S1-Pb may be an inner surface of the first upper layer L1b, and the second upper inner surface S2-Pb may be an inner surface of the second upper layer L2b. The first upper inner surface S1-Pb and the second upper inner surface S2-Pb may be equally included in the second partition wall openings OP2-P2 and OP3-P2 corresponding to the second light emitting region PXA-G and the third light emitting region PXA-B.

[0125] The first upper inner surface S1-Pb of the first upper layer L1b may be disposed to be relatively recessed in a direction away from the first light emitting region PXA-R than the second upper inner surface S2-Pb of the second upper layer L2b. That is, the first upper inner surface S1-Pb may be formed to have an undercut shape relative to the second upper inner surface S2-Pb.

[0126] The first upper layer L1b and the second upper layer L2b may each include a conductive material. The first upper layer L1b may include a metal. In an embodiment, for example, the first upper layer L1b may include aluminum (Al), but the material of the first upper layer L1b is not limited thereto. The second upper layer L2b may include a metal. In an embodiment, for example, the second upper layer L2b may include titanium (Ti).

[0127] Figure 5 The first upper inner surface S1 -Pb and the second upper inner surface S2 -Pb are exemplarily shown to be orthogonal to the upper surface of the pixel defining film PDL, but the embodiments of the invention are not limited thereto. The second conductive partition wall PW2 may have a tapered shape or an inverse tapered shape.

[0128] The second conductive partition wall PW2 may define a dummy opening OP-DM in the peripheral area NPXA. The dummy opening OP-DM may be defined by a side surface of the second conductive partition wall PW2 and an upper surface of the first conductive partition wall PW1. That is, a side surface S-DM of the dummy opening OP-DM may correspond to one of the side surfaces of the second conductive partition wall PW2, and a bottom surface B-DM of the dummy opening OP-DM may partially correspond to an upper surface of the first conductive partition wall PW1.

[0129] The second conductive partition wall PW2 may expose at least a portion of an upper surface of the first conductive partition wall PW1 in the peripheral area NPXA through the dummy opening OP-DM.

[0130] like Figure 4 and Figure 5 As shown in FIG. 1 , the second conductive partition wall PW2 may be a plurality of partition walls separated by the dummy openings OP-DM so as to be arranged to be spaced apart from each other. Figure 4 As described above, the dummy opening OP-DM may be provided in plurality to have a shape in which the dummy openings OP-DM are spaced apart from each other, in which case the second conductive partition wall PW2 may be an integral partition wall defining the plurality of dummy openings OP-DM.

[0131] In addition, if Figure 4 and Figure 5 As shown in , one dummy opening OP-DM may be provided between adjacent light emitting regions PXA-R, PXA-G, and PXA-B. Figure 4 As described in, two or more dummy openings OP-DM may be disposed between adjacent light emitting regions PXA-R, PXA-G, and PXA-B. In an embodiment, for example, when viewed in cross section, three second conductive partition walls PW2 may be disposed between the light emitting regions PXA-R, PXA-G, and PXA-B, and two dummy openings OP-DM may be defined between the light emitting regions PXA-R, PXA-G, and PXA-B.

[0132] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include an inorganic lower encapsulation pattern LIL (or inorganic pattern), an organic encapsulation film OL, and an inorganic upper encapsulation film UIL. The thin film encapsulation layer TFE may also include an inorganic intermediate encapsulation film MIL.

[0133] The inorganic lower encapsulation pattern LIL may cover the light emitting element ED. Specifically, the inorganic lower encapsulation pattern LIL may be disposed on the second electrodes CE1, CE2, and CE3 to cover the second electrodes CE1, CE2, and CE3 together with the cover patterns CP1, CP2, and CP3 disposed on the second electrodes CE1, CE2, and CE3.

[0134] The inorganic lower encapsulation pattern LIL may be referred to as an inorganic lower encapsulation film. The inorganic lower encapsulation pattern LIL may include a first inorganic lower encapsulation pattern LIL1 disposed corresponding to the first light emitting region PXA-R, a second inorganic lower encapsulation pattern LIL2 disposed corresponding to the second light emitting region PXA-G, and a third inorganic lower encapsulation pattern LIL3 disposed corresponding to the third light emitting region PXA-B.

[0135] A portion of the inorganic lower encapsulation pattern LIL may be disposed in the light emitting openings OP1-E, OP2-E, and OP3-E, the first partition wall openings OP1-P1, OP2-P1, and OP3-P1, and the second partition wall openings OP1-P2, OP2-P2, and OP3-P2. Depending on the thickness of the light emitting patterns EP1, EP2, and EP3, the second electrodes CE1, CE2, and CE3, and the cover patterns CP1, CP2, and CP3, or the thickness of the pixel defining film PDL, the inorganic lower encapsulation pattern LIL may not be disposed in the light emitting openings OP1-E, OP2-E, and OP3-E.

[0136] The inorganic lower encapsulation pattern LIL may contact the first lower inner surface S1-Pa and the second lower inner surface S2-Pa of the first conductive partition wall PW1 defining the first partition wall openings OP1-P1, OP2-P1, and OP3-P1 and the first upper inner surface S1-Pb and the second upper inner surface S2-Pb of the second conductive partition wall PW2 defining the second partition wall openings OP1-P2, OP2-P2, and OP3-P2, and may cover the first lower inner surface S1-Pa and the second lower inner surface S2-Pa and the first upper inner surface S1-Pb and the second upper inner surface S2-Pb. Specifically, a portion of the first lower inner surface S1-Pa that is not in contact with the second electrodes CE1, CE2, and CE3 and is exposed may be covered by the inorganic lower encapsulation pattern LIL.

[0137] The upper surfaces of the dummy openings OP-DM and the second conductive partition walls PW2 may not be covered by the inorganic lower encapsulation pattern LIL.

[0138] The inorganic intermediate encapsulation film MIL may cover the dummy opening OP-DM and the upper surface of the second conductive partition wall PW2 that is not covered by the inorganic lower encapsulation pattern LIL and is exposed. The inorganic intermediate encapsulation film MIL may be entirely disposed to cover the inorganic lower encapsulation pattern LIL.

[0139] The display panel DP according to the invention may define a dummy opening OP-DM in the second conductive partition wall PW2, and may include an inorganic intermediate encapsulation film MIL covering the upper surface of the dummy opening OP-DM and the second conductive partition wall PW2. Therefore, the contact area between the first conductive partition wall PW1 and the second conductive partition wall PW2 and the inorganic films LIL and MIL may be increased. Specifically, the second conductive partition wall PW2 and the inorganic lower encapsulation pattern LIL may contact each other at the two side surfaces S-DM of the dummy opening OP-DM, the upper surface of the second conductive partition wall PW2 and the inorganic intermediate encapsulation film MIL may contact each other, and the first conductive partition wall PW1 and the inorganic intermediate encapsulation film MIL may contact each other at the bottom surface B-DM of the dummy opening OP-DM. Due to the increase in the contact area, the display panel DP according to the invention can prevent external moisture from penetrating into the light-emitting elements ED1, ED2, and ED3, thereby improving the reliability of the display device DD (see FIG. 1).

[0140] The organic encapsulation film OL may cover the inorganic intermediate encapsulation film MIL and may provide a flat upper surface. The inorganic upper encapsulation film UIL may be disposed on the organic encapsulation film OL.

[0141] The inorganic lower encapsulation pattern LIL, the inorganic middle encapsulation film MIL and the inorganic upper encapsulation film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the organic encapsulation film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0142] Figure 6 is a cross-sectional view of a display panel DP-1 according to an embodiment of the invention. Figure 6 It is along Figure 4 In addition to the description below, the following can be applied equally. Figure 5 The description given in .

[0143] Reference Figure 6 The display panel DP-1 may include an inorganic dummy packaging film LIL-DM. The inorganic dummy packaging film LIL-DM may be disposed in the dummy opening OP-DM to cover the side surface S-DM and the bottom surface B-DM of the dummy opening OP-DM.

[0144] The inorganic dummy packaging film LIL-DM may include the same material as the inorganic lower packaging pattern LIL. Specifically, the inorganic dummy packaging film LIL-DM may be formed in the same process as the first inorganic lower packaging pattern LIL1, the second inorganic lower packaging pattern LIL2, or the third inorganic lower packaging pattern LIL3.

[0145] wherein the inorganic intermediate packaging film MIL is disposed in the dummy opening OP-DM Figure 5 Compared with the display panel DP in FIG. 1 , the dummy pattern DMP may be arranged in the dummy opening OP-DM. The dummy pattern DMP may be formed together in the operation of forming the first light emitting element ED1, the operation of forming the second light emitting element ED2, or the operation of forming the third light emitting element ED3. The dummy pattern DMP may include a first dummy pattern DM1, a second dummy pattern DM2, and a third dummy pattern DM3. The first dummy pattern DM1 may include the same material as one of the light emitting patterns EP1, EP2, and EP3 of the light emitting elements ED1, ED2, and ED3, and may be formed in the same process step. The second dummy pattern DM2 may include the same material as the second electrodes CE1, CE2, and CE3. The third dummy pattern DM3 may include the same material as the cover patterns CP1, CP2, and CP3.

[0146] In an embodiment, for example, a light emitting pattern EP3, a second electrode CE3, a covering pattern CP3, and an inorganic lower encapsulation pattern LIL3 may be formed in an operation of forming a third light emitting element ED3, and a photolithography process may be performed by patterning a photoresist on a third light emitting region PXA-B and a portion in which a dummy opening OP-DM is provided.

[0147] In this case, the first dummy pattern DM1 may include the same material as the light-emitting pattern EP3 of the third light-emitting area PXA-B, and may be formed by the same process as the light-emitting pattern EP3 of the third light-emitting area PXA-B, the second dummy pattern DM2 may include the same material as the second electrode CE3 of the third light-emitting area PXA-B, and may be formed by the same process as the second electrode CE3 of the third light-emitting area PXA-B, the third dummy pattern DM3 may include the same material as the covering pattern CP3 of the third light-emitting area PXA-B, and may be formed by the same process as the covering pattern CP3 of the third light-emitting area PXA-B, and the inorganic dummy packaging film LIL-DM may include the same material as the third inorganic lower packaging pattern LIL3, and may be formed by the same process as the third inorganic lower packaging pattern LIL3.

[0148] Since the second conductive partition wall PW2 includes a tip portion, the dummy pattern DMP may not entirely cover the top surface of the first conductive partition wall PW1 exposed through the dummy opening OP-DM (i.e., the bottom surface B-DM of the dummy opening OP-DM). Therefore, a portion of the bottom surface B-DM of the dummy opening OP-DM may be covered by the dummy pattern DMP, and the remaining portion of the bottom surface B-DM of the dummy opening OP-DM may be covered by the inorganic dummy encapsulation film LIL-DM.

[0149] The display panel DP-1 according to the invention may define a dummy opening OP-DM in the second conductive partition wall PW2, and may include an inorganic dummy packaging film LIL-DM covering the dummy opening OP-DM. Therefore, the contact area between the first conductive partition wall PW1 and the second conductive partition wall PW2 and the inorganic films LIL and LIL-DM may be increased. Specifically, the second conductive partition wall PW2 and the inorganic dummy packaging film LIL-DM may contact each other in the two side surfaces S-DM of the dummy opening OP-DM, and the top surface of the first conductive partition wall PW1 and the inorganic dummy packaging film LIL-DM may contact each other in the bottom surface B-DM of the dummy opening OP-DM. When the contact area is increased, the display panel DP-1 according to the invention may prevent external moisture from penetrating into the light-emitting elements ED1, ED2, and ED3, thereby improving the reliability of the display device DD (see FIG. 1).

[0150] Figure 7 is a method for manufacturing a display panel DP (see Figure 5 ) method.

[0151] According to the method for manufacturing a display panel DP (see Figure 5 ) may include an operation of preparing a preliminary display panel (S100), an operation of patterning a photoresist (S200), an operation of forming a first preliminary conductive partition wall and a second preliminary conductive partition wall (S300), an operation of forming a first conductive partition wall and a second conductive partition wall (S400), an operation of forming a light emitting pattern (S500), an operation of forming a second electrode (S600), and an operation of forming an inorganic encapsulation film (S700).

[0152] FIG. 8A to FIG. 16B FIG. 2 is a diagram showing a method for manufacturing a display panel DP (see FIG. 2 ) according to an embodiment of the invention. Figure 5 ) is a cross-sectional view of the operation of the method.

[0153] FIG. 8A to FIG. 16B The method for manufacturing a display panel DP (see Figure 5 ) method operates along the Figure 4Since the third light emitting region PXA-B can be formed by the same operation as the operation of the method for manufacturing the first light emitting region PXA-R and the second light emitting region PXA-G among the operations of the method for manufacturing described later, the description of the operation of the method for manufacturing the third light emitting region PXA-B is omitted.

[0154] Reference FIG. 8A to FIG. 8C , the operation of preparing the preliminary display panel DP-I may include an operation of forming a circuit element layer DP-CL on the base layer BL, an operation of forming a first electrode AE, a sacrificial pattern SP and a preliminary pixel defining film PDL-I on the circuit element layer DP-CL, an operation of forming a first conductive layer PW1-I on the preliminary pixel defining film PDL-I, and an operation of forming a second conductive layer PW2-I on the first conductive layer PW1-I.

[0155] Fig. 8A An operation of forming a circuit element layer DP-CL on the base layer BL and an operation of forming a first electrode AE, a sacrificial pattern SP, and a preliminary pixel defining layer PDL-I on the circuit element layer DP-CL are illustrated.

[0156] The circuit element layer DP-CL may be formed through a typical process for manufacturing circuit elements (forming semiconductor patterns, conductive patterns, and signal lines by forming insulating layers, semiconductor layers, and conductive layers in a manner such as coating or deposition and selectively patterning the insulating layers, semiconductor layers, and conductive layers through photolithography and etching processes).

[0157] The first electrode AE ​​and the sacrificial pattern SP may be formed in the same patterning process. A preliminary pixel defining layer PDL-I may be formed to cover all of the first electrode AE ​​and the sacrificial pattern SP.

[0158] Figure 8B An operation of forming a first conductive layer PW1 -I on the preliminary pixel defining layer PDL-I is shown.

[0159] The operation of forming the first conductive layer PW1-I may include an operation of forming a 1-1th conductive layer L1a-I on the preliminary pixel defining layer PDL-I and an operation of forming a 1-2nd conductive layer L2a-I on the 1-1th conductive layer L1a-I.

[0160] The operation of forming the 1-1st conductive layer L1a-I may be performed in a deposition process of the first conductive material. The first conductive material may include a metal. In an embodiment, for example, the first conductive material may include aluminum (Al). In an embodiment, for example, the operation of forming the 1-1st conductive layer L1a-I may be performed in a sputtering process.

[0161] The operation of forming the 1-2 conductive layer L2a-I may be performed in a deposition process of the second conductive material. The second conductive material may include a metal. In an embodiment, for example, the second conductive material may include titanium (Ti). In an embodiment, for example, the operation of forming the 1-2 conductive layer L2a-I may be performed in a sputtering process.

[0162] Figure 8C An operation of forming a second conductive layer PW2 -I on the first conductive layer PW1 -I is shown.

[0163] The operation of forming the second conductive layer PW2-I may include an operation of forming a 2-1st conductive layer L1b-I on the first conductive layer PW1-I and an operation of forming a 2-2nd conductive layer L2b-I on the 2-1st conductive layer L1b-I.

[0164] The operation of forming the 2-1st conductive layer L1b-I may be performed in a deposition process of the first conductive material. The first conductive material may include a metal. In an embodiment, for example, the first conductive material may include aluminum (Al). In an embodiment, for example, the operation of forming the 2-1st conductive layer L1b-I may be performed in a sputtering process.

[0165] The operation of forming the 2-2nd conductive layer L2b-I may be performed in a deposition process of the second conductive material. The second conductive material may include a metal. In an embodiment, for example, the second conductive material may include titanium (Ti). In an embodiment, for example, the operation of forming the 2-2nd conductive layer L2b-I may be performed in a sputtering process.

[0166] Reference 9A to 9C The operation of patterning the photoresist may include an operation of forming a first photoresist layer PR1 on the second conductive layer PW2-I and an operation of exposing the first photoresist layer PR1.

[0167] Fig. 9A An operation of forming a first photoresist layer PR1 on the second conductive layer PW2-I is shown. The first photoresist layer PR1 may be formed by applying a photoresist material on the second conductive layer PW2-I.

[0168] Fig. 9B An exposure process of patterning through the photomask MSK is shown. The photomask MSK may be configured such that portions corresponding to the first area AR1, the second area AR2, and the third area AR3 have different light blocking properties, respectively.

[0169] In an embodiment, for example, the photomask MSK may be constructed such that when a positive photoresist process is applied, a portion of the photomask MSK corresponding to the first area AR1 is blocked, a portion of the photomask MSK corresponding to the second area AR2 is semi-blocked, and a portion of the photomask MSK corresponding to the third area AR3 is exposed.

[0170] Alternatively, conversely, the photomask MSK may be constructed such that when a negative photoresist process is applied, a portion of the photomask MSK corresponding to the first area AR1 is exposed, a portion of the photomask MSK corresponding to the second area AR2 is semi-blocked, and a portion of the photomask MSK corresponding to the third area AR3 is blocked.

[0171] Fig. 9C The first photoresist layer PR1 may be patterned to a first thickness t in the first region AR1. P1 , the first photoresist layer PR1 may be patterned in the second region AR2 to be thicker than the first thickness t P1 The second small thickness t P2 , and the first photoresist layer PR1 may be patterned not to be disposed in the third region AR3 .

[0172] Reference Fig. 10A and Fig. 10B , the operation of forming the first preliminary conductive partition wall PW1-II and the second preliminary conductive partition wall PW2-II may include the operation of forming a second preliminary partition wall opening OP-P2-I in the second conductive layer PW2-I (the second preliminary partition wall opening OP1-P2-I corresponding to the first light-emitting area PXA-R and the second preliminary partition wall opening OP2-P2-I corresponding to the second light-emitting area PXA-G may be collectively referred to as the second preliminary partition wall opening OP-P2-I) and the operation of forming a first preliminary partition wall opening OP-P1-I in the first conductive layer PW1-I (the first preliminary partition wall opening OP1-P1-I corresponding to the first light-emitting area PXA-R and the first preliminary partition wall opening OP2-P1-I corresponding to the second light-emitting area PXA-G may be collectively referred to as the first preliminary partition wall opening OP-P1-I) and forming a preliminary dummy opening OP-DM-I in the second conductive layer PW2-I.

[0173] Fig. 10A The operation of forming the second preliminary partition wall opening OP-P2-I is shown. The second preliminary partition wall opening OP-P2-I may be formed in the second conductive layer PW2-I by a dry etching process. Specifically, the second conductive layer PW2-I corresponding to the third region AR3 in which the first photoresist layer PR1 is not disposed may be removed by a dry etching process.

[0174] Fig. 10B An operation of forming the first preliminary conductive partition wall PW1-II and the second preliminary conductive partition wall PW2-II is shown.

[0175] The operation of forming the first preliminary conductive partition wall PW1-II and the second preliminary conductive partition wall PW2-II may include the operation of ashing the first photoresist layer PR1, and the operation of forming a first preliminary partition wall opening OP-P1-I in the first conductive layer PW1-I and a preliminary dummy opening OP-DM-I in the second conductive layer PW2-I.

[0176] The first photoresist layer PR1 may be partially removed by an ashing process using oxygen plasma. Fig. 10B As shown in FIG, the thickness of the first photoresist layer PR1 may be entirely reduced by an ashing process so that the first photoresist layer PR1 formed to a small thickness and corresponding to the second area AR2 may be removed and the upper surface of the second conductive layer PW2-I may be exposed.

[0177] Then, the first preliminary partition wall openings OP-P1-I corresponding to the third area AR3 and the preliminary dummy openings OP-DM-I corresponding to the second area AR2 may be formed through a dry etching process.

[0178] like Fig. 10B As shown in , the first preliminary partition wall opening OP-P1-I may be defined in the first preliminary conductive partition wall PW1-II, and the second preliminary partition wall opening OP-P2-I and the preliminary dummy opening OP-DM-I may be defined in the second preliminary conductive partition wall PW2-II.

[0179] The first preliminary conductive partition wall PW1-II may include a first preliminary lower layer L1a-II formed of a 1-1 conductive layer L1a-I and a second preliminary lower layer L2a-II formed of a 1-2 conductive layer L2a-I. The second preliminary conductive partition wall PW2-II may include a first preliminary upper layer L1b-II formed of a 2-1 conductive layer L1b-I and a second preliminary upper layer L2b-II formed of a 2-2 conductive layer L2b-I.

[0180] Reference Fig.11A , the operation of forming the first conductive partition wall PW1 and the second conductive partition wall PW2 may include an operation of forming a tip portion through a wet etching process.

[0181] For the etching solution in the wet etching process, the etching rate of the first preliminary lower layer L1a-II may be greater than the etching rate of the second preliminary lower layer L2a-II. Fig.11AAs shown in FIG. 1 , the tip portion may be formed in the second lower layer L2a of the first conductive partition wall PW1. In addition, for the etching solution in the wet etching process, the etching rate of the first preliminary upper layer L1b-II may be greater than the etching rate of the second preliminary upper layer L2b-II. Fig.11A As shown in FIG. 1 , the tip portion may be formed in the second upper layer L2 b of the second conductive partition wall PW2 .

[0182] The first conductive partition wall PW1 may include a first lower layer L1a formed of a first preliminary lower layer L1a-II and a second lower layer L2a formed of a second preliminary lower layer L2a-II. The second conductive partition wall PW2 may include a first upper layer L1b formed of a first preliminary upper layer L1b-II and a second upper layer L2b formed of a second preliminary upper layer L2b-II.

[0183] Reference Fig. 11B , used to manufacture display panels DP (see Figure 5 ) may include an operation of forming a light emitting opening OP-E in a preliminary pixel defining film PDL-I. In addition, according to the embodiment of the present invention, the method for manufacturing a display panel DP (see Figure 5 ) may further include an operation of forming a sacrificial opening OP-S. When the sacrificial pattern SP is not formed on the first electrode AE, the operation of forming the sacrificial opening OP-S may be omitted.

[0184] The light emission openings OP-E corresponding to the first and second partition wall openings OP-P1 and OP-P2 may be formed by etching the preliminary pixel defining film PDL-I through a dry etching process.

[0185] The sacrificial opening OP-S may be formed by etching the sacrificial pattern SP through a wet etching process. The etching process of the sacrificial pattern SP may be performed by an etching solution, wherein the etching rate of the sacrificial pattern SP is greater than the etching rate of the first electrode AE. Therefore, the first electrode AE ​​may be prevented from being damaged in the etching process of the sacrificial pattern SP.

[0186] The first electrode AE ​​may be partially exposed through the sacrificial opening OP-S and the light emitting opening OP-E.

[0187] Reference Fig.12 , used to manufacture display panels DP (see Figure 5 ) may include an operation of forming a first light emitting pattern EP1. In an embodiment, for example, the first light emitting pattern EP1 may be formed by a thermal evaporation process. The first light emitting pattern EP1 may be formed as a whole, and the first light emitting pattern EP1 except the first light emitting region PXA-R may be removed in the following operation.

[0188] Reference Fig.13A, used to manufacture display panels DP (see Figure 5 ) may include an operation of forming the second electrode CE1. In an embodiment, for example, the second electrode CE1 may be formed by a sputtering process. The second electrode CE1 may be formed integrally, and the second electrode CE1 except the first light emitting region PXA-R may be removed in the following operation.

[0189] Reference Fig. 13B , used to manufacture display panels DP (see Figure 5 ) may further include an operation of forming a covering pattern CP1. In an embodiment, for example, the covering pattern CP1 may be formed by a thermal evaporation process. The covering pattern CP1 may be formed as a whole, and the covering pattern CP1 except for the first light emitting region PXA-R may be removed in the following process. In an embodiment, the operation of forming the covering pattern CP1 may be omitted.

[0190] Reference FIG. 14A to FIG. 14C , the operation of forming the thin film encapsulation layer TFE may include an operation of forming a first inorganic lower encapsulation pattern LIL1.

[0191] Fig.14A FIG. 2 shows an operation of integrally forming the first inorganic lower encapsulation pattern LIL1. The first inorganic lower encapsulation pattern LIL1 may include an inorganic material. In an embodiment, for example, the first inorganic lower encapsulation pattern LIL1 may include silicon nitride (SiN x ). The first inorganic lower encapsulation pattern LIL1 may be formed by, for example, a chemical vapor deposition (CVD) process.

[0192] Fig. 14B An operation of forming the second photoresist layer PR2 is shown. The second photoresist layer PR2 may be patterned in a form of overlapping a region corresponding to the first light emitting region PXA-R in a plan view.

[0193] Fig. 14C It is shown that the first inorganic lower encapsulation pattern LIL1 , the capping pattern CP1 , the second electrode CE1 , and the first light emitting pattern EP1 formed in a region except the second photoresist layer PR2 are removed by dry etching, wet etching, and stripping.

[0194] FIG. 15A to FIG. 15D An operation of patterning the second light emitting region PXA-G is shown.

[0195] Fig.15A The operation of forming the second light emitting pattern EP2, the second electrode CE2 and the cover pattern CP2 is shown. In an embodiment, for example, the second light emitting pattern EP2 may be formed by a thermal evaporation process. The second electrode CE2 may be formed by a sputtering process, and the cover pattern CP2 may be formed by a thermal evaporation process.

[0196] Fig. 15B An operation of integrally forming the second inorganic lower encapsulation pattern LIL2 is shown. The second inorganic lower encapsulation pattern LIL2 may include an inorganic material, for example, silicon nitride. The second inorganic lower encapsulation pattern LIL2 may be formed by, for example, a chemical vapor deposition (CVD) process.

[0197] Fig. 15C An operation of forming the third photoresist layer PR3 is illustrated. The third photoresist layer PR3 may be patterned in a form of overlapping a region corresponding to the second light emitting region PXA-G in a plan view.

[0198] Fig.15D It is shown that the second inorganic lower encapsulation pattern LIL2 , the capping pattern CP2 , the second electrode CE2 , and the second light emitting pattern EP2 formed in the region except the third photoresist layer PR3 are removed by dry etching, wet etching, and stripping.

[0199] After the first and second light emitting regions PXA-R and PXA-G are patterned, the third light emitting region PXA-B may be patterned in the same manner.

[0200] Reference Fig.16A and Fig. 16B The operation of forming the thin film encapsulation layer TFE may include an operation of forming an inorganic intermediate encapsulation film MIL, an operation of forming an organic encapsulation film OL, and an operation of forming an inorganic upper encapsulation film UIL.

[0201] Fig.16A The operation of forming the inorganic intermediate packaging film MIL is shown. The inorganic intermediate packaging film MIL may include an inorganic material. In an embodiment, for example, the inorganic intermediate packaging film MIL may include silicon nitride. The inorganic intermediate packaging film MIL may be formed integrally. Therefore, the contact area between the first conductive partition wall PW1 and the second conductive partition wall PW2 and the inorganic films LIL and MIL may be increased.

[0202] Fig. 16B The operation of forming an organic encapsulation film OL and an inorganic upper encapsulation film UIL on the inorganic intermediate encapsulation film MIL is shown. The organic encapsulation film OL can be formed by applying an organic material, for example, in an inkjet process. The organic encapsulation film OL can provide a flat upper surface. The inorganic upper encapsulation film UIL can be formed by, for example, depositing an inorganic material.

[0203] As above 9A to 10BAs described in the method for manufacturing a display panel according to the invention, the first photoresist layer PR1 can be formed to have different thicknesses according to regions by controlling the exposure respectively according to the regions in the photoresist process accompanying the operation of forming the conductive partition walls PW1 and PW2. Therefore, the dummy openings OP-DM can be formed without an additional photoresist process. In addition, the number, position and / or shape of the dummy openings OP-DM can be controlled by controlling the regions in the photoresist process without an additional photoresist process. That is, a display panel having a structure capable of increasing the contact area between the conductive partition walls PW1 and PW2 and the inorganic film for blocking moisture can be manufactured without an additional photoresist process.

[0204] According to the above, the display panel according to the invention has a structure in which the contact area between the inorganic encapsulation film and the conductive partition wall is increased, thereby preventing the penetration of moisture and improving the reliability of the display panel.

[0205] In addition, the method for manufacturing a display panel according to the invention can form a structure in which a contact area between an inorganic encapsulating film and a conductive partition wall is increased without an additional photomask, thereby having excellent workability.

[0206] In the above, the invention has been described with reference to the preferred embodiments, but it can be understood by those skilled in the art or those of ordinary skill in the relevant technical field that various modifications and changes can be made to the invention without departing from the spirit and technical scope of the invention described in the claims. Therefore, the technical scope of the invention is not limited to the contents described in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display panel, comprising: Base layer; A first electrode is disposed on the substrate layer; a pixel defining film, wherein a light emitting opening partially exposing the first electrode is defined in the pixel defining film, and the pixel defining film is disposed on the base layer; a first conductive partition wall, in which a first partition wall opening overlapping the light emitting opening in a plan view is defined, and the first conductive partition wall is disposed on the pixel defining film; a second conductive partition wall, in which a second partition wall opening overlapping the first partition wall opening in a plan view and a dummy opening overlapping the first conductive partition wall are defined, and the second conductive partition wall is disposed on the first conductive partition wall; a second electrode, disposed on the first electrode; as well as The light emitting pattern is arranged between the first electrode and the second electrode. 2 . The display panel according to claim 1 , further comprising an inorganic lower encapsulation pattern disposed on the second electrode and configured to cover the light emitting opening, the first partition wall opening, and the second partition wall opening. 3 . The display panel according to claim 2 , further comprising an inorganic intermediate encapsulation film configured to cover the dummy opening and an upper surface of the second conductive partition wall.

4. The display panel according to claim 3, wherein: An upper surface of the first conductive partition wall exposed through the dummy opening is in contact with the inorganic intermediate encapsulation film.

5. The display panel according to claim 3, wherein: A side surface of the second conductive partition wall defining the second partition wall opening is in contact with the inorganic lower encapsulation pattern, and A side surface of the second conductive partition wall defining the dummy opening is in contact with the inorganic intermediate encapsulation film.

6. The display panel according to claim 1, wherein: The dummy opening is provided in plurality.

7. The display panel according to claim 1, wherein: The first conductive partition wall includes a first lower layer disposed on the pixel definition film and a second lower layer disposed on the first lower layer, and In a plan view, a side surface of the second lower layer protrudes more than a side surface of the first lower layer.

8. The display panel according to claim 1, wherein: The second conductive partition wall includes a first upper layer disposed on the first conductive partition wall and a second upper layer disposed on the first upper layer, and In a plan view, a side surface of the second upper layer protrudes more than a side surface of the first upper layer.

9. The display panel according to claim 1, wherein: The second electrode contacts a side surface of the first conductive partition wall to be electrically connected to each other.

10. The display panel according to claim 1, wherein: A bias voltage is applied to the first conductive partition wall. 11 . The display panel according to claim 2 , further comprising an inorganic dummy packaging film configured to cover the dummy opening. 12 . The display panel of claim 11 , further comprising a dummy pattern disposed on the first conductive partition wall in the dummy opening.

13. The display panel according to claim 12, wherein: The dummy pattern does not contact the second conductive partition wall.

14. The display panel according to claim 11, wherein: A side surface of the second conductive partition wall defining the second partition wall opening is in contact with the inorganic lower encapsulation pattern, and A side surface of the second conductive partition wall defining the dummy opening is in contact with the inorganic dummy encapsulation film.

15. A method for manufacturing a display panel, the method comprising: preparing a preliminary display panel, the preliminary display panel comprising a base layer, a first electrode disposed on the base layer, a preliminary pixel defining film configured to cover the first electrode and disposed on the base layer, a first conductive layer disposed on the preliminary pixel defining film, and a second conductive layer disposed on the first conductive layer; patterning a photoresist on the preliminary display panel; forming a second preliminary partition wall opening in the second conductive layer; forming a first preliminary conductive partition wall by forming a first preliminary partition wall opening in the first conductive layer, the first preliminary partition wall opening overlapping the second preliminary partition wall opening in a plan view; forming a second preliminary conductive partition wall by forming a preliminary dummy opening in the second conductive layer, the preliminary dummy opening being spaced apart from the second preliminary partition wall opening; forming a light-emitting pattern on the first electrode; as well as forming a second electrode on the light emitting pattern, Wherein, in the step of patterning the photoresist, The photoresist is patterned to have a first thickness in a first region that overlaps neither the second preliminary partition wall opening nor the preliminary dummy opening in a plan view, The photoresist is patterned to have a second thickness less than the first thickness in a second region, the second region overlapping the preliminary dummy opening in a plan view, and The photoresist is patterned not to be disposed in a third region overlapping the second preliminary partition wall opening in a plan view.

16. The method according to claim 15, wherein: The step of forming the second preliminary partition wall opening includes forming the second conductive layer corresponding to the third region by dry etching, The step of forming the second preliminary conductive partition wall includes removing the photoresist corresponding to the second region by ashing the photoresist and dry-etching the second conductive layer corresponding to the second region, and The step of forming the first preliminary conductive partition wall includes dry-etching the first conductive layer corresponding to the third region.

17. The method according to claim 15, further comprising forming a first conductive partition wall defining a first partition wall opening and a second conductive partition wall defining a second partition wall opening by wet etching side surfaces of the first preliminary conductive partition wall and the second preliminary conductive partition wall, in, The first preliminary conductive partition wall includes a first preliminary lower layer disposed on the preliminary pixel definition film and a second preliminary lower layer disposed on the first preliminary lower layer. The second preliminary conductive partition wall includes a first preliminary upper layer and a second preliminary upper layer disposed on the first preliminary upper layer, The etching rate of the first preliminary lower layer is greater than the etching rate of the second preliminary lower layer, and An etching rate of the first preliminary upper layer is greater than an etching rate of the second preliminary upper layer. 18 . The method according to claim 17 , further comprising forming a pixel defining film having a light emitting opening defined therein by dry etching the preliminary pixel defining film corresponding to the first partition wall opening. 19 . The method of claim 18 , further comprising forming an inorganic lower encapsulation pattern on the second electrode, the inorganic lower encapsulation pattern being configured to cover the light emitting opening, the first partition wall opening, and the second partition wall opening. 20 . The method of claim 17 , further comprising forming an inorganic intermediate encapsulation film configured to cover upper surfaces of the dummy opening and the second conductive partition wall.

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