Semiconductor device

Abstract

The invention relates to a semiconductor device (2). The semiconductor component has a circuit carrier (S) having a first conductor layer (CU1) in which a first conductor circuit (F1) is formed. The semiconductor component has a first thyristor chip (C1) which has an anode contact (A10) and a gate contact (G10) on the upper side thereof and a cathode contact (K10) on the lower side thereof, the cathode contact (K10) of the first thyristor chip (C1) being arranged on the first conductor circuit (CU1, F1) such that there is an electrical connection between the cathode contact (K10) and the first conductor circuit (CU1, F1). The semiconductor component further comprises a second thyristor chip (C2) which has a cathode contact (K2) and a gate contact (G2) on the upper side thereof and an anode contact (A2) on the lower side thereof, the anode contact (A2) of the second thyristor chip (C2) being arranged on the first conductor circuit (CU1, F1) such that an electrical connection exists between the anode contact (A2) and the first conductor circuit (CU1, F1). The semiconductor component also has at least one electrically conductive connection element (22, D) which electrically connects the anode contact (A10) of the first thyristor chip (C1) to the cathode contact (K2) of the second thyristor chip (C2). A first conductor circuit (CU1, F1) establishes an electrical connection between the cathode contact (K10) of the first thyristor chip (C1) and the anode contact (A2) of the second thyristor chip (C2).

Description

[0001] The invention relates to a semiconductor device with two thyristor chips; the invention also relates to a power semiconductor module with the semiconductor device.

[0002] In semiconductor switching devices, such as soft starters, an anti-parallel circuit of two thyristors can be used as a semiconductor switch for switching AC, for example, see document DE 102016214419 A1 (Siemens AG) February 8, 2018. To this end, the cathode of the first thyristor chip must be connected to the anode of the second thyristor chip; in addition, another electrical connection must be established in the anti-parallel circuit.

[0003] It is known to realize the electrical connection of thyristors by means of bonding wires, for example see the document WO 2008 / 071134 A1 (Siemens AG) of June 19, 2008 and the document DE 102008031297 A1 (Siemens AG) of January 14, 2010. In order to be able to handle the current intensities occurring in power semiconductor modules, each electrical connection may require a plurality of bonding wires connected in parallel, which in many cases must also be routed and bonded at a certain angle. This increases the difficulty of producing an anti-parallel circuit of two thyristors.

[0004] The technical problem to be solved by the present invention is to simplify the manufacture of an anti-parallel circuit of two thyristors. The technical problem to be solved by the present invention is also to provide a thyristor circuit that is easier to manufacture.

[0005] According to the invention, the technical problem is solved by a semiconductor device having the features given in claim 1. The semiconductor device has a circuit carrier, which has a first conductor layer, in which a first conductor circuit is formed. The circuit carrier can also be alternatively referred to as a "substrate". The circuit carrier can be designed as a so-called DCB (=direct copper bonding). A DCB is a sandwich consisting of two conductor layers, such as a copper layer or an aluminum layer, and an insulating layer, such as a ceramic layer, located therebetween. Compared with conventional printed circuit boards, such as epoxy resin printed circuit boards, this DCB allows the components to be carried, especially power semiconductors, to withstand significantly higher temperatures. The first conductor circuit can be formed by dividing the first conductor layer into a conductor structure and a connection structure that are electrically insulated from each other, and the division is achieved, for example, by a structuring method such as photolithography in semiconductor technology. Therefore, the first conductor circuit of the first conductor layer is a conductive surface arranged on the electrically insulating layer of the circuit carrier, which is electrically insulated from other conductor circuits of the first conductor layer. These conductor circuits are used both as conductor structures and as contact surfaces for electronic devices. All conductor circuits of the circuit carrier form a circuit layout on the insulating carrier layer.

[0006] The semiconductor device has a first thyristor chip, which has an anode contact and a gate contact on its upper side and a cathode contact on its lower side; the first thyristor chip is arranged with its cathode contact on the first conductor circuit, so that there is an electrical connection between the cathode contact and the first conductor circuit. The first conductor circuit has a first contact surface of planar design, against which the cathode contact of the first thyristor chip rests. In particular, the cathode contact is electrically connected to the first contact surface by welding, so that a low-resistance electrical path with low thermal resistance is established. The electrical connection, for example in the form of welding, also ensures that the first thyristor chip is mechanically fixed to the first conductor circuit of the first conductor layer.

[0007] The semiconductor device has a second thyristor chip, which has a cathode contact and a gate contact on its upper side and an anode contact on its lower side; the second thyristor chip is arranged on the first conductor circuit with its anode contact, so that there is an electrical connection between the anode contact and the first conductor circuit. The first conductor circuit has a second contact surface of planar design, on which the anode contact of the second thyristor chip rests. In particular, the anode contact is electrically connected to the second contact surface by welding, so that a low-resistance electrical path with low thermal resistance is established. The electrical connection, for example in the form of welding, also ensures that the second thyristor chip is mechanically fixed to the first conductor circuit of the first conductor layer.

[0008] A thyristor chip is a thyristor designed as a microchip. In this specification, a thyristor chip is also referred to as a thyristor for short. Each individual thyristor chip can be designed in a plate or disk shape. These thyristor chips each have two main connection terminals, namely a cathode contact and an anode contact, and a control electrode connection terminal, namely a gate contact, wherein one of these main connection terminals and one of the control electrode connection terminals are located on the upper side of the thyristor chip, and the other main connection terminal is located on the lower side of the thyristor chip.

[0009] Such thyristor chips are particularly housing-free. Basically, such thyristor chips consist of the semiconductor chip itself, the so-called "die" (German: Würfel, Plättchen). Contact surfaces are provided on the die for bonding, i.e. for making electrical contact with the electrodes of the thyristor chip. This compact design allows for a low connection resistance of the thyristor chip to the conductor layer and at the same time a low thermal resistance for cooling the thyristor chip.

[0010] The semiconductor device has at least one electrically conductive connection element, in particular a metal element, for example a metal element made of copper or aluminum, which electrically connects the anode contact of the first thyristor chip to the cathode contact of the second thyristor chip. In addition, the first conductor circuit of the first conductor layer establishes an electrical connection between the cathode contact of the first thyristor chip and the anode contact of the second thyristor chip. Bonding wires, stampings or arbitrarily manufactured metal parts can be used as the at least one electrically conductive connection element; in principle, any electrically conductive element that can be electrically conductively connected to the anode contact and the cathode contact can be used. The arrangement of the electrically conductive connection elements in the semiconductor device for establishing the required electrical connections of the semiconductor device, in particular the course of the bonding wires, is simplified to be referred to as a "bonding diagram", although it is more correct to use the more general term "connection element diagram" here.

[0011] The invention is based on the recognition that the bond diagram and thus the production of an antiparallel circuit of two thyristors can be greatly simplified by using two different thyristor chips, namely a first thyristor chip with the cathode at the bottom and a second thyristor chip with the cathode at the top. The anode contact and the cathode contact of the first thyristor chip are located opposite to those of the second thyristor chip.

[0012] The present invention enables an anti-parallel circuit of a thyristor with a greatly simplified bonding diagram. The number of conductive connection elements that need to be arranged, in particular the number of bonding wires that need to be pulled, is significantly reduced. The conductive connection elements only need to be arranged on the upper side of the chip. The direction of the conductive connection elements is also straightened, for example, a straight direction of the bonding wire can be used for bonding.

[0013] The present invention can realize simpler bonding wire placement and reduce the number of bonding wires, which reduces the bonding cost. Due to the simplified bonding pattern, more installation space is obtained, so that a larger semiconductor can be placed in a predetermined installation space.

[0014] Advantageous embodiments and developments of the invention are specified in the dependent claims.

[0015] According to a preferred design of the present invention, the semiconductor device has an input contact and an output contact. Through these two contacts, the semiconductor device can be connected to a circuit in which the semiconductor device acts as a switch. The output contact is electrically connected to the anode contact of the second thyristor chip through the first conductor circuit. The semiconductor device also has at least one conductive connection element, such as at least one bonding wire, which electrically connects the input contact to the anode contact of the first thyristor chip. The advantage is that the electrical connection required for the operation of the semiconductor device is established through the conductive connection element, such as the bonding wire and the conductor circuit of the first conductor layer, thereby generating a simple bonding diagram.

[0016] According to a preferred design of the present invention, the semiconductor device has a first control contact and a second control contact. These control contacts can be designed as contact surfaces, which are arranged on the carrier layer of the circuit carrier. These control contacts can be designed as conductor circuits of the first conductor layer, such as copper fields or aluminum fields (Kupfer- oderAluminumfelder), which are arranged on the carrier layer of the circuit carrier and are electrically insulated from other conductor circuits of the first conductor layer. The semiconductor device also has at least one control line, which electrically connects the first control contact to the gate contact of the first thyristor chip. And the semiconductor device also has at least one control line, which electrically connects the second control contact to the gate contact of the second thyristor chip. The advantage is that the electrical connection required for the operation of the semiconductor device is established by conductive connecting elements, such as bonding wires, thereby generating a simple bonding diagram.

[0017] According to a preferred design of the present invention, the semiconductor device has a third control contact. The control contact can be designed as a contact surface, which is arranged on the carrier layer of the circuit carrier. The control contact can be designed as a conductor circuit of the first conductor layer, such as a copper field or an aluminum field, which is arranged on the carrier layer of the circuit carrier and is electrically insulated from other conductor circuits of the first conductor layer. And the semiconductor device has at least one auxiliary wire, which electrically connects the third control contact to the cathode contact of the second thyristor chip. The advantage is that the electrical connection required for the operation of the semiconductor device is established by a bonding wire, thereby generating a simple bonding diagram.

[0018] According to a preferred design of the present invention, the semiconductor device has a fourth control contact, which is electrically connected to the cathode contact of the first thyristor chip through the first conductor circuit of the first conductor layer. The fourth control contact can be designed as a contact surface of the first conductor circuit. The advantage is that the electrical connection required for the operation of the semiconductor device is established through the conductor circuit of the first conductor layer, thereby generating a simple bonding diagram.

[0019] Another preferred embodiment of the present invention is a power module, which is an abbreviation of "power semiconductor module" and has a semiconductor device according to one of the above embodiments. A power semiconductor module is an electrical device that can convert electrical energy into a form required for different applications as efficiently as possible with the help of semiconductor devices and can reliably control the power flow through suitable circuits. In addition to the semiconductor device according to the present invention, the power module according to the present invention also has a cooling body, a housing and a casting material, such as plastic. The circuit carrier of the semiconductor device has a second conductor layer arranged on the bottom side of the circuit carrier in addition to a first conductor layer arranged on the upper side of the circuit carrier and an intermediate layer that electrically insulates the two conductor layers mentioned from each other.

[0020] The circuit carrier can be a DCB; the two conductor layers can be copper layers or aluminum layers, and the intermediate layer can be a ceramic layer. Possible designs of the DCB are sufficiently known to those skilled in the art and do not need to be further described here. The semiconductor device is arranged on a cooling body and encapsulated in a housing, which is filled with a casting compound. The power semiconductor module is installed in the housing to isolate it from environmental influences. These housings protect the modules from mechanical damage, moisture and other harmful external influences. The housing is usually cast with a filler, which serves as an electrical insulation layer and at the same time as a mechanical support. This produces a plastic body, in which the electrical and / or electronic components and parts are completely embedded and from which only the power supply and discharge lines of the power module extend.

[0021] According to a preferred design of the power module, connecting layers are arranged between the plurality of thyristor chips and the first conductor layer and between the cooling body and the second conductor layer. These connecting layers can be layers made of solder or other conductive materials. The connecting layers establish mechanical fixation, electrical connection and thermal connection between the connected components.

[0022] According to a preferred design of the power module, the input contacts and the output contacts of the semiconductor device are electrically connected to the first or second contact device arranged outside the housing through the potting material. Therefore, the power module has a plastic body, the electrical and / or electronic components and parts are completely embedded in the plastic body, and only the power supply lines and discharge lines of the power module extend out of the plastic body.

[0023] The invention is explained below with reference to the drawings.

[0024] Figure 1 A circuit diagram showing a thyristor pair;

[0025] Figure 2 A cross-sectional view showing a conventional power module;

[0026] Figure 3 A circuit diagram and bonding diagram showing a conventional thyristor pair;

[0027] Figure 4 A cross-sectional view showing a conventionally connected thyristor pair;

[0028] Figure 5 A circuit diagram and a bonding diagram showing a thyristor pair according to the present invention;

[0029] Figure 6 A cross-sectional view showing a thyristor pair connected according to the present invention;

[0030] Figure 7 shows a cross-sectional view of a power module according to the invention according to a first embodiment; and

[0031] Figure 8 A sectional view of a power module according to the invention is shown according to a further exemplary embodiment.

[0032] Figure 1 A schematic circuit diagram of a device with an anti-parallel thyristor pair T1.1, T1.2 is shown, which is connected to the two poles of an AC voltage source via the contact elements L1, L2 of the device. The thyristors T1.1, T1.2 can be designed in the form of semiconductor chips C1, C2, respectively. The thyristors T1.1, T1.2 have anodes A1, A2, cathodes K1, K2 and gate electrodes G1, G2, respectively. The two thyristors T1.1, T1.2 can be switched on by a controller by applying a current to the gate electrodes G1, G2, respectively, i.e., they are switched from a blocked initial state to a conductive state. Switching on the thyristor by applying this current is called "ignition". Once the thyristor is ignited, it remains conductive even without an applied gate current until the current flowing through the conductive thyristor falls below a minimum value, the so-called holding current.

[0033] In the conventional anti-parallel thyristor pair T1.1, T1.2, two thyristors of the same type T1 with the same structure are used: the cathodes K1, K2 are in the same position in the two thyristor chips T1.1, T1.2, for example, on the top of the chip. In contrast, in the anti-parallel thyristor pair according to the present invention, two thyristors of different types T10, T1 with different structures are used: the cathode K1 of the first thyristor chip C1, T10 is located at the bottom, and the cathode K2 of the second thyristor chip C2, T1 is located at the top, i.e., mirrored with the first thyristor chip C1, T10.

[0034] Figure 2 A cross-sectional view of a conventional power semiconductor module 4 is shown, in which conventional anti-parallel thyristors T1.1, T1.2 are installed. The power semiconductor module has a typical hybrid power electronic structure, which has a plurality of power semiconductor devices C1, C2 combined on a substrate / circuit carrier and connected to each other. The components of the power semiconductor module 4 include at least one semiconductor device C1, C2, which has an anti-parallel thyristor pair T1.1, T1.2. The power semiconductor module 4 can also have other semiconductor devices, such as GTO (=gate turn-off thyristor), MCT (=MOS controlled thyristor), power diode, IGBT (=insulated gate bipolar transistor) or MOSFET (=metal oxide semiconductor field effect transistor). However, the module 4 can also contain other different circuit components, such as passive devices and sensors. The semiconductor devices of the conventional power semiconductor module 4 are commercially common components and are therefore not described in detail below.

[0035] The power semiconductor module 4 includes a base plate P. In the example shown, the base plate P is connected to a cooling body KK via a heat conducting layer I. The cooling body may have a heat sink to dissipate the heat generated by the semiconductor device. Figure 2 The heat sink on the cooling body KK is not shown. A different advantageous embodiment is, for example, a liquid cooler. The heat conducting layer I can consist of a TIM (=thermal interface material), which improves the thermal coupling between the base plate P and the cooling body KK. The base plate P is connected to the cooling body KK via a fastening device B; the closest possible contact between the base plate P and the cooling body KK helps to dissipate heat from the semiconductor components C1, C2.

[0036] The base plate P is preferably made of a material with good thermal conductivity, for example, a metal such as aluminum or copper, or a metal / matrix composite material such as aluminum silicon carbide (AlSiC) or copper silicon carbide (CuSiC). A base plate P made of a metal-ceramic composite material (AlSiC, CuSiC) can be easily combined with a cooling structure KK made of the same composite material or the corresponding metal (Al, Cu).

[0037] In the structure shown, the power semiconductor devices C1, C2 are mounted on a circuit carrier S. The circuit carrier S forms electrical insulation between the semiconductor devices C1, C2 and the base plate P and also has good thermal conductivity so as to dissipate the heat of the semiconductor devices C1, C2 to the base plate P. The circuit carrier S may have a ceramic layer CC, wherein aluminum nitride (AlN), aluminum oxide (Al2O3), beryllium oxide (BeO), silicon carbide (SiC) or silicon nitride (SiN) are preferred materials. Due to the high thermal conductivity and thermal expansion coefficient, a ceramic circuit carrier S, a so-called DCB substrate, is preferably used. The ceramic circuit carrier S is composed of a ceramic insulator CC, such as aluminum oxide or aluminum nitride, and thin pure copper layers are coated on both sides of the ceramic insulator, namely, a first conductor layer CU1 is coated on the upper side of the ceramic layer CC and a second conductor layer CU2 is coated on the lower side of the ceramic layer CC, as shown in FIG. Figure 2 As shown, the circuit carrier S is connected to the base plate P via the solder layer V.

[0038] The circuit carrier S has metallized conductor paths F1, F2, F3, F4 on its upper side facing the semiconductor components C1, C2, which are structured according to circuit technology requirements: in the present embodiment, the conductor paths F1 to F4 include input contacts L1, output contacts L2, first conductor paths F1 and second conductor paths F2. The conductor paths F1 to F4 are produced by subdividing the first conductor layer CU1 arranged on the upper side of the ceramic layer CC.

[0039] The electronic semiconductor components C1, C2 are mechanically and electrically connected to the conductor tracks F1 to F4; these electrical connections can be produced by means of a soldering layer V. Instead of a soldering layer V between the semiconductor components C1, C2 and the circuit carrier S, different material-bonded connections or fastenings are also conceivable, which ensure good electrical and thermal contact, for example, by means of an intermediate layer in the form of a metal plate. The electrical connection between the conductor tracks F1 to F4 and the semiconductor components C1, C2 is produced by means of bonding wires D.

[0040] The power semiconductor module 4 also includes a housing H, which is sealed by a base plate P, thereby forming an interior space of the housing. It is usually a plastic housing. In addition to plastic, the housing H can also be made of other different dielectrics, especially ceramics. Ceramics are both cheap and resistant and have good thermal conductivity for electrical insulators. This thermal conductivity is important for dissipating the generated heat.

[0041] In order to electrically insulate the components of the power semiconductor module 4 from each other and to isolate the circuit structure from the external atmosphere, the housing H is at least partially cast with a casting compound M in the direction of the base plate P. Usually, the housing volume is filled with the casting compound M to such an extent that the housing volume uniformly surrounds the semiconductor components C1, C2 and meets the usual standard regulations. The connection terminals 51, 52 of the power semiconductor module 4 are led out of the cast housing H at suitable positions through the contacts L1, L2 of the circuit carrier S and the solder layer V to provide the external connection terminals of the power semiconductor module 4.

[0042] Figure 3 Part a shows a circuit diagram of a conventional semiconductor device having an anti-parallel thyristor pair and part b shows a bonding diagram of the semiconductor device. Figure 3 a) shows two thyristors T1.1 and T1.2 of the same design, which are connected to each other in anti-parallel. The cathodes K1 and K2 of the two thyristor chips T1.1 and T1.2 are located at the same position on the upper side of the chip. The gates G1 and G2 of the two thyristor chips T1.1 and T1.2 are located at the same position on the upper side of the chip. The anodes A1 and A2 of the two thyristor chips T1.1 and T1.2 are located at the same position on the lower side of the chip.

[0043] The two thyristor chips T1.1, T1.2 are connected as follows: the input contact L1 of the circuit is connected to the cathode K1 of the first transistor chip T1.1 via a first bonding connection 11. The anode A1 of the first transistor chip T1.1 is connected to the cathode K2 of the second transistor chip T1.2 via a second bonding connection 12. The cathode K1 of the first transistor chip T1.1 is connected to the anode A2 of the second transistor chip T1.2 via a third bonding connection 13. The cathode K2 of the second transistor chip T1.2 is connected to the output contact L2 via a fourth bonding connection 14.

[0044] Bond Graph( Figure 3 b) shows a top view of a conventionally connected thyristor pair. Eight electrically insulated conductor paths are formed by a structuring method from a copper layer arranged as a first conductor layer CU1 on a ceramic layer CC of a circuit carrier: The input contact L1 of the semiconductor device forms a third conductor path F3. The first transistor chip C1, T1.1 is arranged with its anode contact A1 on the first conductor path F1. The second transistor chip C2T1.2 is arranged with its anode contact A2 on the second conductor path F2. And the output contact L2 of the semiconductor device forms a fourth conductor path F4. In addition, the first control contact 31 forms a fifth conductor path F5, the second control contact 32 forms a sixth conductor path F6, the third control contact 33 forms a seventh conductor path F7, and the fourth control contact 34 forms an eighth conductor path F8.

[0045] The two thyristor chips T1.1 and T1.2 are connected as follows: the third conductor circuit F3, i.e. the input contact L1 of the circuit, is connected to the cathode K1 of the first transistor chip T1.1 via a first bonding connection 11. The anode A1 of the first transistor chip T1.1 is welded to the first conductor circuit F1, which is connected to the cathode K2 of the second transistor chip T1.2 via a second bonding connection 12. The cathode K1 of the first transistor chip T1.1 is connected to the second conductor circuit F2 via a third bonding connection 13, to which the anode A2 of the second transistor chip T1.2 is welded. The cathode K2 of the second transistor chip T1.2 is connected to the fourth conductor circuit F4, i.e. the output contact L2 of the circuit, via a fourth bonding connection 14.

[0046] The potential of the cathode K1 of the first transistor T1.1 is transmitted to the fifth conductor path F5 forming the first control contact 31 (auxiliary cathode) of the circuit via the first auxiliary line 16, wherein the first auxiliary line 16 is connected at a first end to the anode A2 of the second transistor T1.2, the anode of the second transistor being at the potential of the cathode K1 of the first transistor T1.1. The first auxiliary line 16 is connected at the other end to the first control contact 31, from which an electrical connection can be established with respect to a controller for driving the first thyristor T1.1. Energy from the main circuit can be supplied to the controller via the first control contact 31, which is used to drive the gate G1 of the first thyristor chip T1.1.

[0047] The first control line 15 extends from a sixth conductor path F6 forming a second control contact 32 of the circuit to the gate G1 of the first thyristor T1 . 1 .

[0048] The second control line 17 extends from a seventh conductor path F7 forming a third control contact 33 of the circuit to the gate G2 of the second thyristor T1 . 2 .

[0049] The potential of the cathode K2 of the second transistor T1.2 is transmitted to the eighth conductor path F8 forming the fourth control contact 34 (auxiliary cathode) of the circuit via the second auxiliary line 18, wherein the first end of the second auxiliary line 18 is connected to the anode A1 of the first transistor T1.1, which is at the potential of the cathode K2 of the second transistor T1.2. The second auxiliary line 18 is connected with the other end to the fourth control contact 34, from which an electrical connection to a controller for driving the second thyristor T1.2 can be established. The fourth control contact 34 is used to drive the gate G2 of the second thyristor chip T1.2, and energy from the main circuit can be provided to the controller via the fourth control contact.

[0050] In order to be able to handle the currents occurring in the power semiconductor devices C1, C2, each electrical connection 11, 12, 13, 14 requires a plurality of parallel bond wires, which must also be routed and bonded at a certain angle. Figure 3 b The difficulty of the anti-parallel circuit of two thyristors in the bonding diagram.

[0051] Figure 4 Show according to Figure 3 1 . A cross-sectional view of two conventionally interconnected thyristors T1 and T2 in accordance with a circuit / bonding diagram of FIG. The two thyristor chips C1 and C2 have the same structure, i.e., they each have an anode contact A1 and A2 arranged on the bottom side of the chip, a cathode contact K1 and K2 arranged on the top side of the chip, and a gate contact G1 and G2 arranged on the top side of the chip. Between the contacts on the top side and the contacts on the bottom side there is a semiconductor layer structure 1, which is also designed identically in the two thyristor chips C1 and C2.

[0052] The first thyristor chip C1, T1.1 is located on the first conductor circuit F1. The anode contact A1 located on the lower side of the first thyristor chip C1, T1.1 is electrically and mechanically connected to the first conductor circuit F1 through the solder layer V. The cathode contact K1 and the gate contact G1 are located on the upper side of the first thyristor chip C1, T1.1.

[0053] The second thyristor chip C2, T1.2 is arranged on the second conductor circuit F2. The anode contact A2 located on the lower side of the second thyristor chip C2, T1.2 is electrically and mechanically connected to the second conductor circuit F2 via the solder layer V. The cathode contact K2 and the gate contact G2 are located on the upper side of the second thyristor chip C2, T1.2.

[0054] For the electrical connection of the two thyristor chips C1 and C2 through the bonding wire D, refer to Figure 3 Description of b.

[0055] Figure 5 Detail a shows a circuit diagram of a semiconductor device according to the present invention having an anti-parallel thyristor pair C1, C2, and detail b shows a bonding diagram of the semiconductor device. Figure 5 a) shows two thyristors T10 and T1 of different designs, which are connected to each other in anti-parallel. The cathode K10 of the first thyristor chip T10 is located on the lower side of the chip, while the cathode K2 of the second thyristor chip T1 is located on the upper side of the chip. The anode A10 of the first thyristor chip T10 is located on the upper side of the chip, while the anode A2 of the second thyristor chip T1 is located on the lower side of the chip. The gate G10 of the first thyristor chip T10 and the gate G2 of the second thyristor chip T1 are respectively located on the upper side of the corresponding chip.

[0056] The two thyristor chips T10, T1 are connected as follows: the input contact L1 of the circuit is connected to the anode A10 of the first transistor chip T10 via a first bonding connection 21. The anode A10 of the first transistor chip T10 is connected to the cathode K2 of the second transistor chip T1 via a second bonding connection 22. The anode A2 of the second transistor chip T1 is connected to the output contact L2 via a third bonding connection 23. The cathode K10 of the first transistor chip T10 is connected to the anode A2 of the second transistor chip T1 via a connection 24 other than a bonding wire connection. The electrical connections 21, 22, 23 can also be made using other different connection elements instead of bonding wires.

[0057] Bond Graph( Figure 5 b) shows a top view of the thyristor pair C1, C2 connected according to the invention. Six electrically insulated conductor circuits are formed from a copper layer arranged as a first conductor layer CU1 on the ceramic layer CC of the circuit carrier by a known structuring method: Both transistor chips C1, C2 are arranged on the first conductor circuit F1: the cathode contact K10 of the first transistor chip C1, T10 is arranged on the first conductor circuit F1, and the anode contact A2 of the second transistor chip C2T1 is arranged on the first conductor circuit F1. Like the output contact L2 of the semiconductor device, the fourth control contact 44 is also located on the first conductor circuit F1. The input contact L1 of the semiconductor device constitutes the second conductor circuit F2. In addition, the first control contact 41 constitutes the third conductor circuit F3, the second control contact 42 constitutes the fourth conductor circuit F4, and the third control contact 43 constitutes the fifth conductor circuit F5.

[0058] The two thyristor chips T10, T1 are connected as follows: The second conductor circuit F2, i.e. the input contact L1 of the circuit, is connected to the anode A10 of the first transistor chip T10 via a first bonding connection 21. The cathode K10 of the first transistor chip T10 and the anode K2 of the second transistor chip T1 are soldered to the first conductor circuit F1 designed as a copper layer, which connects the cathode K10 of the first transistor chip T10 to the anode K2 of the second transistor chip T1. The anode A10 of the first transistor chip T10 is connected to the cathode K2 of the second transistor chip T1 via a second bonding connection 22. The anode A2 of the second transistor chip T1 is connected to the output contact L2 of the circuit via the first conductor circuit F1. The electrical connections 21, 22 can also be made with other different connection elements instead of bonding wires.

[0059] The fourth control contact 44 is designed as an extension of the first conductor circuit F1 and is at the potential of the cathode K10 of the first transistor T10. An electrical connection with a controller for driving the first thyristor T10 can be established from the fourth control contact. The fourth control contact 44 is used to drive the gate G10 of the first thyristor chip T10. Energy from the main circuit can be provided to the controller through the fourth control contact.

[0060] The first control line 25 extends from the third conductor path F3 forming the first control contact 41 of the circuit to the gate G10 of the first thyristor T10 .

[0061] The second control line 26 extends from a fourth conductor path F4 forming a second control contact 42 of the circuit to the gate G2 of the second thyristor T1 .

[0062] The potential of the cathode K2 of the second transistor T1 is transmitted to the fifth conductor circuit F5 of the third control contact 43 constituting the circuit via the auxiliary line 27, wherein the auxiliary line 27 is connected to the cathode K2 of the second transistor T1 at a first end. The auxiliary line 27 is connected to the third control contact 43 at the other end, and an electrical connection with respect to the controller driving the second thyristor T1 can be established from the third control contact. The third control contact 43 is used to drive the gate G2 of the second thyristor chip T1, and energy from the main circuit can be provided to the controller via the third control contact.

[0063] In order to be able to cope with the currents occurring in the power semiconductor components C1, C2, each electrical connection 21, 22 requires a plurality of parallel bonding wires. However, the design of the thyristor and the antiparallel circuit according to the invention allows a greatly simplified bonding diagram in which the total number of wires to be established is significantly reduced and bonding only has to be performed on the upper side of the chip. The invention also allows a straight run of the bonding wires. This greatly simplifies the production of a device having a structure according to the invention by wire bonding. Figure 5b is a bonding diagram of an antiparallel circuit of two thyristors. The arrangement of the thyristor chips according to the invention also simplifies the production of electrical connections using connecting elements other than bonding wires: Furthermore, the connecting elements can extend in a straight line.

[0064] As Figure 5 As an alternative to the design shown in FIG. 2 b, the output contact L2 of the semiconductor device can also be designed as a conductor circuit separated from the first conductor circuit F1, and the separated conductor circuit is electrically connected to the first conductor circuit F1 through an electrical connection element, such as one or more bonding wires. For example, when the first conductor circuit F1 and the conductor circuit separated from the output contact L2 are at different heights relative to the plane of the ceramic layer CC, this alternative design is advantageous.

[0065] Figure 6 Show according to Figure 5 A cross-sectional view of two thyristors T10 and T1 interconnected according to the present invention according to a circuit / bonding diagram. The two thyristor chips C1 and C2 have different structures: the cathode K10 of the first thyristor chip C1 and T10 is located on the lower side of the chip, while the cathode K2 of the second thyristor chip C2 and T1 is located on the upper side of the chip. The anode A10 of the first thyristor chip C1 and T10 is located on the upper side of the chip, while the anode A2 of the second thyristor chip C2 and T1 is located on the lower side of the chip. The gate G10 of the first thyristor chip C1 and T10 and the gate G2 of the second thyristor chip C2 and T1 are both located on the upper side of the corresponding chip. There are semiconductor layer structures 1 and 10 between the contacts on the upper side and the contacts on the lower side, and these semiconductor layer structures are also designed differently in the two thyristor chips C1 and C2.

[0066] The first thyristor chip C1, T10 is located on the first conductor circuit F1. The cathode contact K10 located on the lower side of the first thyristor chip C1, T10 is electrically and mechanically connected to the first conductor circuit F1 through the solder layer V. The anode contact A10 and the gate contact G10 are located on the upper side of the first thyristor chip C1, T10.

[0067] The second thyristor chip C2, T1 is also arranged on the first conductor circuit F1. The anode contact A2 located on the lower side of the second thyristor chip C2, T1 is electrically and mechanically connected to the first conductor circuit F1 through the solder layer V. The cathode contact K2 and the gate contact G2 are located on the upper side of the second thyristor chip C2, T1.

[0068] For the electrical connection of the two thyristor chips C1 and C2 through the bonding wire D, refer to Figure 5 Description of b.

[0069] Figure 7A sectional view of a power module 4 according to a first embodiment of the present invention is shown, in which anti-parallel-connected thyristors T10 , T1 according to the present invention are installed.

[0070] The power semiconductor module has a typical hybrid power electronic structure, which has a plurality of power semiconductor devices C1, C2 combined on a substrate / circuit carrier and connected to each other. The components of the power semiconductor module 4 include at least one semiconductor device C1, C2, which has a thyristor pair T10, T1.2 connected in anti-parallel. The power semiconductor module 4 can also include other semiconductor devices, such as GTO, MCT, power diode, IGBT or MOSFET. However, the module 4 can also include other different circuit components, such as passive devices and sensors. The semiconductor devices of the conventional power semiconductor module 4 are commercially common components and are therefore not described in detail below.

[0071] The power semiconductor module 4 includes a base plate P. In the example shown, the base plate P is connected to a cooling body KK via a heat conducting layer I. The cooling body may have a heat sink to dissipate the heat generated by the semiconductor device. Figure 7 The heat sink on the cooling body KK is not shown. A different advantageous embodiment is, for example, a liquid cooler. The heat conducting layer I can be formed by a thermal interface material, which improves the thermal coupling between the base plate P and the cooling body KK. The base plate P is connected to the cooling body KK via a fastening device B; the closest possible contact between the base plate P and the cooling body KK helps to dissipate heat from the semiconductor devices C1, C2.

[0072] The base plate P is preferably made of a material with good thermal conductivity, for example, a metal such as aluminum or copper, or a metal / matrix composite material such as aluminum silicon carbide (AlSiC) or copper silicon carbide (CuSiC). The base plate P made of a metal-ceramic composite material (AlSiC, CuSiC) can be easily combined with a cooling structure KK made of the same composite material or the corresponding metal (Al, Cu).

[0073] In the structure shown, the power semiconductor devices C1, C2 are mounted on a circuit carrier S. The circuit carrier S forms electrical insulation between the semiconductor devices C1, C2 and the base plate P and also has good thermal conductivity so as to dissipate the heat of the semiconductor devices C1, C2 to the base plate P. The circuit carrier S may have a ceramic layer CC, wherein aluminum nitride (AlN), aluminum oxide (Al2O3), beryllium oxide (BeO), silicon carbide (SiC) or silicon nitride (SiN) are preferred materials. Due to the high thermal conductivity and thermal expansion coefficient, a ceramic circuit carrier S, a so-called DCB substrate, is preferably used. The ceramic circuit carrier S is composed of a ceramic insulator CC, such as aluminum oxide or aluminum nitride, and thin pure copper layers are coated on both sides of the ceramic insulator, namely, a first conductor layer CU1 is coated on the upper side of the ceramic layer CC and a second conductor layer CU2 is coated on the lower side of the ceramic layer CC, as shown in FIG. Figure 7 As shown, the circuit carrier S is connected to the base plate P via the solder layer V.

[0074] The circuit carrier S has on its upper side a first conductor layer CU1 facing the semiconductor components C1, C2, which is structured into a plurality of conductor paths F1 and F2 according to circuit technology requirements: in this example, the conductor paths include, in addition to the first conductor path F1, a second conductor path with an input contact L1. The conductor paths F1 and F2 are produced by structuring the first conductor layer CU1 that has been arranged on the upper side of the ceramic layer CC.

[0075] The electronic semiconductor components C1, C2 are mechanically and electrically connected to the conductor tracks F1, F2; these electrical connections can be realized by means of a soldering layer V. Instead of a soldering layer V between the semiconductor components C1, C2 and the circuit carrier S, different material-bonded connections or fastenings are also conceivable, which ensure good electrical and thermal contact, for example, by means of an intermediate layer in the form of a metal plate. The electrical connections between the conductor tracks F1, F2 and the semiconductor components C1, C2 and between the semiconductor components C1, C2 are produced by means of bonding wires D. These electrical connections can also be produced by means of other connecting elements instead of bonding wires.

[0076] The power semiconductor module 4 also includes a housing H, which is sealed by a base plate P, thereby forming an interior space of the housing. It is usually a plastic housing. In addition to plastic, the housing H can also be made of other dielectrics, especially ceramics. Ceramics are both cheap and resistant and have good thermal conductivity for electrical insulators. This thermal conductivity is important for dissipating the generated heat.

[0077] In order to electrically insulate the components of the power semiconductor module 4 from each other and to isolate the circuit structure from the external atmosphere, the housing H is at least partially cast with a casting compound M in the direction of the base plate P. Usually, the housing volume is filled with the casting compound M to such an extent that the housing volume uniformly surrounds the semiconductor components C1, C2 and meets the usual standard regulations. The connection terminals 51, 52 of the power semiconductor module 4 are led out of the cast housing H at suitable positions through the contact surfaces L1, L2 of the circuit carrier S and the solder layer V to provide external connection terminals of the power semiconductor module 4.

[0078] Figure 8 FIG. 4 is a cross-sectional view of a power module 4 according to another design of the present invention. Figure 7 The structure shown is different. Figure 8 The structure of the power module 4 shown lacks a base plate P, a heat conducting layer I and a fastening device B. The circuit carrier S rests on the heat sink KK only via a connecting layer V.

Claims

1. A semiconductor device (2), comprising: - a circuit carrier (S) having a first conductor layer (CU1) in which a first conductor circuit (F1) is formed; - a first thyristor chip (C1) having an anode contact (A10) and a gate contact (G10) on its upper side and a cathode contact (K10) on its lower side, wherein, The first thyristor chip (C1) is arranged on the first conductor circuit (CU1, F1) with its cathode contact (K10), so that there is an electrical connection between the cathode contact (K10) and the first conductor circuit (CU1, F1); - a second thyristor chip (C2), which has a cathode contact (K2) and a gate contact (G2) on its upper side and an anode contact (A2) on its lower side, wherein the second thyristor chip (C2) is arranged with its anode contact (A2) on the first conductor path (CU1, F1) so that there is an electrical connection between the anode contact (A2) and the first conductor path (CU1, F1); and - at least one electrically conductive connecting element (22, D) electrically connecting the anode contact (A10) of the first thyristor chip (C1) to the cathode contact (K2) of the second thyristor chip (C2), The first conductor circuit (CU1, F1) establishes an electrical connection between the cathode contact (K10) of the first thyristor chip (C1) and the anode contact (A2) of the second thyristor chip (C2).

2. The semiconductor device (2) according to claim 1, comprising: - Input contact (L1); - an output contact (L2) electrically connected to the anode contact (A2) of the second thyristor chip (C2) via a first conductor circuit (CU1, F1); and - at least one electrically conductive connection element (21, D) electrically connecting the input contact (L1) to the anode contact (A10) of the first thyristor chip (C1).

3. The semiconductor device (2) according to claim 1, comprising: - a first control contact (41); - a second control contact (42); - at least one control line (25, D), the control line (25, D) electrically connecting the first control contact (41) to the gate contact (G10) of the first thyristor chip (C1); and - at least one control line (26, D), the control line (26, D) electrically connecting the second control contact (42) to the gate contact (G2) of the second thyristor chip (C2).

4. The semiconductor device (2) according to any one of the preceding claims, comprising: - a third control contact (43); - at least one auxiliary line (27, D), which electrically connects the third control contact (43) to the cathode contact (K2) of the second thyristor chip (C2).

5. The semiconductor component (2) according to any one of the preceding claims, comprising a fourth control contact (44), which is electrically connected to the cathode contact (K10) of the first thyristor chip (C1) via a first conductor path (CU1, F1).

6. The semiconductor device (2) according to any one of the preceding claims, wherein: The at least one electrically conductive connecting element (22, D) is one or more elements from the following group: bonding wires, stampings, metal parts.

7. A power semiconductor module (4) comprising a semiconductor device (2) according to any one of the preceding claims, the power semiconductor module further comprising: - cooling body (KK); - housing (H); - Castable (M); in, The circuit carrier (S) of the semiconductor component has, in addition to a first conductor layer (CU1) on its upper side, a second conductor layer (CU2) on its lower side and an intermediate layer (CC) which electrically insulates the two conductor layers from each other; The semiconductor component (2) is arranged on the heat sink (KK) and is enclosed in a housing (H) which is filled with a potting compound.

8. The power semiconductor module (4) according to claim 7, wherein: A connecting layer (V) is arranged between the plurality of thyristor chips (C1, C2) and the first conductor path (F1) of the first conductor layer (CU1) and between the cooling body (KK) and the second conductor layer (CU2).

9. The power semiconductor module (4) according to claim 7 or 8, wherein: The input contact (L1) and the output contact (L2) of the semiconductor device (2) are electrically connected to a first or second contact device (51, 52) arranged outside the housing (H) through a potting compound (M).

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