Anisotropic magnetoresistive sensor circuit with adjustable offset trimming

Abstract

Examples of the present application relate to an anisotropic magnetoresistive sensor circuit with adjustable offset trimming. A circuit (100D in Fig. 5, or 100E in Fig. 6) includes: an anisotropic magnetoresistive (AMR) sensor (516 in Fig. 5, or 606 in Fig. 6); an operational amplifier (550 in Figure 5, or related transistors in Figure 6 such as MP0A, MP0B, MN0A, MN0B, etc.); and a calibration circuit (540 in Figure 5, or related circuits such as 628, 638, 648, 654, 660, 670, and 680 in Figure 6). The AMR sensor (516 or 606) has a first terminal (106A in Figure 6), a second terminal (518 in Figure 5, or 106B in Figure 6), a third terminal (520 in Figure 5, or 106C in Figure 6), and a fourth terminal (106D in Figure 6). The operational amplifier (550) has a first terminal (552), a second terminal (554), a third terminal (556), and a fourth terminal (558).

Description

Technical Field

[0001] The present application relates to electromagnetic components, and in particular to anisotropic magnetoresistance (AMR) sensor circuits. Background Art

[0002] Anisotropic magnetoresistive (AMR) sensors change resistance as they are oriented relative to the ambient magnetic field. The results from AMR sensors can be used for motor or shaft position monitoring and related control options. Errors can be introduced into AMR sensor results due to process, voltage, and temperature (PVT) variations. Summary of the invention

[0003] In one example, a circuit includes: an anisotropic magnetoresistive (AMR) sensor; an operational amplifier; and a calibration circuit. The AMR sensor has a first terminal, a second terminal, a third terminal, and a fourth terminal. The operational amplifier has a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal of the operational amplifier is coupled to the second terminal of the AMR sensor, and the second terminal of the operational amplifier is coupled to the third terminal of the AMR sensor. The calibration circuit is coupled to the first terminal of the operational amplifier. The calibration circuit is configured to provide an adjustable offset trim voltage at the first terminal of the operational amplifier to offset an offset voltage generated by the AMR sensor.

[0004] In another example, a circuit includes: a first AMR sensor; a first operational amplifier; a first calibration circuit; a second AMR sensor; a second operational amplifier; and a second calibration circuit. The first AMR sensor has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first operational amplifier has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the first operational amplifier is coupled to the second terminal of the first AMR sensor. The second terminal of the first operational amplifier is coupled to the third terminal of the first AMR sensor. The first calibration circuit is coupled to the first terminal of the first operational amplifier. The first calibration circuit is configured to provide a temperature-dependent offset trim voltage at the first terminal of the first operational amplifier. The second AMR sensor has a first terminal, a second terminal, a third terminal, and a fourth terminal. The second AMR sensor rotates relative to the first AMR sensor. The second operational amplifier has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the second operational amplifier is coupled to the second terminal of the second AMR sensor. The second terminal of the second operational amplifier is coupled to the third terminal of the second AMR sensor. The second calibration circuit is coupled to the first terminal of the second operational amplifier. The second calibration circuit is configured to provide a temperature-dependent offset trim voltage at the first terminal of the second operational amplifier.

[0005] In yet another example, an AMR sensor circuit includes: an AMR sensor; a gain circuit; and a calibration circuit. The AMR sensor is configured to: receive a voltage; and provide an AMR sensor result in response to the voltage and an ambient magnetic field. The gain circuit is coupled to the AMR sensor and configured to: receive the AMR sensor result; and provide an amplified result in response to the AMR sensor result. The calibration circuit is coupled to the gain circuit and configured to apply a correction to the amplified result, wherein the correction varies with temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a diagram illustrating an example anisotropic magnetoresistive (AMR) sensor circuit with calibration circuitry.

[0007] Figure 2 is a diagram illustrating an example AMR sensor scenario and related parameters.

[0008] Figures 3A to 3C is a diagram illustrating an example shaft position monitoring option using an AMR sensor.

[0009] Figure 4 is a block diagram illustrating an example position-based control system.

[0010] Figure 5 and 6 is a block diagram illustrating another example AMR sensor circuit with calibration circuitry.

[0011] Figures 7A to 7G is shown with Figure 6 Schematic diagram of an example trimming circuit associated with an AMR sensor circuit.

[0012] Figures 8A to 8D 9 are graphs illustrating an example AMR offset trimming procedure.

[0013] Fig.10 is a graph illustrating an example trimming process for an AMR sensor circuit.

[0014] Fig.11 is a flow chart illustrating an example AMR sensor calibration method. DETAILED DESCRIPTION

[0015] The same reference numerals or other reference designators are used in the drawings to designate the same or similar features. Such features may be the same or similar in function and / or structure.

[0016] Described herein is an anisotropic magnetoresistive (AMR) sensor circuit that provides adjustable offset trimming. As used herein, an "AMR sensor" refers to a material having a resistivity that varies with the strength or direction of an ambient magnetic field. In some instances, the AMR sensor includes a distributed layout of AMR materials. The example distributed layout includes AMR materials oriented in different directions (e.g., orthogonal directions) depending on the target sensing application. As used herein, "AMR offset" refers to changes in the output of an AMR sensor relative to an intended sensing operation due to changes in manufacturing, environmental conditions, and / or other factors. Temperature and bias current changes (current passing through the AMR sensor during sensing operations) are two factors that affect AMR offset. Each AMR sensor may have a different AMR offset, and the AMR offset may change over time. In order to account for the AMR offset, the described AMR sensor circuit includes an offset trimming control circuit system. In some instances, each AMR sensor circuit includes a gain control circuit system, wherein the offset trimming control circuit system operates to adjust the reference current, bias current, and / or current mirroring options of the gain control circuit system to account for a specific AMR offset. Because the AMR offset of each AMR sensor varies and may change over time and for different environmental conditions, the adjustments provided by the offset trim control circuitry may be dynamic and adjustable for each AMR sensor.

[0017] In different examples, the number of AMR sensors in the AMR sensor circuit may vary, and the AMR sensor circuit may include offset trimming control circuitry for each AMR sensor. When multiple AMR sensors are used, different orientations of each sensor may be used. In some examples, the AMR sensor circuit may include additional circuitry to store AMR sensor results, process AMR sensor results, derive relevant parameters from the AMR sensor results, and / or generate control signals in response to the AMR sensor results or derived relevant parameters. Examples of derived relevant parameters include the position or orientation of the shaft, the position or orientation of the motor, the position or orientation of the magnet, etc. Examples of additional circuitry that may be included with the AMR sensor circuit include an analog / digital converter (ADC), a digital / analog converter (DAC), position monitoring circuitry, a quadrature encoder, and a motor controller. In some examples, a processor and memory with relevant instructions may perform position monitoring, quadrature encoding, and motor control and / or other operations based on the AMR sensor results.

[0018] In some examples, an AMR sensor circuit includes: a first integrated circuit (IC) having one or more AMR sensors; and a second IC having offset trim control circuitry for each AMR sensor of the first IC. In other examples, the AMR sensor circuit includes an IC that includes one or more AMR sensors and offset trim control circuitry for each AMR sensor of the IC. In different examples, additional circuitry of the AMR sensor circuit (e.g., to store AMR sensor results, process AMR sensor results, derive relevant parameters from the AMR sensor results, and / or generate control signals in response to the AMR sensor results or derived relevant parameters) may be included in the same IC or in one or more other ICs.

[0019] Figure 11 is a diagram showing an example AMR sensor circuit 100 with offset trimming control. As shown, the AMR sensor circuit 100 includes a first group of AMR components 104A to 104D and a second group of AMR components 108A to 108D. The first group of AMR components 104A to 104D is part of a first AMR sensor having a first terminal 106A, a second terminal 106B, a third terminal 106C, and a fourth terminal 106D. The second group of AMR components 108A to 108D is part of a second AMR sensor having a first terminal 110A, a second terminal 110B, a third terminal 110C, and a fourth terminal 110D. The AMR sensor circuit 100 also includes a first offset trimming and gain control circuit 114 and a second offset trimming and gain control circuit 124. The first offset trimming and gain control circuit 114 has a first terminal 116, a second terminal 118, a third terminal 120, and a fourth terminal 122. The second offset trim and gain control circuit 124 has a first terminal 126, a second terminal 128, a third terminal 130, and a fourth terminal 132. The first offset trim and gain control circuit 114 and the second offset trim and gain control circuit 124 are examples of calibration circuitry for the AMR sensor circuit 100.

[0020] exist Figure 1 In the example of FIG. 1 , AMR components 104A and 104C are oriented at +45 degrees relative to the north-south direction, and AMR components 104B and 104D are oriented at −45 degrees relative to the north-south direction. AMR components 108A and 108C are oriented parallel to the north-south direction, and AMR components 108B and 108D are oriented perpendicular to the north-south direction.

[0021] As shown, the first terminal 106A is coupled to a voltage supply (V DD ) terminal. The voltage supply terminal is coupled to provide a supply voltage (also referred to as V DD ) of a voltage supply (not shown). AMR component 104A is coupled between first terminal 106A and second terminal 106B. AMR component 104B is coupled between first terminal 106A and third terminal 106C. AMR component 104C is coupled between third terminal 106C and fourth terminal 106D. AMR component 104D is coupled between second terminal 106B and fourth terminal 106D. Fourth terminals 106D and 110D are coupled to a ground terminal or ground. As shown, first terminal 116 of first offset trimming and gain control circuit 114 is coupled to second terminal 106B. Second terminal 118 of first offset trimming and gain control circuit 114 is coupled to third terminal 106C. First terminal 126 of second offset trimming and gain control circuit 124 is coupled to second terminal 110B. Second terminal 128 of second offset trimming and gain control circuit 124 is coupled to third terminal 110C.

[0022] The first AMR sensor operates to receive V at its first terminal 106A: DD ; In the presence of an ambient magnetic field, it responds to V DD and the resistivity of AMR components 104A and 104D to provide a first AMR result (SIN+) at its second terminal 106B; and in the presence of an ambient magnetic field in response to V DD and the resistivity of AMR components 104B and 104C to provide a second AMR result (SIN-) at its third terminal 106C. The second AMR sensor operates to receive V at its first terminal 110A. DD ; In the presence of an ambient magnetic field, it responds to V DD and the resistivity of AMR components 108A and 108D to provide a third AMR result (COS+) at its second terminal 110B; and in response to V in the presence of an ambient magnetic field DD and the resistivity of AMR components 108B and 108C to provide a fourth AMR result (COS-) at third terminal 110C thereof.

[0023] The first offset and gain control circuit 114 operates to: receive SIN+ at its first terminal 116; receive SIN- at its second terminal 118; provide an adjusted first AMR result (VSIN+) at its third terminal 120 in response to SIN+ and the operation of the first offset trim and gain control circuit 114; and provide an adjusted second AMR result (VSIN-) at its fourth terminal 122 in response to SIN- and the operation of the first offset trim and gain control circuit 114. Example operations of the first offset trim and gain control circuit 114 include: receiving SIN+ and SIN- at a first target orientation for different temperatures; receiving a bias voltage (VBIAS); generating a reference current in response to VBIAS; obtaining a trim value in response to the SIN+ and SIN- values ​​at the target orientation and the different temperatures; and applying a current to the gain circuit to provide VSIN+ and VSIN- in response to the reference current and the trim value.

[0024] The second offset trim and gain control circuit 124 operates to: receive COS+ at its first terminal 126; receive COS- at its second terminal 128; provide an adjusted first AMR result (VCOS+) at its third terminal 130 in response to COS+ and the operation of the second offset trim and gain control circuit 124; and provide an adjusted second AMR result (VCOS-) at its fourth terminal 132 in response to COS- and the operation of the second offset trim and gain control circuit 124. Example operations of the second offset trim and gain control circuit 124 include: receiving COS+ and COS- at target orientations for different temperatures; receiving VBIAS; generating a reference current in response to VBIAS; obtaining trim values ​​in response to COS+ and COS- values ​​at the target orientation and different temperatures; and applying current to the gain circuit to provide VCOS+ and VCOS- in response to the reference current and the trim values. In some examples, VSIN+, VSIN-, VCOS+, and VCOS- are used to trim the offset voltage applied to the gain circuit (not shown).

[0025] Figure 2 2 is a diagram illustrating an example AMR sensor scenario and associated parameters. Figure 2 In the example of FIG. 200 , the diagram 200 includes a rotating magnet 206 and an AMR sensor circuit 100A. The AMR sensor circuit 100A is Figure 1 . A rotating magnet 206 has a first pole 208 (eg, a north pole) and a second pole 210 (eg, a south pole). The AMR sensor circuit 100A has a first layer 202 and a second layer 204. The rotating magnet 206 is axially offset from the AMR sensor circuit 100A and provides a rotating magnetic field.

[0026] exist Figure 2 In the example of FIG. 2 , graph 200 illustrates a magnetic field angular position 212 , a magnetization direction 214 of a first layer 202 of the AMR sensor circuit 100A, a magnetization direction 216 of a second layer 204 of the AMR sensor circuit 100A, and a graph 218 illustrating an AMR resistivity 220 as a function of the magnetic field angular position 212 .

[0027] exist Figure 2In the example of , the AMR resistivity 220 is minimum when the magnetic field angle is at 0 degrees. The AMR resistivity 220 is maximum when the magnetic field angle is at 180 degrees. As shown, the magnetization direction 214 of the first layer 202 of the AMR sensor circuit 100A matches the magnetic field angle position 212. However, the magnetization direction 216 of the second layer 204 of the AMR sensor circuit 100A always remains the same (e.g., the magnetization direction 216 remains at 0 degrees). With the AMR resistivity variation as a function of the magnetic field angle, various AMR sensor usage options are possible, including magnetic field monitoring, shaft position monitoring, motor position monitoring, etc.

[0028] Figures 3A to 3C 300A, 300B, and 300C are diagrams illustrating example shaft position monitoring options using the AMR sensor circuit 100B. The AMR sensor circuit 100B is Figure 1 The AMR sensor circuit 100 or Figure 2 An example of an AMR sensor circuit 100A in FIG. Figure 3A In the example of FIG. 300A, the diagram includes a shaft 302 having a first pole 304 and a second pole 306. The shaft 302 has a rotational direction 308 relative to an axis 310. Figure 3A In the embodiment, the AMR sensor circuit 100B is axially offset (e.g., below) from the shaft 302. Thus, the top of the AMR sensor circuit 100B has one end of the shaft position and faces the end of the shaft 302. In some examples, the AMR sensor having one end of the shaft position can be used for sensing scenarios such as motor shaft angular position detection and speed detection.

[0029] exist Figure 3B In the example of FIG. 300B, the diagram 300B includes a shaft 302 having a first pole 304, a second pole 306, a rotational direction 308, and an axis 310. As shown, the AMR sensor circuit 100B is laterally offset from the shaft 302 (e.g., to the side thereof). Figure 3B In the example of FIG. 1 , the top of the AMR sensor circuit 100B is beside the shaft 302 and does not face the shaft. Thus, the AMR sensor circuit 100B has Figure 3B In some examples, an AMR sensor with a shaft side position can be used to sense situations where the AMR sensor circuit 100B cannot be placed at the end of the shaft. Example shaft side sensing situations include a ring magnet situation, a steering angle positioning situation, or a robot arm joint angle sensing and control.

[0030] exist Figure 3CIn the example of FIG. 300C, the diagram 300C includes a shaft 302 having a first pole 304, a second pole 306, a rotational direction 308, and an axis 310. As shown, the AMR sensor circuit 100B is laterally offset from the shaft 302 (e.g., to the side thereof). Figure 3C In the example of FIG. 1 , the top of the AMR sensor circuit 100B faces the longitudinal side of the shaft 302. Therefore, Figure 3C The AMR sensor circuit 100B in has a shaft-side orthogonal position. In some examples, the AMR sensor with a shaft-side orthogonal position can be used to sense situations where the AMR sensor circuit 100B cannot be placed at the end of the shaft. Example shaft-side orthogonal sensing situations include throttle and / or pedal angle sensing and control.

[0031] Figure 4 is a block diagram illustrating an example position-based control system 400. As shown, the position-based control system 400 includes a controller device 402, an AMR sensor circuit 100C, and an orthogonal encoder 442. The AMR sensor circuit 100C is Figure 1 The AMR sensor circuit 100, Figure 2 AMR sensor circuit 100A or Figure 3A , 3B Controller device 402 has first terminal 404, second terminal 406, third terminal 408, and fourth terminal 410. AMR sensor circuit 100C has first terminal 414, second terminal 416, third terminal 418, fourth terminal 420, fifth terminal 422, sixth terminal 424, seventh terminal 426, eighth terminal 428, ninth terminal 429, and tenth terminal 430. In some examples, AMR sensor circuit 100C includes AMR sensor 432, gain circuitry 434, offset trim control circuitry 436, analog-to-digital converter (ADC) 438, and processor 440. In some examples, AMR sensor 432 includes Figure 1 The gain circuit system 434 and the offset trim control circuit system 436 include the first AMR circuit and the second AMR circuit described in Figure 1 The quadrature encoder 442 has a first terminal 444, a second terminal 446 and a third terminal 448.

[0032] exist Figure 4100C. In the example of , first terminal 404 of controller device 402 is coupled to first terminal 414 of AMR sensor circuit 100C. Second terminal 406 of controller device 402 is coupled to second terminal 416 of AMR sensor circuit 100C. Third terminal 408 of controller device 402 is coupled to third terminal 418 of AMR sensor circuit 100C. Fourth terminal 410 of controller device 402 is coupled to fourth terminal 420 of AMR sensor circuit 100C.

[0033] A fifth terminal 422 of the AMR sensor circuit 100C is coupled to a first terminal 444 of a quadrature encoder 442. A sixth terminal 424 of the AMR sensor circuit 100C is coupled to a second terminal 446 of the quadrature encoder 442. A seventh terminal 426 of the AMR sensor circuit 100C is coupled to a third terminal 448 of the quadrature encoder 442. In some examples, an eighth terminal 428 of the AMR sensor circuit 100C provides a pulse width modulated (PWM) signal to transmit angle information. A ninth terminal 429 of the AMR sensor circuit 100C receives a V DD The tenth terminal 430 of the AMR sensor circuit 100C is coupled to a ground terminal or ground.

[0034] The controller device 402 operates to perform absolute position sensing and programming. In some examples, the controller device 402 and the AMR sensor circuit 100C include standard serial port interface (SPI) terminals to support communication between a processor of the controller device 402 and the AMR sensor circuit 100C. Figure 4In the example of , the first terminal 414 of the AMR sensor circuit 100C is a SPI data output (SDO) terminal, the second terminal 416 of the AMR sensor circuit 100C is a SPI data input (SDI) terminal, the third terminal 418 is a SPI clock (SCLK) terminal, and the fourth terminal 420 is a chip select (CS) terminal. In this case, the first terminal 404 of the controller device 402 is a main output subnode input (MOSI) terminal. The second terminal 406 of the controller device 402 is a main input subnode output (MISO) terminal. The third terminal 408 of the controller device 402 is the SCLK terminal, and the fourth terminal 410 of the controller device 402 is the CS terminal. In this example, the controller device 402 is a SPI master device, and the AMR sensor circuit 100C is a SPI subnode. In other examples, the AMR sensor circuit 100C may be a SPI master device, and the controller device 402 is a SPI subnode. In either case, bidirectional communication between the controller device 402 and the AMR sensor circuit 100C is supported. In some examples, the controller device 402 may send control signals or commands to the AMR sensor circuit 100C and receive back angle information from the AMR sensor circuit 100C for ongoing sensing and control operations.

[0035] The AMR sensor circuit 100C operates to: trim the output stage and common-mode voltage of the gain circuit system 434; trim the AMR sensor offset voltage applied to the gain circuit system 434 at a first target temperature; trim the AMR sensor offset voltage applied to the gain circuit system 434 at a second target temperature; obtain an AMR result in response to the ambient magnetic field and the trimmed result; digitize the AMR result; and determine a position parameter in response to the AMR result.

[0036] More specifically, offset trim control circuitry 436 operates to: trim the output level and common-mode voltage of gain circuitry 434; trim the AMR sensor offset voltage applied to gain circuitry 434 at a first target temperature; and trim the AMR sensor offset voltage applied to gain circuitry 434 at a second target temperature. AMR sensor 432 operates to: receive V DD ; and in response to V DD and ambient magnetic field to provide an AMR result. Gain circuitry 434 operates to amplify the AMR result in response to the trimming result. ADC 438 operates to digitize the amplified AMR sine / cosine signal result. Processor 440 operates to determine a position parameter in response to the digitized AMR result.

[0037] The quadrature encoder 442 operates to: receive angular information from the AMR sensor circuit 100C; and calculate quadrature information and a magnetic turn count based on the angular information.

[0038] Figure 5 and 6 100D and 100E are block diagrams illustrating other example AMR sensor circuits 100D and 100E, respectively, with calibration circuitry. Figure 5 The AMR sensor circuit 100D and Figure 6 The AMR sensor circuit 100E is Figure 1 AMR sensor circuit 100, Figure 2 The AMR sensor circuit 100A in Figure 3A , 3B and the AMR sensor circuit 100B in 3C or Figure 4 An example of an AMR sensor circuit 100C in FIG. Figure 5 , a first AMR sensor 526 and a second AMR sensor 528 having different orientations are shown, as well as corresponding first offset trim control circuits 540 and second offset trim control circuits 560, and corresponding gain control circuit systems (e.g., first operational amplifiers 550 and second operational amplifiers 570). In contrast, Figure 6 A single AMR sensor 606 is shown (with Figure 5 526) and a more detailed example of the offset trimming control circuitry and gain control circuitry for AMR sensor 606. As described herein, the number of AMR sensors of an AMR sensor circuit and the number of ICs used to form the AMR sensor circuit may vary. In some examples, Figure 6 The offset trimming control circuit system and the gain control circuit system are Figure 5 An example of a first offset trimming control circuit 540 and a first operational amplifier 550. Figure 5 The second AMR sensor 528 may include Figure 6 . Thus, an AMR sensor circuit may include offset trim control circuitry and gain control circuitry for each AMR sensor.

[0039] exist Figure 5 In the example of FIG. 1 , the AMR sensor circuit 100D has a first terminal 502, a second terminal 504, a third terminal 506, a fourth terminal 508, a fifth terminal 510, a sixth terminal 512, and a seventh terminal 514. In some examples, the first terminal 502 is V DDThe second terminal 504 is a temperature voltage (VTEMP) terminal. The third terminal 506 is a VSIN+ terminal. The fourth terminal 508 is a VSIN- terminal. The fifth terminal 510 is a VCOS+ terminal. The sixth terminal 512 is a COS- terminal. The seventh terminal 514 is a ground terminal.

[0040] The AMR sensor circuit 100D includes an AMR sensor 516 including a first AMR sensor 526 and a second AMR sensor 528. As shown, the first AMR sensor 526 is rotated relative to the second AMR sensor 528. The AMR sensor 516 has a first terminal 517, a second terminal 518, a third terminal 520, a fourth terminal 522, and a fifth terminal 524. The first AMR sensor 526 is Figure 1 Thus, the resistor of the first AMR sensor 526 is Figure 1 The second AMR sensor 528 is an example of a first group of AMR components 104A to 104D in FIG. Figure 1 Thus, the resistor of the second AMR sensor 528 is Figure 1 The first terminal 517 of the AMR sensor 516 is Figure 1 The second terminal 518 of the AMR sensor 516 is Figure 1 The third terminal 520 of the AMR sensor 516 is Figure 1 The fourth terminal 522 of the AMR sensor 516 is Figure 1 The fifth terminal 524 of the AMR sensor 516 is Figure 1 An example of a third terminal 110C in FIG.

[0041] exist Figure 5 In some examples, the AMR sensor circuit 100D further includes a first offset trim control circuit 540, a second offset trim control circuit 560, a first operational amplifier 550, a second operational amplifier 570, a bias voltage source 580, a voltage supply source 584, and a temperature sensor 588. In some examples, the first offset trim control circuit 540 is Figure 1 The first offset trimming and gain control circuit 114 of the part and / or Figure 4 The second offset trim control circuit 560 is a portion of the offset trim control circuit system 436 in FIG. Figure 1 The second offset trimming and gain control circuit 124 of the part and / or Figure 4The first operational amplifier 550 is a portion of the offset trim control circuit system 436. Figure 1 The first offset trimming and gain control circuit 114 of the part and / or Figure 4 The second operational amplifier 570 is a portion of the gain circuit system 434. Figure 1 The second offset trimming and gain control circuit 124 of the part and / or Figure 4 Part of the gain circuit system 434 in.

[0042] As shown, the first offset trim control circuit 540 has a first terminal 542, a second terminal 544, a third terminal 546, and a fourth terminal 548. The second offset trim circuit 560 has a first terminal 562, a second terminal 564, a third terminal 566, and a fourth terminal 568. The first operational amplifier 550 has a first terminal 552, a second terminal 554, a third terminal 556, and a fourth terminal 558. The second operational amplifier 570 has a first terminal 572, a second terminal 574, a third terminal 576, and a fourth terminal 578. The voltage supply source 584 has a terminal 586. The temperature sensor 588 has a terminal 590.

[0043] exist Figure 5 58, a first terminal 517 of the AMR sensor 516 is coupled to a terminal 586 of a voltage supply 584. A second terminal 518 of the AMR sensor 516 is coupled to a first terminal 542 of a first offset trim control circuit 540. A third terminal 520 of the AMR sensor 516 is coupled to a second terminal 544 of the first offset trim control circuit 540. A fourth terminal 522 of the AMR sensor 516 is coupled to a first terminal 562 of a second offset trim control circuit 560. A fifth terminal 524 of the AMR sensor 516 is coupled to a second terminal 564 of the second offset trim control circuit 560.

[0044] A third terminal 546 of the first offset trim control circuit 540 is coupled to a first terminal 552 (e.g., a non-inverting input) of the first operational amplifier 550. A fourth terminal 548 of the first offset trim control circuit 540 is coupled to a second terminal 554 (e.g., an inverting input) of the first operational amplifier 550. A third terminal 556 of the first operational amplifier 550 is coupled to the third terminal 506 of the AMR sensor circuit 100D. A fourth terminal 558 of the first operational amplifier 550 is coupled to the fourth terminal 508 of the AMR sensor circuit 100D.

[0045] A third terminal 566 of the second offset trim control circuit 560 is coupled to a first terminal 572 (e.g., a non-inverting input) of a second operational amplifier 570. A fourth terminal 568 of the second offset trim control circuit 560 is coupled to a second terminal 574 (e.g., an inverting input) of the second operational amplifier 570. A third terminal 576 of the second operational amplifier 570 is coupled to a fifth terminal 510 of the AMR sensor circuit 100D. A fourth terminal 578 of the second operational amplifier 570 is coupled to a sixth terminal 512 of the AMR sensor circuit 100D.

[0046] exist Figure 5 In the example of FIG. 5 , the bias voltage source 580 provides a bias voltage, such as a bandgap voltage reference (V BG ). The bias voltage source 580 also provides bias current to other components of the AMR sensor circuit 100D, such as the first offset trim control circuit 540, the second offset trim control circuit 560, the first operational amplifier 550, and the second operational amplifier 570. A terminal 590 of the temperature sensor 588 is coupled to the second terminal 504 of the AMR sensor circuit 100D.

[0047] AMR sensor circuit 100D operates to: trim the output level and common mode voltage for each of first operational amplifier 550 and second operational amplifier 570; trim the AMR sensor offset voltage applied to each of first operational amplifier 550 and second operational amplifier 570 at a first target temperature; trim the AMR sensor offset voltage applied to each of first operational amplifier 550 and second operational amplifier 570 at a second target temperature; and provide AMR results in response to an ambient magnetic field and the trimmed results. Example AMR results include VSIN+, VSIN-, VCOS+, and VCOS-.

[0048] More specifically, the AMR sensor 516 operates to: receive V at its first terminal 517 DD ; In response to V DD and the ambient magnetic field to provide a first AMR result (eg, SIN+ result) at its second terminal 518; in response to V DD and the ambient magnetic field and provide a second AMR result (eg, SIN-result) at its third terminal 520; in response to V DD and the ambient magnetic field to provide a third AMR result (eg, COS+ result) at its fourth terminal 522; and in response to V DD and the ambient magnetic field to provide a fourth AMR result (eg, COS-result) at its fifth terminal 524 .

[0049] Bias voltage source 580 operates to provide VBIAS based on a target VBIAS reference. Voltage supply source 584 operates in response to a target VDD The temperature sensor 588 provides a temperature sensing signal (e.g., VTEMP) at its terminal 590 in response to the ambient temperature and the temperature sensing operation of the temperature sensor 588. In some examples, the temperature sensor 588 uses a thermistor and / or other temperature-dependent components to generate a temperature-dependent VTEMP.

[0050] The first offset trim control circuit 540 operates to: receive a first AMR result (e.g., SIN+) at its first terminal 542; receive a second AMR result (e.g., SIN-) at its second terminal 544; provide an adjusted first amplified AMR result (VSIN+) at its third terminal 546 in response to the first AMR result and the operation of the first offset trim control circuit 540; and provide an adjusted second amplified AMR result (VSIN-) at its fourth terminal 548 in response to the second AMR result and the operation of the first offset trim control circuit 540. Example operations of the second offset trim control circuit 540 include: receiving SIN+ and SIN- at target orientations at different temperatures; receiving VBIAS; generating a reference current in response to VBIAS; obtaining trim values ​​in response to SIN+ and SIN- values ​​at the target orientation and different temperatures; and applying current to the first operational amplifier 550 in response to the reference current and the trim values ​​to provide VSIN+ and VSIN-. In some examples, the first offset trim control circuit 540 operates to: trim the AMR sensor offset voltage applied to the first operational amplifier 550 at a first target temperature and a first target orientation; and trim the AMR sensor offset voltage applied to the first operational amplifier 550 at a second target temperature and a first target orientation.

[0051] The second offset trim control circuit 560 operates to: receive a third AMR result (e.g., COS+) at its first terminal 562; receive a fourth AMR result (e.g., COS-) at its second terminal 564; provide an adjusted third amplified AMR result (VCOS+) at its third terminal 566 in response to the third AMR result and operation of the second offset trim control circuit 560; and provide an adjusted fourth amplified AMR result (VCOS-) at its fourth terminal 568 in response to the fourth AMR result and operation of the first offset trim control circuit 540. Example operations of the second offset trim control circuit 560 include: receiving COS+ and COS- at target orientations for different temperatures; receiving VBIAS; generating a reference current in response to VBIAS; obtaining trim values ​​in response to COS+ and COS- values ​​at the target orientation and different temperatures; and applying current to the gain circuit to provide VCOS+ and VCOS- in response to the reference current and the trim values. In some examples, the second offset trim control circuit 560 operates to: trim the AMR sensor offset voltage applied to the second operational amplifier 570 at a first target temperature and a second target orientation; and trim the AMR sensor offset voltage applied to the second operational amplifier 570 at a second target temperature and a second target orientation.

[0052] The first operational amplifier 550 operates to receive SIN+ at its first terminal 552, receive SIN- at its second terminal 554, provide VSIN+ at its third terminal 556 in response to SIN+ and a gain setting of the first operational amplifier 550, and provide VSIN- at its fourth terminal 558 in response to SIN- and a gain setting of the first operational amplifier 550. In some examples, the gain setting of the first operational amplifier 550 is based on the output stage offset and common mode voltage of the first operational amplifier 550 trimmed by the first offset trim control circuit 540.

[0053] The second operational amplifier 570 operates to receive COS+ at its first terminal 572, receive COS- at its second terminal 574, provide VCOS+ at its third terminal 576 in response to COS- and the gain setting of the second operational amplifier 570, and provide VCOS- at its fourth terminal 578 in response to COS- and the gain setting of the second operational amplifier 570. In some examples, the gain setting of the second operational amplifier 570 is based on the output stage offset and common mode voltage of the second operational amplifier 570 trimmed by the second offset trim control circuit 560.

[0054] exist Figure 6 In the example of FIG. 1 , the AMR sensor circuit 100E includes a low dropout regulator (LDO) 602, an AMR sensor 606, a first offset voltage (V os1) source 616, a second offset voltage (V os2 ) source 622, a first reference current (IREF1) generating circuit 628, a second reference current (IREF2) generating circuit 638, a third reference current (IREF3) generating circuit 648, a constant transconductance (Gm) bias current generating circuit 654, an IREF1 current mirror circuit 660, an IREF2 current mirror circuit 670, and an IREF3 current mirror circuit 680. As shown in the figure, the AMR sensor circuit 100E further includes transistors MP13, MP0A, MP0B, MN0A, and MN0B.

[0055] Transistors MP13, MP0A, MP0B, MN0A, and MN0B are part of a gain circuit or an analog front end (AFE) operational amplifier. In some examples, transistors MP13, MP0A, MP0B, MN0A, and MN0B may be Figure 1 The first offset trimming and gain control circuit 114, Figure 1 The second offset trimming and gain control circuit 124, Figure 4 Gain circuit system 434, Figure 5 The first operational amplifier 550 or Figure 5 The LDO 602 is a Figure 5 6. In some examples, the AMR sensor circuit 100E may include a second AMR sensor that is offset from the AMR sensor 606 to obtain the COS+, COS-, VCOS+, and VCOS- results as described herein. In such examples, V os1 Source 616, V os2 Source 622, IREF1 generation circuit 628, IREF2 generation circuit 638, IREF3 generation circuit 648, constant Gm bias current generation circuit 654, IREF1 current mirror circuit 660, IREF2 current mirror circuit 670, and IREF3 current mirror circuit 680 are repeated for the second AMR sensor.

[0056] exist Figure 6 In the example of FIG. 6 , LDO 602 has terminal 604. AMR sensor 606 has first terminal 106A, second terminal 106B, third terminal 106C, fourth terminal 106D, and includes Figure 1 The first set of AMR components 104A to 104D described in FIG. 1A and 1B are shown in FIG. 1A . Thus, the AMR sensor 606 is Figure 1 The first AMR sensor example. os1 Source 616 has a first terminal 618 and a second terminal 620. os2Source 622 has a first terminal 624 and a second terminal 626. IREF1 generation circuit 628 has a first terminal 630 and a second terminal 632. IREF2 generation circuit 638 has a first terminal 640 and a second terminal 642. IREF3 generation circuit 648 has a first terminal 650 and a second terminal 652. Constant Gm bias current generation circuit 654 has a first terminal 656 and a second terminal 658. In some examples, IREF1 generation circuit 628, IREF2 generation circuit 638, IREF3 generation circuit 648, and constant Gm bias current generation circuit 654 can each include a ground terminal (not shown).

[0057] The IREF1 current mirror circuit 660 has a first terminal 662, a second terminal 664, a third terminal 665, and a fourth terminal 668. The IREF2 current mirror 670 has a first terminal 672, a second terminal 674, a third terminal 676, and a fourth terminal 678. The IREF3 current mirror 680 has a first terminal 682, a second terminal 684, a third terminal 686, and a fourth terminal 688. Each of the transistors MP13, MP0A, and MP0B is a p-channel metal oxide semiconductor (PMOS) transistor having a respective first terminal, a respective second terminal, and a respective control terminal. Each of the transistors MN0A and MN0B is an n-channel metal oxide semiconductor (NMOS) transistor having a respective first terminal, a respective second terminal, and a respective control terminal.

[0058] exist Figure 6 In the example of FIG. 6 , a first terminal 106A of the AMR sensor 606 is coupled to the terminal 604 of the LDO 602. A second terminal 106B of the AMR sensor 606 is coupled to the control terminal of the transistor MP0A. A third terminal 106C of the AMR sensor 606 is coupled to the control terminal of the transistor MP0B. A fourth terminal 106D of the AMR sensor 606 is coupled to a ground terminal or ground. os1 The first terminal 618 of the source 616 is coupled to the second terminal 106B. os1 The second terminal 620 of the source 616 is coupled to V os2 The first terminal 624 of the source 622. V os2 A second terminal 626 of source 622 is coupled to a control terminal of transistor MP0A. os1 represents the offset generated by the AMR sensor 606. V os2 Indicates to offset V os1 The input reference equivalent offset. Figure 6 In the example, V os2Provided by trimming circuits, such as IREF1 generation circuit 628 , IREF2 generation circuit 638 , IREF3 generation circuit 648 , IREF1 current mirror circuit 660 , IREF2 current mirror circuit 670 , IREF3 current mirror circuit 680 and constant Gm bias current generation circuit 654 .

[0059] A first terminal 630 of the IREF1 generation circuit 628 is coupled to the terminal 604 of the LDO 602. A second terminal 632 of the IREF1 generation circuit 628 is coupled to a first terminal 662 of the IREF1 current mirror circuit 660. A second terminal 664 of the IREF1 current mirror circuit 660 is coupled to the second terminal of the transistor MP0A and the first terminal of the transistor MN0A. A third terminal 665 of the IREF1 current mirror circuit 660 is coupled to the second terminal of the transistor MP0B and the first terminal of the transistor MN0B. A fourth terminal 668 of the IREF1 current mirror circuit 660 is coupled to a ground terminal or ground.

[0060] A first terminal 640 of the IREF2 generation circuit 638 is coupled to the terminal 604 of the LDO 602. A second terminal 642 of the IREF2 generation circuit 638 is coupled to a first terminal 672 of the IREF2 current mirror circuit 670. A second terminal 674 of the IREF2 current mirror circuit 670 is coupled to the second terminal of the transistor MP0A and the first terminal of the transistor MN0A. A third terminal 676 of the IREF2 current mirror circuit 670 is coupled to the second terminal of the transistor MP0B and the first terminal of the transistor MN0B. A fourth terminal 678 of the IREF2 current mirror circuit 670 is coupled to a ground terminal or ground.

[0061] A first terminal 648 of the IREF3 generation circuit 648 is coupled to the terminal 604 of the LDO 602. A second terminal 652 of the IREF3 generation circuit 648 is coupled to a first terminal 682 of the IREF3 current mirror circuit 680. A second terminal 684 of the IREF3 current mirror circuit 680 is coupled to the second terminal of the transistor MP0A and the first terminal of the transistor MN0A. A third terminal 686 of the IREF3 current mirror circuit 680 is coupled to the second terminal of the transistor MP0B and the first terminal of the transistor MN0B. A fourth terminal 688 of the IREF3 current mirror circuit 680 is coupled to a ground terminal or ground. Second terminals of the transistors MN0A and MN0B are coupled to a ground terminal or ground.

[0062] A first terminal 656 of a constant Gm bias current generating circuit 654 is coupled to a terminal 604 of LDO 602. A second terminal 658 of a constant Gm bias current generating circuit 654 is coupled to a control terminal of transistor MP13. A first terminal of transistor MP13 is coupled to terminal 604 of LDO 602. A second terminal of transistor MP13 is coupled to first terminals of transistors MP0A and MP0B.

[0063] exist Figure 6 , LDO 602 operates to generate VBIAS in response to a target bias voltage reference. IREF1 generation circuit 628 operates to receive VBIAS at its first terminal 630; and to provide IREF1 at its second terminal 632 in response to VBIAS and a target IREF1 reference. IREF2 generation circuit 638 operates to receive VBIAS at its first terminal 640; and to provide IREF2 at its second terminal 642 in response to VBIAS and a target IREF2 reference. IREF3 generation circuit 648 operates to receive VBIAS at its first terminal 650; and to provide IREF3 at its second terminal 652 in response to VBIAS and a target IREF3 reference. Constant Gm bias current generation circuit 654 operates to receive VBIAS at its first terminal 656; and to provide a gate control signal at its second terminal 658 in response to VBIAS and a target constant Gm bias setting. In the case of constant Gm bias current generation, the bias current varies as needed to maintain a constant transconductance of transistor MP13. As used herein, "constant transconductance" refers to a target transconductance that is accurate to within a predetermined tolerance.

[0064] The IREF1 current mirror circuit 660 operates to receive IREF1 at its first terminal 662, provide a first mirror current at its second terminal 664 in response to IREF1 and a scaling control signal, and provide a second mirror current at its third terminal 665 in response to IREF1 and the scaling control signal. The IREF2 current mirror circuit 670 operates to receive IREF2 at its first terminal 672, provide a first mirror current at its second terminal 674 in response to IREF2 and a scaling control signal, and provide a second mirror current at its third terminal 676 in response to IREF2 and the scaling control signal. The IREF3 current mirror circuit 680 operates to receive IREF3 at its first terminal 682, provide a first mirror current at its second terminal 684 in response to IREF3 and a scaling control signal, and provide a second mirror current at its third terminal 686 in response to IREF3 and the scaling control signal. In some examples, scaling control signals for IREF1 current mirror circuit 660, IREF2 current mirror circuit 670, and IREF3 current mirror circuit 680 are obtained by testing AMR sensor circuit 100E at different temperatures and generating scaling control signals in response to the test results. As used herein, "scaling control signals" refer to transistor gate control signals used to select which transistors of a scalable current mirror topology are turned on or off.

[0065] AMR sensor 606 operates to: receive VBIAS at its first terminal 106A; provide a first AMR result at its second terminal 106B in response to VBIAS and the ambient magnetic field; and provide a second AMR result at its third terminal 106C in response to VBIAS and the ambient magnetic field. The first and second AMR results vary as a function of the resistivity of the first set of AMR components 104A-104D, which varies depending on the orientation of the set of AMR components 104A-104D relative to the magnetic flux direction of the ambient magnetic field.

[0066] exist Figure 6 In the example, V os1 and V os2 is added to the differential output of the AMR sensor 606 (SIN+ minus SIN-). Again, V os1 represents the offset originally generated by the AMR sensor 606. V os2 Indicates the tracking and offset of V os1 The input reference equivalent offset. Figure 6 In the example, V os2Generated by the AFE operational amplifier (including transistors MP13, MP0A, MP0B, MN0A, MN) and related trimming circuits. The example trimming circuit includes IREF1 generation circuit 628A, IREF2 generation circuit 638A, IREF3 generation circuit 648A, IREF1 current mirror circuit 660A, IREF2 current mirror circuit 670A, IREF3 current mirror circuit 680A, and constant Gm bias current generation circuit 654A. In some examples, V os1 is modeled as:

[0067] V os1 =V os0 *VBIAS+TC1*(Temp-27), Equation (1)

[0068] Where V os0 can be a random value within + / -2.91mV / V, TC1 can be a random value within + / -0.072mV / C, and Temp is the measured temperature. In equation (1), the first term (V os0 *VBIAS) is a random variable that depends only on VBIAS, and the second term TC1*(Temp-27) is another random variable that depends only on temperature drift. These two terms are completely independent or uncorrelated with each other.

[0069] Figures 7A to 7G is shown with Figure 6 FIG. 1 is a schematic diagram of an example trimming circuit associated with an AMR sensor circuit 100E. Fig. 7A , an IREF1 generating circuit 628A is shown, which is Figure 6 An example of IREF1 generation circuit 628 in FIG. Figure 7B , a constant Gm bias current generating circuit 654A is shown, which is Figure 6 An example of a constant Gm bias current generating circuit 654 in FIG. Figure 7C , an IREF2 generating circuit 638A is shown, which is Figure 6 An example of IREF2 generation circuit 638 in FIG. Fig.7D , an IREF3 generating circuit 648A is shown, which is Figure 6 An example of IREF3 generation circuit 648 in FIG. Fig. 7E , an IREF2 current mirror circuit 670A is shown, which is Figure 6 An example of IREF2 current mirror circuit 670 in FIG. Figure 7F , an IREF1 current mirror circuit 660A is shown, which is Figure 6 An example of IREF1 current mirror circuit 660 is shown in FIG. Figure 7G , an IREF3 current mirror circuit 680A is shown, which is Figure 6An example of the IREF3 current mirror circuit 680 in FIG.

[0070] exist Fig. 7A In the example of FIG. 6 , the IREF1 generating circuit 628A has a first terminal 630 and a second terminal 632 and includes an operational amplifier OPA2, a transistor MP21, a resistor R 1B , R 2A and R 2B The transistor MP21 is a PMOS transistor having a first terminal, a second terminal, and a control terminal. The operational amplifier OPA2 has an inverting (“-”) input, a non-inverting (“+”) input, and an output. The resistor R 1B , R 2A and R 2B Each of has a respective first terminal and a respective second terminal.

[0071] exist Fig. 7A In the example of IREF1 generation circuit 628A, the first terminal 630 is coupled to the resistor R 1B and R 2A The first terminal of the resistor R 2A The second terminal is coupled to the resistor R 2B The first terminal of the resistor R 2B The second terminal of the resistor R is coupled to the ground terminal or ground. 2A The second terminal and resistor R 2B The first terminal of the resistor R is coupled to the non-inverting ("+") input of the operational amplifier OPA2. 1B The second terminal of IREF1 generating circuit 628A is coupled to the inverting ("-") input of operational amplifier OPA2 and the first terminal of transistor MP21. The output of operational amplifier OPA2 is coupled to the control terminal of transistor MP21. The second terminal 632 of IREF1 generating circuit 628A is coupled to the second terminal of transistor MP21. Fig. 7A In the example of IREF1, the IREF1 generating circuit 628A operates to: receive VBIAS at its first terminal 630; and generate VBIAS based on the operational amplifier OPA2 and the resistor R 2A , R 2B and R 1B The arrangement provides a target IREF1 reference at its second terminal 632 that is linearly proportional to VBIAS.

[0072] exist Figure 7B In the example of FIG. 6 , the constant Gm bias current generating circuit 654A has a first terminal 656 and a second terminal 658 and includes a resistor R in the arrangement shown. 1A and transistors MP11, MP12, MN11 and MN12. Resistor R 1AEach of the transistors MP11 and MP12 is a PMOS transistor having a corresponding first terminal, a corresponding second terminal and a corresponding control terminal. Each of the transistors MN11 and MN12 is an NMOS transistor having a corresponding first terminal, a corresponding second terminal and a corresponding control terminal.

[0073] The first terminal 656 of the constant Gm bias current generating circuit 654A is coupled to the resistor R 1A and a first terminal of the transistor MP12. 1A The second terminal of the transistor MP11 is coupled to the first terminal of the transistor MP11. The second terminal of the transistor MP11 is coupled to the first terminal of the transistor MN11 and the control terminals of the transistors MN11 and MN12. The second terminal of the transistor MP12 is coupled to the first terminal of the transistor MN12, the control terminals of the transistors MP11 and MP12, and the second terminal 658 of the constant Gm bias current generating circuit 654A. The second terminals of the transistors MN11 and MN12 are coupled to the ground terminal or ground. Figure 7B In the example of constant Gm bias current generating circuit 654A operates to: receive VBIAS at its first terminal 656; and based on resistor R 1A and an arrangement of transistors MP11, MP12, MN11 and MN12 providing a gate control signal at a second terminal 658 thereof in response to VBIAS and a target constant Gm bias setting.

[0074] exist Figure 7C In the example of FIG. 6 , the IREF2 generating circuit 638A has a first terminal 640 and a second terminal 642 and includes transistors MP31, MP32, MP33, Q1 and Q2 and a resistor R in the arrangement shown. 1C Each of the transistors MP31, MP32, and MP33 is a PMOS transistor having a respective first terminal, a respective second terminal, and a respective control terminal. Each of the transistors Q1 and Q2 is an NPN bipolar junction transistor (BJT) having a respective first terminal, a respective second terminal, and a respective control terminal. The resistor R 1C The device has a first terminal and a second terminal.

[0075] The first terminal 640 of the IREF2 generating circuit 638A is coupled to the first terminals of transistors MP31, MP32, and MP33. The second terminal of transistor MP31 is coupled to the first terminal of transistor Q1 and the control terminals of transistors Q1 and Q2. The second terminal of transistor Q1 is coupled to the ground terminal or ground. The second terminal of transistor M32 is coupled to the first terminal of transistor Q2 and the control terminals of transistors MP31, MP32, and MP33. The second terminal of transistor Q2 is coupled to the resistor R1C The first terminal of the resistor R 1C The second terminal of IREF2 generating circuit 638A is coupled to the ground terminal or ground. The second terminal 642 of IREF2 generating circuit 638A is coupled to the second terminal of transistor MP33. Figure 7C In the example of , IREF2 generating circuit 638A operates to: receive VBIAS at its first terminal 640; force two equal currents into bipolar devices Q1 and Q2 having different emitter areas; and based on transistors MP31, MP32, MP33, Q1, Q2 and resistor R 1C The arrangement provides a target proportional to absolute temperature (PTAT) current IREF2 reference.

[0076] exist Fig.7D In the example of FIG. 6 , the IREF3 generating circuit 648A has a first terminal 650 and a second terminal 652 and includes an operational amplifier OPA3, transistors MP41, MP42, MN42, and a resistor R 1D Operational amplifier OPA3 has an inverting ("-") input, a non-inverting ("+") input, and an output. Each of transistors MP41 and MP42 is a PMOS transistor having a respective first terminal, a respective second terminal, and a respective control terminal. Transistor MN42 is an NMOS transistor having a first terminal, a second terminal, and a third terminal. Resistor R 1D The device has a first terminal and a second terminal.

[0077] The first terminal 650 of the IREF3 generation circuit 648A is coupled to the first terminals of transistors MP41 and MP42. The second terminal of transistor MP41 is coupled to the first terminal of transistor MN42 and the control terminals of transistors MP41 and MP42. The second terminal of transistor MN42 is coupled to the resistor R 1D The first terminal of the resistor R is connected to the inverting (“-”) input of the operational amplifier OPA3. 1D The second terminal of the operational amplifier OPA3 is coupled to the ground terminal or ground. The non-inverting ("+") input of the operational amplifier OPA3 receives V BG The second terminal 652 of the IREF3 generating circuit 648A is coupled to the second terminal of the transistor MP42. Fig.7D In the example of , IREF3 generating circuit 648A operates to: receive VBIAS at its first terminal 650; and generate VBIAS based on operational amplifier OPA3, transistors MP41, MP42, MN42 and resistor R 1D The arrangement provides IREF3 at its second terminal 652 in response to VBIAS and a target IREF3 reference. Fig.7DIn some examples, the target IREF3 reference is adjustable by controlling the control terminal voltage of transistor MN42. BG With resistor R 1D The operational amplifier OPA3 adjusts the voltage at the control terminal of the transistor MN42 by comparing the voltage at the first terminal of the transistor MN42. The IREF3 generated by the control of the transistor MN42 is mirrored to the second terminal 652 by the transistors MP41 and MP42.

[0078] exist Fig. 7E In the example of , IREF2 current mirror circuit 670A has a first terminal 672, a second terminal 674, a third terminal 676, and a fourth terminal 678, and in the illustrated arrangement includes transistors MN31A, MN31B, MN31C, MN31D, MN31E, MN31F, and MN31G, and switches SW31B, SW31C, SW31D, SW31E, SW31F, and SW31G. Each of transistors MN31A, MN31B, MN31C, MN31D, MN31E, MN31F, and MN31G is an NMOS transistor having a respective first terminal, a respective second terminal, and a respective control terminal. In some examples, each of switches SW31B, SW31C, SW31D, SW31E, SW31F, and SW31G is an NMOS transistor. In other examples, PMOS transistors may be used for switches SW31B, SW31C, SW31D, SW31E, SW31F, and SW31G.

[0079] A first terminal 672 of the IREF2 current mirror circuit 670A is coupled to a first terminal of transistor MN31A and control terminals of transistors MN31A, MN31B, MN31C, MN31D, MN31E, MN31F, and MN31G. A first terminal of transistor MN31B is coupled to a first terminal of switch SW31B. A first terminal of transistor MN31C is coupled to a first terminal of switch SW31C. A first terminal of transistor MN31D is coupled to a first terminal of switch SW31D. A first terminal of transistor MN31E is coupled to a first terminal of switch SW31E. A first terminal of transistor MN31F is coupled to a first terminal of switch SW31F. A first terminal of transistor MN31G is coupled to a first terminal of switch SW31G. Second terminals of switches SW31B, SW31C, and SW31D are coupled to a third terminal 676 of the IREF2 current mirror circuit 670A. Second terminals of switches SW31E, SW31F, and SW31G are coupled to a second terminal 674 of the IREF2 current mirror circuit 670A. The second terminals of transistors MN31A, MN31B, MN31C, MN31D, MN31E, MN31F and MN31G are coupled to a ground terminal or ground. The control terminals of transistors SW31B, SW31C, SW31D, SW31E, SW31F and SW31G are controlled by EERPROM / OTP memory bits (not shown) that are programmed so that the overall offset is as close to zero as possible during the circuit testing phase. Fig. 7E In the example, the IREF2 current mirror circuit 670A operates to: receive IREF2 at its first terminal 672; provide a first mirror current at its second terminal 674 in response to IREF2 and a scaling control signal for switches SW31E, SW31F and SW31G; and provide a second mirror current at its third terminal 676 in response to IREF2 and a scaling control signal for switches SW31B, SW31C and SW31D.

[0080] exist Figure 7FIn the example of , IREF1 current mirror circuit 660A has a first terminal 662, a second terminal 664, a third terminal 665 and a fourth terminal 668, and in the illustrated arrangement includes transistors MN21A, MN21B, MN21C, MN21D, MN21E, MN21F and MN21G and switches SW21B, SW21C, SW21D, SW21E, SW21F and SW21G. Each of transistors MN21A, MN21B, MN21C, MN21D, MN21E, MN21F and MN21G is an NMOS transistor having a respective first terminal, a respective second terminal and a respective control terminal. In some examples, each of switches SW21B, SW21C, SW21D, SW21E, SW21F and SW21G is an NMOS transistor having a respective first terminal, a respective second terminal and a respective control terminal. In other examples, PMOS transistors may be used for switches SW21B, SW21C, SW21D, SW21E, SW21F, and SW21G.

[0081] A first terminal 662 of the IREF1 current mirror circuit 660A is coupled to a first terminal of transistor MN21A and control terminals of transistors MN21A, MN21B, MN21C, MN21D, MN21E, MN21F, and MN21G. A first terminal of transistor MN21B is coupled to a first terminal of switch SW21B. A first terminal of transistor MN21C is coupled to a first terminal of switch SW21C. A first terminal of transistor MN21D is coupled to a first terminal of switch SW21D. A first terminal of transistor MN21E is coupled to a first terminal of switch SW21E. A first terminal of transistor MN21F is coupled to a first terminal of switch SW21F. A first terminal of transistor MN21G is coupled to a first terminal of switch SW21G. Second terminals of switches SW21B, SW21C, and SW21D are coupled to a second terminal 664 of the IREF1 current mirror circuit 660A. Second terminals of switches SW21E, SW21F, and SW21G are coupled to a third terminal 665 of the IREF1 current mirror circuit 660A. The second terminals of transistors MN21A, MN21B, MN21C, MN21D, MN21E, MN21F and MN21G are coupled to a ground terminal or ground. The control terminals of switches SW21B, SW21C, SW21D, SW21E, SW21F and SW21G are controlled based on EEPROM / OTP memory bits (not shown) that are programmed so that the overall offset is as close to zero as possible during the circuit testing phase. Figure 7FIn the example, the IREF1 current mirror circuit 660A operates to: receive IREF1 at its first terminal 662; provide a first mirror current at its second terminal 664 in response to IREF1 and the scaling control signal for switches SW21B, SW21C and SW21D; and provide a second mirror current at its third terminal 665 in response to IREF1 and the scaling control signal for switches SW21E, SW21F and SW21G.

[0082] exist Figure 7G In the example of , IREF3 current mirror circuit 680A has a first terminal 682, a second terminal 684, a third terminal 686, and a fourth terminal 688, and in the illustrated arrangement includes transistors MN41A, MN41B, MN41C, MN41D, MN41E, MN41F, and MN41G, and switches SW41B, SW41C, SW41D, SW41E, SW41F, and SW41G. Each of transistors MN41A, MN41B, MN41C, MN41D, MN41E, MN41F, and MN41G is an NMOS transistor having a respective first terminal, a respective second terminal, and a respective control terminal. In some examples, each of switches SW41B, SW41C, SW41D, SW41E, SW41F, and SW41G is an NMOS transistor. In other examples, PMOS transistors may be used for switches SW41B, SW41C, SW41D, SW41E, SW41F, and SW41G.

[0083] A first terminal 682 of the IREF3 current mirror circuit 680A is coupled to a first terminal of transistor MN41A and control terminals of transistors MN41A, MN41B, MN41C, MN41D, MN41E, MN41F, and MN41G. A first terminal of transistor MN41B is coupled to a first terminal of switch SW41B. A first terminal of transistor MN41C is coupled to a first terminal of switch SW41C. A first terminal of transistor MN41D is coupled to a first terminal of switch SW41D. A first terminal of transistor MN41E is coupled to a first terminal of switch SW41E. A first terminal of transistor MN41F is coupled to a first terminal of switch SW41F. A first terminal of transistor MN41G is coupled to a first terminal of switch SW41G. Second terminals of switches SW41B, SW41C, and SW41D are coupled to a second terminal 684 of the IREF3 current mirror circuit 680A. Second terminals of switches SW41E, SW41F, and SW41G are coupled to a third terminal 686 of the IREF3 current mirror circuit 680A. The second terminals of transistors MN41A, MN41B, MN41C, MN41D, MN41E, MN41F, and MN41G are coupled to a ground terminal or ground. The control terminals of transistors SW41B, SW41C, SW41D, SW41E, SW41F, and SW41G are controlled by EEPROM / OTP memory bits (not shown) that are programmed so that the overall offset is as close to zero as possible during the circuit test phase. In some examples, the IREF3 current mirror circuit 680 operates to: receive IREF3 at its first terminal 682; provide a first mirror current at its second terminal 684 in response to IREF3 and a scaling control signal for switches SW41B, SW41C, and SW41D; and provide a second mirror current at its third terminal 686 in response to IREF3 and a scaling control signal for switches SW41E, SW41F, and SW41G.

[0084] In some examples, the scaling control signals for IREF1 current mirror circuit 660A, IREF2 current mirror circuit 670A, and IREF3 current mirror circuit 680A are obtained by testing the AMR sensor circuit 100F at different temperatures and generating scaling control signals in response to the test results. When the AMR sensor is biased with VBIAS, it generates sine / cosine output signals (SIN+, SIN-, COS+, and COS-) relative to the position of the external magnet. The sensed sine / cosine signals are processed to calculate the magnetic position angle. During the AMR sensing operation, the offset error (e.g., V os1 ) is added to the sine / cosine signal. The calibration process described in this article adjusts V os2 To offset V os1 To improve the accuracy of position angle calculation.

[0085] In some instances, Figures 7A to 7G The trimming circuit and Figure 6 The AFE op amp input stage is used together to generate V os2 To track and offset V os1 Again, the AMR sensor 606 generates an offset V that is added to its differential output (SIN+ minus SIN-). os1 , where V os1 Described in equation (1). The AFE operational amplifier input stage includes input pair transistors MP0A and MP0B, and load transistors MN0A and MN0B. The input stage is biased with a tail current (I_TAIL), and currents I_P and I_N are nominally balanced before offset trimming. Offset trim cancellation is performed at the AFE operational amplifier input stage formed using tail current transistor MP13, input pair transistors MP0A and MP0B, and load pair transistors MN0A, MN0B. In some instances, the two terms in equation (1) are trimmed independently. Again, the first term of equation (1) is a VBIAS dependent random variable, and the second term of equation (1) is a temperature drift dependent random variable.

[0086] In some instances, Figure 7B The constant Gm bias current generating circuit 654A provides two equal currents I1 and I2, which are forced into transistors MP11 and MP12. Transistor MP11 may have a size P (W / L), where P is an integer greater than 1, W is the width, and L is the length. Transistor MP12 may have a size W / L. The equal currents I1 and I2 are ensured by the current mirror including MN11 and MN12. Each of transistors MN11 and MN12 may have a size W / L. The gate-to-source voltage (V GS ) provides a difference across the resistor R 1A Therefore:

[0087]

[0088] In some examples, transistors MP11 and MP12 are matched PMOS transistors with similar threshold voltages: V T,MP11 =V T,MP12 In such an example, I1 and I2 can be calculated using equation (2b) as:

[0089]

[0090] Where k' is the Boltzmann constant. The Gm of transistor MP12 can be calculated as:

[0091]

[0092] Thus, a constant gm bias current I2 is generated (independent of the MOS process and temperature and related to the resistor R 1A This bias current is mirrored to the tail current of the AFE op amp for biasing the input transistor pair MP0A and MP0B of the AFE op amp. In some examples, transistors MP0A and MP0B have similar constant Gm, which varies with 1 / R over process and temperature. 1A If the size ratio P between MP11 and MP12 is selected to be 4, and the current through MP12 is amplified 2N times (by using the current mirror formed by transistors MP12 and MP13), then transistors MP0A and MP0B may have a size N times larger than the size of transistor MP12. In this case,

[0093]

[0094] In some examples, IREF1 generation circuit 628A includes a voltage divider (eg, resistor R 2A and R 2B ) to divide VBIAS to provide voltage V1 = [R 2A / (R 2A +R 2B )]*VBIAS. Fig. 7A In the example, V1 is buffered by operational amplifier OPA2 to drive resistor R 1B . R 1B The reference current on IREF1 = [R 2A / (R 2A +R 2B )]*VBIAS / R 1B If R 2A =R 2B , then IREF1 can be defined as:

[0095]

[0096] In some examples, IREF2 generation circuit 638A provides IREF2 as a PTAT reference current. Figure 7C In the example of FIG. 1 , a current mirror including transistors MP31 and MP32 provides equal current I injected into transistors Q1 and Q2. C_Q1 and I C_Q2 In some examples, transistor Q1 has an emitter area A, and transistor Q2 has an emitter area MA, where M is an integer greater than 1. The base-to-emitter voltage (V BE ) provides a resistor R 1C In some examples, I C_Q1 is given as:

[0097]

[0098] Among them I S is the saturation current related to the emitter area. In this case, V be,Q1 -V be,Q2 is given as:

[0099]

[0100] and IREF2 is given by:

[0101]

[0102] Where k is the Boltzmann constant, T is the absolute temperature, and q is the charge of the electron.

[0103] Therefore, in some examples, IREF2 is composed of resistor R 1C Defined and copied by mirror MP32 to MP33 as PTAT current. Since absolute temperature T=temp+273=temp-27+300, equation (4C) can be rewritten as:

[0104]

[0105] The first term in equation (4d) is proportional to (temp-27). Therefore, the first term in equation (4d) has a format similar to the second term in equation (1). The first term in equation (4d) can therefore be used to cancel the second term in equation (1). The second term in equation (4d) can be further canceled with a constant reference current IREF3.

[0106] In some examples, IREF3 generation circuit 648A provides IREF3 based on the following formula:

[0107]

[0108] In some examples, IREF1 (with VBIAS / R 1B proportional to T / R 1C proportional to V BG / R 1DThe current mirror circuits 660A and 670A are provided by IREF1, IREF2, and IREF3 current mirror circuits. In some examples, the current mirror circuits are programmed using values ​​stored by an electrically erasable programmable read-only memory (EEPROM) and / or a one-time programmable (OTP) value at the AFE operational amplifier NMOS load side. In some examples, the IREF1 current mirror circuit 660A includes transistors MN21A, MN21B (x4), MN21C (x2), MN21D (x1), MN21E (x1), MN21F (x2), and MN21G (x4) having sizes that are binary scaled on both the positive and negative sides of the AFE operational amplifier input stage. The current that passes through the mirrors and contributes to the current difference between I_P and I_N is controlled by switches SW21B, SW21C, SW21D, SW21E, SW21F, and SW21G. In some examples, these switches are turned on or off by a 4-bit memory OTP / EEPROM trim code b[3:0]. Figures 7E to 7G The memory OTP / EEPROM bits are not shown.

[0109] In some examples, the most significant bit (MSB) b[3] of the trim code b[3:0] is used to control the offset trim direction. For example, switches SW21B, SW21C, SW21D are turned on while switches SW21E, SW21F, SW21G are turned off to select a first offset trim direction. To select a second offset trim direction, SW21B, SW21C, SW21D may be turned off while switches SW21E, SW21F, and SW21G are turned on. The least significant bit (LSB) b[2:0] is used for binary scale programming. In some examples, b[2] controls the X4 scale switches SW21B and SW21G, b[1] controls the X2 scale switches SW21C and SW21F, and b[0] controls the X1 scale switches SW21D and SW21E.

[0110] In some examples, the trimming circuitry associated with IREF2 can be programmed using OTP / EEROM memory trim code d[3:0]. The trimming circuitry associated with IREF3 can be programmed using OTP / EEPROM memory trim code c[3:0]. The overall trimming action results in the current difference between I_P and I_N being given by:

[0111]

[0112] To achieve the target equivalent offset V os2, the trimming action can be referred to as the input node, and the AFE operational amplifier input stage current difference (I_P-I_N) in equation (6) can be divided by the input pair Gm in equation (2e). In some examples, the resistor R in equation (2e) 1A and the resistor R in equation (6) 1B , R 1C and R 1D are resistors of the same type and have matching layout and value. In this example, R 1A , R 1B , R 1C and R 1D Any mismatch between them tracks each other over manufacturing process variations and temperature changes and can be eliminated in a first order.

[0113] In some examples, the current offset I_P-I_N is referred to as the AFE operating input node to determine the equivalent offset V os2 In these instances:

[0114]

[0115] In equation (7), V os2 has four terms. The first term is proportional to VBIAS. The second term is proportional to the temperature drift (temp-27). Therefore, for V os2 The first and second terms of correspond to the terms for V in equation (1) os1 For V os2 The third term of is the side effect constant to be eliminated by the fourth term. The trim bits b[3:0], d[3:0], and c[3:0] are used to balance V expressed in equation (1). os1 Randomness. os2 The result is only related to the current mirror ratio N (e.g., the size of transistor MP13 relative to the size of transistor MP12, and / or the size of transistor MP0A relative to the size of transistor MP12) and the emitter area ratio M (NPN devices Q2 and Q1). Here, N and M are integer numbers that can be easily implemented in circuit design and layout to maintain high accuracy by using multiple copies of unit components. Other parameters in equation (6), such as k (Boltzmann constant) and q (charge of electron), are physical constants. Therefore, trimming the circuit system can achieve relatively high accuracy.

[0116] Once V in equation (1) os1 The randomness of is determined by the trim bits b[3:0], and the randomness of TC1 is determined by the trim bits d[3:0] in equation (6), then V os2 and V os1Track each other and cancel over process and temperature variations as well as VBIAS changes.

[0117] As indicated in equations (4c) and (4d), the trim code d[3:0] moves the offset TC ramp, which has an offset zero crossing at temperature = -273C. The DC shift of the second term in equation (4d) causes an offset drift from -40C to 150C in the positive or negative range. Therefore, even if V os1 Trimming techniques are also effective when drift crosses the zero line.

[0118] Figures 8A to 8D 9 are graphs illustrating an example AMR sensor circuit offset trimming procedure. In some examples, the example AMR sensor signal involves two temperature trimming processes. Figures 8A to 8D , four cases 800, 810, 820, and 830 of an AMR sensor offset trimming step are plotted. In each plot, the vertical axis is the offset voltage with polarity definition and the horizontal axis is the temperature range from -40C degrees to 150C degrees.

[0119] exist Fig. 8A In the case of 800, the example AMR sensor is at room temperature and has a positive temperature coefficient (TC) (i.e., V os1 increases with increasing temperature) with positive V os1 In some examples, the first trimming operation (trimming at temperature = 27°C) involves adjusting the IREF1 scaling (e.g., 1X, 2X, or 4X scaling) using the associated trim code b[3:0]. The first trimming operation adjusts the IREF1 scaling so that the trim offset in the negative direction offsets the V os1 Using equation (7), applying the trimming code b[3]=1 results in (-1) b[3] = -1. Therefore, the offset trim contribution of b[2:0] is in the negative direction to offset the positive V os1 In the second trimming operation, the temperature is moved from 27°C to 150°C. Regarding the second trimming operation, V os1 is no longer in balance with IREF1 because V os1 As temperature increases, the drift is higher. Therefore, the IREF2 (PTAT current) scaling is adjusted (e.g., 1X, 2X, or 4X scaling) using the associated trim code d[3:0] during the second trim operation. Applying d[3]=1 results in a d[2:0] offset trim contribution in the negative direction. And, adjusting trim code c[3:0] scales IREF3 up. Therefore, the combined effect of scaling IREF1, IREF2, and IREF3 results in a cancellation of V over the full temperature range. os1 V os2In the first trimming operation, only IREF1 related trimming code b[3:0] is used at temperature = 27°C. In the second trimming operation at temperature = 150°C, IREF2 related trimming code d[3:0] and IREF3 related trimming code c[3:0] are used. This is because in the second trimming operation, the trimmed offset is the only net drift caused by the temperature change from 27°C to 150°C. The trimming code c[3:0] is adjusted in the second trimming operation to compensate for the side effects caused by the IREF2 related trimming code d[3:0].

[0120] exist Figure 8B In case 810, the example AMR sensor has a high sensitivity at room temperature and negative TC (i.e., V os1 decreases with increasing temperature) under positive V os1 In some examples, the first trimming operation (trimming at temperature = 27°C) involves adjusting the IREF1 scaling using the associated trim code b[3:0]. The first trimming operation adjusts the IREF1 scaling so that the trim offset in the negative direction offsets the V os1 Using equation (7), applying the trimming code b[3]=1 results in (-1) b[3] = -1. Therefore, the offset trim contribution of b[2:0] is in the negative direction to offset the positive V os1 In the second trimming operation, the temperature is moved from 27°C to 150°C. Regarding the second trimming operation, at temperature = 150°C, V os1 is no longer in balance with IREF1 because V os1 As temperature increases the drift is lower. Therefore, the IREF2 (PTAT current) scaling is adjusted during the second trim operation using the associated trim code d[3:0]. Applying d[3]=0 results in (-1) d[3] = +1 and results in a d[2:0] offset trim contribution with a positive direction. And, the IREF3 scaling is adjusted in the negative direction using trim code c[3:0] (e.g., 1X, 2X, or 4X scaling). Therefore, the combined effect of scaling IREF1, IREF2, and IREF3 results in a cancellation of V over the full temperature range. os1 V os2 In the first trimming operation, only IREF1 related trimming code b[3:0] is used at temperature = 27°C. In the second trimming operation at temperature = 150°C, IREF2 related trimming code d[3:0] and IREF3 related trimming code c[3:0] are used. This is because in the second trimming operation, the trimmed offset is the only net drift caused by the temperature change from 27°C to 150°C. The trimming code c[3:0] is adjusted in the second trimming operation to compensate for the side effects caused by the IREF2 related trimming code d[3:0].

[0121] exist Figure 8C In case 820, the example AMR sensor is at room temperature and has a positive temperature coefficient (TC) (i.e., V os1 increases with increasing temperature) with negative V os1 In some examples, the first trimming operation (trimming at temperature = 27°C) involves adjusting the IREF1 scaling using the associated trim code b[3:0]. The first trimming operation adjusts the IREF1 scaling so that the trim offset in the positive direction offsets the V os1 Using equation (7), applying the trimming code b[3]=0 results in (-1) b[3] = 1. Therefore, the offset trim contribution of b[2:0] is in the positive direction to offset the negative V os1 In the second trimming operation, the temperature is moved from 27°C to 150°C. Regarding the second trimming operation, V os1 is no longer in balance with IREF1 because V os1 As temperature increases, the drift is higher. Therefore, the IREF2 (PTAT current) scaling is adjusted during the second trim operation using the associated trim code d[3:0]. Applying d[3]=1 results in a d[2:0] offset trim contribution in the negative direction. And, adjusting trim code c[3:0] moves IREF3 upward. Therefore, the combined effect of scaling IREF1, IREF2, and IREF3 results in a cancellation of V over the full temperature range. os1 V os2 In the first trimming operation, only IREF1 related trimming code b[3:0] is used at temperature = 27°C. In the second trimming operation at temperature = 150°C, IREF2 related trimming code d[3:0] and IREF3 related trimming code c[3:0] are used. This is because in the second trimming operation, the trimmed offset is the only net drift caused by the temperature change from 27°C to 150°C. The trimming code c[3:0] is adjusted in the second trimming operation to compensate for the side effects caused by the IREF2 related trimming code d[3:0].

[0122] exist Fig.8D In case 830, the example AMR sensor has a high sensitivity at room temperature and negative TC (i.e., V os1 decreases with increasing temperature) under negative V os1 In some examples, the first trimming operation (trimming at temperature = 27°C) involves adjusting IREF1 scaling using the associated trim code b[3:0]. The first trimming operation adjusts IREF1 so that the trimming offset in the positive direction offsets the V os1 Using equation (7), applying the trimming code b[3]=0 results in (-1) b[3] = 1. Therefore, the offset trim contribution of b[2:0] is in the positive direction to offset the negative V os1In the second trimming operation, the temperature is moved from 27°C to 150°C. Regarding the second trimming operation, V os1 At temperature = 150°C, it is no longer in equilibrium with IREF1 because V os1 As temperature increases the drift is lower. Therefore, the IREF2 (PTAT current) scaling is adjusted during the second trim operation using the associated trim code d[3:0]. Applying d[3]=0 results in (-1) d[3] = +1 and results in a d[2:0] offset trim contribution with a positive direction. And, IREF3 scaling is adjusted in the negative direction using trim code c[3:0]. Therefore, the combined effect of scaling IREF1, IREF2, and IREF3 results in a cancellation of V over the full temperature range. os1 V os2 In the first trimming operation, only IREF1 related trimming code b[3:0] is used at temperature = 27°C. In the second trimming operation at temperature = 150°C, IREF2 related trimming code d[3:0] and IREF3 related trimming code c[3:0] are used. This is because in the second trimming operation, the trimmed offset is the only net drift caused by the temperature change from 27°C to 150°C. The trimming code c[3:0] is adjusted in the second trimming operation to compensate for the side effects caused by the IREF2 related trimming code d[3:0].

[0123] exist Fig. 9 In case 900, the example AMR sensor is at room temperature and non-zero positive TC (i.e., V os1 increases with increasing temperature) with zero (or very close to zero) V os1 Therefore, for this example AMR sensor, the first term in equation (1) is zero, but the second term in equation (1) is not zero. In this case, V os1 Crosses the zero line at temperature = 27. Therefore, V os2 (For example, V os1 The mirror image with respect to the zero line) will also have a zero crossing at the same temperature point but in the opposite direction. However, the EEPROM / OTP offset trim bits are only programmed once before the associated product is shipped. Once the EEPROM / OTP is programmed, the IREF2 trim bits (e.g., temperature drift related trim bits, including the sign bit) are fixed and when V os1 When changing its direction across the zero line, it does not change. To solve this problem, Fig. 9 As shown in os2 Use a combination of scaled IREF2 and IREF3 to offset V os1This operation can be seen using equation (4c) and equation (4d). By using T = Temp + 273 = (Temp - 27) + 300, where (Temp - 27) reflects the actual temperature difference drift from 27C degrees, the temperature constant shift of 300 degrees moves the IREF2 zero crossing to temperature = -273°C (i.e., 0T degrees absolute temperature), which is completely outside the target operating temperature range (e.g., -50°C to 150°C). Therefore, the second term in equation (4d) (i.e., the constant shift term) is eliminated by the IREF3 trim bit. At the same time, the IREF2 (PTAT current) related offset trim is in the positive half plane or the negative half plane and does not cross line zero in the target operating temperature range. Fig. 9 The description applies to the case with zero space-temperature offset and non-zero negative TC AMR offset. This means that even if V os1 If the drift crosses the zero line, the offset correction technique is still effective.

[0124] Fig.10 1 is a graph 1000 showing an example trimming process for an AMR sensor circuit. In steps 1 and 2 of the trimming process of graph 1000 (e.g., from 0 ms to 0.25 ms), the output stage offset and common mode voltage are trimmed. In step 3 of the trimming process of graph 1000 (e.g., from 0.25 ms to 0.44 ms), the first channel (e.g., channel A or the sine channel) is trimmed at T=27°C. By applying an external magnetic angle of 0 degrees, the sine channel signal sin(2θ)=0. Therefore, anything measured at the output stage is only the offset of the first channel (e.g., the sine channel) amplified with a certain gain. In step 3, the initial first channel offset indicated by the arrow (approximately + / -250 mV) is trimmed, resulting in a residual offset of less than + / -10 mV at the end of step 3. A similar trimming operation is performed for the second channel (e.g., channel B or cosine channel) in step 4 of the trimming process of graph 1000 (e.g., from 0.44 ms to 0.64 ms). By applying an external magnetic angle of +45 degrees, cos(2θ)=0. Therefore, anything measured at the output stage is only the second channel offset amplified by some gain. In step 4, the initial second channel offset indicated by the arrow (approximately + / -250 mV) is trimmed, resulting in a residual offset of less than + / -10 mV at the end of step 4.

[0125] In step 5 of the trimming process of graph 1000 (e.g., from 0.64 ms to 0.92 ms), the temperature is increased from a first target temperature (e.g., 27° C.) to a second target temperature (e.g., 150° C.), and the first channel offset drift is trimmed, resulting in a residual offset of less than + / -10 mV at the end of step 5. In step 6 of the trimming process of graph 1000 (e.g., from 0.92 ms to 1.21 ms), the temperature is increased from a first target temperature (e.g., 27° C.) to a second target temperature (e.g., 150° C.). Thus, the second channel offset drift is trimmed, resulting in a residual offset of less than + / -10 mV at the end of step 6. In step 7 of the trimming process of graph 1000 (e.g., starting at 1.21 ms), the trimming process is complete, and a magnetic field rotation (e.g., 2 kHz rotation) begins. As shown in graph 1000, the sine / cosine wave zero crossings are all clearly aligned at one point close to zero. This is because the first channel offset and the second channel offset have been trimmed. Only a small amount of residual offset (e.g., less than + / -10mV) remains at the zero crossing. Comparing the offset residual (e.g., less than + / -10mV) with the signal amplitude (+ / -3V), the ratio is about + / 10mV / 3V=0.33%, which is less than the target tolerance of 0.36%. Therefore, the position angle calculation error is less than 0.5 degrees.

[0126] Fig.11 1 is a flow chart illustrating an example AMR sensor calibration method 1100. The method 1100 is performed using an AMR sensor circuit (e.g., any of the AMR sensor circuits 100, 100A to 100F described herein) and a test circuit system. As shown, the method 1100 includes trimming an output stage of a common-mode voltage of a gain circuit at block 1102. At block 1104, a first AMR sensor offset is trimmed at a first target temperature (e.g., associated with a first channel such as a sine channel described herein). At block 1106, a second AMR sensor offset is trimmed at the first target temperature (e.g., associated with a second channel such as a cosine channel described herein). At block 1108, the first AMR sensor offset is trimmed at a second target temperature. At block 1110, the second AMR sensor offset is trimmed at a second target temperature.

[0127] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, if the intermediate component C does not change the functional relationship between device A and device B, device A is coupled to device B through an intermediate component C, so that device B is controlled by device A via the control signal generated by device A.

[0128] Additionally, in this specification, the statement “based on” means “based at least in part on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0129] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0130] As used herein, the terms "terminal", "node", "interconnect", "lead" and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components and / or conductors or their ends.

[0131] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0132] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuitry. For example, field effect transistors ("FETs") (e.g., NFETs or PFETs), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0133] In the claims reference may be made to the control terminal of a transistor and to its first and second terminals. In the context of a FET, the control terminal is the gate, and the first and second terminals are the drain and source. In the context of a BJT, the control terminal is the base, and the first and second terminals are the collector and emitter.

[0134] Reference herein to a FET being "on" means that there is a conduction channel for the FET and drain current can flow through the FET. Reference herein to a FET being "off" means that the conduction channel does not exist, and therefore drain current does not flow through the FET. However, an "off" FET can have current flowing through the body diode of the transistor.

[0135] The circuits described herein may be reconfigured to include additional components or different components to provide functionality at least partially similar to functionality available prior to component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0136] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0137] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / -10% of the parameter, or if the parameter is zero, within a reasonable range of values ​​about zero. Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A circuit comprising: an anisotropic magnetoresistive (AMR) sensor having a first terminal, a second terminal, a third terminal, and a fourth terminal; an operational amplifier having a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal of the operational amplifier being coupled to the second terminal of the AMR sensor, the second terminal of the operational amplifier being coupled to the third terminal of the AMR sensor; as well as A calibration circuit is coupled to the first terminal of the operational amplifier, the calibration circuit being configured to provide an adjustable offset trim voltage at the first terminal of the operational amplifier to cancel an offset voltage generated by the AMR sensor.

2. The circuit of claim 1 , further comprising a bias voltage source having a terminal, wherein the operational amplifier comprises a first transistor and a second transistor, the first transistor having a first terminal, a second terminal, and a control terminal, the second transistor having a first terminal, a second terminal, and a control terminal, the control terminal of the first transistor being coupled to the first terminal of the operational amplifier, and the control terminal of the second transistor being coupled to the second terminal of the operational amplifier.

3. The circuit of claim 2 , further comprising a bias voltage source having a terminal, wherein the calibration circuit comprises a first reference current generating circuit and a first current mirror circuit, the first reference current generating circuit having a first terminal and a second terminal, the first current mirror circuit having a first terminal, a second terminal and a third terminal, the first terminal of the first reference current generating circuit being coupled to the terminal of the bias voltage source, the second terminal of the first reference current generating circuit being coupled to the first terminal of the first current mirror circuit, the second terminal of the first current mirror circuit being coupled to the second terminal of the first transistor, and the third terminal of the first current mirror circuit being coupled to the second terminal of the second transistor.

4. The circuit of claim 3 , wherein the calibration circuit comprises a second reference current generating circuit and a second current mirror circuit, the second reference current generating circuit having a first terminal and a second terminal, the second current mirror circuit having a first terminal, a second terminal and a third terminal, the first terminal of the second reference current generating circuit being coupled to the terminal of the bias voltage source, the second terminal of the second reference current generating circuit being coupled to the first terminal of the second current mirror circuit, the second terminal of the second current mirror circuit being coupled to the second terminal of the first transistor, and the third terminal of the second current mirror circuit being coupled to the second terminal of the second transistor.

5. The circuit of claim 4 , wherein the calibration circuit comprises a third reference current generating circuit and a third current mirror circuit, the third reference current generating circuit having a first terminal and a second terminal, the third current mirror circuit having a first terminal, a second terminal and a third terminal, the first terminal of the third reference current generating circuit being coupled to the terminal of the bias voltage source, the second terminal of the third reference current generating circuit being coupled to the first terminal of the third current mirror circuit, the second terminal of the third current mirror circuit being coupled to the second terminal of the first transistor, and the third terminal of the third current mirror circuit being coupled to the second terminal of the second transistor.

6. The circuit of claim 2 , wherein the calibration circuit comprises a third transistor and a transconductance bias current generating circuit, the third transistor having a first terminal, a second terminal and a control terminal, the transconductance bias current generating circuit having a first terminal and a second terminal, the first terminal of the third transistor being coupled to the terminal of the bias voltage, the second terminal of the third transistor being coupled to the first terminals of the first transistor and the second transistor, the first terminal of the transconductance bias current generating circuit being coupled to the terminal of the bias voltage source, and the second terminal of the transconductance bias current generating circuit being coupled to the control terminal of the third transistor.

7. The circuit of claim 1, wherein the calibration circuit is configured to provide a positive offset trim voltage that increases with increasing temperature.

8. The circuit of claim 1, wherein the calibration circuit is configured to provide a positive offset trim voltage that decreases as temperature increases.

9. The circuit of claim 1, wherein the calibration circuit is configured to provide a negative offset trim voltage that increases with increasing temperature.

10. The circuit of claim 1, wherein the calibration circuit is configured to provide a negative offset trim voltage that decreases as temperature increases.

11. A circuit comprising: a first anisotropic magnetoresistive (AMR) sensor having a first terminal, a second terminal, a third terminal, and a fourth terminal; a first operational amplifier having a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal of the first operational amplifier being coupled to the second terminal of the first AMR sensor, the second terminal of the first operational amplifier being coupled to the third terminal of the first AMR sensor; a first calibration circuit coupled to the first terminal of the first operational amplifier, the first calibration circuit configured to provide a temperature varying offset trim voltage at the first terminal of the first operational amplifier; a second AMR sensor having a first terminal, a second terminal, a third terminal, and a fourth terminal, the second AMR sensor being rotated relative to the first AMR sensor; a second operational amplifier having a first terminal, a second terminal, a third terminal, and a fourth terminal, the first terminal of the second operational amplifier being coupled to the second terminal of the second AMR sensor, the second terminal of the second operational amplifier being coupled to the third terminal of the second AMR sensor; as well as A second calibration circuit is coupled to the first terminal of the second operational amplifier, the second calibration circuit being configured to provide a temperature varying offset trim voltage at the first terminal of the second operational amplifier.

12. The circuit of claim 11, further comprising position monitoring circuitry coupled to the third and fourth terminals of the first operational amplifier and to the third and fourth terminals of the second operational amplifier, the position monitoring circuitry configured to: receiving a first AMR result from the third terminal and the fourth terminal of the first operational amplifier; receiving a second AMR result from the third terminal and the fourth terminal of the second operational amplifier; as well as A position parameter is determined in response to the first AMR result and the second AMR result.

13. The circuit of claim 12, wherein the position monitoring circuitry comprises an analog-to-digital converter (ADC) and a processor, the ADC being configured to: digitizing a first AMR sensor result from the first AMR sensor; and digitizing a second AMR sensor result from the second AMR sensor; and The processor is configured to: receiving the digitized first AMR sensor result; receiving the digitized second AMR sensor result; as well as A position result is determined in response to the digitized first AMR sensor result and the digitized second AMR sensor result.

14. The circuit of claim 12 , further comprising a motor control circuit system coupled to the position monitoring circuit system, the motor control circuit system configured to provide a motor control signal in response to a position result determined by the position monitoring circuit system based on a first AMR sensor result from the first AMR sensor and a second AMR sensor result from the second AMR sensor.

15. The circuit of claim 11, wherein the first calibration circuit is configured to: trimming an output stage offset and a common-mode voltage of the first operational amplifier; trimming an offset voltage applied to the first operational amplifier at a first target temperature; trimming an offset voltage applied to the first operational amplifier at a second target temperature; And the second calibration circuit is configured to: trimming an output stage offset and a common-mode voltage of the second operational amplifier; trimming an offset voltage applied to the second operational amplifier at a first target temperature; and An offset voltage applied to the second operational amplifier is trimmed at a second target temperature.

16. An anisotropic magnetoresistive (AMR) sensor circuit, comprising: An AMR sensor configured to: Receive voltage; as well as providing an AMR sensor result in response to the voltage and the ambient magnetic field; a gain circuit coupled to the AMR sensor and configured to provide an amplified result in response to an AMR sensor result; as well as A calibration circuit is coupled to the gain circuit, the calibration circuit being configured to apply a correction to the amplified result, wherein the correction varies with temperature. 17 . The AMR sensor circuit of claim 16 , wherein the calibration circuit is configured to apply an offset trim voltage to the gain circuit, the offset trim voltage increasing as temperature increases.

18. The AMR sensor circuit of claim 16, wherein the calibration circuit is configured to apply an offset trim voltage to the gain circuit, the offset trim voltage decreasing as temperature increases.

19. The AMR sensor circuit of claim 16, wherein the calibration circuit is configured to apply an offset trim voltage to the gain circuit, the offset trim voltage being based on a first term and a second term, the first term being proportional to a bias voltage and the second term being proportional to a proportional to absolute temperature (PTAT) current.

20. The AMR sensor circuit of claim 19, wherein the calibration circuit is configured to apply a correction to the PTAT current based on trimming output stage offset and common mode voltage of the gain circuit; trimming an offset voltage applied to the gain circuit at a first target temperature; as well as An offset voltage applied to the gain circuit is trimmed at a second target temperature.

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