Programmable controller, electronic equipment and control method

Abstract

The invention discloses a programmable controller, electronic equipment and a control method. The programmable controller comprises a transmission component and a delay control component, wherein the transmission component is used for receiving a request for a processor; the delay control component is used for monitoring whether a wake-up condition is met or not, and the wake-up condition is related to the request; under the condition that the awakening condition is met, controlling the processor to enter a second state from a first state, and controlling the transmission component to send the request to the processor, so that the processor processes the request in the second state; wherein the power consumption of the processor in the first state is lower than that of the processor in the second state.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a programmable controller, an electronic device and a control method. Background Art

[0002] Currently, when computers perform various computing tasks, they require the support of various functional modules, such as processor cores, buses, phase-locked loops, memory, etc.

[0003] If the computer continues to perform various computing tasks, these functional modules will continue to be in operation, resulting in higher power consumption of the computer. Summary of the invention

[0004] In view of this, the present application provides a programmable controller, an electronic device and a control method as follows:

[0005] A programmable controller, comprising:

[0006] transmission components and delay control components;

[0007] Wherein, the transmission component is used to receive a request for a processor;

[0008] The delay control component is used to monitor whether a wake-up condition is met, and the wake-up condition is related to the request; if the wake-up condition is met, control the processor to enter the second state from the first state, and control the transmission component to send the request to the processor, so that the processor processes the request in the second state;

[0009] The power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

[0010] In the above programmable controller, preferably, the wake-up condition includes at least one of the following:

[0011] When the processor is in the first state, the request received by the transmission component satisfies a threshold parameter, and the request satisfies the threshold parameter including: the number of the requests reaches a preset request threshold, and / or the waiting time of a target request in the request reaches a time threshold;

[0012] The duration threshold and the request are independent of each other, or the duration threshold is determined by a delay parameter of the request, and the delay parameter represents a maximum waiting time that can be delayed for processing corresponding to the request.

[0013] The above-mentioned programmable controller, preferably, the delay control component adjusts the threshold parameter according to the processing parameter;

[0014] The processing parameters are parameters related to the timeliness requirement for request processing, and include at least one of the following: the reception rate of the request, the application type to which the request belongs, the current power consumption of the electronic device to which the processor belongs, and the resource utilization rate of the electronic device.

[0015] In the above-mentioned programmable controller, preferably, the delay control component comprises: an accumulator, a delay component;

[0016] The accumulator is used to receive the request sent by the transmission component, and perform numerical statistics on the requests received by the transmission component when the processor is in the first state to obtain a target value;

[0017] The delay component is used to obtain the target value from the accumulator, and when the target value meets the threshold parameter, control the processor to enter the second state from the first state, and control the transmission component to send the request to the processor.

[0018] The above-mentioned programmable controller preferably further comprises: an activation component;

[0019] Among them, the activation component is connected to the delay control component; the delay control component is also used to control the activation component to send an activation signal to the task execution component when the wake-up condition is met, so that the task execution component executes the task corresponding to the request.

[0020] In the above programmable controller, preferably, the activation component comprises:

[0021] a first output structure and a plurality of first AND gates;

[0022] Wherein, the first input port of each of the first AND gates is respectively connected to a signal source, each of the signal sources corresponds to a task execution component, and the signal source provides an activation signal of the corresponding task execution component, and the second input port of each of the first AND gates is an enable port, and the enable port is connected to the delay component, and the enable port is enabled when receiving the enable signal transmitted by the delay component;

[0023] The output port of each of the first AND gates is respectively connected to the first output structure, the first output structure is connected to the task execution component, and the activation component transmits the activation signal corresponding to the second AND gate whose enable port is enabled to the corresponding task execution component, so that the task execution component executes the task corresponding to the request.

[0024] The above programmable controller is preferably wherein:

[0025] In the case where there are multiple requests, the delay control component controls the transmission component to send the requests to the processor in a processing order so that the processor processes the requests in the processing order, and the processing order is at least related to an arrival order and / or a request priority corresponding to the requests;

[0026] and / or, in the case where there are multiple requests corresponding to the same task execution component, the delay control component enables the enable port corresponding to the task execution component so that the task execution component executes the task corresponding to each request according to a task order, and the task order is at least related to the task priority corresponding to the request;

[0027] And / or, in the case where there are multiple requests corresponding to different task execution components, the delay control component enables the enable port corresponding to each task execution component synchronously or in sequence according to the task order, and the task order is at least related to the task priority corresponding to the request.

[0028] In the above-mentioned programmable controller, preferably, the transmission component comprises:

[0029] at least one switching component, the switching component comprising at least a first input port, a second input port, a first output port, and a second output port;

[0030] Wherein, the first input port is used to receive the request; the first input port is connected to the first output port under a first instruction, and the first output port is connected to the delay control component; the first instruction is used to instruct to delay the request;

[0031] The second input port is connected to the delay control component, the second input port is connected to the second output port, and the second output port is connected to the processor.

[0032] In the above-mentioned programmable controller, preferably, the transmission component comprises:

[0033] a second output structure, the second output structure connected to the processor;

[0034] Wherein, the switching component further includes:

[0035] a third output port; the third output port is connected to the second output structure; and the first input port is connected to the third output port under a second instruction; the second instruction is used to indicate not to delay the request.

[0036] In the above-mentioned programmable controller, preferably, after the wake-up condition is met, when the transmission component receives a new request for the processor, the delay control component determines whether the processing condition is met; if the processing condition is met, the transmission component is controlled to send the new request to the processor, so that the processor processes the new request in the second state;

[0037] If the processing condition is not met, the delay control component controls the transmission component to send the request to the processor when the wake-up condition is met again, so that the processor processes the new request when the wake-up condition is met again;

[0038] The processing conditions include: the maximum delay duration corresponding to the new request is less than or equal to a delay threshold, and the delay threshold is related to the remaining processing duration of the current processing request by the processor.

[0039] An electronic device, comprising at least: a programmable controller and a processor; the programmable controller comprises: a transmission component and a delay control component;

[0040] Wherein, the transmission component is used to receive a request for a processor;

[0041] The delay control component is used to monitor whether a wake-up condition is met, and the wake-up condition is related to the request; if the wake-up condition is met, control the processor to enter the second state from the first state, and control the transmission component to send the request to the processor, so that the processor processes the request in the second state;

[0042] The power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

[0043] The above electronic device preferably further includes:

[0044] at least one task execution component; the programmable controller further comprises: an activation component;

[0045] Wherein, the delay control component includes: an accumulator, a delay component; the activation component includes: a first output structure and a plurality of first AND gates;

[0046] The accumulator is used to receive the request sent by the transmission component, and perform numerical statistics on the requests received by the transmission component when the processor is in the first state to obtain a target value;

[0047] The delay component is used to obtain the target value from the accumulator, and when the target value satisfies the threshold parameter, control the processor to enter the second state from the first state, and control the transmission component to send the request to the processor;

[0048] Wherein, the first input port of each of the first AND gates is respectively connected to a signal source, each of the signal sources corresponds to a task execution component, and the signal source provides an activation signal of the corresponding task execution component, and the second input port of each of the first AND gates is an enable port, and the enable port is connected to the delay component, and the enable port is enabled when receiving the enable signal transmitted by the delay component;

[0049] The output port of each of the first AND gates is respectively connected to the first output structure, the first output structure is connected to the task execution component, and the activation component transmits the activation signal corresponding to the second AND gate whose enable port is enabled to the corresponding task execution component, so that the task execution component executes the task corresponding to the request.

[0050] A control method, applied to a programmable controller, comprising:

[0051] receiving a request for a processor;

[0052] monitoring whether a wake-up condition is satisfied, the wake-up condition being related to the request; if the wake-up condition is satisfied, controlling the processor to enter a second state from a first state, and sending the request to the processor so that the processor processes the request in the second state;

[0053] The power consumption of the processor in the first state is lower than the power consumption of the processor in the second state. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0055] Figure 1 A schematic diagram of the structure of a programmable controller provided in Example 1 of the present application;

[0056] Figure 2 This is an example diagram of a wake-up condition control processor based on a request threshold in Embodiment 1 of the present application;

[0057] Figure 3This is an example diagram of a wake-up condition control processor based on a duration threshold in Embodiment 1 of the present application;

[0058] Figure 4 This is an example diagram of a wake-up condition control processor based on a request threshold and a duration threshold in Embodiment 1 of the present application;

[0059] Figure 5 This is another example diagram of a wake-up condition control processor based on a request threshold and a duration threshold in Embodiment 1 of the present application;

[0060] Figure 6 , Figure 7 , Figure 8 They are respectively another structural schematic diagram of a programmable controller provided in the first embodiment of the present application;

[0061] Fig. 9 This is a structural example diagram of the activation component in Embodiment 1 of the present application;

[0062] Fig.10 This is a schematic diagram of the structure of the transmission component in Example 1 of the present application;

[0063] Fig.11 This is another structural schematic diagram of the transmission component in the first embodiment of the present application;

[0064] Fig.12 This is another structural schematic diagram of the transmission component in the first embodiment of the present application;

[0065] Fig.13 A schematic diagram of the structure of an electronic device provided in Embodiment 2 of the present application;

[0066] Fig.14 Another structural schematic diagram of an electronic device provided in Embodiment 2 of the present application;

[0067] Fig.15 A flow chart of a control method provided in Embodiment 3 of the present application;

[0068] Fig.16 It is a schematic diagram of non-aligned activities of functional modules and common modules in the system of the computer in this embodiment;

[0069] Fig.17 It is a schematic diagram of the common module alignment activity in the system awakening state of the computer in this embodiment;

[0070] Fig.18 This is a hardware architecture diagram of the device where the platform system activity controller PAC is located in this embodiment;

[0071] Fig.19 Schematic diagram of the structure of PAC in this embodiment;

[0072] Fig. 20 This is a schematic diagram of the structure of the PAC activation hardware module in this embodiment;

[0073] Fig.21 This is an example diagram for recording status information of hardware modules in this embodiment;

[0074] Fig. 22 It is a schematic diagram of comparing the scenarios with and without interruption alignment in this embodiment. DETAILED DESCRIPTION

[0075] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0076] At present, after the processor in the computer completes the processing of an interrupt, it usually enters a low-power sleep state until the next interrupt arrives. However, each time an interrupt arrives, the processor needs to be woken up, causing the processor to frequently switch between sleep and wake-up, which results in a relatively short and scattered period of time in the processor's sleep state, resulting in higher power consumption of the processor.

[0077] In view of this, refer to Figure 1 As shown, it is a schematic diagram of the structure of a programmable controller provided in the first embodiment of the present application, and the programmable controller can be applied to an electronic device with a processor, such as a computer or a server. The programmable controller can be represented by PAC (Programmable Automation Controller). The technical solution in this embodiment is mainly used to reduce the power consumption of electronic equipment.

[0078] Specifically, the programmable controller in this embodiment may include the following structure:

[0079] A transmission component 1 and a delay control component 2;

[0080] The transmission component 1 is used to receive a request for the processor; the request here may be an interrupt request, or may be called an interrupt instruction, such as interrupts, which is used to instruct the processor to perform corresponding processing.

[0081] The delay control component 2 is used to monitor whether the wake-up condition is met. When the wake-up condition is met, the delay control component 2 controls the processor to enter the second state from the first state, and controls the transmission component 1 to send the request to the processor, so that the processor processes the request in the second state.

[0082] The wake-up condition is related to the request, and the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

[0083] Specifically, the transmission component 1 can be implemented using logic gates to receive a request for a processor and send the request to the processor under the control of the delay control component 2 .

[0084] The delay control component 2 can be implemented by logic gates and state machines, so that when the wake-up condition is detected to be met, the transmission component 1 is controlled to send the received request to the processor that has been controlled to enter the second state. Specifically, the delay control component 2 can send a start signal to the processor to make the processor enter the second state, and the delay control component 2 can send a control signal to the transmission component 1 to make the transmission component 1 send the received request to the processor.

[0085] It can be seen from the above technical scheme that the present application provides a programmable controller in the first embodiment, in which a transmission component and a delay control component are set in the programmable controller, and the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state. Based on this, in the programmable controller, a request for the processor is received through the transmission component, so that the wake-up condition related to the request is monitored through the delay control component. If the wake-up condition is met, the processor is controlled to enter the second state from the first state and the transmission component is controlled to send the request to the processor, so that the processor processes the request in the second state. It can be seen that in this embodiment, the wake-up condition corresponding to the request is configured for the processor. Only when the wake-up condition is met, the processor will enter a state with higher power consumption to process the request. If the wake-up condition is not met, the processor is in a state with lower power consumption and does not process the request. Therefore, by concentrating the request for processing after the wake-up condition is met, the processor is prevented from frequently switching between the high power consumption state and the low power consumption state, and the processor is prevented from being in a state of higher power consumption continuously, thereby reducing the power consumption of the electronic device where the processor is located by reducing the duration of the processor in the state of higher power consumption.

[0086] Furthermore, since the wake-up conditions can be flexibly configured, the wake-up conditions can be adjusted based on various conditions such as the current state of the system, the busyness of the request, and the tolerance for task delays.

[0087] Specifically, the wake-up condition is related to the request itself, and the satisfaction of the wake-up condition is based on the request itself. For example, the request itself can be delayed for a longer time or the request cannot be delayed for a long time. Therefore, in this embodiment, through the wake-up condition related to the request itself, flexible processor wake-up can be achieved without a fixed time interval, avoiding the situation of large delay.

[0088] Moreover, compared with the software method, the hardware implementation of the programmable controller in this embodiment has a faster response speed, which can improve the efficient control of the processor and avoid excessive delay.

[0089] In one implementation, the wake-up condition may include at least one of the following:

[0090] When the processor is in the first state, the request received by the transmission component 1 satisfies the threshold parameter. The threshold parameter here is a parameter related to the urgency of the request to be processed. Specifically, the threshold parameter may include: at least one of the request threshold, the duration threshold, and other threshold parameters related to the urgency of the request to be processed; the greater the urgency of the request to be processed, the more it is necessary to process the request as soon as possible. Generally, the longer the request is delayed and the closer it is to the tolerable delay duration, the more the accumulated number of unprocessed requests, and the greater the urgency of these requests to be processed. The setting of the threshold parameter is related to the urgency that the system can tolerate.

[0091] Correspondingly, the request meets the threshold parameters including: the parameter characterizing the urgency of the request to be processed reaches the corresponding threshold, such as the number of requests reaches a preset request threshold, the waiting time of the target request in the request reaches the time threshold, etc.

[0092] For example, after the processor enters the first state, the transmission component 1 continues to receive requests for the processor, but these requests are waiting to be processed. During this process, the delay control component 2 continuously monitors whether the number of requests received by the transmission component 1 has accumulated to the request threshold. If so, the processor is controlled to enter the second state from the first state, and the transmission component 1 is controlled to send the received requests to the processor. Figure 2 As shown in , the processor centrally processes these requests in the second state, thereby reducing the time the processor is in the second state and reducing power consumption.

[0093] For another example, after the processor enters the first state, the transmission component 1 continues to receive requests for the processor, but these requests are all waiting to be processed. During this process, the delay control component 2 continuously monitors whether the waiting time of the target request in the requests received by the transmission component 1 has accumulated to the time threshold. If so, the processor is controlled to enter the second state from the first state, and the transmission component 1 is controlled to send the request to the processor. Figure 3 As shown in , the processor centrally processes these requests in the second state, thereby reducing the time the processor is in the second state and reducing power consumption.

[0094] For another example, after the processor enters the first state, the transmission component 1 continues to receive requests for the processor, but these requests are all waiting to be processed. During this process, the delay control component 2 continuously monitors whether the number of requests received by the transmission component 1 has accumulated to the request threshold and continuously monitors whether the waiting time of the target request in the requests received by the transmission component 1 has accumulated to the time threshold. If any one of the following conditions is met: the number of requests received by the transmission component 1 has accumulated to the request threshold and the waiting time of the target request in the requests received by the transmission component 1 has accumulated to the time threshold, then the processor is controlled to enter the second state from the first state, and the transmission component 1 is controlled to send the request to the processor, such as Figure 4 As shown in , the processor centrally processes these requests in the second state, thereby reducing the time the processor is in the second state and reducing power consumption.

[0095] It should be noted that in this embodiment, the wake-up condition can be set according to the system state: the number of requests accumulates to the request threshold, or the wake-up condition is set to: the waiting time of the target request in the request accumulates to the duration threshold. Specifically, if the system state requires a higher timeliness, and the request is not allowed to wait for too long, the wake-up condition can be set to: the waiting time of the target request in the request accumulates to the duration threshold, so that as long as the waiting time of the target request reaches the duration threshold, the transmission component 1 can be controlled to send the request to the processor for processing. If the system state requires lower power consumption and does not allow the processor to wake up too frequently, the wake-up condition can be set to: the number of requests accumulates to the request threshold. In this way, the waiting time of the request is not limited, and only when the number of requests accumulates to the request threshold, the transmission component 1 is controlled to send the request to the processor for processing.

[0096] Furthermore, the electronic device can switch between the two wake-up conditions according to the system status to meet the real-time requirements of the system operation.

[0097] For another example, after the processor enters the first state, the transmission component 1 continues to receive requests for the processor, but these requests are all waiting to be processed. During this process, the delay control component 2 continuously monitors whether the number of requests received by the transmission component 1 has accumulated to the request threshold and continuously monitors whether the waiting time of the target request in the requests received by the transmission component 1 has accumulated to the time threshold. If the number of requests received by the transmission component 1 has accumulated to the request threshold and the waiting time of the target request in the requests received by the transmission component 1 has accumulated to the time threshold, then the processor is controlled to enter the second state from the first state, and the transmission component 1 is controlled to send the request to the processor, such as Figure 5 As shown in , the processor centrally processes these requests in the second state, thereby further reducing the time the processor is in the second state and reducing power consumption.

[0098] The duration threshold is independent of the request, or the duration threshold is determined by the delay parameter of the request, and the delay parameter represents the maximum waiting time that can be delayed for the request. The maximum waiting time is related to the type of application to which the request belongs. For example, when the application type is a game that requires a high running speed, the maximum waiting time is short; for another example, when the application type is a shopping application that does not require a high running speed, the maximum waiting time is long.

[0099] In one implementation, the duration threshold is a value set according to demand and has nothing to do with the request itself. The duration threshold corresponding to each request is the same. For example, the duration threshold is set to 2ms. In this embodiment, when the processor is in the first state, the waiting time of each request to the processor received by the transmission component is judged according to 2ms. If the waiting time of one or more target requests has reached 2ms, then it is determined that the request received by the transmission component 1 meets the threshold parameter, that is, the wake-up condition is met. Therefore, in this embodiment, a unified duration threshold is set for different requests to reduce the complexity of the implementation of the solution.

[0100] In another implementation, the duration threshold is a value set according to the maximum waiting time in the delay parameter of the request. Different requests have different corresponding duration thresholds. For example, according to the maximum waiting time of request 1 of 1ms, the duration threshold corresponding to request 1 is set to 1ms; according to the maximum waiting time of request 2 of 2ms, the duration threshold corresponding to request 2 is set to 2ms. Based on this, in this embodiment, when the processor is in the first state, each request received by the transmission component is judged according to the corresponding duration threshold. If the waiting time of one or more target requests reaches its corresponding duration threshold, such as the waiting time of request 1 reaches 1ms and the waiting time of request 2 reaches 1ms, and for example, the waiting time of request 2 reaches 2ms but the waiting time of request 1 only reaches 0.5ms, at this time, it can be determined that the request received by the transmission component meets the threshold parameter, that is, the wake-up condition is met. Therefore, in this embodiment, through the duration threshold related to the request itself, flexible processor wake-up can be achieved without a fixed time interval, avoiding the situation where individual requests are delayed.

[0101] It should be noted that when the waiting time of a target request reaches its time threshold, the waiting time of other requests may not have reached their time threshold. At this time, the delay control component 2 can control the transmission component 1 to send all requests to the processor to speed up the processing of other requests whose waiting time has not reached the time threshold to ensure timeliness.

[0102] Specifically, the delay control component 2 may adjust the threshold parameter according to the processing parameter. The processing parameter may include at least one of the following:

[0103] Parameters related to the system's requirements for request processing timeliness include the request receiving rate, the application type to which the request belongs, the current power consumption of the electronic device where the processor is located, and the resource utilization rate of the electronic device.

[0104] For example, the higher the request receiving rate is, the smaller the request threshold or duration threshold in the threshold parameter is set, thereby avoiding waiting congestion of requests while reducing power consumption and meeting the user's demand for the operation of the electronic device;

[0105] For another example, when the request belongs to a first application type, such as a game type, a smaller request threshold or duration threshold is set in the threshold parameter to meet the running requirements of the application of the first application type while reducing power consumption; when the request belongs to a second application type, such as a shopping type, a larger request threshold or duration threshold is set in the threshold parameter to increase the time the processor is in the first state and reduce power consumption.

[0106] For another example, the higher the current power consumption of the electronic device where the processor is located, the larger the request threshold or duration threshold in the threshold parameter is set to increase the time the processor is in the first state and reduce power consumption; the lower the current power consumption of the electronic device where the processor is located, the smaller the request threshold or duration threshold in the threshold parameter is set to meet the user's operation requirements for the electronic device under the premise of reducing power consumption;

[0107] For another example, the higher the resource utilization rate of the electronic device, the larger the request threshold or duration threshold in the threshold parameters is set to increase the time the processor is in the first state, reduce resource occupancy, and reduce power consumption; the lower the resource utilization rate of the electronic device, the smaller the request threshold or duration threshold in the threshold parameters is set to meet the user's operation requirements for the electronic device while reducing power consumption.

[0108] In one implementation, the delay control component 2 may include the following structure: Figure 6 As shown in:

[0109] Accumulator 3 and delay component 4;

[0110] The accumulator 3 is used to receive the request sent by the transmission component 1, and perform numerical statistics on the request received by the transmission component 1 in the first state of the processor to obtain a target value;

[0111] The delay component 4 is used to obtain a target value from the accumulator 3, and when the target value meets the threshold parameter, control the processor to enter the second state from the first state, and control the transmission component to send a request to the processor so that the processor processes the request in the second state.

[0112] For example, when the target value meets the threshold parameter, the delay component 4 can send a start signal to the processor to make the processor enter the second state, and can send a control signal to the transmission component 1 to make the transmission component 1 send the received request to the processor.

[0113] The delay component 4 may be implemented as a state machine.

[0114] Specifically, the accumulator 3 may include a counter 5 and / or a timer 6, such as Figure 7 , where:

[0115] The counter 5 is connected to the transmission component 1 and the delay component 4 respectively, and the counter 5 is used to receive the request sent by the transmission component 1, and count the requests received by the transmission component 1 in the first state of the processor to obtain a first number. Based on this, the delay component 4 obtains the first number from the counter 5, and when the first number reaches the request threshold, controls the processor to enter the second state from the first state, and controls the transmission component 1 to send the request to the processor, so that the processor processes the request in the second state;

[0116] It should be noted that after the first number reaches the request threshold and controls the transmission component 1 to send the request to the processor, the counter 5 is cleared, and the counter 5 starts counting the requests received by the transmission component 1 from 0 again until the first number counted by the counter 5 reaches the request threshold again.

[0117] The timer 6 is connected to the transmission component 1 and the delay component 4 respectively. The timer 6 is used to receive the request sent by the transmission component 1, and to respectively time the waiting time of the request received by the transmission component 1 in the first state of the processor to obtain the first time. The first time represents the waiting time of the request. The time when each request arrives at the transmission component 1 is different, and the corresponding waiting time of each request may be different. Based on this, the delay component 4 obtains the first time from the timer 6, and when the first time corresponding to the target request reaches the corresponding time threshold, the delay component 4 controls the processor to enter the second state from the first state, and controls the transmission component 1 to send the request to the processor, so that the processor processes the request in the second state.

[0118] It should be noted that after the first duration corresponding to the target request reaches the corresponding duration threshold and controls the transmission component 1 to send the request to the processor, timer 6 is cleared, and timer 6 restarts when the transmission component 1 receives a request until the first duration of timer 6 reaches the request threshold again.

[0119] In a specific implementation, the user can set the delay control component 2 to use a counter or a counter or both counters at the same time according to the needs to meet the needs of the application scenario.

[0120] Based on the above implementation, the programmable controller in this embodiment may also include an activation component 7, such as Figure 8 as shown in .

[0121] Among them, the activation component 7 is connected to the delay control component 2, and the delay control component 2 is also used to control the activation component 7 to send an activation signal to the task execution component when the wake-up condition is met, so that the task execution component executes the task corresponding to the request.

[0122] Among them, the activation component 7 can connect to each task execution component in the electronic device, so that for any request, the activation component 7 can send a corresponding activation signal to the task execution component corresponding to each request under the control of the delay control component 2, so that the task execution component executes the task corresponding to the request.

[0123] It should be noted that before receiving the activation signal, the task execution component is in the third state, i.e., the dormant state, and after receiving the activation signal, the task execution component enters the fourth state, i.e., the activated state. The power consumption of the task execution component in the dormant state is lower than that in the activated state. Furthermore, the task execution component enters the dormant state again after completing the task.

[0124] Specifically, the activation component 7 may include the following structure: Fig. 9 As shown in:

[0125] A first output structure 8 and a plurality of first AND gates 9 .

[0126] Among them, the first input port 10 of each first AND gate 9 is respectively connected to a signal source b, each signal source corresponds to a task execution component c, the signal source b provides an activation signal of its corresponding task execution component c, and the second input port 11 of each first AND gate 9 is an enable port, and the enable port is connected to the delay component 4, and the enable port is enabled when receiving the enable signal transmitted by the delay component 4.

[0127] Among them, the task execution component is a component that executes the task corresponding to the request, such as a communication module, a bus, a codec and other components.

[0128] Moreover, the output port 12 of each first AND gate 9 is respectively connected to the first output structure 8, and the first output structure 8 is connected to the task execution component c. The activation component 7 transmits the activation signal corresponding to the first AND gate 9 whose enable port is enabled to the corresponding task execution component c through the first output structure 8, so that the task execution component c enters the activation state and executes the task corresponding to the request.

[0129] The first output structure 8 can be realized by an OR gate.

[0130] In one implementation, the delay component 4 transmits an enable signal through a connection with the enable port to reduce signal transmission delay;

[0131] In another implementation, the delay component 4 is configured with a register, the register stores configuration information, and the corresponding enable port is enabled according to the configuration information.

[0132] It can be seen that in this embodiment, the delay component 4 not only controls the processor to enter the second state from the first state and controls the transmission component 1 to send the request to the processor, but also sends an enable signal to the enable port on the first AND gate 9 in the activation component 7, such as Fig. 9 As shown in the figure, the signal source corresponding to the first AND gate 9 that enables the enable port provides an activation signal for the corresponding task execution component, and then the activation signal is output to the corresponding task execution component through the first output structure 8. Thus, after the processor processes the request in the second state, the task execution component corresponding to the request can execute the corresponding task in the activated state.

[0133] In a specific implementation, the request may be one or more.

[0134] In one implementation, when there are multiple requests, the delay control component 2 controls the transmission component to send the requests to the processor in a processing order so that the processor processes the requests in the processing order. The processing order here is related to the arrival order and / or request priority of the requests.

[0135] For example, the processing order includes: the order of request priority from high to low, and the order of arrival from first to last in the same request priority. That is, the delay control component 2 controls the transmission component 1 to preferentially transmit the request with higher request priority. When the request priorities are the same, the delay control component 2 controls the transmission component 1 to preferentially transmit the request that arrives first. Based on this, the processor preferentially processes the request with higher request priority. When the request priorities are the same, the processor preferentially processes the request that arrives first.

[0136] In another implementation, the delay control component 2 controls the transmission component 1 to send multiple requests to the processor together or in the order in which the transmission component 1 receives the requests, but processes the requests on the processor in the order described above.

[0137] In another implementation, when there are multiple requests corresponding to the same task execution component, the delay control component 2 enables the enable port corresponding to the task execution component so that the task execution component executes the task corresponding to each request according to the task order. The task order is at least related to the task priority corresponding to the request.

[0138] The request priorities between different requests and the task priorities of the corresponding requests may be the same or different.

[0139] For example, the task order includes: the order of task priorities from high to low. Further, the task order also includes: the order of arrival of requests with the same task priority from first to last. For example, after the delay control component 2 enables the enable port corresponding to the task execution component, the task execution component with a higher task priority will give priority to executing the task corresponding to the request. When the task priorities are the same, the task execution component will give priority to executing the task corresponding to the request that arrives first.

[0140] Specifically: the delay component 4 controls the processor to enter the second state and controls the transmission component 1 to send the request to the processor according to the processing order, and the delay component 4 sends an enable signal to the enable port corresponding to the task execution component on the first AND gate 9 in the activation component 7, so that the signal source corresponding to the first AND gate 9 whose enable port is enabled provides an activation signal for the corresponding task execution component, and then the activation signal is output to the corresponding task execution component through the first output structure 8. Therefore, after the processor processes the request in the second state according to the processing order, the task execution component corresponding to the request can also execute the corresponding task in the activation state in sequence according to the task order under the activation signal.

[0141] For example, there are three requests for the processor, namely, request 1, request 2 and request 3. Request 1 arrives at transmission component 1 before request 2 and request 3. Request 2 and request 1 have the same priority, and request 3 has a higher priority than request 2 and request 1. Request 1, request 2 and request 3 all correspond to task execution component 1. Based on this, when delay component 4 detects that the wake-up condition is met, delay component 4 controls the processor to enter the second state and controls transmission component 1 to send requests 3, request 1 and request 2 to the processor in the order of request 3, request 1 and request 2, and sends an enable signal to the enable port corresponding to task execution component [1] on the first AND gate 9 in activation component 7, thereby enabling task execution component [1]. Based on this, the processor processes the three requests in the second state in the order of request 3, request 1 and request 2, and task execution component [1] first processes the task corresponding to request 3, and then task execution component [1] executes the task corresponding to request 1, and task execution component [1] executes the task corresponding to request 2.

[0142] In another implementation, when there are multiple requests corresponding to different task execution components, the delay control component 2 enables the enable port corresponding to each task execution component synchronously or in sequence according to the task order, so that each task execution component executes the task corresponding to the corresponding request according to the task order. The task order is at least related to the task priority corresponding to the request.

[0143] For example, the task order includes: the order of task priorities from high to low. Further, the task order also includes: the order of arrival of requests in the same task priority from first to last. For example, the delay control component 2 gives priority to enabling the enable port corresponding to the task execution component with a higher task priority. When the task priorities are the same, the delay control component 2 gives priority to enabling the enable port corresponding to the task execution component corresponding to the request that arrives first. Based on this, the task execution component with a higher task priority gives priority to executing the task corresponding to the request. When the task priorities are the same, the task execution component corresponding to the request that arrives first gives priority to executing the task corresponding to the request.

[0144] Specifically: the delay component 4 controls the processor to enter the second state and controls the transmission component 1 to send the request to the processor according to the processing order, and the delay component 4 sends an enable signal to the enable port corresponding to the task execution component on the first AND gate 9 in the activation component 7 in the task order, so that the signal source corresponding to the first AND gate 9 whose enable port is enabled provides the activation signal of the corresponding task execution component in the task order, and then the activation signal is output to the corresponding task execution component through the first output structure 8. Therefore, after the processor processes the request in the second state in the processing order, the task execution component corresponding to the request can also execute the corresponding task in the activation state in the task order under the activation signal.

[0145] For example, there are three requests for the processor, request 1, request 2, and request 3. Request 1, request 2, and request 3 arrive at transmission component 1 in sequence. Request 2 and request 1 have the same request priority, and request 3 has a higher request priority than request 2 and request 1. Request 1 corresponds to task execution component [1], request 2 corresponds to task execution component [2], and request 3 corresponds to task execution component [3]. The task priority of request 2 is the same as the task priority of request 3, and is higher than the task priority of request 1. Based on this, when delay component 4 detects that the wake-up condition is met, delay component 4 controls the processor to enter the second state and controls transmission component 1 to execute requests 3 and 3. The processor sends the three requests in the order of request 1 and request 2 to the processor, and sends enable signals to the enable ports corresponding to the task execution components on the first AND gate 9 in the activation component 7 in the order of task execution component [2], task execution component [3], and task execution component [1], thereby enabling task execution component [2], task execution component [3], and task execution component [1] in turn. Based on this, the processor processes the three requests in the second state in the order of request 3, request 1, and request 2, and task execution component [2] first processes the task corresponding to request 2, then task execution component [3] executes the task corresponding to request 3, and task execution component [1] executes the task corresponding to request 1.

[0146] In one implementation, the transmission component 1 may include the following structure: Fig.10 As shown:

[0147] At least one switching component 13, the switching component 13 can be represented by switch, and the switching component 13 at least includes a first input port 14, a second input port 15, a first output port 16, and a second output port 17;

[0148] The first input port 14 is used to receive a request for the processor; the first input port 14 is connected to the first output port 16 under a first instruction, the first output port 16 is connected to the delay control component 2, and the first instruction is used to instruct to delay the request for the processor.

[0149] The second input port 15 is connected to the delay control component 2 , the second input port 15 is connected to the second output port 17 , and the second output port 17 is connected to the processor.

[0150] Thus, a request for the processor is received through the first input port 14, and the first output port 16 is connected under the first instruction, so that the request is transmitted to the delay control component 2. When the delay control component 2 detects that the wake-up condition is met, such as the number of requests reaches the request threshold or the waiting time of the target request in the request reaches the time threshold, the delay control component 2 sends a start signal and a control signal to the second input port 15. The start signal is transmitted to the processor connected to the second output port 17 through the second output port 17 connected to the second output port 15, so that the processor enters the second state, and the control signal is transmitted to the second output port 17 through the second input port 15, controlling the second output port 17 to transmit the request to the processor connected to the second output port 17, so that the processor processes the request in the second state.

[0151] It should be noted that the first input port 14 is also connected to the second output port 17. Fig.11 As shown in , the second output port 17 sends the request received by the first input port 14 to the processor when receiving the control signal, so that the processor can process the received request in response to the received control signal after entering the second state.

[0152] Furthermore, the programmable controller in this embodiment may also include the following structure: Fig.12 As shown in:

[0153] A second output structure 18, the second output structure 18 is connected to the processor;

[0154] The switching component 13 may also include the following structure:

[0155] The third output port 19 is connected to the second output structure 18, and the first input port 14 is connected to the third output port 19 under the second instruction, and the second instruction is used to indicate not to delay the request.

[0156] Therefore, in this embodiment, the first input port 14, the first output port 16 and the third output port 19 are configured in the switching component 13 to facilitate delay control and delay bypass. That is to say, in the case of a first instruction indicating a delay request, the first input port 14 is connected to the first output port 16, so that the request is transmitted to the delay control component 2, and the delay control component 2 implements the delay processing of the request by monitoring the wake-up condition, and in the case of a second instruction indicating no delay request, the first input port 14 is not connected to the first output port 16, but to the third output port 19. At this time, the delay control component 2 will not receive the request, and the request is transmitted to the processor through the second output structure 18 connected to the third output port 19, and the processor directly processes the request without delaying the request. Therefore, the programmable controller in this embodiment can achieve flexible control of delay.

[0157] In one implementation, after the wake-up condition is met, the transmission component 1 may receive a new request for the processor, that is, the transmission component 1 receives the new request after the processor enters the second state. Based on this, when the transmission component 1 receives the new request for the processor, the delay control component 2 first determines whether the processing condition is met;

[0158] If the processing condition is met, the delay control component 2 controls the transmission component 1 to send the new request to the processor, so that the processor processes the new request in the second state;

[0159] If the processing condition is not met, the delay control component 2 controls the transmission component 1 to send a new request to the processor when the wake-up condition is met again, so that the processor processes the new request when the wake-up condition is met again, that is, the processor enters the second state next time.

[0160] The processing conditions include: the maximum delay time corresponding to the new request is less than or equal to the delay threshold, and the delay threshold is related to the remaining processing time of the processor currently processing the request.

[0161] The maximum delay time corresponding to the new request may also be understood as the maximum waiting time for the delayed processing of the new request.

[0162] It should be noted that the time required for a request to be processed includes: the time required for the processor to process the request, and the time required for the task execution component corresponding to the request to execute the task corresponding to the request. Correspondingly, the remaining processing time is: the remaining time required for the processor to process one or more requests currently being processed, plus the remaining time required for the task execution component corresponding to the one or more requests currently being processed to execute the task corresponding to the request.

[0163] The delay threshold may be set based on the remaining processing time. For example, the delay threshold is set to a value consistent with the remaining processing time to indicate:

[0164] If the maximum delay duration is less than or equal to the delay threshold, the new request must be processed before the processor completes processing of the current request. In order to avoid the processor repeatedly switching between the second state and the first state, the electronic device can process the new request before or after processing the current request. At this time, the processor remains in the second state and the task execution component remains in the activated state, that is, the delay control component 2 can control the transmission component 1 to send the new request to the processor, so that the processor processes the new request in the current second state, and controls the activation component 7 to send an activation signal to the task execution component, and the task execution component executes the task corresponding to the new request in the current activated state.

[0165] It should be noted that when the processor processes a new request in the current second state, it may wait until all currently processed requests are completed before processing the new request, or it may give priority to processing the new request when the priority of the new request is higher than that of the remaining requests.

[0166] If the maximum delay time is greater than the delay threshold, after the processor completes processing of the current request, the new request can still wait for a certain period of time (the difference between the maximum delay time and the delay threshold), that is, the new request can be delayed until it is concentrated with other requests until the wake-up condition is met again, that is, the processor enters the second state again, and then processed. That is, the delay control component 2 can control the transmission component 1 to send the new request to the processor when the wake-up condition is met again, so that the processor will process the new request when it enters the second state next time, and control the activation component 7 to send an activation signal to the task execution component when the wake-up condition is met again, and the task execution component will execute the task corresponding to the new request when it enters the activation state next time.

[0167] It should be noted that after the processor in this embodiment processes all requests sent by the transmission component 1 in the second state, it enters the first state, and when the delay control component 2 again detects that the wake-up condition is met, the processor enters the second state. Therefore, in this embodiment, the requests after the processor enters the first state are concentrated and processed after the processor enters the second state, thereby reducing the time the processor is in the second state and reducing power consumption.

[0168] Synchronously, after the task execution component in this embodiment executes the tasks corresponding to all requests in the activated state, it enters the sleep state. When the delay control component 2 detects that the wake-up condition is met again, the task execution component enters the activated state again. Therefore, in this embodiment, the tasks corresponding to the requests after the task execution component enters the sleep state are concentrated and executed after the task execution component enters the activated state, thereby reducing the time that the task execution component is in the activated state and reducing power consumption.

[0169] refer to Fig.13 , is a schematic diagram of the structure of an electronic device provided in Embodiment 2 of the present application, and the electronic device may include the following structure:

[0170] Programmable controller 20, processor 21;

[0171] Wherein, the programmable controller 20 comprises: a transmission component 1 and a delay control component 2;

[0172] The transmission component 1 is used to receive a request for the processor 21;

[0173] The delay control component 2 is used to monitor whether a wake-up condition is met, where the wake-up condition is related to the request; if the wake-up condition is met, control the processor 21 to enter the second state from the first state, and control the transmission component 1 to send the request to the processor 21, so that the processor 21 processes the request in the second state;

[0174] The power consumption of the processor 21 in the first state is lower than the power consumption of the processor 21 in the second state.

[0175] It can be seen from the above technical scheme that in an electronic device provided by the second embodiment of the present application, a transmission component and a delay control component are set in the programmable controller in the electronic device, and the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state. Based on this, in the programmable controller, a request for the processor is received through the transmission component, so that the delay control component monitors whether the wake-up condition related to the request is met. When the wake-up condition is met, the processor is controlled to enter the second state from the first state and the transmission component is controlled to send the request to the processor, so that the processor processes the request in the second state. It can be seen that in this embodiment, the wake-up condition corresponding to the request is configured for the processor. Only when the wake-up condition is met, the processor will enter a state with higher power consumption to process the request. When the wake-up condition is not met, the processor is in a state with lower power consumption and does not process the request. Therefore, by concentrating the request for processing after the wake-up condition is met, the processor is prevented from frequently switching between the high power consumption state and the low power consumption state, and the processor is prevented from being in a state of higher power consumption continuously, thereby reducing the power consumption of the electronic device where the processor is located by reducing the duration of the processor in the state of higher power consumption.

[0176] Moreover, in this embodiment, the hardware implementation of the programmable controller can improve the efficient control of the processor.

[0177] In one implementation, the electronic device in this embodiment may also include the following structure: Fig.14 As shown in;

[0178] at least one task execution component 22; the programmable controller 20 further comprises: an activation component 7;

[0179] The delay control component 2 includes: an accumulator 3, a delay component 4; the activation component 7 includes: a first output structure 8 and a plurality of first AND gates 9;

[0180] The accumulator 3 is used to receive the request sent by the transmission component 1, and perform numerical statistics on the request received by the transmission component 1 in the first state of the processor to obtain a target value;

[0181] The delay component 4 is used to obtain a target value from the accumulator 3, and when the target value meets the threshold parameter, control the processor to enter the second state from the first state, and control the transmission component to send a request to the processor so that the processor processes the request in the second state.

[0182] Among them, the first input port 10 of each first AND gate 9 is respectively connected to a signal source b, each signal source corresponds to a task execution component c, the signal source b provides an activation signal of its corresponding task execution component c, and the second input port 11 of each first AND gate 9 is an enable port, and the enable port is connected to the delay component 4, and the enable port is enabled when receiving the enable signal transmitted by the delay component 4.

[0183] Moreover, the output port 12 of each first AND gate 9 is respectively connected to the first output structure 8, and the first output structure 8 is connected to the task execution component c. The activation component 7 transmits the activation signal corresponding to the first AND gate 9 whose enable port is enabled to the corresponding task execution component c through the first output structure 8, so that the task execution component c enters the activation state and executes the task corresponding to the request.

[0184] refer to Fig.15 , is a flow chart of a control method provided in the third embodiment of the present application, which can be applied to Figure 1 In the programmable controller shown. The method in this embodiment may include the following steps:

[0185] Step 1501: Receive a request for a processor;

[0186] Step 1502: monitor whether a wake-up condition is met, where the wake-up condition is related to the request; if the wake-up condition is met, execute step 1503.

[0187] Step 1503: Control the processor to enter the second state from the first state, and send the request to the processor, so that the processor processes the request in the second state;

[0188] The power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

[0189] Specifically, in this embodiment, the delay control component in the programmable controller can monitor whether the wake-up condition is met. When the wake-up condition is met, the request is sent to the processor by controlling the transmission component in the programmable control component, so that the processor processes the request in the second state.

[0190] Taking the electronic device as a computer as an example, the specific implementation of this application is illustrated by way of example:

[0191] First, the computer contains functional modules (i.e., the processor mentioned above) and common modules (shared modules, i.e., the task execution components mentioned above). Among them, functional modules are modules that execute system functions, such as the central processing unit (CPU) cores CPU Core1-2, the audio digital signal processor (DSP), etc., and the firmware hardware modules HW mod1 and HW mod2. Common modules only provide services for functional modules to enable them to perform their functions, such as external memory, bus and phase-locked loop, which are mainly the infrastructure resources of the system.

[0192] like Fig.16 As shown in the figure, it is a schematic diagram of unaligned system activities of functional modules and common modules in the computer system. Specifically, different periodic system interrupt activities can have different trigger events and start times, which are not synchronized with each other, which has the following disadvantages:

[0193] 1. The activation status of the common module is ACTIVE for a long time.

[0194] 2. Shorter inactive periods of common modules may have a negative impact on power consumption due to the power state entry / exit transitions of these modules.

[0195] 3. Multiple dedicated wake-ups for common modules and functional modules.

[0196] 4. It is difficult to predict the start of the next activity, so it is impossible to effectively decide to enter a deeper inactive power saving state, which may affect the latency requirement of the next activity due to the entry / exit latency of the corresponding inactive power saving state.

[0197] Based on this, the basic idea in this embodiment is to define a system activation behavior control module (i.e., the monitoring and control of the wake-up condition mentioned above), in which, at the beginning of the system activity, the activities of the common modules are aligned or unaligned. The system activation start triggers the system to enter the activation state based on the accumulation of a certain number of interrupts, i.e., the programmable controller PAC mentioned above.

[0198] refer to Fig.17 As shown in FIG. 1 , it is a schematic diagram of common module alignment activities (Aligned Activities Within Activation Cycle) within the system wake-up state of the computer. Fig.17 The figure shows the system activity after accumulating 6 interrupts, which helps to reduce the overall system power consumption in the following ways:

[0199] 1. Increase the inactive time of common modules and improve their utilization by serving multiple functional modules within the same active time (when the wake-up condition is met).

[0200] 2. Reduce the number of dedicated wakeups of common modules and functional modules by merging different activity execution times into a single wakeup.

[0201] 3. Safely and efficiently enter the inactive power-saving state of common modules and functional modules.

[0202] 4. Interrupts continue to accumulate in the inactive state.

[0203] Furthermore, in this embodiment, the "platform system activity controller" or PAC can perform activity alignment based on the hardware modules in the chip. Fig.18 As shown in FIG. 1 , it is a hardware architecture diagram of a device where a platform system activity controller PAC is located in one embodiment, specifically including:

[0204] 1. Power management controller PCU (Power control unit):

[0205] The PCU is a control unit that manages the power supply and system status of the overall system. It can adjust the PAC strategy from the overall perspective through software. For example, the PCU provides the PAC with the power status, and the PAC wakes up the PCU through the wake-up signal and feeds back the PAC information, namely PAC_ResReq, to ​​the PCU.

[0206] 2. PAC, which includes INT Delay, Activation and Tracking Activity:

[0207] PAC supports software to adjust the activities of certain hardware modules to a specific time period, that is, the time period after the wake-up condition is met, to avoid the CPU being woken up too frequently, thereby affecting the processing of concentrated activities. In some way, the sleep time of key hardware modules is extended to increase power benefits.

[0208] 3. INT Delay is the delay control component, including OR gate, Adder (accumulator) and Interrupt Delay FSM (Quantity Based) (delay component):

[0209] The distributed interrupt events (i.e. requests) to be processed are concentrated in a common CPU activity time period to avoid the CPU from servicing interrupts randomly and frequently. To achieve this, an accumulator is designed to count the number of interrupts to be responded to in the current system. For example, if there are 6 interrupts to be processed in the system, the system is awakened and the interrupts are processed centrally.

[0210] For example, Fig.19 As shown in, an OR gate for bypassing delay and multiple DelayUnits (i.e., transmission components) are configured in the PAC, and each DelayUnit is used to receive corresponding interrupts, such as IRQ32, IRQ33, IRQ***, etc. There are two input ports in the DelayUnit, which are used to receive interrupts and receive control signals and start signals of the Interrupt Delay FSM respectively. There are also four output ports A, B, C, and D in the DelayUnit. Output port A is connected to the OR for bypassing delay, output port B is connected to the Adder in the delay control component, output port C is connected to the MUX in the CPU subsystem (i.e., processor), and output port D is a spare port. Among them, the input port for receiving interrupts is connected to output port A or output port C to facilitate bypassing delay or realizing delay.

[0211] In addition, after Adder obtains the interrupt from OR, it counts the interrupts and transmits the accumulated number of interrupts to Interrupt Delay FSM (Quantity Based). When the accumulated number of interrupts reaches the request threshold (such as 1 or a larger value), Interrupt Delay FSM (Quantity Based) sends a control signal IntDelayTimerExpire_QuantityBased and a start signal to the input port of DelayUnit to control the output port C to send the interrupt to the CPU subsystem entering the second state.

[0212] It should be noted that for the accumulation of interrupt numbers, delay can be enabled in the following cases:

[0213] (1) When the CPU enters a specific power state (such as deep sleep state);

[0214] (2) The interrupt delay time can be configured.

[0215] Specifically, the platform software can completely bypass the PAC through the PCU register, so that the interrupt goes through the MUX and Wake uplogics to the interrupt controller GIC, which connects to the various cores core0-core3 in the CPU. For example, Fig.19As shown in , IRQ32, IRQ33, IRQ***, etc. are directly connected to the MUX (Raw IRQS[***]) in the CPU subsystem. This bypass (bypass_pac) logic must always be implemented in the non-power-down domain. Therefore, if PAC is not needed, the PAC domain can be turned off by software in this embodiment to reduce leakage.

[0216] 4. Activation is to activate the component:

[0217] PAC can provide "activation signals" (activation) to other hardware modules (module1-2, i.e., task execution components). The "activation signal" will be triggered after a certain number of interrupts have accumulated, and the number of interrupts accumulated is configurable for each corresponding hardware module. The hardware module should decide which activities should be delayed until the "activation signal" is received. The principle is that all external module access activities should be synchronized with the receipt of this "activation signal" as much as possible.

[0218] For example, Fig. 20 As shown in , the signal source signale1-3 of each hardware module is connected to an input port of each AND gate, and the other input port of each AND gate is the enable port En[0]-[2]. The output port of the AND gate is connected to the corresponding hardware module through the OR gate. Based on this, the signal source provides the activation signal of the hardware module to the input port to which it is connected. When the Interrupt Delay FSM detects that the wake-up condition is met, it provides the enable signal to the AND gate connected to the hardware module corresponding to the interrupt, so that the corresponding enable port is enabled, so that the signal source connected to the AND gate where the enable port is located outputs the activation signal HW_Act_En to the corresponding hardware module through the OR gate, and the hardware module executes the task corresponding to the interrupt.

[0219] 6. Tracking Activity, namely PAC_Track_Module in PAC:

[0220] Record the status information of all modules. Fig.21 As shown in , each hardware module is connected to one input port of each AND gate, and the other input port is the enable port. The output port of each AND gate is connected to the OR gate. Based on this, the status information Module 0status-Module xstatus (Activity status) of each hardware module whose enable port is enabled is output (OR_Act_Status) and stored through the OR gate OR.

[0221] The following describes a typical scenario of this embodiment:

[0222] First, the Platform System Activity Controller can be configured to trigger system processing based on the accumulation of the number of interrupts received. This helps achieve the following goals:

[0223] 1. Reduce the number of operating system task context switches on the CPU core, because all "interrupt service routines" will be executed at the beginning of activation, so the operating system task execution of the CPU core during the activation period will not be interrupted.

[0224] 2. Avoid small inactive times / gaps where entering an inactive state may be inefficient due to entry / exit transition power.

[0225] 3. Reduce the number of asynchronous dedicated wake-up times of the CPU core.

[0226] Scenario: If Fig. 22 As shown in the figure, it is a schematic diagram of the comparison of the scenarios with interrupt alignment (Aligned) and without interrupt alignment (Unaligned). When the system receives a certain number of interrupts cumulatively, the system activates centralized processing.

[0227] Among them, the left figure shows the scenario without interrupt alignment. The CPU-ISR processes interrupts int1, int2 and int3 in turn. Each time an interrupt is processed, the corresponding module CPU-task executes the corresponding task, that is, after the CPU-ISR processes int1, CPU-Task1 executes task 1, after the CPU-ISR processes int2, CPU-Task2 (Highest Priority) executes task 2, and CPU-Task3 (least Priority) executes task 3. It can be seen that the CPU usage is in a dormant state for a relatively scattered period of time, and the CPU needs to be constantly woken up. For example, when request 3 arrives, the CPU that was originally in a dormant state is temporarily woken up again, resulting in high power consumption.

[0228] The figure on the right shows the scenario with interrupt alignment. The CPU-ISR processes interrupts int1, int2, and int3 in turn. After the interrupts are processed, the corresponding module CPU-task executes the corresponding task according to the priority of the interrupts. That is, the CPU-ISR waits for all interrupts to arrive, and then processes int1, 2, and 3. After that, CPU-Task2 (Highest Priority) executes Task 2, and CPU-Task1 executes Task 1. After the CPU-ISR processes int2, CPU-Task3 (least Priority) executes Task 3. It can be seen that the CPU Usage is more concentrated in the active and dormant states. If the requests and tasks are completed within the concentrated activation cycle, the dormant state time can be extended and the overall power consumption can be reduced.

[0229] It should be noted that each interrupt can be configured with a delay condition and a maximum delay value to control when interrupt processing starts.

[0230] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0231] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0232] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0233] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A programmable controller comprising: transmission components and delay control components; Wherein, the transmission component is used to receive a request for a processor; The delay control component is used to monitor whether a wake-up condition is met, and the wake-up condition is related to the request; if the wake-up condition is met, control the processor to enter the second state from the first state, and control the transmission component to send the request to the processor, so that the processor processes the request in the second state; The power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

2. The programmable controller according to claim 1, wherein the wake-up condition comprises at least one of the following: When the processor is in the first state, the request received by the transmission component satisfies a threshold parameter, and the request satisfies the threshold parameter includes: The number of the requests reaches a preset request threshold, and / or the waiting time of a target request among the requests reaches a time threshold; The duration threshold and the request are independent of each other, or the duration threshold is determined by a delay parameter of the request, and the delay parameter represents a maximum waiting time that can be delayed for processing corresponding to the request.

3. The programmable controller according to claim 2, wherein the delay control component adjusts the threshold parameter according to a processing parameter; in, The processing parameters are parameters related to the timeliness requirement for request processing.

4. The programmable controller according to claim 1 or 2, wherein the delay control component comprises: Accumulator, delay component; The accumulator is used to receive the request sent by the transmission component, and perform numerical statistics on the requests received by the transmission component when the processor is in the first state to obtain a target value; The delay component is used to obtain the target value from the accumulator, and when the target value meets the threshold parameter, control the processor to enter the second state from the first state, and control the transmission component to send the request to the processor.

5. The programmable controller according to claim 4 further comprising: Activate the component; Among them, the activation component is connected to the delay control component; the delay control component is also used to control the activation component to send an activation signal to the task execution component when the wake-up condition is met, so that the task execution component executes the task corresponding to the request.

6. The programmable controller according to claim 5, wherein the activation component comprises: a first output structure and a plurality of first AND gates; Wherein, the first input port of each of the first AND gates is respectively connected to a signal source, each of the signal sources corresponds to a task execution component, and the signal source provides an activation signal of the corresponding task execution component, and the second input port of each of the first AND gates is an enable port, and the enable port is connected to the delay component, and the enable port is enabled when receiving the enable signal transmitted by the delay component; The output port of each of the first AND gates is respectively connected to the first output structure, the first output structure is connected to the task execution component, and the activation component transmits the activation signal corresponding to the second AND gate whose enable port is enabled to the corresponding task execution component, so that the task execution component executes the task corresponding to the request.

7. The programmable controller according to claim 6, wherein: In the case where there are multiple requests, the delay control component controls the transmission component to send the requests to the processor in a processing order so that the processor processes the requests in the processing order, and the processing order is at least related to an arrival order and / or a request priority corresponding to the requests; and / or, in the case where there are multiple requests corresponding to the same task execution component, the delay control component enables the enable port corresponding to the task execution component so that the task execution component executes the task corresponding to each request according to a task order, and the task order is at least related to the task priority corresponding to the request; And / or, in the case where there are multiple requests corresponding to different task execution components, the delay control component enables the enable port corresponding to each task execution component synchronously or in sequence according to the task order, and the task order is at least related to the task priority corresponding to the request.

8. The programmable controller according to claim 1 or 2, wherein the transmission component comprises: at least one switching component, the switching component comprising at least a first input port, a second input port, a first output port, and a second output port; Wherein, the first input port is used to receive the request; the first input port is connected to the first output port under a first instruction, and the first output port is connected to the delay control component; the first instruction is used to instruct to delay the request; The second input port is connected to the delay control component, the second input port is connected to the second output port, and the second output port is connected to the processor.

9. The programmable controller according to claim 8, wherein the transmission component comprises: a second output structure, the second output structure being connected to the processor; Wherein, the switching component further includes: a third output port; the third output port is connected to the second output structure; and the first input port is connected to the third output port under a second instruction; the second instruction is used to indicate not to delay the request.

10. The programmable controller according to claim 1 or 2, after the wake-up condition is met, when the transmission component receives a new request for the processor, the delay control component determines whether the processing condition is met; if the processing condition is met, the transmission component is controlled to send the new request to the processor, so that the processor processes the new request in the second state; If the processing condition is not met, the delay control component controls the transmission component to send the request to the processor when the wake-up condition is met again, so that the processor processes the new request when the wake-up condition is met again; in, The processing condition includes: a maximum delay duration corresponding to the new request is less than or equal to a delay threshold, and the delay threshold is related to a remaining processing duration of a current processing request by the processor.

11. An electronic device, comprising at least: Programmable controllers, processors; The programmable controller includes: a transmission component and a delay control component; Wherein, the transmission component is used to receive a request for a processor; The delay control component is used to monitor whether a wake-up condition is met, and the wake-up condition is related to the request; if the wake-up condition is met, control the processor to enter the second state from the first state, and control the transmission component to send the request to the processor, so that the processor processes the request in the second state; The power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

12. The electronic device according to claim 11, further comprising: at least one task execution component; The programmable controller further comprises: an activation component; Wherein, the delay control component includes: an accumulator, a delay component; the activation component includes: a first output structure and a plurality of first AND gates; The accumulator is used to receive the request sent by the transmission component, and perform numerical statistics on the requests received by the transmission component when the processor is in the first state to obtain a target value; The delay component is used to obtain the target value from the accumulator, and when the target value satisfies the threshold parameter, control the processor to enter the second state from the first state, and control the transmission component to send the request to the processor; Wherein, the first input port of each of the first AND gates is respectively connected to a signal source, each of the signal sources corresponds to a task execution component, and the signal source provides an activation signal of the corresponding task execution component, and the second input port of each of the first AND gates is an enable port, and the enable port is connected to the delay component, and the enable port is enabled when receiving the enable signal transmitted by the delay component; The output port of each of the first AND gates is respectively connected to the first output structure, the first output structure is connected to the task execution component, and the activation component transmits the activation signal corresponding to the second AND gate whose enable port is enabled to the corresponding task execution component, so that the task execution component executes the task corresponding to the request.

13. A control method, applied to a programmable controller, comprising: receiving a request for a processor; monitoring whether a wake-up condition is satisfied, the wake-up condition being associated with the request; When the wake-up condition is met, controlling the processor to enter a second state from the first state, and sending the request to the processor so that the processor processes the request in the second state; The power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

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