Programmable controller, electronic equipment and control method

Abstract

The invention discloses a programmable controller, electronic equipment and a control method. The programmable controller comprises a transmission component and a delay control component, wherein the transmission component is used for receiving a request for a processor; the delay control component is used for monitoring whether a wake-up period is reached or not, and controlling the transmission component to send the request to the processor under the condition that the wake-up period is reached, so that the processor processes the request in the wake-up period; wherein the processor is in a first state under the condition that the wake-up period is not reached, and the processor is in a second state under the condition that the wake-up period is reached; the power consumption of the processor in the first state is lower than that of the processor in the second state.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a programmable controller, an electronic device and a control method. Background Art

[0002] Currently, when computers perform various computing tasks, they require the support of various functional modules, such as processor cores, buses, phase-locked loops, memory, etc.

[0003] If the computer continues to perform various computing tasks, the processor will continue to be in a running state, resulting in higher power consumption of the computer. Summary of the invention

[0004] In view of this, the present application provides a programmable controller, an electronic device and a control method as follows:

[0005] A programmable controller, comprising:

[0006] transmission components and delay control components;

[0007] Wherein, the transmission component is used to receive a request for a processor;

[0008] The delay control component is used to monitor whether the wake-up cycle arrives, and when the wake-up cycle arrives, control the transmission component to send the request to the processor so that the processor processes the request within the wake-up cycle;

[0009] Wherein, when the wake-up cycle has not arrived, the processor is in a first state, and when the wake-up cycle arrives, the processor is in a second state; the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

[0010] The above programmable controller, preferably, the wake-up cycle arrives, including:

[0011] The first quantity reaches a preset target quantity;

[0012] The first number is: the number of clock ticks experienced by the processor in the first state.

[0013] In the above-mentioned programmable controller, preferably, the clock beat is the clock beat of the target component, and the target component is a component selected from a plurality of components having clock beats;

[0014] The clock beat of the target component is selected by the following structure:

[0015] a plurality of first AND gates and a first output structure;

[0016] The first input port of each of the first AND gates is connected to a clock beat source, the clock beat source is derived from a component with a clock beat, the second input port of each of the first AND gates is an enable port, the enable port is enabled when an enable signal is received, and the component connected to the first AND gate with the enabled enable port is the target component;

[0017] The output port of each of the first AND gates is connected to the first output structure, and the first output structure is connected to the delay control component, so that the first output structure provides the clock beat of the target component to the delay control component.

[0018] In the above programmable controller, preferably, the delay control component comprises:

[0019] An input structure, a first component, and a second component;

[0020] Wherein, the input structure is used to receive the request sent by the transmission component;

[0021] The first component is used to obtain a delay parameter corresponding to the request;

[0022] The second component is used to obtain the number of delay cycles corresponding to the request based on the delay parameter; monitor whether the wake-up cycle has arrived, and when the wake-up cycle arrives and the wake-up cycle matches the number of delay cycles, control the transmission component to send the request to the processor so that the processor processes the request within the wake-up cycle.

[0023] The above-mentioned programmable controller preferably further comprises: an activation component;

[0024] Among them, the activation component is connected to the delay control component; the delay control component is also used to control the activation component to send an activation signal to the task execution component when the wake-up cycle arrives, so that the task execution component executes the task corresponding to the request within the wake-up cycle.

[0025] In the above programmable controller, preferably, the activation component comprises:

[0026] a second output structure and a plurality of second AND gates;

[0027] Wherein, the first input port of each second AND gate is respectively connected to a signal source, each signal source corresponds to a task execution component, the signal source provides an activation signal of the corresponding task execution component, the second input port of each second AND gate is an enable port, and the enable port is connected to the second component, and the enable port is enabled when receiving the enable signal transmitted by the second component;

[0028] The output port of each of the second AND gates is respectively connected to the second output structure, the second output structure is connected to the task execution component, and the activation component transmits the activation signal corresponding to the second AND gate whose enable port is enabled to the corresponding task execution component, so that the task execution component executes the task corresponding to the request within the wake-up cycle.

[0029] The above programmable controller is preferably wherein:

[0030] In the case where there are multiple requests, the delay control component controls the transmission component to send the requests to the processor in a processing order so that the processor processes the requests in the processing order, and the processing order is related to the arrival order and / or request priority corresponding to the requests;

[0031] and / or, in the case where there are multiple requests corresponding to the same task execution component, the delay control component enables the enable port corresponding to the task execution component so that the task execution component executes the task corresponding to each request according to the task sequence; the task sequence is at least related to the task priority corresponding to the request;

[0032] And / or, in the case where there are multiple requests corresponding to different task execution components, the delay control component enables the enable port corresponding to each task execution component synchronously or in sequence according to the task order, so that each task execution component executes the task corresponding to the corresponding request according to the task order; the task order is at least related to the task priority corresponding to the request.

[0033] In the above programmable controller, preferably, the transmission component comprises:

[0034] at least one switching component, the switching component comprising at least a first input port, a second input port, a first output port, and a second output port;

[0035] Wherein, the first input port is used to receive the request; the first input port is connected to the first output port under a first instruction, and the first output port is connected to the delay control component; the first instruction is used to instruct to delay the request;

[0036] The second input port is connected to the delay control component, the second input port is connected to the second output port, and the second output port is connected to the processor.

[0037] In the above programmable controller, preferably, the transmission component further comprises:

[0038] a third output structure, the third output structure connected to the processor;

[0039] Wherein, the switching component further includes:

[0040] a third output port; the third output port is connected to the third output structure; and the first input port is connected to the third output port under a second instruction; the second instruction is used to indicate not to delay the request.

[0041] The above-mentioned programmable controller, preferably, after the wake-up cycle is reached, when the transmission component receives a new request for the processor, the delay control component determines whether the processing condition is met; if the processing condition is met, the transmission component is controlled to send the new request to the processor, so that the processor processes the new request within the wake-up cycle;

[0042] If the processing condition is not met, the delay control component controls the transmission component to send the new request to the processor in a subsequent wake-up cycle corresponding to the wake-up cycle, so that the processor processes the new request in the subsequent wake-up cycle corresponding to the wake-up cycle;

[0043] The processing condition includes: the number of beats required for processing the new request is less than or equal to the number of remaining beats in the wake-up cycle.

[0044] An electronic device comprising at least:

[0045] A programmable controller, a processor and a target component; the target component provides a clock beat for the programmable controller;

[0046] Wherein, the programmable controller comprises: a transmission component and a delay control component;

[0047] The transmission component is used to receive a request for the processor;

[0048] The delay control component is used to monitor whether a wake-up cycle has arrived. When the wake-up cycle has arrived, the delay control component controls the transmission component to send the request to the processor so that the processor processes the request within the wake-up cycle. The arrival of the wake-up cycle includes: a first number reaching a preset target number; the first number is: the number of clock beats experienced by the processor in the first state;

[0049] Wherein, when the wake-up cycle has not arrived, the processor is in the first state, and when the wake-up cycle arrives, the processor is in the second state; the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

[0050] The above electronic device preferably further includes:

[0051] at least one task execution component; the programmable controller further comprises: an activation component;

[0052] Wherein, the delay control component comprises: an input structure, a first component, and a second component; the activation component comprises: a second output structure and a plurality of second AND gates;

[0053] Wherein, the input structure is used to receive the request sent by the transmission component;

[0054] The first component is used to obtain a delay parameter corresponding to the request;

[0055] The second component is used to obtain the number of delay cycles corresponding to the request according to the delay parameter; monitor whether the wake-up cycle has arrived, and when the wake-up cycle has arrived and the wake-up cycle matches the number of delay cycles, control the transmission component to send the request to the processor so that the processor processes the request within the wake-up cycle;

[0056] Wherein, the first input port of each of the second AND gates is respectively connected to a signal source, each of the signal sources corresponds to one of the task execution components, the signal source provides an activation signal of the corresponding task execution component, the second input port of each of the second AND gates is an enable port, and the enable port is connected to the second component, and the enable port is enabled when receiving an enable signal transmitted by the second component;

[0057] The output port of each of the second AND gates is respectively connected to the second output structure, the second output structure is connected to the task execution component, and the activation component transmits the activation signal corresponding to the second AND gate whose enable port is enabled to the corresponding task execution component, so that the task execution component executes the task corresponding to the request within the wake-up cycle.

[0058] A control method, applied to a programmable controller, comprising:

[0059] receiving a request for a processor;

[0060] monitoring whether a wake-up cycle has arrived, and sending the request to the processor when the wake-up cycle has arrived, so that the processor processes the request within the wake-up cycle;

[0061] Wherein, when the wake-up cycle has not arrived, the processor is in a first state, and when the wake-up cycle arrives, the processor is in a second state; the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0063] Figure 1 A schematic diagram of the structure of a programmable controller provided in Example 1 of the present application;

[0064] Figure 2 This is an example diagram of a wake-up cycle based on a clock beat in an embodiment of the present application;

[0065] Figure 3 This is an example diagram of a time-based wake-up cycle in an embodiment of the present application;

[0066] Figure 4 This is an example diagram of a wake-up cycle based on clock beats and time in an embodiment of the present application;

[0067] Figure 5 A schematic diagram of a structure for selecting a target component to provide a clock beat for a delay control component in an embodiment of the present application;

[0068] Figure 6 An example diagram for providing a clock beat for selecting a target component in an embodiment of the present application;

[0069] Figure 7 This is a schematic diagram of the structure of the delay control component in the embodiment of the present application;

[0070] Figure 8 Another structural schematic diagram of a programmable controller provided in Embodiment 1 of the present application;

[0071] Fig. 9 This is a schematic diagram of the structure of the activation component in Example 1 of the present application;

[0072] Fig.10 This is a schematic diagram of the structure of the transmission component in Example 1 of the present application;

[0073] Fig.11 This is another structural schematic diagram of the transmission component in the first embodiment of the present application;

[0074] Fig.12This is another structural schematic diagram of the transmission component in the first embodiment of the present application;

[0075] Fig.13 A schematic diagram of the structure of an electronic device provided in Embodiment 2 of the present application;

[0076] Fig.14 Another structural schematic diagram of an electronic device provided in Embodiment 2 of the present application;

[0077] Fig.15 A flow chart of a control method provided in Embodiment 3 of the present application;

[0078] Fig.16 It is a schematic diagram of non-aligned activities of functional modules and common modules in the system of the computer in this embodiment;

[0079] Fig.17 It is a schematic diagram of the common module alignment activity in the system wake-up cycle of the computer in this embodiment;

[0080] Fig.18 This is a hardware architecture diagram of the device where the periodic activity controller PAC is located in this embodiment;

[0081] Fig.19 This is a schematic diagram of the structure of selecting a Tick source for PAC in this embodiment;

[0082] Fig. 20 Schematic diagram of the structure of PAC in this embodiment;

[0083] Fig.21 This is a schematic diagram of the structure of the PAC activation hardware module in this embodiment;

[0084] Fig. 22 This is an example diagram for recording status information of hardware modules in this embodiment;

[0085] Fig.23 This is a schematic diagram of comparing the scenarios with and without interruption alignment in this embodiment;

[0086] Fig.24 This is a schematic diagram of a scenario in which an interrupt is received in an inactive state in this embodiment;

[0087] Fig.25 This is a schematic diagram of a scenario in which the interrupt delay exceeds the activation period in this embodiment;

[0088] Fig.26 This is a schematic diagram of a scenario in which a delayed interrupt is triggered based on time within an activation cycle in this embodiment. DETAILED DESCRIPTION

[0089] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0090] At present, after the processor in the computer completes the processing of an interrupt, it usually enters a low-power sleep state until the next interrupt arrives. However, each time an interrupt arrives, the processor needs to be woken up, causing the processor to frequently switch between sleep and wake-up, which results in a relatively short and scattered period of time in the processor's sleep state, resulting in higher power consumption of the processor.

[0091] In view of this, refer to Figure 1 As shown, it is a schematic diagram of the structure of a programmable controller provided in the first embodiment of the present application, and the programmable controller can be applied to an electronic device with a processor, such as a computer or a server. The programmable controller can be represented by PAC (Programmable Automation Controller). The technical solution in this embodiment is mainly used to reduce the power consumption of electronic equipment.

[0092] Specifically, the programmable controller in this embodiment may include the following structure:

[0093] A transmission component 1 and a delay control component 2;

[0094] The transmission component 1 is used to receive a request for the processor; the request here may be an interrupt request, or may be called an interrupt instruction, such as interrupts, which is used to instruct the processor to perform corresponding processing.

[0095] The delay control component 2 is used to monitor whether the wake-up cycle has arrived. When the wake-up cycle has arrived, the control transmission component 1 sends the request to the processor so that the processor processes the request within the wake-up cycle;

[0096] Wherein, when the wake-up cycle has not arrived, the processor is in the first state, and when the wake-up cycle has arrived, the processor is in the second state; the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

[0097] Specifically, the transmission component 1 can be implemented using logic gates to receive a request for a processor and send the request to the processor under the control of the delay control component 2 .

[0098] The delay control component 2 can be implemented by logic gates and state machines to monitor whether the wake-up cycle has arrived and control the transmission component 1 to send the received request to the processor when the wake-up cycle has arrived. Specifically, the delay control component 2 can send a control signal to the transmission component 1 so that the transmission component 1 sends the received request to the processor.

[0099] In one implementation, the wake-up cycle can be set based on the clock beats on the electronic device. For example, a wake-up cycle is a target number of clock beats, that is, a wake-up cycle is reached every target number of clock beats, and the number of clock beats in the wake-up cycle can be the target number or other numbers. Correspondingly, the arrival of the wake-up cycle can be: the first number reaches the target number, and the first number is: the number of clock beats experienced by the processor in the first state. Thus, after the processor enters the first state, the delay control component 2 monitors whether the number of clock beats experienced by the processor reaches the target number. If the number of clock beats experienced by the processor reaches the target number, it is determined that the wake-up cycle has arrived. At this time, the processor enters the second state, and the delay control component 2 controls the transmission component 1 to send a request for the processor to the processor, so that the processor in the second state processes the corresponding request.

[0100] It should be noted that after the wake-up cycle ends, the processor enters the first state again. For example, in this embodiment, after the processor enters the first state, it reaches a wake-up cycle every target number of clock beats. After reaching the wake-up cycle, the processor enters the second state, and after the target number of clock beats, the processor enters the first state, and the cycle repeats. The processor switches between the first state and the second state every target number of clock beats. Figure 2 as shown in .

[0101] In another implementation, the wake-up cycle can be set based on the time on the electronic device. For example, a wake-up cycle is a target duration, that is, a wake-up cycle is reached every target duration, and the duration in the wake-up cycle can be the target duration or other durations. Correspondingly, the wake-up cycle can be reached from the first duration to the target duration; the first duration is the duration experienced by the processor in the first state. Thus, after the processor enters the first state, the delay control component 2 monitors whether the duration experienced by the processor reaches the target duration. If the duration experienced by the processor reaches the target duration, it is determined that the wake-up cycle has arrived. At this time, the processor enters the second state, and the delay control component 2 controls the transmission component 1 to send a request for the processor to the processor, so that the processor in the second state processes the corresponding request.

[0102] It should be noted that after the wake-up cycle ends, the processor enters the first state again. For example, in this embodiment, after the processor enters the first state, a wake-up cycle is reached every target time. After reaching the wake-up cycle, the processor enters the second state, and after the target time, the processor enters the first state, and the cycle repeats. The processor switches between the first state and the second state every target time. Figure 3 as shown in .

[0103] In one implementation, the wake-up period may be based on a clock tick on the electronic device and / or a time setting on the electronic device.

[0104] Among them, when the wake-up cycle is based on the clock beats on the electronic device and the time setting on the electronic device, a wake-up cycle is a target number of clock beats or a target duration, that is, after experiencing a target number of clock beats or a target duration, a wake-up cycle is reached. Specifically, it can be understood that if any of the two conditions that the number of experienced clock beats reaches the target number and the experienced duration reaches the target duration is met, then the wake-up cycle arrives. The length of the wake-up cycle can be a target duration or a target number of clock beats. For example, if the number of experienced clock beats reaches the target number first, then the wake-up cycle arrives; if the experienced duration reaches the target duration first, then the wake-up cycle arrives.

[0105] Specifically, the arrival of the wake-up cycle can be: the first number reaches the target number or the first duration reaches the target duration. Therefore, after the processor enters the first state, the delay control component 2 monitors whether the number of clock beats experienced by the processor reaches the target number, and monitors whether the duration experienced by the processor reaches the target duration. If the number of clock beats experienced by the processor reaches the target number or the duration experienced by the processor reaches the target duration, it is determined that the wake-up cycle has arrived. At this time, the processor enters the second state, and the delay control component 2 controls the transmission component 1 to send a request for the processor to the processor, so that the processor in the second state processes the corresponding request.

[0106] It should be noted that after the wake-up cycle ends, the processor enters the first state again. For example, in this embodiment, after the processor enters the first state, if the number of experienced clock beats reaches the target number first, then the processor enters the second state and enters the first state again after experiencing the target number of clock beats; if the experienced duration reaches the target duration first, then the processor enters the second state and enters the first state again after experiencing the target duration, and the cycle repeats. The processor switches between the first state and the second state based on the target number of clock beats and the target duration. Figure 4 as shown in .

[0107] In the case where the wake-up cycle is based on a clock tick on the electronic device or a time setting on the electronic device, a wake-up cycle is a target number of clock ticks or a target duration, one of which is selected. For example, if the wake-up cycle is based on a clock tick setting, the wake-up cycle is reached when the number of experienced clock ticks reaches the target number; if the wake-up cycle is based on a time setting, the wake-up cycle is reached when the experienced duration reaches the target duration.

[0108] Among them, in this embodiment, the wake-up period can be set based on the clock beat or the time setting according to actual needs. In one case, if the electronic device includes a component with a clock beat, such as a communication module, the wake-up period can be set to: a target number of clock beats. In another case, if the electronic device does not include a component with a clock beat, the wake-up period can be set to: a target duration. In another case, if the electronic device includes a component with a clock beat, such as a communication module, the wake-up period can be set to: a target number of clock beats or a target duration according to the user's selection operation.

[0109] Specifically, after the processor enters the first state, the delay control component 2 monitors whether the number of clock beats experienced by the processor reaches the target number, or monitors whether the duration experienced by the processor reaches the target duration. If the number of clock beats experienced by the processor reaches the target number or the duration experienced by the processor reaches the target duration, it is determined that the wake-up cycle has arrived. At this time, the processor enters the second state, and the delay control component 2 controls the transmission component 1 to send a request for the processor to the processor, so that the processor in the second state processes the corresponding request.

[0110] It should be noted that when the processor is in the first state, a request to the processor arrives but will be delayed until the processor enters the second state. Different requests can accept different maximum delay times. In this embodiment, the number of cycles or duration for which the request is delayed can be set based on parameters such as the priority of the request, so that the request can be processed before the latest acceptable processing time, without affecting the user's use of the electronic device.

[0111] It can be seen from the above technical scheme that in a programmable controller provided in the first embodiment of the present application, a transmission component and a delay control component are set in the programmable controller, and the processor is in a first state when the wake-up cycle has not arrived, and in a second state when the wake-up cycle has arrived. The power consumption of the processor in the first state is lower than the power consumption of the processor in the second state. Based on this, in the programmable controller, a request for the processor is received through the transmission component, so that the delay control component monitors whether the wake-up cycle has arrived. When the wake-up cycle arrives, the transmission component is controlled to send the request to the processor so that the processor processes the request within the wake-up cycle. It can be seen that in this embodiment, the processor is configured with a wake-up cycle. Only when the wake-up cycle arrives, the processor will enter a state with higher power consumption to process the request. When the wake-up cycle does not arrive, the processor is in a state with lower power consumption and does not process the request. Therefore, by concentrating the request in the wake-up cycle for processing, the processor is prevented from frequently switching between high power consumption and low power consumption, and the processor is prevented from being in a state of higher power consumption continuously. Then, by reducing the duration of the processor in a state of higher power consumption, the power consumption of the electronic device where the processor is located is reduced.

[0112] Moreover, in this embodiment, the hardware implementation of the programmable controller has a faster response speed than the software method, which can improve the efficient control of the processor and avoid excessive delay.

[0113] Taking the wake-up cycle as an example, the technical solution in this embodiment is described below:

[0114] In one implementation, the clock beat is the clock beat of the target component, the target component is a component selected from multiple components with clock beats, a component with a clock beat can be used as one or more clock beat sources, and each clock beat source can provide a clock beat for the wake-up cycle. For example, the electronic device includes multiple components with clock beats, such as a communication component, an audio component, etc. Based on this, one of these components is selected as the target component, and the clock beat of the target component is used as the beat source of the wake-up cycle.

[0115] Based on this, in this embodiment, the clock beat of the target component is selected through the following structure, such as Figure 5 As shown in:

[0116] A plurality of first AND gates 3 and a first output structure 4, wherein a first input port 5 of each first AND gate 3 is connected to a clock beat source a, the clock beat source is derived from a component having a clock beat, and a second input port 6 of each first AND gate 3 is an enable port, which is enabled when receiving an enable signal, i.e., the enable port is in an enabled state, and the component connected to the first AND gate 3 whose enable port is enabled, i.e., in an enabled state, is a target component;

[0117] The output port 7 of each first AND gate 3 is connected to the first output structure 4 , and the first output structure 4 is connected to the delay control component 2 , so that the first output structure 4 provides the clock beat of the target component to the delay control component 2 .

[0118] Specifically, the first output structure 4 can be implemented by using an OR gate.

[0119] It should be noted that Figure 5 The structure shown, i.e., the plurality of first AND gates 3 and the first output structure 4, may be a structure configured inside the programmable controller, or may be a structure connected to the programmable controller and independent of the programmable controller. Figure 5 The structure shown can be integrated into a module (component) that provides a clock beat, and the module will filter the appropriate clock beat and then send it to the programmable controller.

[0120] based on Figure 5 As shown in the structure, in this embodiment, each clock beat source in the electronic device is connected to a first input port 5 of a first AND gate 3, and by enabling the second input port 6 of one of the first AND gates 3, the component connected to the first AND gate 3 becomes the target component, thereby providing the clock beat of the target component to the delay control component 2 through the first output structure 4.

[0121] For example, Figure 6 As shown in the figure, there are three components in the electronic device with clock beats: component [1], component [2] and component [3], which respectively provide clock beats of different periods. The second input port 6 of the first AND gate 3 connected to component [2] is enabled according to demand, so that component [2] is the target component. The clock beat of component [2] is output to the delay control component 2 through the first output structure. The delay control component 2 monitors whether the number of clock beats experienced by the processor reaches the target number after the processor enters the first state according to the clock beat provided by component [2]. If the number of clock beats experienced by the processor reaches the target number, it is determined that the wake-up cycle has arrived. At this time, the processor enters the second state, and the delay control component 2 controls the transmission component 1 to send a request for the processor to the processor, so that the processor in the second state processes the corresponding request.

[0122] It should be noted that the duration of the clock tick is related to the target component. For example, in LTE (Long Term Evolution) firmware, the clock tick is triggered every 1ms; in 3G communication scenarios, the clock tick is triggered every 2ms or 10ms, and so on.

[0123] In one implementation, the delay control component 2 may include the following structure: Figure 7 As shown in:

[0124] An input structure 8, a first component 9 and a second component 10;

[0125] Wherein, the input structure 8 can be implemented with an OR gate, and is used to receive the request sent by the transmission component 1;

[0126] The first component 9 is connected to the input structure 8 and is used to obtain the delay parameter corresponding to the request;

[0127] The second component 10 is connected to the first component 9, and is used to obtain the number of delay cycles corresponding to the request based on the delay parameter; monitor whether the wake-up cycle has arrived, and when the wake-up cycle arrives and the wake-up cycle matches the number of delay cycles, control the transmission component 1 to send the request to the processor so that the processor processes the request within the wake-up cycle.

[0128] Specifically, the second component 10 sends a control signal to the transmission component 1, so that the transmission component 1 sends the request to the processor.

[0129] Among them, the first component 9 and the second component 10 can be implemented as a state machine. Based on this, the first component 9 obtains the corresponding delay parameters for the request received by the input structure 8, such as priority parameters or maximum delay duration, and the delay parameters can characterize the number of delay cycles corresponding to the request. For example, if the priority of the request is the highest priority, then the delay parameter characterizes the minimum number of delay cycles corresponding to the request, such as 0; for another example, if the priority of the request is a medium priority, then the delay parameter characterizes the medium number of delay cycles corresponding to the request, such as 2; for another example, if the priority of the request is the lowest priority, then the delay parameter characterizes the maximum number of delay cycles corresponding to the request, such as 5. Based on this, the second component 10 can parse the delay parameter according to the target number corresponding to the wake-up cycle, and then obtain the number of delay cycles corresponding to the request.

[0130] For example, the delay parameter includes the priority of the request, and the second component 10 allocates the number of delay cycles to the request according to the priority.

[0131] For example, the delay parameters include the maximum delay duration of the request. The second component 10 compares the maximum delay duration with the duration of the target number of clock beats to obtain the number of cycles of the target number of clock beats included in the maximum delay duration, that is, the requested number of delay cycles.

[0132] It should be noted that the number of delay cycles can be understood as: the number of wake-up cycles that the request can be delayed. For example, the request can be delayed for 2 wake-up cycles before processing, or the request can only be delayed for one wake-up cycle before processing. Based on this, when the second component 10 detects the arrival of the wake-up cycle, it also determines whether the currently arrived wake-up cycle matches the number of delay cycles requested, that is, whether the number of wake-up cycles that have been delayed in the currently arrived wake-up cycle has reached the number of delay cycles. If so, the second component 10 controls the transmission component 1 to send the request to the processor so that the processor processes the request within the wake-up cycle.

[0133] For example, when the second component 10 monitors the arrival of the wake-up cycle, it finds that the request has been delayed by 2 wake-up cycles, which is consistent with the number of delay cycles of 2 requested. This indicates that the request can no longer be delayed to the next wake-up cycle for processing. At this time, the second component 10 controls the transmission component 1 to send the request to the processor so that the processor processes the request within the wake-up cycle.

[0134] Among them, when the wake-up cycle arrives and matches its delay cycle number, there may be a request in a waiting state but the currently arrived wake-up cycle does not match its delay cycle number, that is, the number of cycles the request is waiting for has not reached the delay cycle number. At this time, the second component 10 controls the transmission component 1 to send the request to the processor while controlling the transmission component 1 to send all requests in the waiting state to the processor to speed up the processing of other requests whose waiting time has not reached the maximum delay time to ensure timeliness.

[0135] Based on the above implementation, the programmable controller in this embodiment may also include the following structure, such as Figure 8 As shown in:

[0136] The activation component 11 is connected to the delay control component 2. The delay control component 2 is also used to control the activation component 11 to send an activation signal to the task execution component when the wake-up cycle arrives, so that the task execution component executes the task corresponding to the request within the wake-up cycle.

[0137] Among them, the activation component 11 can be connected to each task execution component in the electronic device, so that for any request, the activation component 11 can send a corresponding activation signal to the task execution component corresponding to each request under the control of the delay control component 2, so that the task execution component executes the task corresponding to the request within the wake-up cycle.

[0138] It should be noted that the task execution component is in a dormant state before receiving the activation signal, and enters an activated state after receiving the activation signal. The power consumption of the task execution component in the dormant state is lower than that in the activated state. Furthermore, the task execution component enters a dormant state again after completing the task.

[0139] Specifically, the activation component 11 may include the following structure: Fig. 9 As shown in:

[0140] a second output structure 12 and a plurality of second AND gates 13 .

[0141] Among them, the first input port 14 of each second AND gate 13 is respectively connected to a signal source b, each signal source corresponds to a task execution component c, and the signal source b provides an activation signal for its corresponding task execution component c. The second input port 15 of each second AND gate 13 is an enable port, and the enable port is connected to the second component 10. The enable port is enabled when it receives the enable signal transmitted by the second component 10.

[0142] Among them, the task execution component is a component that executes the task corresponding to the request, such as a communication module, a bus, a codec and other components.

[0143] Moreover, the output port 16 of each second AND gate 13 is respectively connected to the second output structure 12, and the second output structure 12 is connected to the task execution component c. The activation component 11 transmits the activation signal corresponding to the second AND gate 13 whose enable port is enabled to the corresponding task execution component c through the second output structure 12, so that the task execution component c executes the task corresponding to the request within the wake-up cycle.

[0144] The second output structure 12 can be implemented by an OR gate.

[0145] In one implementation, the second component 10 transmits the enable signal through the connection with the enable port to reduce signal transmission delay;

[0146] In another implementation, the second component 10 is configured with a register, the register stores configuration information, and the corresponding enable port is enabled according to the configuration information.

[0147] It can be seen that in this embodiment, in addition to controlling the transmission component 1 to send the request to the processor, the second component 10 also sends an enable signal to the enable port on the second AND gate 13 in the activation component 11, such as Fig. 9As shown in the figure, the signal source corresponding to the second AND gate 13 that enables the enable port provides an activation signal for the corresponding task execution component, and then the activation signal is output to the corresponding task execution component through the second output structure 12. Thus, after the processor processes the request within the wake-up cycle, the task execution component corresponding to the request can execute the corresponding task within the wake-up cycle.

[0148] In a specific implementation, the request may be one or more.

[0149] In one implementation, when there are multiple requests, the delay control component 2 controls the transmission component to send the requests to the processor in a processing order so that the processor processes the requests in the processing order. The processing order here is related to the arrival order and / or request priority of the requests.

[0150] For example, the processing order includes: the order of request priority from high to low, and the order of arrival from first to last in the same request priority. That is, the delay control component 2 controls the transmission component 1 to preferentially transmit the request with higher request priority. When the request priorities are the same, the delay control component 2 controls the transmission component 1 to preferentially transmit the request that arrives first. Based on this, the processor preferentially processes the request with higher request priority. When the request priorities are the same, the processor preferentially processes the request that arrives first.

[0151] In another implementation, when there are multiple requests corresponding to the same task execution component, the delay control component 2 enables the enable port corresponding to the task execution component so that the task execution component executes the task corresponding to each request according to the task order. The task order is at least related to the task priority corresponding to the request.

[0152] The request priorities between different requests and the task priorities of the corresponding requests may be the same or different.

[0153] For example, the task order includes: the order of task priorities from high to low. Further, the task order also includes: the order of arrival of requests with the same task priority from first to last. For example, after the delay control component 2 enables the enable port corresponding to the task execution component, the task execution component with a higher task priority will give priority to executing the task corresponding to the request. When the task priorities are the same, the task execution component will give priority to executing the task corresponding to the request that arrives first.

[0154] Specifically: the second component 10 controls the transmission component 1 to send the request to the processor according to the processing order, and the second component 10 sends an enable signal to the enable port corresponding to the task execution component on the second AND gate 13 in the activation component 11, so that the signal source corresponding to the second AND gate 13 whose enable port is enabled provides an activation signal for the corresponding task execution component, and then the activation signal is output to the corresponding task execution component through the second output structure 12. Therefore, after the processor processes the request according to the processing order within the wake-up cycle, the task execution component corresponding to the request can also execute the corresponding task in the wake-up cycle in sequence according to the task order under the activation signal.

[0155] For example, there are three requests for the processor, namely, request 1, request 2 and request 3. Request 1 arrives at transmission component 1 earlier than request 2 and request 3. Request 2 and request 1 have the same priority, and request 3 has a higher priority than request 2 and request 1. Request 1, request 2 and request 3 all correspond to task execution component [1]. Based on this, when the second component 10 detects that the wake-up cycle arrives and matches the number of delay cycles of the three requests, the second component 10 controls transmission component 1 to send requests 3, request 1 and request 2 to the processor in the order of request 3, request 1 and request 2, and sends an enable signal to the enable port corresponding to task execution component [1] on the second AND gate 13 in the activation component 11, thereby enabling task execution component [1]. Based on this, the processor processes the three requests in the order of request 3, request 1 and request 2 during the wake-up cycle, and task execution component [1] first processes the task corresponding to request 3, then task execution component [1] executes the task corresponding to request 1, and task execution component [1] executes the task corresponding to request 2.

[0156] In another implementation, when there are multiple requests corresponding to different task execution components, the delay control component 2 enables the enable port corresponding to each task execution component synchronously or in sequence according to the task order, so that each task execution component executes the task corresponding to the corresponding request according to the task order. The task order is at least related to the task priority corresponding to the request.

[0157] For example, the task order includes: the order of task priorities from high to low. Further, the task order also includes: the order of arrival of requests in the same task priority from first to last. For example, the delay control component 2 gives priority to enabling the enable port corresponding to the task execution component with a higher task priority. When the task priorities are the same, the delay control component 2 gives priority to enabling the enable port corresponding to the task execution component corresponding to the request that arrives first. Based on this, the task execution component with a higher task priority gives priority to executing the task corresponding to the request. When the task priorities are the same, the task execution component corresponding to the request that arrives first gives priority to executing the task corresponding to the request.

[0158] Specifically: the second component 10 controls the transmission component 1 to send the request to the processor according to the processing order, and the second component 10 sends an enable signal to the enable port corresponding to the task execution component on the second AND gate 13 in the activation component 11 in the task order, so that the signal source corresponding to the second AND gate 13 whose enable port is enabled provides the activation signal of the corresponding task execution component in the task order, and then the activation signal is output to the corresponding task execution component through the second output structure 12. Therefore, after the processor processes the request in the processing order within the wake-up cycle, the task execution component corresponding to the request can also execute the corresponding task in the wake-up cycle in the task order under the activation signal.

[0159] For example, there are three requests for the processor, request 1, request 2, and request 3. Request 1, request 2, and request 3 arrive at transmission component 1 in sequence. Request 2 and request 1 have the same request priority, and request 3 has a higher request priority than request 2 and request 1. Request 1 corresponds to task execution component [1], request 2 corresponds to task execution component [2], and request 3 corresponds to task execution component [3]. The task priority of request 2 is the same as the task priority of request 3 and is higher than the task priority of request 1. Based on this, when the second component 10 detects that the wake-up cycle arrives and matches the number of delay cycles of the three requests, the second component 10 controls the transmission component 1 to execute request 3. , request 1, and request 2 are sent to the processor in the order of task execution component [2], task execution component [3], and task execution component [1], and enable signals are sent to the enable ports corresponding to the task execution components on the second AND gate 13 in the activation component 11 in the order of task execution component [2], task execution component [3], and task execution component [1], thereby enabling task execution component [2], task execution component [3], and task execution component [1] in turn. Based on this, the processor processes the three requests in the order of request 3, request 1, and request 2 during the wake-up cycle, and task execution component [2] first processes the task corresponding to request 2, then task execution component [3] executes the task corresponding to request 3, and task execution component [1] executes the task corresponding to request 1.

[0160] In one implementation, the transmission component 1 may include the following structure: Fig.10 As shown:

[0161] At least one switching component 17, the switching component 17 can be represented by switch, and the switching component 17 at least includes a first input port 18, a second input port 19, a first output port 20, and a second output port 21;

[0162] The first input port 18 is used to receive a request for the processor; the first input port 18 is connected to the first output port 20 under a first instruction, the first output port 20 is connected to the delay control component 2, and the first instruction is used to instruct to delay the request for the processor.

[0163] The second input port 19 is connected to the delay control component 2 , the second input port 19 is connected to the second output port 21 , and the second output port 21 is connected to the processor.

[0164] Thus, a request for the processor is received through the first input port 18, and the first output port 20 is connected under the first instruction, so that the request is transmitted to the delay control component 2, the delay control component 2 obtains the corresponding delay parameter based on the content of the request, and obtains the number of delay cycles corresponding to the request according to the delay parameter, and sends a control signal to the second input port 19 when monitoring the arrival of the wake-up cycle and the arrived wake-up cycle matches the number of delay cycles corresponding to the request, and the control signal is transmitted to the second output port 21 through the second input port 19, and the second output port 21 is controlled to transmit the request to the processor connected to the second output port 21, so that the processor processes the request within the wake-up cycle.

[0165] It should be noted that the first input port 18 is also connected to the second output port 21. Fig.11 As shown in , the second output port 21 sends the request received by the first input port 18 to the processor when receiving the control signal, so that the processor can process the received request in response to the received control signal during the wake-up period.

[0166] Furthermore, the programmable controller in this embodiment may also include the following structure: Fig.12 As shown in:

[0167] A third output structure 22, the third output structure is connected to the processor;

[0168] The switching component 17 may also include the following structure:

[0169] The third output port 23 is connected to the third output structure 22, and the first input port 18 is connected to the third output port 23 under the second instruction, and the second instruction is used to indicate not to delay the request.

[0170] Therefore, in this embodiment, the first input port 18, the first output port 20 and the third output port 23 are configured in the switching component to facilitate delay control and delay bypass. That is to say, in the case of a first instruction indicating a delay request, the first input port 18 is connected to the first output port 20, so that the request is transmitted to the delay control component 2, and the delay control component 2 implements the delay processing of the request through the monitoring of the wake-up cycle, and in the case of a second instruction indicating no delay request, the first input port 18 is not connected to the first output port 20, but to the third output port 23. At this time, the delay control component 2 will not receive the request, and the request is transmitted to the processor through the third output structure 22 connected to the third output port 23, and the processor directly processes the request without delaying the request. Therefore, the programmable controller in this embodiment can achieve flexible control of delay.

[0171] In one implementation, after the wake-up cycle arrives, the transmission component 1 may receive a new request for the processor, that is, the transmission component 1 receives a new request during the wake-up cycle. Based on this, when the transmission component 1 receives a new request for the processor, the delay control component 2 first determines whether the processing condition is met;

[0172] If the processing condition is met, the delay control component 2 controls the transmission component 1 to send the new request to the processor, so that the processor processes the new request within the wake-up cycle;

[0173] If the processing condition is not met, the delay control component 2 controls the transmission component 1 to send the new request to the processor in a subsequent wake-up cycle corresponding to the wake-up cycle, so that the processor processes the new request in the subsequent wake-up cycle corresponding to the wake-up cycle.

[0174] Wherein, when the wake-up cycle reaches: the first number reaches the target number, the processing condition includes: the number of beats required for processing the new request is less than or equal to the remaining number of beats of the wake-up cycle.

[0175] It should be noted that the number of beats required for processing a new request includes: the number of beats required for the processor to process the new request, and the number of beats required for the task execution component corresponding to the new request to execute the task corresponding to the new request.

[0176] When the wake-up cycle reaches: the first duration to the target duration, the processing condition includes: the duration required for processing the new request is less than or equal to the remaining duration of the wake-up cycle.

[0177] It should be noted that the time required for processing a new request includes: the time required for the processor to process the new request, and the time required for the task execution component corresponding to the new request to execute the task corresponding to the new request.

[0178] That is to say, in this embodiment, the delay control component 2 can control the transmission component 1 to allow the processor to process the new request in the current wake-up cycle for the new request received by the transmission component 1 in the wake-up cycle when the processing conditions are met, and the task execution component corresponding to the new request also executes the task corresponding to the new request in the current wake-up cycle; if the processing conditions are not met, that is, the current wake-up cycle cannot process the new request, the new request is delayed in processing, that is, the transmission component is controlled to allow the processor to process the new request in other subsequent wake-up cycles, so as to avoid the situation where the remaining duration of the current wake-up cycle cannot meet the processing of the new request and cause the request processing to fail.

[0179] refer to Fig.13 , is a schematic diagram of the structure of an electronic device provided in Embodiment 2 of the present application, and the electronic device may include the following structure:

[0180] Programmable controller 24, processor 25 and target component 26; target component 26 provides clock beats for programmable controller. Target component 26 can be Figure 5 The structure shown in was determined.

[0181] Wherein, the programmable controller 24 includes: a transmission component 1 and a delay control component 2;

[0182] The transmission component 1 is used to receive a request for the processor 25;

[0183] The delay control component 2 is used to monitor whether the wake-up cycle has arrived. When the wake-up cycle has arrived, the control transmission component 1 sends the request to the processor 25 so that the processor 25 processes the request within the wake-up cycle. The wake-up cycle has arrived, including: the first number has reached a preset target number; the first number is: the number of clock beats experienced by the processor 25 in the first state;

[0184] Among them, when the wake-up cycle has not arrived, the processor 25 is in the first state, and when the wake-up cycle arrives, the processor 25 is in the second state; the power consumption of the processor 25 in the first state is lower than the power consumption of the processor 25 in the second state.

[0185] It can be seen from the above technical scheme that in an electronic device provided by the second embodiment of the present application, a transmission component and a delay control component are set in the programmable controller, and a wake-up cycle based on the clock beat of the target component is configured, and the processor is in a first state when the wake-up cycle has not arrived, and in a second state when the wake-up cycle has arrived. The power consumption of the processor in the first state is lower than the power consumption of the processor in the second state. Based on this, in the programmable controller, a request for the processor is received through the transmission component, so that the delay control component monitors whether the wake-up cycle based on the clock beat has arrived. When the wake-up cycle arrives, the transmission component is controlled to send the request to the processor so that the processor processes the request within the wake-up cycle. It can be seen that in this embodiment, the wake-up cycle is configured for the processor. Only when the wake-up cycle arrives, the processor will enter a state with higher power consumption to process the request. When the wake-up cycle does not arrive, the processor is in a state with lower power consumption and does not process the request. Therefore, by concentrating the request in the wake-up cycle for processing, the processor is prevented from frequently switching between high power consumption and low power consumption, and the processor is also prevented from being in a state of higher power consumption continuously, thereby reducing the power consumption of the electronic device where the processor is located by reducing the duration of the processor in a state of higher power consumption.

[0186] Moreover, in this embodiment, the hardware implementation of the programmable controller can improve the efficient control of the processor.

[0187] In one implementation, the electronic device in this embodiment may also include the following structure: Fig.14 As shown in;

[0188] at least one task execution component 27; the programmable controller 24 further comprises: an activation component 11;

[0189] The delay control component 2 includes: an input structure 8, a first component 9 and a second component 10, such as Figure 7 As shown in; the activation component 11 includes a second output structure 12 and a plurality of second AND gates 13; Fig. 9 As shown in;

[0190] Wherein, the input structure 8 can be implemented with an OR gate, and is used to receive the request sent by the transmission component 1;

[0191] The first component 9 is connected to the input structure 8 and is used to obtain the delay parameter corresponding to the request;

[0192] The second component 10 is connected to the first component 9, and is used to obtain the number of delay cycles corresponding to the request based on the delay parameter; monitor whether the wake-up cycle has arrived, and when the wake-up cycle arrives and the wake-up cycle matches the number of delay cycles, control the transmission component 1 to send the request to the processor 25, so that the processor 25 processes the request within the wake-up cycle.

[0193] Among them, the first input port 14 of each second AND gate 13 is respectively connected to a signal source, each signal source corresponds to a task execution component 27, and the signal source provides an activation signal of the corresponding task execution component 27. The second input port 15 of each second AND gate 13 is an enable port, and the enable port is connected to the second component 10. The enable port is enabled when it receives the enable signal transmitted by the second component 10.

[0194] Moreover, the output port 16 of each second AND gate 13 is respectively connected to the second output structure 12, and the second output structure 12 is connected to the task execution component 27. The activation component 11 transmits the activation signal corresponding to the second AND gate 13 whose enable port is enabled to the corresponding task execution component 27 through the second output structure 12, so that the task execution component 27 executes the task corresponding to the request within the wake-up cycle.

[0195] refer to Fig.15 , is a flow chart of a control method provided in the third embodiment of the present application, which can be applied to Figure 1 In the programmable controller shown. The method in this embodiment may include the following steps:

[0196] Step 1501: Receive a request for a processor.

[0197] In this embodiment, the request for the processor can be received through the transmission component in the programmable controller.

[0198] Step 1502: monitor whether the wake-up cycle has arrived, and if the wake-up cycle has arrived, execute step 1503.

[0199] Step 1503: Send the request to the processor so that the processor processes the request within the wake-up cycle;

[0200] Wherein, when the wake-up cycle has not arrived, the processor is in a first state, and when the wake-up cycle arrives, the processor is in a second state; the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

[0201] Specifically, in this embodiment, the delay control component in the programmable controller can monitor whether the wake-up cycle has arrived. When the wake-up cycle has arrived, the request is sent to the processor by controlling the transmission component in the programmable control component so that the processor processes the request within the wake-up cycle.

[0202] Taking the electronic device as a computer as an example, the specific implementation of this application is illustrated by way of example:

[0203] First, the computer contains functional modules (i.e., the processor mentioned above) and common modules (shared modules, i.e., the task execution components mentioned above). Among them, functional modules are modules that execute system functions, such as the central processing unit (CPU) cores CPU Core1-2, the audio digital signal processor (DSP), etc., and the firmware hardware modules HW mod1 and HW mod2. Common modules only provide services for functional modules to enable them to perform their functions, such as external memory, bus and phase-locked loop, which are mainly the infrastructure resources of the system.

[0204] In this embodiment, the functional modules and the common modules are activated periodically to maximize the alignment of the execution time of the system interrupt activities to reduce power consumption.

[0205] like Fig.16 As shown in the figure, it is a schematic diagram of unaligned system activities of functional modules and common modules in the computer system. Specifically, different periodic system interrupt activities can have different trigger events and start times, which are not synchronized with each other, which has the following disadvantages:

[0206] 1. The activation cycle of the public module is long.

[0207] 2. Shorter inactive periods of common modules may have a negative impact on power consumption due to the power state entry / exit transitions of these modules.

[0208] 3. Multiple dedicated wake-ups for common modules and functional modules.

[0209] 4. It is difficult to predict the start of the next activity, so it is impossible to effectively decide to enter a deeper inactive power saving state, which may affect the latency requirement of the next activity due to the entry / exit latency of the corresponding inactive power saving state.

[0210] Based on this, the implementation scheme of the periodic activity controller is proposed in this embodiment. The basic idea is to define a system activation cycle (including a wake-up cycle and a non-wake-up cycle, and the non-wake-up cycle is the time period between two wake-up cycles), wherein, at the start time of the system periodic activity, the activities of the common modules can be aligned or not, but the activities of the common modules are concentrated in the activation cycle. The activation cycle of the system is started based on a periodic system trigger, that is, the programmable controller PAC mentioned above.

[0211] refer to Fig.17 As shown in , it is a schematic diagram of common module alignment activities (Aligned Activities Within Activation Cycle) within the system wake-up cycle of the computer. Fig.17 , shows system activity consistent with a periodic activation cycle, which helps reduce overall system power consumption by:

[0212] 1. Increase the inactive time of common modules and improve their utilization by serving multiple functional modules during the same active time (wake-up cycle).

[0213] 2. Reduce the number of dedicated wake-up times for common modules and functional modules by merging different activity execution times into a single wake-up cycle.

[0214] 3. Safely and efficiently enter the inactive power-saving state of common modules and functional modules to ensure that the remaining idle time of each activation cycle is as long as possible.

[0215] Thereby, the likelihood of activity being asynchronously initiated at a late point in time within an active cycle can be reduced, and the depth of the inactive power state can be determined based on the remaining time until the next active cycle.

[0216] Furthermore, in this embodiment, the "periodic activity controller" or PAC can perform activity alignment based on each hardware module in the chip, which can avoid misaligned activation of the CPU core within the activation cycle to improve resource utilization. By applying configurable delays to various requests, such as interrupts, task requests, etc., their corresponding processing is consistent with other activities. At the same time, in this embodiment, the activities of hardware modules with common module dependencies can be aligned to speed up the task execution rate. By triggering a periodic activation signal that is aligned with the start of the activation cycle, the corresponding hardware module is used to align activities that do not have delay critical timing requirements. In addition, the present embodiment has a configurable scale for aligning the start of the activation cycle, which means that the system needs to have a tick source with periodic wake-up capability such as a modem or WiFi, that is, the target component provides a clock beat.

[0217] like Fig.18As shown in FIG. 1 , it is a hardware architecture diagram of a device where a periodic activity controller PAC is located in one embodiment, specifically including:

[0218] 1. Power management controller PCU (Power control unit):

[0219] The PCU is a control unit that manages the power supply and system status of the overall system. It can adjust the PAC strategy from the overall perspective through software. For example, the PCU provides the PAC with the power status, and the PAC wakes up the PCU through the wake-up signal and feeds back the PAC information, namely PAC_ResReq, to ​​the PCU.

[0220] 2. PAC, which includes INT Delay, Activation and Tracking Activity:

[0221] PAC supports software to adjust the activities of certain hardware modules to specific time intervals (i.e. wake-up cycles) to prevent the CPU from being woken up too frequently, which would affect the processing of concentrated activities. In some way, the sleep time of key hardware modules is extended to increase power benefits.

[0222] 3. Tick:

[0223] In computers, the modem subsystem (2G, 3G, 4G, and 5G) can trigger Tick events periodically at regular intervals. For example, the LTE firmware can trigger a Tick every 1ms, or 3G can trigger a Tick every 2ms / 10ms, or 2G can trigger a Tick every 4.615ms.

[0224] The PAC can have a tick source based on a periodic timer whose period can be configured through registers. All ticks are combined together through a logical OR operation as the final tick used by the PAC state machine, and each tick can be enabled or disabled by a register. For example, Fig.19 In the structure shown in , each Tick source is connected to an input port of the corresponding AND gate, and the other input port of each AND gate is an enable port, namely Tick_En[1]-Tick_En

[20] . Based on this, the Tick source configuration information in the register is used to provide an enable signal to the enable port corresponding to one of the 20 Tick sources, thereby selecting a Tick source for the PAC. The selected Tick source (ie, PAC_Tick) provides Ticks for the PAC through the OR gate.

[0225] 4. INT Delay is the delay control component, including OR gate, TickBased Timer Update FSM (the first component) and Interrupt Delay FSM (TickBased) (the second component):

[0226] The distributed interrupt events (i.e., requests) to be processed are concentrated in a common CPU activity cycle, thereby avoiding random and frequent service interrupts by the CPU. To achieve this, each subsystem module can periodically receive a Tick as an indicator, based on which non-critical interrupts can be concentrated (delayed) to a specific CPU activity cycle for processing, where the activity cycle refers to the interval event between two Ticks.

[0227] For example, Fig. 20 As shown in, an OR gate for bypassing delay and multiple DelayUnits (i.e., transmission components) are configured in the PAC, and each DelayUnit is used to receive corresponding interrupts, such as IRQ32, IRQ33, IRQ***, etc. There are two input ports in the DelayUnit, which are used to receive interrupts and receive control signals of the Interrupt Delay FSM, respectively. There are also four output ports A, B, C, and D in the DelayUnit. Output port A is connected to the OR for bypassing delay, output port B is connected to the OR in the delay control component, output port C is connected to the MUX in the CPU subsystem (i.e., processor), and output port D is a spare port. Among them, the input port for receiving interrupts is connected to output port A or output port C to facilitate bypassing delay or realizing delay.

[0228] In addition, after the TickBased Timer Update FSM obtains the interrupt from the OR, it responds to the corresponding delay enable instruction Common_Delay_en_TickBased, obtains the delay parameter of the interrupt, namely Update_TickBased, and provides the delay parameter to the Interrupt Delay FSM (TickBased). The number of delay cycles (namely DelayTimer_TickBased) parsed by the Interrupt Delay FSM (TickBased) is provided to the TickBased Timer Update FSM. In addition, the Interrupt Delay FSM also monitors whether the wake-up cycle arrives and matches the number of delay cycles. If so, it sends a control signal IntDelayTimerExpire_TickBased to the input port of the DelayUnit to control the output port C to send the interrupt to the CPU subsystem.

[0229] It should be noted that for each interrupt, a delay can be enabled in the following cases:

[0230] (1) When the CPU enters a specific power state (such as deep sleep state);

[0231] (2) After a certain point in time, even if the CPU is still active.

[0232] The purpose here is to avoid race conditions, where the CPU might trigger a sleeping process, responding to this interrupt would prolong the CPU activity time, and this might not be a runtime critical event and could in principle be delayed to be handled in the next CPU activity cycle.

[0233] To be clear, if an interrupt is enabled for any time-based or interval-based delay, it must be the wakeup source because it needs to be serviced after the delay timer expires.

[0234] The tick-based interrupt delay refers to the interrupt delayed according to the Tick event.

[0235] Specifically, the platform software can completely bypass the PAC through the PCU register, so that the interrupt goes through the MUX and Wake uplogics to the interrupt controller GIC, which connects to the various cores core0-core3 in the CPU. For example, Fig. 20 As shown in , IRQ32, IRQ33, IRQ***, etc. are directly connected to the MUX (Raw IRQS[***]) in the CPU subsystem. This bypass (bypass_pac) logic must always be implemented in the non-power-down domain. Therefore, if PAC is not needed, the PAC domain can be turned off by software in this embodiment to reduce leakage.

[0236] 5. Activation is to activate the component:

[0237] PAC can provide periodic "activation signals" (activation) to other hardware modules (module1-2, i.e., task execution components). The "activation signal" will be triggered after a certain number of ticks, and the number of ticks is configurable for each corresponding hardware module. The hardware module should decide which activities should be delayed until the "activation signal" is received. The principle is that all external module access activities should be synchronized with the receipt of this "activation signal" as much as possible.

[0238] For example, Fig.21As shown in , the signal source signale1-3 of each hardware module is connected to an input port of each AND gate, and the other input port of each AND gate is the enable port En[0]-[2]. The output port of the AND gate is connected to the corresponding hardware module through the OR gate. Based on this, the signal source provides the activation signal of the hardware module to the input port to which it is connected. When the Interrupt Delay FSM detects the arrival of the wake-up cycle, it provides the enable signal to the AND gate connected to the hardware module corresponding to the interrupt, so that the corresponding enable port is enabled, so that the signal source connected to the AND gate where the enable port is located outputs the activation signal HW_Act_En to the corresponding hardware module through the OR gate, and the hardware module executes the task corresponding to the interrupt.

[0239] 6. Tracking Activity, namely PAC_Track_Module in PAC:

[0240] Record the status information of all modules. Fig. 22 As shown in , each hardware module is connected to one input port of each AND gate, and the other input port is the enable port. The output port of each AND gate is connected to the OR gate. Based on this, the status information Module 0status-Module xstatus (Activity status) of each hardware module whose enable port is enabled is output (OR_Act_Status) and stored through the OR gate OR.

[0241] Several typical scenarios of this embodiment are described below:

[0242] First, the "Periodic Activity Controller" can be configured to impose delays on interrupts based on their allowed processing delays, so that their processing is aligned with the next activation cycle or the next CPU core activity. This helps achieve the following goals:

[0243] 1. Reduce the number of operating system task context switches on the CPU core, because all "interrupt service routines" will be executed at the beginning of the active cycle, so the execution of operating system tasks within the active cycle of the CPU core will not be interrupted.

[0244] 2. Avoid small inactive times / gaps where entering an inactive state may be inefficient due to entry / exit transition power.

[0245] 3. Reduce the number of asynchronous dedicated wake-up times of the CPU core.

[0246] Scenario 1: Fig.23 As shown in , it is a schematic diagram of the comparison of scenes with interrupt alignment (Aligned) and without interrupt alignment (Unaligned).

[0247] Among them, the left figure shows the scenario without interrupt alignment. The CPU-ISR processes interrupts int1, int2 and int3 in turn. Each time an interrupt is processed, the corresponding module CPU-task executes the corresponding task, that is, after the CPU-ISR processes int1, CPU-Task1 executes task 1, after the CPU-ISR processes int2, CPU-Task2 (Highest Priority) executes task 2, and CPU-Task3 (least Priority) executes task 3. It can be seen that the CPU usage is in a dormant state for a relatively scattered period of time, and the CPU needs to be constantly woken up. For example, when request 3 arrives, the CPU that was originally in a dormant state is temporarily woken up again, resulting in high power consumption.

[0248] The figure on the right shows the scenario with interrupt alignment. The CPU-ISR processes interrupts int1, int2, and int3 in turn. After the interrupts are processed, the corresponding module CPU-task executes the corresponding task according to the priority of the interrupts. That is, the CPU-ISR waits for all interrupts to arrive, and then processes int1, 2, and 3. After that, CPU-Task2 (Highest Priority) executes Task 2, and CPU-Task1 executes Task 1. After the CPU-ISR processes int2, CPU-Task3 (least Priority) executes Task 3. It can be seen that the CPU Usage is more concentrated in the active and dormant states. If the requests and tasks are completed within the concentrated activation cycle, the dormant state time can be extended and the overall power consumption can be reduced.

[0249] It should be noted that each interrupt can be configured with a delay condition and a maximum delay value to control when interrupt processing starts.

[0250] Scenario 2: Delayed interruption based on system power state: An activation cycle includes an active time PowerState Active (the wake-up cycle mentioned above) and an inactive time Power State Inactive. The active time of an activation cycle is entered under the system trigger.

[0251] For example, Fig.24As shown in the figure, it is a schematic diagram of the scenario of receiving an interrupt in the inactive state. If interrupt Int A is valid during the inactive time of the activation cycle (for example, the CPU core is in the inactive state, that is, Power State Inactive) and this delay condition is enabled for interrupt A, then interrupt A can be delayed to the active time of the X+1th activation cycle Activation Cycle X+1 without activating the CPU in the xth activation cycle Activation Cycle X, thereby reducing power consumption.

[0252] Furthermore, if no activity is triggered in the next one or more activation cycles (for example, no CPU core activity is required), the interrupt can be configured to be delayed by N activation cycles ActivationCycle X+N according to the interrupt processing delay requirement, such as Fig.25 As shown in FIG. 1 , it is a schematic diagram of a scenario where the interrupt delay exceeds the activation cycle. The CPU is not activated in Activation Cycle X+1, but is activated in Activation Cycle X+N to process interrupt A, thereby reducing power consumption. Therefore, in this embodiment, as many activities as possible can be integrated in the same activation cycle, the sleep state time can be extended, and the overall power consumption can be reduced.

[0253] Scenario 3: Delayed interruption is triggered based on the time within the activation cycle:

[0254] If the interrupt is triggered at a later point in time within the active cycle, and the allowed delay value is greater than the active cycle, the interrupt can be configured to be delayed independently of the system power state, that is, processed during the next active cycle, such as Fig.26 As shown in the figure.

[0255] If an interrupt is triggered within the "interrupt allowed time" window of the current activation cycle (i.e. the remaining duration of the current activation cycle allows the interrupt to be processed) and no other delay conditions (if any) are met, it will not be delayed and will be processed immediately. Only if an interrupt is triggered after the "interrupt allowed time" window has passed and the "interrupt allowed time" is configured as a delay condition, i.e. the remaining time becomes insufficient to process the interrupt, the interrupt will be delayed to the next activation cycle, i.e. the interrupt is allowed to be delayed to the subsequent activation cycle.

[0256] Thus, for interrupts that can be delayed until the next activation cycle, unnecessary delays in processing in the current activation cycle can be avoided, and blocking of entering the inactive power saving state (i.e., the remaining time becomes insufficient because the interrupt processing makes it impossible to enter the inactive state) can be avoided. In addition, the possibility of merging the delayed interrupt with other interrupts at the start of the next activation cycle can be increased.

[0257] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0258] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0259] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0260] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A programmable controller comprising: transmission components and delay control components; Wherein, the transmission component is used to receive a request for a processor; The delay control component is used to monitor whether a wake-up cycle has arrived. When the wake-up cycle has arrived, the delay control component controls the transmission component to send the request to the processor so that the processor processes the request within the wake-up cycle. The arrival of the wake-up cycle includes: a first number reaching a preset target number; the first number is: the number of clock beats experienced by the processor in the first state; Wherein, when the wake-up cycle has not arrived, the processor is in a first state, and when the wake-up cycle arrives, the processor is in a second state; the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

2. The programmable controller according to claim 1, wherein the clock beat is the clock beat of the target component, and the target component is a component selected from a plurality of components having clock beats; in, The clock tick of the target component is selected by the following structure: a plurality of first AND gates and a first output structure; The first input port of each of the first AND gates is connected to a clock beat source, the clock beat source is derived from a component with a clock beat, the second input port of each of the first AND gates is an enable port, the enable port is enabled when an enable signal is received, and the component connected to the first AND gate with the enabled enable port is the target component; The output port of each of the first AND gates is connected to the first output structure, and the first output structure is connected to the delay control component, so that the first output structure provides the clock beat of the target component to the delay control component.

3. The programmable controller according to claim 1 or 2, wherein the delay control component comprises: An input structure, a first component, and a second component; Wherein, the input structure is used to receive the request sent by the transmission component; The first component is used to obtain a delay parameter corresponding to the request; The second component is used to obtain the number of delay cycles corresponding to the request based on the delay parameter; monitor whether the wake-up cycle has arrived, and when the wake-up cycle arrives and the wake-up cycle matches the number of delay cycles, control the transmission component to send the request to the processor so that the processor processes the request within the wake-up cycle.

4. The programmable controller according to claim 3 further comprising: Activate the component; Among them, the activation component is connected to the delay control component; the delay control component is also used to control the activation component to send an activation signal to the task execution component when the wake-up cycle arrives, so that the task execution component executes the task corresponding to the request within the wake-up cycle.

5. The programmable controller according to claim 4, wherein the activation component comprises: a second output structure and a plurality of second AND gates; Wherein, the first input port of each second AND gate is respectively connected to a signal source, each signal source corresponds to a task execution component, the signal source provides an activation signal of the corresponding task execution component, the second input port of each second AND gate is an enable port, and the enable port is connected to the second component, and the enable port is enabled when receiving the enable signal transmitted by the second component; The output port of each of the second AND gates is respectively connected to the second output structure, the second output structure is connected to the task execution component, and the activation component transmits the activation signal corresponding to the second AND gate whose enable port is enabled to the corresponding task execution component, so that the task execution component executes the task corresponding to the request within the wake-up cycle.

6. The programmable controller according to claim 4, wherein: In the case where there are multiple requests, the delay control component controls the transmission component to send the requests to the processor in a processing order so that the processor processes the requests in the processing order, and the processing order is related to the arrival order and / or request priority corresponding to the requests; and / or, in the case where there are multiple requests corresponding to the same task execution component, the delay control component enables the enable port corresponding to the task execution component so that the task execution component executes the task corresponding to each request according to the task sequence; the task sequence is at least related to the task priority corresponding to the request; And / or, in the case where there are multiple requests corresponding to different task execution components, the delay control component enables the enable port corresponding to each task execution component synchronously or in sequence according to the task order, so that each task execution component executes the task corresponding to the corresponding request according to the task order; the task order is at least related to the task priority corresponding to the request.

7. The programmable controller according to claim 1 or 2, wherein the transmission component comprises: at least one switching component, the switching component comprising at least a first input port, a second input port, a first output port, and a second output port; Wherein, the first input port is used to receive the request; the first input port is connected to the first output port under a first instruction, and the first output port is connected to the delay control component; the first instruction is used to instruct to delay the request; The second input port is connected to the delay control component, the second input port is connected to the second output port, and the second output port is connected to the processor.

8. The programmable controller according to claim 7, wherein the transmission component further comprises: a third output structure, the third output structure being connected to the processor; Wherein, the switching component further includes: a third output port; the third output port is connected to the third output structure; and the first input port is connected to the third output port under a second instruction; the second instruction is used to indicate not to delay the request.

9. The programmable controller according to claim 1 or 2, after the wake-up cycle is reached, when the transmission component receives a new request for the processor, the delay control component determines whether a processing condition is met; if the processing condition is met, the transmission component is controlled to send the new request to the processor, so that the processor processes the new request within the wake-up cycle; If the processing condition is not met, the delay control component controls the transmission component to send the new request to the processor in a subsequent wake-up cycle corresponding to the wake-up cycle, so that the processor processes the new request in the subsequent wake-up cycle corresponding to the wake-up cycle; in, The processing condition includes: the number of beats required for processing the new request is less than or equal to the number of remaining beats in the wake-up cycle.

10. An electronic device, comprising at least: Programmable controllers, processors and target components; The target component provides a clock beat for the programmable controller; Wherein, the programmable controller comprises: a transmission component and a delay control component; The transmission component is used to receive a request for the processor; The delay control component is used to monitor whether a wake-up cycle has arrived. When the wake-up cycle has arrived, the delay control component controls the transmission component to send the request to the processor so that the processor processes the request within the wake-up cycle. The arrival of the wake-up cycle includes: a first number reaching a preset target number; the first number is: the number of clock beats experienced by the processor in the first state; Wherein, when the wake-up cycle has not arrived, the processor is in the first state, and when the wake-up cycle arrives, the processor is in the second state; the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

11. The electronic device according to claim 10, further comprising: at least one task execution component; The programmable controller further comprises: an activation component; Wherein, the delay control component comprises: an input structure, a first component, and a second component; the activation component comprises: a second output structure and a plurality of second AND gates; Wherein, the input structure is used to receive the request sent by the transmission component; The first component is used to obtain a delay parameter corresponding to the request; The second component is used to obtain the number of delay cycles corresponding to the request according to the delay parameter; monitor whether the wake-up cycle has arrived, and when the wake-up cycle has arrived and the wake-up cycle matches the number of delay cycles, control the transmission component to send the request to the processor so that the processor processes the request within the wake-up cycle; Wherein, the first input port of each of the second AND gates is respectively connected to a signal source, each of the signal sources corresponds to one of the task execution components, the signal source provides an activation signal of the corresponding task execution component, the second input port of each of the second AND gates is an enable port, and the enable port is connected to the second component, and the enable port is enabled when receiving an enable signal transmitted by the second component; The output port of each of the second AND gates is respectively connected to the second output structure, the second output structure is connected to the task execution component, and the activation component transmits the activation signal corresponding to the second AND gate whose enable port is enabled to the corresponding task execution component, so that the task execution component executes the task corresponding to the request within the wake-up cycle.

12. A control method, applied to a programmable controller, comprising: receiving a request for a processor; monitoring whether a wake-up cycle has arrived, and sending the request to the processor when the wake-up cycle has arrived, so that the processor processes the request within the wake-up cycle; Wherein, when the wake-up cycle has not arrived, the processor is in a first state, and when the wake-up cycle arrives, the processor is in a second state; the power consumption of the processor in the first state is lower than the power consumption of the processor in the second state.

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