LDO circuit with low quiescent current

Abstract

The application discloses a low quiescent current LDO circuit, which mainly solves the problem of poor stability of the existing LDO circuit in the case of reducing the quiescent current. The circuit comprises a bias circuit, an error amplifier, a transconductance linear loop, a CLASS-AB output stage, a resistance feedback network and an output load which are connected in sequence; the error amplifier is further connected with the resistance feedback network. The LDO structure of the application adopts the CLASS-AB output stage, uses two adjusting tubes, and can make the LDO simultaneously realize the charging and discharging requirements. The LDO structure of the application adopts the transconductance linear loop to bias the CLASS-AB output stage, which can ensure that the quiescent current is reduced while the load response is fast. The output end of the error amplifier is set as the main pole in the LDO structure, a parallel negative feedback mechanism is ingeniously introduced at the output end, the LDO output impedance is reduced, the pole of the LDO output end is pushed to high frequency, and the LDO can drive the large capacitance and small resistance while ensuring the loop stability.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of integrated circuit, and particularly relates to a low static power consumption LDO circuit. BACKGROUND

[0002] High-precision ADC needs to use switches and capacitors. For example, Sigma-delta ADC is a kind of digital signal which can convert analog signal into time and amplitude discrete, and its structure mainly consists of sigma-delta modulator and digital filter. According to the working principle of Sigma-delta ADC, LDO needs to provide high and low levels and common mode level required by switch switching. The signal input circuit of Sigma-delta ADC is shown in Figure 1 , and the output voltage VOUT of LDO needs to provide common mode level VCM required by switch switching for capacitors. In order to meet the principle of charge conservation, the energy flow between capacitors requires the reference voltage VCM provided by LDO to charge and discharge.

[0003] However, as shown in Figure 2 , the output stage of the traditional LDO structure often adopts CLASS-A structure, and only uses a single adjusting tube, which cannot realize the charging and discharging requirements at the same time.

[0004] In addition, the main pole of the structure of the traditional LDO is located at the output end of the adjusting tube, and the position of the main pole will shift with the change of the load, which will cause the stability problem of LDO.

[0005] Low static power consumption means small static current, but the reduction of static current inevitably causes poor transient response of LDO, therefore, how to reduce the static current of LDO structure while having good output voltage control and fast load transient response is also of great significance. SUMMARY

[0006] The present application aims to provide a low static power consumption LDO circuit, and mainly solves the problems that the stability of the existing LDO circuit is poor in the case of reducing static current and cannot simultaneously have output and absorption current capacity.

[0007] In order to achieve the above-mentioned purpose, the technical scheme adopted by the present application is as follows:

[0008] A low static power consumption LDO circuit, comprising bias circuit, error amplifier, transconductance linear ring, CLASS-AB output stage, resistance feedback network and output end load connected in sequence; the error amplifier is also connected with the resistance feedback network;

[0009] The translinear loop is composed of a PMOS translinear loop and an NMOS translinear loop, a current source mirror MN7, a current source mirror MP14 and a resistor R3; the translinear loop receives an error signal amplified by an error amplifier, and an output signal of the translinear loop is used to drive a CLASS-AB output stage;

[0010] The PMOS translinear loop is composed of PMOS transistors MP11, MP12 and MP13; the gate and the drain of the PMOS transistor MP11 are connected, the gate and the drain of the PMOS transistor MP12 are connected, the gate of the PMOS transistor MP12 is connected with the gate of the PMOS transistor MP13, the source of the PMOS transistor MP13 is connected with the gate of the PMOS transistor MP16; the source of the PMOS transistor MP11 is connected with the error amplifier, the drain of the PMOS transistor MP12 is connected with the drain of the current source mirror MN7, the drain of the PMOS transistor MP13 is connected with the NMOS translinear loop; the source of the PMOS transistor MP13 is connected with one end of the resistor R3; the other end of the resistor R3 is connected with the source of the PMOS transistor MP11;

[0011] The NMOS translinear loop is composed of NMOS transistors MN8, MN10 and MN11; the gate and the drain of the NMOS transistor MN8 are connected, the source of the NMOS transistor MN8 is connected with a power ground GND, the drain of the NMOS transistor MN8 is connected with the source of the NMOS transistor MN10, the gate of the NMOS transistor MN10 is connected with the gate of the NMOS transistor MN11, the drain of the NMOS transistor MN11 is connected with the source of the PMOS transistor MP13, the gate of the NMOS transistor MN10 is connected with the drain of the NMOS transistor MN10 and the drain of the current source mirror MP14, the drain of the NMOS transistor MN9 is connected with the source of the NMOS transistor MN11, the gate of the current source mirror MP14 is connected with a bias circuit, and the source of the current source mirror MP14 is connected with a power VCC.

[0012] Further, in the application, the bias circuit comprises a low-voltage cascode current mirror structure composed of PMOS tubes MP1-MP6 and an NMOS tube MN1; wherein the gate of the PMOS tube MP1 is connected with the gate of the PMOS tube MP2, the source of the PMOS tube MP1 is connected with the drain of the PMOS tube MP2, the source of the PMOS tube MP2 is connected with the source of the PMOS tube MP3, the source of the PMOS tube MP3 is connected with the source of the PMOS tube MP4, the gate of the PMOS tube MP3 is connected with the gate of the PMOS tube MP4, the source of the PMOS tube MP3 is connected with the source of the PMOS tube MP4 and both are connected with the power supply VCC terminal, the gate of the PMOS tube MP3 is connected with the drain of the PMOS tube MP5, the gate of the PMOS tube MP1 is connected with the gate of the PMOS tube MP5, the gate of the PMOS tube MP6 is connected with the gate of the PMOS tube MP5, the drain of the PMOS tube MP4 is connected with the source of the PMOS tube MP6, the drain and the gate of the NMOS tube MN1 are connected; the drain of the PMOS tube MP6 is connected with the drain of the NMOS tube MN1, the gate and the drain of the PMOS tube MP1 are connected and used as a port IB_N1 for receiving external bias current, the drain of the PMOS tube MP5 is used as a port IB_N2 for receiving external bias current, the source of the NMOS tube MN1 is connected with the ground GND terminal, the source of the PMOS tube MP2 is connected with the VDD terminal; the gate of the PMOS tube MP4 and the gate of the NMOS tube MN1 are both connected with an error amplifier, a transconductance linear loop and a CLASS-AB output stage, and the source, the gate of the PMOS tube MP5 is connected with the error amplifier.

[0013] Further, in the application, the error amplifier is composed of NMOS tubes MN2-MN6, PMOS tubes MP7-MP10 and NMOS tube MN13; wherein, the gate of NMOS tube MN2 is connected with the gate of NMOS tube MN1, the source of NMOS tube MN3 is connected with the drain of NMOS tube MN2, the source of NMOS tube MN4 is connected with the drain of NMOS tube MN2, the source of NMOS tube MN5 is connected with the source of NMOS tube MN2, the source of NMOS tube MN6 is connected with the source of NMOS tube MN5, the gate of NMOS tube MN6 is connected with the gate of NMOS tube MN5, the gate of PMOS tube MP7 is connected with the gate of PMOS tube MP4, the gate of PMOS tube MP7 is connected with the gate of PMOS tube MP8, the source of PMOS tube MP10 is connected with the drain of PMOS tube MP8 and the drain of NMOS tube MN4, the gate of PMOS tube MP9 is connected with the gate of PMOS tube MP10, the drain of PMOS tube MP10 is connected with the drain of NMOS tube MN6; the drain of PMOS tube MP9 is connected with the drain of NMOS tube MN5, the source of PMOS tube MP9 is connected with the drain of PMOS tube MP7 and the drain of NMOS tube MN3; the gate of NMOS tube MN3 is connected with reference voltage VREF, the source of PMOS tube MP7 and the source of PMOS tube MP8 are connected with the source of PMOS tube MP4, the gate of NMOS tube MN5 is connected with the drain of NMOS tube MN5; the gate of NMOS tube MN13 is connected with the drain of PMOS tube MP10 and the CLASS-AB output stage, the drain of PMOS tube MP16 is connected with the CLASS-AB output stage, the drain of NMOS tube MN9 is connected with the CLASS-AB output stage, the gate of NMOS tube MN2 is connected with the gate of NMOS tube M7, the source of PMOS tube MP7 and the source of PMOS tube MP8 are connected with the source of PMOS tube MP4 and PMOS tube MP11; the gate of NMOS tube MN4 is connected with the resistance feedback network.

[0014] Further, in the application, the CLASS-AB output stage comprises PMOS tubes MP15, MP16 and NMOS tubes MN9, MN12; the gate of the PMOS tube MP15 is connected with the drain of the PMOS tube MP10, the source of the PMOS tube MP15 is connected with the source of the PMOS tube MP16, and the drain of the PMOS tube MP15 is connected with the drain of the NMOS tube MN9; the gate of the NMOS tube MN12 is connected with the drain of the NMOS tube MN9, the drain of the NMOS tube MN12 is connected with the drain of the PMOS tube MP16, and the source of the NMOS tube MN12 is connected with the source of the NMOS tube MN9; the PMOS tube MP16 is used as a PMOS output adjusting tube of the CLASS-AB, and the source thereof is connected with the power supply VCC terminal; the NMOS tube MN12 is used as an NMOS output adjusting tube of the CLASS-AB, and the source thereof is connected with the power supply GND terminal; the drain of the PMOS tube MP16 is connected with the drain of the NMOS tube MP12 and used as the VOUT terminal; the drain of the NMOS tube MN12 is connected with the resistance feedback network, and the source of the NMOS tube MN12 is connected with the resistance feedback network.

[0015] Further, in the application, the resistance feedback network is composed of voltage dividing resistors R1, R2; one end of the voltage dividing resistor R1 is connected with the source of the PMOS tube MP15, the other end of the voltage dividing resistor R1 is connected with one end of the voltage dividing resistor R2, the other end of the voltage dividing resistor R2 is connected with the source of the NMOS tube MN12, and the common end of the voltage dividing resistors R1, R2 is also connected with the gate of the NMOS tube MN4.

[0016] Further, in the application, the output terminal load comprises a load resistor RL and a load capacitor CL connected in parallel; the two ends of the load resistor RL are connected with the source of the NMOS tube MN12 and the source of the PMOS tube MP15 respectively.

[0017] Compared with the prior art, the application has the following beneficial effects:

[0018] The LDO structure of the application adopts the CLASS-AB output stage, uses two adjusting tubes, and can make the LDO realize the charging and discharging requirements at the same time. The LDO structure of the application adopts the transconductance linear loop biasing CLASS-AB output stage, can guarantee the reduction of the static current while the load response is fast. The LDO structure of the application sets the output terminal of the error amplifier as the main pole, ingeniously introduces the parallel negative feedback mechanism at the output terminal, reduces the LDO output impedance, pushes the pole of the LDO output terminal to high frequency, and can make the LDO drive the large capacitor and small resistor while guaranteeing the loop stability. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1This is the signal input circuit structure of the Sigma-delta ADC in the prior art.

[0020] Figure 2 It is a traditional LDO architecture.

[0021] Figure 3 Schematic diagram of the LDO circuit structure of the present invention.

[0022] Figure 4 This is a diagram of the LDO architecture of the present invention.

[0023] Figure 5 This is an input-output characteristic curve diagram of the LDO structure of the present invention.

[0024] Figure 6 1 is a curve diagram comparing the linear adjustment capabilities of a traditional LDO structure and the LDO structure of the present invention.

[0025] Figure 7 The figure is a comparison curve of the power supply rejection ratio between the traditional LDO structure and the LDO structure of the present invention.

[0026] Figure 8 The figure is a temperature characteristic comparison curve diagram of a traditional LDO structure and the LDO structure of the present invention.

[0027] Figure 9 Graphs showing the loop amplitude-frequency characteristics and phase-frequency characteristics of the LDO of the present invention.

[0028] Figure 10 FIG. 4 is a load transient response curve diagram of the LDO structure of the present invention.

[0029] Figure 11 The figure is a comparison diagram of the load transient response curve of the traditional LDO structure and the load transient response curve of the LDO structure of the present invention. DETAILED DESCRIPTION

[0030] The present invention will be further described below with reference to the accompanying drawings and examples. The embodiments of the present invention include but are not limited to the following examples.

[0031] Example

[0032] like Figure 3 、 4 As shown, the present invention discloses a low static power consumption LDO circuit, which includes a bias circuit, an error amplifier, a translinear loop, a CLASS-AB output stage, a resistor feedback network and an output load connected in sequence; the error amplifier is also connected to the resistor feedback network.

[0033] The bias circuit adopts a low-voltage common-source common-gate current mirror structure to provide accurate currents for error amplifiers, transconductance linear rings and other circuits. The low-voltage common-source common-gate structure has greater output impedance, stable output current and greater output voltage swing. In the embodiment, the bias circuit includes a low-voltage common-source common-gate current mirror structure composed of PMOS tubes MP1-MP6 and an NMOS tube MN1; wherein the gate of the PMOS tube MP1 is connected with the gate of the PMOS tube MP2, the source of the PMOS tube MP1 is connected with the drain of the PMOS tube MP2, the source of the PMOS tube MP2 is connected with the source of the PMOS tube MP3, the source of the PMOS tube MP3 is connected with the source of the PMOS tube MP4, the gate of the PMOS tube MP3 is connected with the gate of the PMOS tube MP4, the source of the PMOS tube MP3 is connected with the source of the PMOS tube MP4 and both are connected with the power supply VCC terminal, the gate of the PMOS tube MP3 is connected with the drain of the PMOS tube MP5, the gate of the PMOS tube MP1 is connected with the gate of the PMOS tube MP5, the gate of the PMOS tube MP6 is connected with the gate of the PMOS tube MP5, the drain of the PMOS tube MP4 is connected with the source of the PMOS tube MP6, and the drain and the gate of the NMOS tube MN1 are connected; the drain of the PMOS tube MP6 is connected with the drain of the NMOS tube MN1, the gate and the drain of the PMOS tube MP1 are connected and serve as a port IB_N1 for receiving externally provided bias current, the drain of the PMOS tube MP5 serves as a port IB_N2 for receiving externally provided bias current, the source of the NMOS tube MN1 is connected with a ground GND terminal, and the source of the PMOS tube MP2 is connected with a VDD terminal; the gate of the PMOS tube MP4 and the gate of the NMOS tube MN1 are both connected with error amplifiers, transconductance linear rings and CLASS-AB output stages, and the source of the PMOS tube MP5 is connected with the error amplifiers. The port IB_N1 receives externally provided bias current, the current flows through MP1 and MP2 to provide bias voltage for the gates of MP5 and MP6, so as to ensure that MP5 and MP6 work in the saturation region.

[0034] The error amplifier mainly functions to compare the voltage and the reference voltage as the input end of the loop feedback of the resistance feedback network, and amplify the error of the two, and output to the transconductance linear ring. The error amplifier adopts the folded common source common gate structure, has large output swing, and only one stage of operational amplifier is needed to obtain high low frequency gain; and has high output impedance, and can improve the power supply rejection capability of the circuit. In the embodiment, the error amplifier is composed of NMOS tubes MN2-MN6, PMOS tubes MP7-MP10 and NMOS tube MN13; wherein, the gate of the NMOS tube MN2 is connected with the gate of the NMOS tube MN1, the source of the NMOS tube MN3 is connected with the drain of the NMOS tube MN2, the source of the NMOS tube MN4 is connected with the drain of the NMOS tube MN2, the source of the NMOS tube MN5 is connected with the source of the NMOS tube MN2, the source of the NMOS tube MN6 is connected with the source of the NMOS tube MN5, the gate of the NMOS tube MN6 is connected with the gate of the NMOS tube MN5, the gate of the PMOS tube MP7 is connected with the gate of the PMOS tube MP4, the gate of the PMOS tube MP7 is connected with the gate of the PMOS tube MP8, the source of the PMOS tube MP10 is connected with the drain of the PMOS tube MP8 and the drain of the NMOS tube MN4, the gate of the PMOS tube MP9 is connected with the gate of the PMOS tube MP10, the drain of the PMOS tube MP10 is connected with the drain of the NMOS tube MN6; the drain of the PMOS tube MP9 is connected with the drain of the NMOS tube MN5, the source of the PMOS tube MP9 is connected with the drain of the PMOS tube MP7 and the drain of the NMOS tube MN3; the gate of the NMOS tube MN3 is connected with the reference voltage VREF, the source of the PMOS tube MP7 and the source of the PMOS tube MP8 are connected with the source of the PMOS tube MP4, the gate of the NMOS tube MN5 is connected with the drain of the NMOS tube MN5; the gate of the NMOS tube MN13 is connected with the drain of the PMOS tube MP10 and the CLASS-AB output stage, the drain of the PMOS tube MP16 is connected with the CLASS-AB output stage, the drain of the NMOS tube MN9 is connected with the CLASS-AB output stage, the gate of the NMOS tube MN2 is connected with the gate of the NMOS tube M7, the source of the PMOS tube MP7 and the source of the PMOS tube MP8 are connected with the source of the PMOS tube MP4 and the source of the PMOS tube MP11; the gate of the NMOS tube MN4 is connected with the resistance feedback network. Among them, MN2 as a mirror tube "copies" the current of the branch where MN1 is located in proportion, which is equivalent to the tail current source of the folding stage of the error amplifier. MN3 and MN4 are differential input pair tubes, the gate of MN3 is the reverse input end of the error amplifier, and is connected with the external reference voltage; the gate of MN4 is the same direction input end of the error amplifier, and is connected with the resistance feedback network. MP7-MP10 constitute a common source common gate current mirror, and the gate bias voltage thereof is provided by a low voltage common source common gate current mirror bias circuit.MN5 and MN6 constitute a current mirror structure as an active load of the error amplifier. The source end of MP10 is connected with the drain end of MN6 as an output end of the error amplifier.

[0035] The gate end of MN13 is connected with the output end of the error amplifier, and the source end, the drain end and the substrate of MN13 are grounded, which is equivalent to a MOS capacitor. MN13 functions to introduce a large capacitor at the output node of the error amplifier, so as to push the pole at this place to low frequency as a main pole, thereby improving the loop stability of the LDO.

[0036] The transconductance linear loop is composed of a PMOS transconductance linear loop, an NMOS transconductance linear loop, a current source mirror tube MN7, a current source mirror tube MP14 and a resistor R3. The transconductance linear loop receives the error signal amplified by the error amplifier, and the output signal thereof is used to drive the CLASS-AB output stage. The transconductance linear loop receives the error signal amplified by the error amplifier, and the output signal thereof is used to drive the output power tubes PMOS and NMOS of the CLASS-AB structure of the output stage. The transconductance linear loop can not only set the static current of the LDO output stage to realize very low static power consumption, but also can improve the output slew rate of the LDO output stage, and provide a large charging current for the gate capacitor of the output power tube during transient switching of the output power tube, thereby improving the transient response speed of the LDO to the load. In the embodiment, the PMOS transconductance linear loop is composed of PMOS tubes MP11, MP12 and MP13, and shares the PMOS tube MP16 in the CLASS-AB output stage. The gate and the drain of the PMOS tube MP11 are connected, the gate and the drain of the PMOS tube MP12 are connected, the gate of the PMOS tube MP12 is connected with the gate of the PMOS tube MP13, and the source of the PMOS tube MP13 is connected with the gate of the PMOS tube MP16. The source of the PMOS tube MP11 is connected with the error amplifier, the drain of the PMOS tube MP12 is connected with the drain of the current source mirror tube MN7, and the drain of the PMOS tube MP13 is connected with the NMOS transconductance linear loop. The source of the PMOS tube MP13 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the source of the PMOS tube MP11.

[0037] The NMOS transconductance linear loop is composed of NMOS tubes MN8, MN10 and MN11, and shares NMOS tube MN9 in the CLASS-AB output stage; wherein the gate of NMOS tube MN8 is connected with the drain, the source of NMOS tube MN8 is connected with the power ground terminal GND, the drain of NMOS tube MN8 is connected with the source of NMOS tube MN10, the gate of NMOS tube MN10 is connected with the gate of NMOS tube MN11, the drain of NMOS tube MN11 is connected with the source of PMOS tube MP13, the gate of NMOS tube MN10 is connected with the drain after which the drain of NMOS tube MN10 is connected with the drain of current source mirror tube MP14, the drain of NMOS tube MN9 is connected with the source of NMOS tube MN11, the gate of current source mirror tube MP14 is connected with the bias circuit, and the source of current source mirror tube MP14 is connected with the power supply VCC terminal.

[0038] The CLASS-AB output stage has the advantages of small static power consumption, small distortion and high efficiency. In the embodiment, the CLASS-AB output stage includes PMOS tubes MP15 and MP16 and NMOS tubes MN9 and MN12; wherein the gate of PMOS tube MP15 is connected with the drain of PMOS tube MP10, the source of PMOS tube MP15 is connected with the source of PMOS tube MP16, and the drain of PMOS tube MP15 is connected with the drain of NMOS tube MN9; the gate of NMOS tube MN12 is connected with the drain of NMOS tube MN9, the drain of NMOS tube MN12 is connected with the drain of PMOS tube MP16, and the source of NMOS tube MN12 is connected with the source of NMOS tube MN9; PMOS tube MP16 is the PMOS output adjusting tube of the CLASS-AB, and its source is connected with the power supply VCC terminal; NMOS tube MN12 is the NMOS output adjusting tube of the CLASS-AB, and its source is connected with the power ground terminal GND; the drain of PMOS tube MP16 is connected with the drain of NMOS tube MP12 and serves as the VOUT terminal; the drain of NMOS tube MN12 is connected with the resistance feedback network, and the source of NMOS tube MN12 is connected with the resistance feedback network. The working state of the CLASS-AB output stage is between CLASS-A and CLASS-B, so that the two power tubes work in the push-pull mode, which makes up for the shortcomings of large static power consumption of the CLASS-A output stage and distortion of the CLASS-B output stage. In order to realize different load conditions, the PMOS power tube is turned on when the current needs to be outputted outward, and the NMOS power tube is turned on when the current needs to be absorbed inward.

[0039] The resistance feedback network is composed of two sampling resistors in voltage division. The voltage change at the output of the LDO is fed back to the input of the error amplifier in time, compared with the reference voltage, amplified by the transconductance linear loop, and output to the gate of the power transistor, so as to adjust the working state of the power transistor, change the output current of the power transistor, and finally keep the output voltage of the LDO stable. In this embodiment, the resistance feedback network is composed of voltage dividing resistors R1 and R2. One end of the voltage dividing resistor R1 is connected to the source of the PMOS transistor MP15, the other end of the voltage dividing resistor R1 is connected to one end of the voltage dividing resistor R2, the other end of the voltage dividing resistor R2 is connected to the source of the NMOS transistor MN12, and the common end of the voltage dividing resistors R1 and R2 is also connected to the gate of the NMOS transistor MN4.

[0040] The output load is composed of a load resistor and a load capacitor, which is used to simulate different load conditions, including no load, light load and heavy load. The load capacitor is equivalent to the built-in capacitor of the LDO, which can filter and stabilize the output voltage of the LDO, so there is no need for external capacitor for the LDO. The output load includes a load resistor RL and a load capacitor CL connected in parallel; wherein the two ends of the load resistor RL are respectively connected to the source of the NMOS transistor MN12 and the source of the PMOS transistor MP15.

[0041] In this embodiment, the output end of the error amplifier is connected to the gate of MP15, and MP15 converts the output voltage signal of the error amplifier into a current signal as the input of the transconductance linear loop.

[0042] For the PMOS transconductance linear loop:

[0043] The PMOS transistors MP11, MP12, MP13 and MP16 constitute a transconductance linear loop, and their gate-source voltages have the following relationship:

[0044] V GS，MP11 +V GS，MP12 =V GS，MP13 +V GS，MP16

[0045] Without considering the secondary effects such as channel length modulation effect and body effect, if the current ratio of MP12 and MP13 is equal to the width-length ratio of MP12 and MP13, i.e.:

[0046]

[0047] According to the current formula of the PMOS transistor working in the saturation region:

[0048]

[0049] We can get:

[0050] V GS，MP12 =VGS，MP13

[0051] Then:

[0052] V GS，MP16 = V GS，MP11

[0053] That is, the gate-source voltage of the output transistor MP16 is equal to that of MP11. If the width-length ratio of MP16 is M times that of MP11, then the current flowing through MP16 is also M times that of MP11.

[0054] The current source mirror transistor MN7 of MP11 is copied, and if it is denoted as IB7, then the static current of the output NMOS transistor MN12 is M*IB7.

[0055] For the NMOS translinear loop:

[0056] The NMOS transistors MN8, MN10, MN11 and MN12 constitute a translinear loop, and their gate-source voltages have the following relationship:

[0057] V GS，MN8 + V GS，MN10 = V GS，MN11 + V GS，MN12

[0058] Without considering the second-order effects such as channel length modulation and bulk effect, if the current ratio of MN10 and MN11 is equal to the ratio of their width-length ratios, that is:

[0059]

[0060] From the current formula of the NMOS transistor working in the saturation region:

[0061]

[0062] It can be obtained that:

[0063] V GS，MN10 = V GS，MN11

[0064] Then:

[0065] V GS，MN8 = V GS，MN12

[0066] That is, the gate-source voltage of the output transistor MN12 is equal to that of MN8. If the width-length ratio of MN12 is M times that of MN8, then the current flowing through MN12 is also M times that of MN8.

[0067] The current source mirror tube MP14 of MN8 is "copied" and is recorded as IB14. Then the static circuit of the output stage NMOS tube MN12 is M*IB14.

[0068] In summary, the translinear loop structure determines the quiescent current of the output stage and can achieve low quiescent power consumption.

[0069] like Figure 3 As shown in the figure, when the LDO needs to output a current, the output voltage decreases. This voltage is fed back to the input of the error amplifier through the feedback network R1 and R2, and then output to the subsequent translinear loop, causing the voltage at point B to decrease. This turns off the power transistor MN12, reducing the current drawn by the power transistor MN12. At the same time, the voltage at point A decreases, turning off the PMOS transistor MP13.

[0070] like Figure 3 As shown in the figure, when the LDO needs to extract a current, the output voltage increases. This voltage is fed back to the input of the error amplifier through the feedback network R1 and R2, and then output to the subsequent translinear loop. This causes the voltage at point A to rise, turning off power transistor MP16 and reducing its output current. At the same time, the voltage at point B rises, turning off NMOS transistor MN11.

[0071] Therefore, the LDO structure of the present invention can meet the requirements of charging and discharging.

[0072] Analysis of the stability and fast transient response of the entire LDO:

[0073] The LDO structure of the present invention has two loops, namely a current loop and a voltage loop. Figure 3 The blue line shows that when the load resistance R L When the resistance value decreases instantaneously, the output voltage VOUT of the LDO will be pulled down, so that the feedback voltage generated by the resistors R1 and R2 on the VOUT voltage divider will be reduced. After the error amplifier is adjusted, the output voltage of the error amplifier will increase, that is, the gate voltage of MP15 will increase, which will reduce the voltage at point B and turn off the power tube MN12. At the same time, the voltage at point A will decrease, which will increase the degree of opening of the power tube MP16, further increasing the load capacity of the LDO and making the output voltage VOUT of the LDO stable. When the load resistor R L When the resistance value increases momentarily, the LDO's output voltage, VOUT, increases, causing the feedback voltage generated by the VOUT voltage divider generated by resistors R1 and R2 to increase. After adjustment by the error amplifier, the error amplifier's output voltage decreases, which in turn reduces the gate voltage of MP15. This reduces the voltage at point A, turning off power transistor MP16. Simultaneously, the voltage at point B increases, increasing the turn-on level of power transistor MN12, further reducing the LDO's load capacity and stabilizing the LDO's output voltage, VOUT.

[0074] Voltage loop such asFigure 3 The middle red line represents that when the load resistance R L When the resistance instantaneously decreases, the output voltage VOUT of the LDO is pulled down, so that the feedback voltage generated by the voltage division of resistors R1 and R2 on VOUT is reduced, and after adjustment by the error amplifier, the output voltage of the error amplifier is increased, that is, the gate voltage of MP15 is increased, so the source voltage of MP15 is also increased, which can quickly offset the decrease of VOUT caused by the load change, so that the output voltage VOUT of the LDO is quickly stabilized. When the load resistance R L When the resistance instantaneously increases, the output voltage VOUT of the LDO is pulled up, so that the feedback voltage generated by the voltage division of resistors R1 and R2 on VOUT is increased, and after adjustment by the error amplifier, the output voltage of the error amplifier is reduced, that is, the gate voltage of MP15 is reduced, so the source voltage of MP15 is also reduced, which can quickly offset the increase of VOUT caused by the load change, so that the output voltage VOUT of the LDO is quickly stabilized.

[0075] Therefore, the existence of the two loops greatly improves the stability and fast transient response capability of the LDO structure of the application.

[0076] The structure loop of the LDO mainly has three poles P1, P2 and P3, which are located as shown in the figure. Figure 3

[0077]

[0078]

[0079]

[0080] R eq,1 is the total output resistance of the error amplifier, C eq,1 is the total equivalent capacitance of the gate node of MP15, including the equivalent capacitance of MN13 and other parasitic capacitances of the node. R eq,2 is the total equivalent resistance of the gate node of power tube MP16, C eq,2 is the total equivalent capacitance of the gate node of power tube MP16. R eq,3 is the total equivalent resistance of the output node VOUT, C eq,3 is the total equivalent capacitance of the output node VOUT.

[0081] MN13 is introduced at the output node of the error amplifier, and the size of MN13 is large, that is, it is equivalent to a large capacitor, so that C eq,1 is large, thereby pushing the frequency of P1 to low frequency. By reasonably setting the size of MN13, P1 can be the main pole in the full load range.

[0082] ​Since the resistance of R3 is much smaller than the impedance r of the MOS current source o , then the resistance of the equivalent resistor Req,2 is approximately equal to R3, that is

[0083] R eq，2 ≈R3

[0084] Reasonable setting of the resistance value of R3 can push P2 to high frequency and ensure that the main pole is P1.

[0085] The structures MP15, MP16, MN9, and MN12 of the LDO of the present invention are equivalent to a parallel negative feedback structure. The additional parallel negative feedback mechanism can make the output impedance R out Further reduce.

[0086]

[0087] R eq，3 =R out / / R L / / R FB

[0088] R out The reduction of R eq,3 Reduced, so that the secondary point frequency position of the output node can be pushed to a higher frequency, ensuring that the main pole is P1.

[0089] Compared with the main pole position of the traditional LDO structure, the change of the main pole of the LDO structure of the present invention can reduce the impact of the load on the stability of the entire circuit. Therefore, the LDO structure of the present invention has good stability.

[0090] The following describes in detail the simulation results of the technical solution of the present invention in conjunction with the accompanying drawings.

[0091] based on Figure 3 The simulation results of the example show that:

[0092] The input and output characteristics of the LDO structure of the present invention are as follows: Figure 5 As shown in the figure, when the VDD voltage is 4.2V, the VOUT output voltage is 4.1871V, and when the VDD voltage is 6V, the VOUT output voltage is 4.18727V.

[0093] The simulation results of the traditional LDO structure example show that:

[0094] Comparison of the linear adjustment capabilities of the traditional LDO structure and the LDO structure of the present invention Figure 6 The linear adjustment curve of the traditional LDO structure is shown as a dotted line, and the linear adjustment curve of the LDO structure of the present invention is shown as a solid line.

[0095] The linear regulation rate of the traditional LDO structure is:

[0096]

[0097] The linear regulation rate of the LDO structure of the present invention is:

[0098]

[0099] The smaller the linear regulation rate, the smaller the impact of input voltage changes on the output voltage. Therefore, the linear regulation performance of the LDO structure of the present invention is greatly improved.

[0100] The power supply rejection ratio comparison between the traditional LDO structure and the LDO structure of the present invention is as follows: Figure 7 The power supply rejection ratio of the conventional LDO structure is shown by the dotted line, and the power supply rejection ratio of the LDO structure of the present invention is shown by the solid line.

[0101] At a low frequency of about 10 Hz, the power supply rejection ratio of the conventional LDO structure is about -56.2546 dB, while the power supply rejection ratio of the LDO structure of the present invention is about -92.1917 dB. Therefore, the power supply rejection capability of the LDO structure of the present invention is greatly improved.

[0102] The temperature characteristics of the traditional LDO structure and the LDO structure of the present invention are compared. Figure 8 The temperature characteristic curve of the traditional LDO structure is shown as a dotted line, and the temperature characteristic curve of the LDO structure of the present invention is shown as a solid line.

[0103] When the temperature changes from -40°C to 125°C, the output voltage of a conventional LDO structure changes from 4.188152V to 4.196709V, with a temperature variation of 8.557mV. The output voltage of the LDO structure of the present invention changes from 4.187138V to 4.187155V, with a temperature variation of only 17.2μV. Therefore, the LDO structure of the present invention has better temperature characteristics and a lower temperature coefficient.

[0104] The loop amplitude-frequency characteristics and phase-frequency characteristics of the LDO of the present invention are as follows: Figure 9 The dotted line represents the change of loop gain with frequency in the form of dB20, and the solid line represents the change of loop phase with frequency.

[0105] Depend on Figure 9 It can be obtained that the low-frequency gain of the LDO of the present invention is about 75.7046 dB, and the phase margin is about 87.28°.

[0106] Therefore, the LDO structure of the present invention has better loop stability and good amplitude-frequency and phase-frequency characteristics.

[0107] The load transient response curve of the structure of the LDO of the present application is shown in Figure 10 The dashed line is the curve of the load current changing from -30mA to 30mA at 30mA / μs, and the solid line is the transient response curve of the output voltage with the change of the load current. When the load current changes from -30mA to 0A, the output voltage deviation of the structure of the LDO of the present application is only 24.50903mV, and the setting time is about 2μs; when the load current changes from 0A to 30mA, the output voltage deviation of the structure of the LDO of the present application is only 20.719228mV, and the setting time is about 1.8μs.

[0108] The load transient response curve of the structure of the LDO of the present application is shown in Figure 11 The dashed line I_Load represents the load current changing from 100μA to 100mA at 100mA / μs, the dashed line Traditional_LDO_VOUT represents the load transient response curve of the traditional LDO structure, and the solid line LDO_VOUT represents the load transient response curve of the structure of the LDO of the present application.

[0109] When the load current changes from 100μA to 100mA within 1μs, the output voltage deviation of the traditional LDO structure is about 781.263mV, and the setting time is about 2.5μs; the output voltage deviation of the structure of the LDO of the present application is only 88.7536mV, and the setting time is about 2.1μs.

[0110] When the load current changes from 100mA to 100μA within 1μs, the output voltage deviation of the traditional LDO structure is about 810.057mV, and the setting time is about 3μs; the output voltage deviation of the structure of the LDO of the present application is only 102.677mV, and the setting time is about 2μs.

[0111] Therefore, the structure of the LDO of the present application has better load transient response.

[0112] The above embodiment is only one of the preferred embodiments of the present application, and should not be used to limit the protection scope of the present application, but any modification or polishing without substantial meaning made in the main design idea and spirit of the present application, and the technical problems solved are still consistent with the present application, which should be included in the protection scope of the present application.

Claims

1. A low static power consumption LDO circuit, characterized in that: The circuit includes a bias circuit, an error amplifier, a translinear loop, a CLASS-AB output stage, a resistor feedback network, and an output load connected in sequence; the error amplifier is also connected to the resistor feedback network; The translinear loop is composed of a PMOS translinear loop, an NMOS translinear loop, a current source mirror tube MN7, a current source mirror tube MP14 and a resistor R3; the translinear loop receives the error signal amplified by the error amplifier, and its output signal is used to drive the CLASS-AB output stage; The PMOS translinear loop is composed of PMOS transistors MP11, MP12, and MP13; wherein the gate and drain of the PMOS transistor MP11 are connected, the gate and drain of the PMOS transistor MP12 are connected, the gate of the PMOS transistor MP12 is connected to the gate of the PMOS transistor MP13, and the source of the PMOS transistor MP13 is connected to the gate of the PMOS transistor MP16; the source of the PMOS transistor MP11 is connected to the power supply VDD, the drain of the PMOS transistor MP12 is connected to the drain of the current source mirror transistor MN7, and the drain of the PMOS transistor MP13 is connected to the NMOS translinear loop; the source of the PMOS transistor MP13 is connected to one end of the resistor R3; the other end of the resistor R3 is connected to the source of the PMOS transistor MP11; the gate of the current source mirror transistor MN7 is connected to the error amplifier, and the source of the current source mirror transistor MN7 is connected to the GND port; The NMOS translinear loop is composed of NMOS transistors MN8, MN10, and MN11; wherein the gate and drain of NMOS transistor MN8 are connected, the source of NMOS transistor MN8 is connected to the GND port, the drain of NMOS transistor MN8 is connected to the source of NMOS transistor MN10, the gate of NMOS transistor MN10 is connected to the gate of NMOS transistor MN11, the drain of NMOS transistor MN11 is connected to the source of PMOS transistor MP13, the gate and drain of NMOS transistor MN10 are connected and then connected to the drain of current source mirror transistor MP14, the drain of PMOS transistor MP13 is connected to the source of NMOS transistor MN11, the gate of current source mirror transistor MP14 is connected to the bias circuit, and the source of current source mirror transistor MP14 is connected to the power supply VDD terminal; the source of NMOS transistor MN11 is also connected to the CLASS-AB output stage; The CLASS-AB output stage includes PMOS transistors MP15 and MP16 and NMOS transistors MN9 and MN12; wherein the gate of the PMOS transistor MP15 is connected to the output end of the error amplifier, the source of the PMOS transistor MP15 is connected to the drain of the PMOS transistor MP16, and the drain of the PMOS transistor MP15 is connected to the drain of the NMOS transistor MN9; the gate of the NMOS transistor MN12 is connected to the drain of the NMOS transistor MN9, the drain of the NMOS transistor MN12 is connected to the drain of the PMOS transistor MP16, and the source of the NMOS transistor MN12 is connected to the source of the NMOS transistor MN9; the PMOS transistor MP16 serves as the PMOS output regulator of the CLASS-AB. The source of the entire transistor is connected to the power supply VDD terminal; the NMOS transistor MN12 serves as the NMOS output adjustment transistor of CLASS_AB, and its source is connected to the GND port; the drain of the PMOS transistor MP16 is connected to the drain of the NMOS transistor MP12 and serves as the VOUT port; the drain and source of the NMOS transistor MN12 are both connected to the resistor feedback network; the gate of the PMOS transistor MP16 is connected to the drain of the NMOS transistor MN11, the gate of the NMOS transistor MN9 is connected to the gate of the NMOS transistor MN7 and the bias circuit, the drain of the NMOS transistor MN9 is connected to the source of the NMOS transistor MN11, and the source of the NMOS transistor MN9 and the source of the NMOS transistor MN7 are connected to the GND port.

2. The low static power consumption LDO circuit according to claim 1, wherein: The bias circuit includes a low-voltage cascode current mirror structure composed of PMOS transistors MP1-MP6 and an NMOS transistor MN1; wherein the gate of the PMOS transistor MP1 is connected to the gate of the PMOS transistor MP2, the source of the PMOS transistor MP1 is connected to the drain of the PMOS transistor MP2, the source of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP3, the source of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP4, the gate of the PMOS transistor MP3 is connected to the gate of the PMOS transistor MP4, the source of the PMOS transistor MP3 is connected to the source of the PMOS transistor MP4 and both are connected to the power supply VDD terminal, the gate of the PMOS transistor MP3 is connected to the drain of the PMOS transistor MP5, the gate of the PMOS transistor MP1 is connected to the gate of the PMOS transistor MP5, the gate of the PMOS transistor MP6 is connected to the gate of the PMOS transistor MP5, the drain of the PMOS transistor MP4 is connected to the gate of the PMOS transistor MP5, and the gate of the PMOS transistor MP4 is connected to the gate of the PMOS transistor MP5. The source of the PMOS transistor P6 is connected, and the drain of the NMOS transistor MN1 is connected to the gate; the drain of the PMOS transistor MP6 is connected to the drain of the NMOS transistor MN1, the gate and drain of the PMOS transistor MP1 are connected and serve as the port IB_N1 for receiving the external bias current, the drain of the MOS transistor MP5 serves as the port IB_N2 for receiving the external bias current, the source of the NMOS transistor MN1 is connected to the GND port, and the source of the PMOS transistor MP2 is the VDD access port; the gates of the PMOS transistor MP4 and the NMOS transistor MN1 are both connected to the error amplifier; the gate of the PMOS transistor MP4 is also connected to the gate of the current source mirror transistor MP14; the gate of the NMOS transistor MN1 is connected to the gate of the NMOS transistor MN7; the source of the NMOS transistor MN1 is also connected to the source of the NMOS transistor MN7, and the gate of MP5 is also connected to the error amplifier.

3. The low static power consumption LDO circuit according to claim 2, characterized in that: The error amplifier is composed of NMOS transistors MN2 to MN6, PMOS transistors MP7 to MP10, and NMOS transistor MN13; wherein the gate of NMOS transistor MN2 is connected to the gate of NMOS transistor MN1, the source of NMOS transistor MN3 is connected to the drain of NMOS transistor MN2, the source of NMOS transistor MN4 is connected to the drain of NMOS transistor MN2, the source of NMOS transistor MN5 is connected to the source of NMOS transistor MN2, the source of NMOS transistor MN6 is connected to the source of NMOS transistor MN5 and connected to the GND port, the gate of NMOS transistor MN6 is connected to the gate of NMOS transistor MN5, the gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP4, the gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP8, the source of PMOS transistor MP10 is connected to the drain of PMOS transistor MP8 and the GND port of NMOS transistor MN4. The drain of the PMOS transistor MP9 is connected to the gate of the PMOS transistor MP10 and then to the gate of MP5. The drain of the PMOS transistor MP10 is connected to the drain of the NMOS transistor MN6. The drain of the PMOS transistor MP9 is connected to the drain of the NMOS transistor MN5. The source of the PMOS transistor MP9 is connected to the drain of the PMOS transistor MP7 and the drain of the NMOS transistor MN3. The gate of the NMOS transistor MN3 is connected to the reference voltage VREF. The sources of the PMOS transistors MP7 and MP8 are connected to the source of the PMOS transistor MP4. The gate and drain of the NMOS transistor MN5 are connected. The gate of the NMOS transistor MN13 is connected to the drain of the PMOS transistor MP10 and the gate of the PMOS transistor MP15. The source, drain and substrate of the NMOS transistor MN13 are interconnected and connected to the GND port. The gate of the NMOS transistor MN4 is connected to the resistor feedback network.

4. The low static power consumption LDO circuit according to claim 3, characterized in that: The resistor feedback network is composed of voltage-dividing resistors R1 and R2. One end of the voltage-dividing resistor R1 is connected to the source of the PMOS transistor MP15, the other end of the voltage-dividing resistor R1 is connected to one end of the voltage-dividing resistor R2, and the other end of the voltage-dividing resistor R2 is connected to the source of the NMOS transistor MN12. The common end of the voltage-dividing resistors R1 and R2 is also connected to the gate of the NMOS transistor MN4.

5. The low static power consumption LDO circuit according to claim 4, characterized in that: The output end load comprises a load resistor RL and a load capacitor CL connected in parallel; wherein, two ends of the load resistor RL are connected to the source of the NMOS transistor MN12 and the source of the PMOS transistor MP15 respectively.

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