Adaptive power adjustment method and system for powered equipment

Abstract

The present invention discloses an adaptive power adjustment method and system for a powered device. The method adjusts a voltage clamp circuit by obtaining power matching information from a target power supply device to obtain a voltage control signal. The current signal of the target powered device is sampled in real time and differentially adjusted according to the power matching information to obtain a current control signal. The duty cycle of an initial determination signal is adjusted according to the voltage control signal and the current control signal, and then the initial output power of the target powered device is adjusted according to the adjusted drive signal to obtain the adjusted output power. The corresponding current control signal and voltage control signal are determined by the power matching information, and then the output power of the powered device is limited and adjusted according to the determined control signal. This improves the stability and reliability of the device's output power, as well as the device's adaptability and compatibility to different POE standards, and reduces the device's limitations in terms of power limitation.

Description

Technical Field

[0001] The present invention relates to the technical field of powered devices, and in particular to an adaptive power adjustment method and system for powered devices. Background Art

[0002] In modern network communications equipment, Power over Ethernet (POE) is a key technology that simultaneously transmits data and power over Ethernet cables, making network equipment deployment more convenient and flexible. A POE system consists of power sourcing equipment (PSE) and powered devices (PD). The PSE provides power, while the PD uses the power provided by the PSE for operation and communication. POE technology is categorized into multiple standards, such as POE, POE+, and POE++. Different types of PSE devices exist on the market, corresponding to different POE standards.

[0003] In a POE system, the PD requires internal power conversion circuitry to convert the power transmitted by the PSE into power suitable for internal use. Currently, most PD power supplies offered by existing technologies lack power limiting functionality. Excessive output power from PDs without power limiting functionality can trigger the PSE's overload protection, causing the PD to lose power and disconnect, impacting network operation. A small number of PDs do have overcurrent limiting functionality, but these are limited to specific POE standards and are incompatible with multiple PSE types, limiting their adaptability to different POE standards. Summary of the Invention

[0004] The present invention provides an adaptive power adjustment method and system for a powered device, so as to achieve the technical effect of improving the power output stability and safety of the powered device while reducing the limitations of the powered device in terms of power restriction.

[0005] In order to solve the above technical problems, an embodiment of the present invention provides an adaptive power adjustment method for a powered device, comprising the following steps:

[0006] Obtaining power matching information of a target power supply device, adjusting a voltage clamping circuit according to the power matching information, and obtaining a voltage control signal;

[0007] real-time sampling to obtain a current signal of the target powered device, and differentially adjust the current signal according to the power matching information to obtain a current control signal;

[0008] The duty cycle of the initial driving signal is adjusted according to the voltage control signal and the current control signal, and a corresponding driving signal is output. Then, the initial output power of the target powered device is adjusted according to the driving signal, and the adjusted output power is obtained and output.

[0009] The adaptive power adjustment method provided by the present invention first obtains the power matching information of the target power supply device. Specifically, the system must first determine the power information that matches the target power supply device. This prevents the receiving device's output power from being too high, triggering the target power supply device's overload protection, thereby improving the operational stability of the system network. Secondly, after determining the power matching information of the power supply device, the system can adjust the voltage clamping circuit within the system based on the determined power matching information to obtain a voltage control signal for the circuit output. By adjusting the voltage clamping circuit once using the power matching information to obtain a corresponding voltage control signal, the voltage control signal can be used to adjust the output power of the receiving device. Specifically, the voltage control signal adjusts the output voltage of the receiving device, thereby adjusting the output power of the receiving device, thereby improving the stability, safety, and reliability of the power output of the receiving device.

[0010] When determining the voltage control signal, the system also samples the current signal of the powered device in real time, specifically the device's input current data. It then differentially adjusts the acquired current signal based on the power matching information of the power supply device to generate a corresponding current control signal. By adjusting the powered device's current signal based on the power matching information to generate a current control signal, the system then uses the current control signal to adjust the device's output current, thereby adjusting the device's output power. This secondary adjustment of the output power further ensures the stability and reliability of the device's power output.

[0011] By determining the power matching information of the self-powered device, the corresponding current control signal and voltage control signal are determined. The output current and voltage of the powered device are then adjusted based on the determined current and voltage control signals. This limits and adjusts the output power, improving the stability of the powered device's normal power output while also reducing the device's power limitation limitations. By adjusting the powered device's output power based on the power matching information of the power supply device, the powered device's output power is adaptively adjusted, improving its adaptability and compatibility with different PoE standards.

[0012] As a preferred example, adjusting the voltage clamping circuit according to the power matching information to obtain a voltage control signal specifically includes:

[0013] parsing the power matching information to obtain a corresponding logic control signal, and inputting the logic control signal into a voltage analog switch of the voltage clamp circuit so that the voltage analog switch adjusts the input impedance of the voltage reference according to the logic control signal;

[0014] The output voltage of the voltage clamp circuit is adjusted according to the input impedance of the voltage reference, and the adjusted output voltage is output as the voltage control signal.

[0015] After obtaining the power matching information, the system parses the matching information and obtains the corresponding logic control signal, that is, converting the obtained matching information into a data format that can be understood by the voltage clamping circuit, so that the voltage clamping circuit can understand the matching information and perform a corresponding response, that is, the voltage analog switch in the circuit adjusts the input impedance of the voltage reference in the circuit according to the logic control signal, thereby achieving adjustment of the output voltage of the voltage clamping circuit, and the output voltage of the voltage clamping circuit is the voltage control signal.

[0016] Therefore, the voltage control signal can be adjusted by adjusting the input impedance of the reference device, that is, the voltage control signal can be adjusted through power matching information, thereby adjusting the output power of the powered device, ensuring that the output power of the powered device does not trigger the overload protection of the power supply device, and thus improving the operational stability of the power Ethernet system.

[0017] As a preferred example, the real-time sampling to obtain the current signal of the target powered device, and performing differential adjustment on the current signal according to the power matching information to obtain the current control signal, includes:

[0018] sampling the input current of the target powered device in real time to obtain the current signal, and inputting the current signal and the logic control signal into a current analog switch of a gain adjustment circuit so that the current analog switch adjusts the output impedance of the gain adjustment circuit according to the current signal and the logic control signal;

[0019] The output differential current of the gain adjustment circuit is adjusted according to the adjusted output impedance, and the adjusted output differential current is output as the current control signal.

[0020] By sampling the input current of the powered device to obtain a current signal, the current signal and the logic control signal converted from the power matching information are input into the current analog switch of the gain adjustment circuit together, so that the current analog switch adjusts its output impedance according to the above two signals, and then adjusts the output current of the gain adjustment circuit through the output impedance, and outputs the adjusted output differential current signal as the current control signal, thereby achieving adjustment of the current control signal.

[0021] By adjusting the output impedance of the gain circuit, the output current of the gain circuit is adjusted, that is, the current control signal is adjusted according to the power matching information, thereby adjusting the output power of the powered device, further ensuring that the output power of the powered device does not trigger the overload protection of the power supply device, thereby ensuring the operational reliability of the power Ethernet.

[0022] As a preferred example, adjusting the duty cycle of the initial driving signal according to the voltage control signal and the current control signal and outputting the corresponding driving signal specifically includes:

[0023] Inputting the voltage control signal into a power management chip, so that the power management chip determines a duty cycle threshold of the drive signal according to the voltage control signal, and adjusts the initial drive signal according to the duty cycle threshold to obtain a first drive signal;

[0024] The current control signal is input into the power management chip so that the current gain of the power management chip is adjusted accordingly, and the first drive signal is adjusted according to the comparison result of the output voltage after gain adjustment and the preset reference voltage to obtain and output the drive signal.

[0025] After obtaining the voltage control signal and the current control signal, the system inputs the above two signals into the power management chip respectively, so that the power management chip adjusts the internal parameters of the chip accordingly according to the two received signals.

[0026] If the received signal is determined to be a voltage control signal, the system will adjust the duty cycle threshold of the drive signal output by the chip according to the voltage control signal, and adjust the initial drive signal according to the adjusted duty cycle threshold to obtain a first drive signal. That is, the voltage control signal is used to limit the maximum duty cycle of the drive signal, thereby limiting the output power of the powered device.

[0027] If the received signal is determined to be a current control signal, the system will adjust the current gain inside the chip according to the current control signal, and compare the chip output voltage after gain adjustment with the reference voltage preset in the chip, and then make a secondary adjustment to the first drive signal output by the chip based on the comparison result to obtain the drive signal.

[0028] The above dual adjustment method can effectively limit the duty cycle of the driving signal output by the power management chip, and then adjust the output power of the powered device by the driving signal output by the chip, thereby achieving adaptive limiting adjustment of the output power of the powered device.

[0029] As a preferred example, adjusting the initial output power of the target powered device according to the driving signal, and obtaining and outputting the adjusted output power, is specifically as follows:

[0030] The initial output voltage of the target powered device is adjusted according to the driving signal, so that the initial output power of the target powered device is adjusted accordingly, and the adjusted output power is obtained and output.

[0031] The driving signal adjusts the output power of the powered device by adjusting the output voltage of the powered device.

[0032] Accordingly, an embodiment of the present invention further provides an adaptive power adjustment system for a powered device, the adaptive power adjustment system comprising a powered device detection circuit, a control unit, a current limit threshold adjustment circuit, a power management circuit, a resistance sampling unit, and a powered device power output unit; wherein:

[0033] The powered device detection circuit is used to obtain power matching information of the target power supply device and transmit the power matching information to the control unit;

[0034] The control unit is configured to adjust the voltage clamping circuit in the current limit threshold adjustment circuit according to the power matching information;

[0035] The powered device power output unit is configured to receive an initial power signal transmitted by the powered device detection unit, and adjust the initial power signal according to a driving signal received from the power management circuit to obtain an adjusted output power;

[0036] The resistance sampling unit is used to sample the current signal of the power output unit of the powered device and send the current signal to the gain adjustment circuit of the current limit threshold adjustment circuit;

[0037] The current limit threshold adjustment circuit is used to adjust the received power matching information and the current signal, and obtain and transmit the output voltage control signal and the current control signal to the power management circuit;

[0038] The power management circuit is used to adjust the duty cycle of the initial driving signal according to the voltage control signal and the current control signal, and output the corresponding driving signal to the power output unit of the powered device.

[0039] To achieve adaptive power adjustment for a target powered device, the system provided by the present invention first obtains power matching information from the target power supply device through a powered device detection circuit. This matching information is then transmitted to a control unit, which then adjusts the parameters of the voltage clamping circuit in the current limit threshold adjustment circuit based on this matching information, thereby generating a voltage control signal. A resistance sampling unit then samples the current signal from the target powered device in real time and transmits the sampled current signal to the current limit threshold adjustment circuit. The current limit threshold adjustment circuit, after adjustment by the control unit, then adjusts the received current signal accordingly, thereby generating a current control signal.

[0040] The obtained voltage control signal and current control signal are then input into the power management circuit. The power management circuit adjusts the duty cycle of the initial drive signal based on the two received control signals and outputs the adjusted drive signal to the power output unit of the powered device. Upon receiving the adjusted drive signal, the power output unit of the powered device adjusts the initial output power of the target powered device based on the drive signal to obtain the corresponding output power. Through this adaptive power adjustment process, the power adjustment system can achieve adaptive adjustment of the output power of the powered device, thereby improving the adaptability and compatibility of the powered device with different POE standards.

[0041] As a preferred example, the voltage clamping circuit in the current limit threshold adjustment circuit includes: a voltage analog switch, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first diode, and a voltage reference; wherein:

[0042] The first pin of the voltage simulation switch is electrically connected to the first end of the third resistor, and the second end of the third resistor is grounded through the seventh resistor;

[0043] The second pin of the voltage simulation switch is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is grounded through the seventh resistor;

[0044] The fourth pin of the voltage simulation switch is electrically connected to the first end of the fifth resistor, and the second end of the fifth resistor is grounded through the seventh resistor;

[0045] The fifth pin of the voltage simulation switch is electrically connected to the first end of the sixth resistor, and the second end of the sixth resistor is grounded through the seventh resistor;

[0046] The third pin of the voltage simulation switch is grounded;

[0047] The sixth pin of the voltage simulation switch is grounded;

[0048] The seventh pin of the voltage simulation switch is grounded;

[0049] The eighth pin of the voltage simulation switch is grounded;

[0050] The sixteenth pin of the voltage simulation switch is electrically connected to the external power supply;

[0051] The cathode of the voltage reference is electrically connected to the external power supply through the first resistor, the reference end is electrically connected to the second end of the third resistor, and the anode is grounded;

[0052] The cathode of the voltage reference is electrically connected to the cathode of the first diode;

[0053] The second end of the fourth resistor is electrically connected to the reference end of the voltage reference;

[0054] The second end of the fifth resistor is electrically connected to the reference end of the voltage reference;

[0055] The second end of the sixth resistor is electrically connected to the reference end of the voltage reference;

[0056] The cathode of the first diode is electrically connected to the first end of the second resistor, and the anode of the first diode is electrically connected to the output end of the voltage clamping circuit;

[0057] The second end of the second resistor is grounded through the seventh resistor.

[0058] When the voltage clamping circuit in the system current limit threshold adjustment circuit receives an adjustment signal input by the control unit based on the power matching information, that is, when the voltage analog switch of the voltage clamping circuit receives the corresponding adjustment signal, it will first control one of the four channels of the analog switch to be turned on according to the received adjustment signal, and turn off the remaining three channels. The four channels are the channels corresponding to the first pin, the second pin, the fourth pin, and the fifth pin of the analog switch. Therefore, only one circuit corresponding to the four pins is in the on state, and the other three channels are in the closed state.

[0059] When one of the four channels of the analog switch is adjusted to the on state, the resistor set in the channel is connected in parallel with the seventh resistor after the channel is turned on, and the resistance value of the resistor after the parallel connection of the seventh resistor becomes the input impedance of the voltage reference. According to the adjustment of the input impedance of the voltage reference, the cathode voltage of the first diode connected to the cathode of the voltage reference also changes accordingly, and the corresponding anode voltage of the first diode also changes accordingly.

[0060] Specifically, by changing the conduction state of the four channels of the voltage analog switch, the input impedance of the voltage reference is adjusted. This adjusted input impedance will correspondingly adjust the voltage at the cathode of the first diode. Consequently, the voltage at the output terminal of the voltage clamp circuit, which is electrically connected to the anode of the first diode, i.e., the anode voltage of the first diode, will also change accordingly. Therefore, by adjusting the conduction state of the four output channels of the voltage analog switch, the output voltage of the voltage clamp circuit can be adjusted, thereby generating a corresponding voltage control signal that is input to the power management circuit.

[0061] As a preferred example, the gain adjustment circuit in the current limit threshold adjustment circuit includes: a current analog switch, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor; wherein:

[0062] The first pin of the current simulation switch is electrically connected to the first output terminal of the gain adjustment circuit through the eighth resistor;

[0063] The second pin of the current simulation switch is electrically connected to the first output end of the gain adjustment circuit through the ninth resistor;

[0064] The fourth pin of the current simulation switch is electrically connected to the first output terminal of the gain adjustment circuit through the twelfth resistor;

[0065] The fifth pin of the current simulation switch is electrically connected to the first output terminal of the gain adjustment circuit through the thirteenth resistor;

[0066] The eleventh pin of the current simulation switch is electrically connected to the second output terminal of the gain adjustment circuit through the fifteenth resistor;

[0067] The twelfth pin of the current analog switch is electrically connected to the second output end of the gain adjustment circuit through the fourteenth resistor;

[0068] The fourteenth pin of the current analog switch is electrically connected to the second output end of the gain adjustment circuit through the eleventh resistor;

[0069] The fifteenth pin of the current simulation switch is electrically connected to the second output end of the gain adjustment circuit through the tenth resistor;

[0070] The third pin of the current simulation switch is electrically connected to the first input terminal of the gain adjustment circuit;

[0071] The thirteenth pin of the current simulation switch is electrically connected to the second input terminal of the gain adjustment circuit;

[0072] The sixteenth pin of the current simulation switch is electrically connected to the external power supply;

[0073] The sixth pin of the current simulation switch is grounded;

[0074] The seventh pin of the current simulation switch is grounded;

[0075] The eighth pin of the current simulation switch is grounded.

[0076] When the current analog switch in the gain adjustment circuit of the system's current limit threshold adjustment circuit receives a current signal transmitted by the resistance sampling unit, it adjusts the conduction state of each channel of the analog switch based on the received current signal. The channels corresponding to the first, second, fourth, and fifth pins of the analog switch are all connected to the first output terminal of the gain adjustment circuit. Therefore, the input resistance of the first output terminal of the adjustment circuit is determined by the resistance values ​​of the eighth, ninth, twelfth, and thirteenth resistors electrically connected to the analog switch. By adjusting the conduction state of these four channels of the analog switch, the output resistance of the first output terminal of the gain adjustment circuit can be adjusted, thereby adjusting the output current of the first output terminal.

[0077] At the same time, the channels corresponding to the eleventh, twelfth, fourteenth, and fifteenth pins of the current analog switch serve as the second output terminal of the gain adjustment circuit. This means that by adjusting the conduction states of these four channels, the system can adjust the resistors connected to these four channels, i.e., the output resistance of the second output terminal of the gain adjustment circuit, thereby adjusting the output current of the second output terminal. Therefore, by adjusting the conduction states of the eight channels of the current analog switch, the current control signal output by the gain adjustment circuit can be adjusted.

[0078] As a preferred example, the power management circuit includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a second diode, and a synchronous buck controller; wherein:

[0079] The first pin of the synchronous buck controller is electrically connected to an external power supply;

[0080] The first pin of the synchronous buck controller is grounded through the first capacitor;

[0081] The first pin of the synchronous buck controller is electrically connected to the second pin of the synchronous buck controller through the sixteenth resistor;

[0082] The first pin of the synchronous buck controller is grounded via the sixteenth resistor and the eighteenth resistor in sequence;

[0083] The second pin of the synchronous buck controller is grounded via the third capacitor;

[0084] The second pin of the synchronous buck controller is grounded through the eighteenth resistor;

[0085] The third pin of the synchronous buck controller is grounded through the nineteenth resistor;

[0086] The fourth pin of the synchronous buck controller is electrically connected to the external power supply through the seventeenth resistor;

[0087] The fourth pin of the synchronous buck controller is grounded through the fifth capacitor;

[0088] The fifth pin of the synchronous buck controller is grounded via the sixth capacitor;

[0089] The sixth pin of the synchronous buck controller is grounded;

[0090] The seventh pin of the synchronous buck controller is grounded through the seventh capacitor;

[0091] The eighth pin of the synchronous buck controller is grounded via the twenty-third resistor;

[0092] The eighth pin of the synchronous buck controller is electrically connected to the ninth pin of the synchronous buck controller through the ninth capacitor;

[0093] The eighth pin of the synchronous buck controller is electrically connected to the ninth pin of the synchronous buck controller via the eighth capacitor and the twentieth resistor in sequence;

[0094] The eighth pin of the synchronous buck controller is electrically connected to the tenth pin of the synchronous buck controller through the twenty-second resistor;

[0095] The ninth pin of the synchronous buck controller is electrically connected to the output end of the voltage clamping circuit in the current limit threshold adjustment circuit;

[0096] The tenth pin of the synchronous buck controller is connected to the ground via the twenty-second resistor and the twenty-third resistor in sequence;

[0097] The eleventh pin of the synchronous buck controller is grounded via a twenty-first resistor;

[0098] The twelfth pin of the synchronous buck controller is electrically connected to the second output end of the gain adjustment circuit in the current limit threshold adjustment circuit;

[0099] The thirteenth pin of the synchronous buck controller is electrically connected to the first output end of the gain adjustment circuit in the current limit threshold adjustment circuit;

[0100] The fourteenth pin of the synchronous buck controller is grounded;

[0101] The sixteenth pin of the synchronous buck controller is grounded via the fourth capacitor;

[0102] The sixteenth pin of the synchronous buck controller is electrically connected to the eighteenth pin of the synchronous buck controller through the second diode;

[0103] The sixteenth pin of the synchronous buck controller is electrically connected to the eighteenth pin of the synchronous buck controller through the second capacitor;

[0104] The seventeenth pin of the synchronous buck controller is electrically connected to an external power supply.

[0105] The twelfth and thirteenth pins of the synchronous buck controller in the power management circuit of the system provided by the present invention are electrically connected to the first and second output terminals of the gain adjustment circuit in the current limit threshold adjustment circuit. In other words, the synchronous buck controller receives the current control signal output by the gain adjustment circuit via the twelfth and thirteenth pins. Furthermore, the ninth pin of the synchronous buck controller is electrically connected to the output terminal of the voltage clamp circuit in the current limit threshold adjustment circuit. In other words, the synchronous buck controller receives the voltage control signal output by the voltage clamp circuit via the ninth pin.

[0106] Therefore, when the synchronous buck controller of the power management circuit receives the current control signal output by the gain adjustment circuit and the voltage control signal output by the voltage clamp circuit, the synchronous buck controller can analyze the above two types of signals, and then adjust the duty cycle of the initial drive signal according to the above two signals to obtain the corresponding adjusted drive signal and output it to the power output unit of the powered device.

[0107] As a preferred example, the powered device detection circuit includes: a first light-emitting diode, a second light-emitting diode, a third light-emitting diode, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a twenty-ninth resistor, a thirtieth resistor, a thirty-first resistor, a thirty-second resistor, a thirty-third resistor, and a powered device detection chip; wherein:

[0108] The fourth pin of the powered device detection chip is electrically connected to the fifth pin of the powered device detection chip via the twenty-seventh resistor;

[0109] The fourth pin of the powered device detection chip is connected to ground via the twenty-seventh resistor and the twenty-eighth resistor in sequence;

[0110] The fifth pin of the powered device detection chip is grounded via the twenty-eighth resistor;

[0111] The sixth pin of the powered device detection chip is grounded via the twenty-ninth resistor;

[0112] The seventh pin of the powered device detection chip is grounded through the 30th resistor;

[0113] The eighth pin of the powered device detection chip is grounded via the thirty-first resistor;

[0114] The tenth pin of the powered device detection chip is grounded via the thirty-second resistor;

[0115] The eleventh pin of the powered device detection chip is grounded via the thirty-third resistor;

[0116] The twelfth pin of the powered device detection chip is electrically connected to the cathode of the third light emitting diode;

[0117] The anode of the third light emitting diode is electrically connected to the external power supply via the twenty-sixth resistor;

[0118] The thirteenth pin of the powered device detection chip is electrically connected to the cathode of the second light-emitting diode;

[0119] The anode of the second light emitting diode is electrically connected to the external power supply via the twenty-fifth resistor;

[0120] The fourteenth pin of the powered device detection chip is electrically connected to the cathode of the first light-emitting diode;

[0121] The anode of the first light emitting diode is electrically connected to the external power supply through the twenty-fourth resistor.

[0122] The received power matching information is marked through the twelfth pin, thirteenth pin and fourteenth pin of the powered device detection chip of the powered device detection circuit, that is, the power matching information of the target power supply device detected and determined by the powered device detection circuit is determined by three light-emitting diode marks electrically connected to the above three pins, and the marking status determined from the three pins is transmitted to the control unit through the powered device detection chip, and the control unit performs signal analysis and subsequent signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0123] Figure 1 : A flow chart of an embodiment of an adaptive power adjustment method for a powered device provided by the present invention;

[0124] Figure 2 : A structural diagram of an embodiment of an adaptive power adjustment system for a powered device provided by the present invention;

[0125] Figure 3: A structural diagram of an embodiment of the adaptive power adjustment POE system provided by the present invention;

[0126] Figure 4 : A chip schematic diagram of an embodiment of the PD detection IC provided by the present invention;

[0127] Figure 5 : A circuit diagram of an embodiment of a voltage clamping circuit provided by the present invention;

[0128] Figure 6 : A circuit diagram of an embodiment of a gain adjustment circuit provided by the present invention;

[0129] Figure 7 : A circuit diagram of an embodiment of the power management circuit provided by the present invention. DETAILED DESCRIPTION

[0130] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0131] Example 1

[0132] Please refer to Figure 1 , which is a flow chart of an embodiment of the adaptive power adjustment method for a powered device provided by the present invention, including steps 101 to 103, each of which is specifically as follows:

[0133] Step 101: Acquire power matching information of a target power supply device, adjust a voltage clamping circuit according to the power matching information, and obtain a voltage control signal.

[0134] The adaptive power adjustment method provided in an embodiment of the present invention first obtains the power matching information of the target power supply device. Specifically, the system must first determine the power information that matches the target power supply device. This prevents the receiving device's output power from being too high, triggering the target power supply device's overload protection, and improving the operational stability of the system network. Secondly, after determining the power matching information of the power supply device, the system can adjust the voltage clamping circuit within the system based on the determined power matching information to obtain a voltage control signal output by the circuit. By adjusting the voltage clamping circuit once using the power matching information to obtain a corresponding voltage control signal, the voltage control signal can be used to adjust the output power of the receiving device. Specifically, the voltage control signal is used to adjust the output voltage of the receiving device, thereby adjusting the output power of the receiving device, thereby improving the stability, safety, and reliability of the power output of the receiving device.

[0135] In this embodiment, specifically Figure 3 As shown, Figure 3 This is a structural diagram of an embodiment of the adaptive power adjustment POE system provided by the present invention. Figure 3 As shown, the target power supply device in the system is Figure 3 The PSE device shown in the figure is used, and the power matching information obtained by the system is obtained by Figure 3 The PD detection IC shown in the figure is determined by the POE protocol obtained from the PSE device. Figure 3 The PD matching information is shown.

[0136] Figure 3 The internal power supply section of the PD device shown in the figure includes not only a PD detection IC that obtains the POE protocol transmitted by the PSE device, but also an MCU that parses the PD matching information output by the PD detection IC, a current limit threshold adjustment circuit that receives the control signal output by the MCU, a buck circuit power section for outputting power to the powered device, a resistor sampling section for sampling the buck circuit power section, and a power management IC for outputting a drive signal to adjust the buck circuit output power.

[0137] Among them, see Figure 4 , Figure 4 This is a chip schematic diagram of an embodiment of the PD detection IC provided by the present invention. Specifically, Figure 4 The PD detection IC shown is the powered device detection unit described in this embodiment. Figure 4 The powered device detection circuit includes: a first light-emitting diode, a second light-emitting diode, a third light-emitting diode, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a twenty-ninth resistor, a thirtieth resistor, a thirty-first resistor, a thirty-second resistor, a thirty-third resistor, and a powered device detection chip; wherein:

[0138] The fourth pin of the powered device detection chip is electrically connected to the fifth pin of the powered device detection chip via the twenty-seventh resistor;

[0139] The fourth pin of the powered device detection chip is connected to ground via the twenty-seventh resistor and the twenty-eighth resistor in sequence;

[0140] The fifth pin of the powered device detection chip is grounded via the twenty-eighth resistor;

[0141] The sixth pin of the powered device detection chip is grounded via the twenty-ninth resistor;

[0142] The seventh pin of the powered device detection chip is grounded through the 30th resistor;

[0143] The eighth pin of the powered device detection chip is grounded via the thirty-first resistor;

[0144] The tenth pin of the powered device detection chip is grounded via the thirty-second resistor;

[0145] The eleventh pin of the powered device detection chip is grounded via the thirty-third resistor;

[0146] The twelfth pin of the powered device detection chip is electrically connected to the cathode of the third light emitting diode;

[0147] The anode of the third light emitting diode is electrically connected to the external power supply via the twenty-sixth resistor;

[0148] The thirteenth pin of the powered device detection chip is electrically connected to the cathode of the second light-emitting diode;

[0149] The anode of the second light emitting diode is electrically connected to the external power supply via the twenty-fifth resistor;

[0150] The fourteenth pin of the powered device detection chip is electrically connected to the cathode of the first light-emitting diode;

[0151] The anode of the first light emitting diode is electrically connected to the external power supply through the twenty-fourth resistor.

[0152] The received power matching information is marked through the twelfth pin, thirteenth pin and fourteenth pin of the powered device detection chip of the powered device detection circuit, that is, the power matching information of the target power supply device detected and determined by the powered device detection circuit is determined by three light-emitting diode marks electrically connected to the above three pins, and the marking status determined from the three pins is transmitted to the control unit through the powered device detection chip, and the control unit performs signal analysis and subsequent signal transmission.

[0153] like Figure 4 As shown, the chip model of the PD detection IC is MP8020GQV-Z. As a PD detection chip compatible with the IEEE802.f / t / bt standard, it can match the received power information, i.e. Figure 3 The POE protocol is indicated by high and low levels on the TYP1, TYP2, and BT pins, and the power information matched by the PSE device is identified by the level status of each of these pins. In the prior art, there are four main types of PSE devices based on different POE standards. The maximum output power of these four different types of PSE devices is 12.95W, 25.5W, 51W, and 71.3W, respectively. The corresponding relationship between the level status of these three pins and the four different types of PSE devices is shown below:

[0154]

[0155] According to the level status of the three pins in the above table, the system can determine the device type of the target power supply device, that is, the maximum output power of the power supply device, and transmit the level status of the three pins to the Figure 3 After the MCU is connected, the MCU can output the corresponding control signal according to the received pin status, that is, according to the determined power matching information, to adaptively control the Figure 3 The current limit threshold adjustment circuit is shown.

[0156] Specifically, in this embodiment, adjusting the voltage clamping circuit according to the power matching information to obtain the voltage control signal specifically includes:

[0157] parsing the power matching information to obtain a corresponding logic control signal, and inputting the logic control signal into a voltage analog switch of the voltage clamp circuit so that the voltage analog switch adjusts the input impedance of the voltage reference according to the logic control signal;

[0158] The output voltage of the voltage clamp circuit is adjusted according to the input impedance of the voltage reference, and the adjusted output voltage is output as the voltage control signal.

[0159] After obtaining the power matching information, the system parses the matching information and obtains the corresponding logic control signal, that is, converting the obtained matching information into a data format that can be understood by the voltage clamping circuit, so that the voltage clamping circuit can understand the matching information and perform corresponding reactions, that is, the voltage analog switch in the circuit adjusts the input impedance of the diode in the circuit according to the logic control signal, thereby achieving adjustment of the output voltage of the voltage clamping circuit, and the output voltage of the voltage clamping circuit is the voltage control signal.

[0160] Therefore, the voltage control signal can be adjusted by adjusting the input impedance of the diode, that is, the voltage control signal can be adjusted through power matching information, thereby adjusting the output power of the powered device, ensuring that the output power of the powered device does not trigger the overload protection of the power supply device, and thus improving the operational stability of the power Ethernet system.

[0161] In this embodiment, after the system obtains the PD matching information, it transmits it to Figure 3 In the MCU shown, the MCU converts it into a control signal and inputs it to Figure 3 In the current limit threshold adjustment circuit shown, the MCU controls and adjusts the current limit threshold adjustment circuit according to the determined matching information, that is, the power matching information is analyzed to obtain the logic control signal in this embodiment. Figure 3 The control signal shown is the logic control signal described in this embodiment, and Figure 3 The current limit threshold adjustment circuit shown includes the voltage clamp circuit described in this embodiment, so Figure 3 The system shown inputs the control signal to the current limit threshold adjustment circuit, that is, in this embodiment, the logic control signal is input to the voltage analog switch of the voltage clamp circuit.

[0162] See Figure 5 , Figure 5 This is a circuit diagram of an embodiment of the voltage clamping circuit provided by the present invention. Specifically, Figure 5 The voltage clamping circuit shown, i.e., the voltage clamping circuit in the current limit threshold adjustment circuit of this embodiment, includes: a voltage analog switch, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first diode, and a voltage reference; wherein:

[0163] The first pin of the voltage simulation switch is electrically connected to the first end of the third resistor, and the second end of the third resistor is grounded through the seventh resistor;

[0164] The second pin of the voltage simulation switch is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is grounded through the seventh resistor;

[0165] The fourth pin of the voltage simulation switch is electrically connected to the first end of the fifth resistor, and the second end of the fifth resistor is grounded through the seventh resistor;

[0166] The fifth pin of the voltage simulation switch is electrically connected to the first end of the sixth resistor, and the second end of the sixth resistor is grounded through the seventh resistor;

[0167] The third pin of the voltage simulation switch is grounded;

[0168] The sixth pin of the voltage simulation switch is grounded;

[0169] The seventh pin of the voltage simulation switch is grounded;

[0170] The eighth pin of the voltage simulation switch is grounded;

[0171] The sixteenth pin of the voltage simulation switch is electrically connected to the external power supply;

[0172] The cathode of the voltage reference is electrically connected to the external power supply through the first resistor, the reference end is electrically connected to the second end of the third resistor, and the anode is grounded;

[0173] The cathode of the voltage reference is electrically connected to the cathode of the first diode;

[0174] The second end of the fourth resistor is electrically connected to the reference end of the voltage reference;

[0175] The second end of the fifth resistor is electrically connected to the reference end of the voltage reference;

[0176] The second end of the sixth resistor is electrically connected to the reference end of the voltage reference;

[0177] The cathode of the first diode is electrically connected to the first end of the second resistor, and the anode of the first diode is electrically connected to the output end of the voltage clamping circuit;

[0178] The second end of the second resistor is grounded through the seventh resistor.

[0179] When the voltage clamping circuit in the system current limit threshold adjustment circuit receives an adjustment signal input by the control unit based on the power matching information, that is, when the voltage analog switch of the voltage clamping circuit receives the corresponding adjustment signal, it will first control one of the four channels of the analog switch to be turned on according to the received adjustment signal, and turn off the remaining three channels. The four channels are the channels corresponding to the first pin, the second pin, the fourth pin, and the fifth pin of the analog switch. Therefore, only one circuit corresponding to the four pins is in the on state, and the other three channels are in the closed state.

[0180] When one of the four channels of the analog switch is adjusted to the on state, the resistor set in the channel is connected in parallel with the seventh resistor R7, and the resistance value of the resistor in parallel with the seventh resistor R7 becomes the input impedance of the voltage reference. According to the adjustment of the input impedance of the voltage reference, the cathode voltage of the first diode D1 connected to the cathode of the voltage reference also changes accordingly, and the corresponding anode voltage of the first diode D1 also changes accordingly.

[0181] Specifically, by changing the conduction state of the four channels of the voltage analog switch, the input impedance of the voltage reference U2 is adjusted. This adjusted input impedance will correspondingly adjust the voltage at the cathode of the first diode D1. Consequently, the voltage at the output terminal of the voltage clamp circuit, which is electrically connected to the anode of the first diode D1, will also change accordingly. Therefore, by adjusting the conduction state of the four output channels of the voltage analog switch, the output voltage of the voltage clamp circuit can be adjusted, thereby generating a corresponding voltage control signal that is input to the power management circuit.

[0182] like Figure 5 As shown, the voltage simulation switch in this embodiment is Figure 5 U1 shown in FIG4 is a CD4052, a two-way differential four-channel multiplexer designed with advanced CMOS technology. U1 is a voltage analog switch in a single-pole four-throw configuration. Figure 5The voltage analog switch U1 shown has two binary channel control input ports, namely A0 and A1, and an enable input port, namely E#. Therefore, the voltage analog switch U1 can be controlled by two binary channel control input ports, namely Figure 5 The A0 and A1 terminals shown receive two binary input signals transmitted by the MCU, and control the four switch output channels connected to the voltage analog switch U1 according to the two received input signals, so that one channel is turned on and the other channels are turned off.

[0183] And, by Figure 5 It can be seen that among the four switch channels connected to the voltage analog switch U1 (model CD4052), channel Y0B and channel Y2B are used in parallel, and channel Y1B and channel Y3B are used in parallel. The system controls the closed state of the four channels of the voltage analog switch U1 through the logic control signals IO-0 and IO-1 output by the MCU. Since each channel of the voltage analog switch U1 is connected to a resistor, that is, Figure 5 The resistor R3 shown is the third resistor described in this embodiment, the resistor R4 is the fourth resistor described in this embodiment, the resistor R5 is the fifth resistor described in this embodiment, and the resistor R6 is the sixth resistor described in this embodiment, and the above four resistors and the resistor R7, the seventh resistor described in this embodiment, are all connected in parallel. Therefore, the voltage analog switch U1 can adjust the input impedance of the diode U2, which is the voltage reference device (model TL432) described in this embodiment, by adjusting the closed state of the four channels connected to it, and the voltage at point A of the diode D1, which is the first diode in this embodiment, can be adjusted by adjusting the input impedance of the diode U2.

[0184] The diode D1, i.e. the first diode in this embodiment, functions as an isolation diode, and the voltage at point B of the diode D1 is Figure 5 The output voltage of the voltage clamp circuit shown, i.e. the voltage control signal in this embodiment, has a voltage value equal to the voltage at point A plus the voltage difference of a BAT54X diode (usually 0.2V). Figure 5 The closed state of each channel of the voltage analog switch U1 in the voltage clamping circuit shown can realize the adjustment of the input impedance of the diode U2, that is, the adjustment of the input impedance of the voltage reference U2 described in this embodiment. By adjusting the input impedance of the diode U2, the voltage at point B of the diode D1 can be adjusted, that is, the adjustment of the output voltage of the voltage clamping circuit described in this embodiment, that is, the adjustment of the voltage control signal.

[0185] pass Figure 5 The voltage clamp circuit shown in the figure realizes the power management chip, namely Figure 5Adjusting the COMP pin voltage value of the power management IC shown can effectively control the duty cycle of the drive signal output by the power management IC, adjust the output voltage of the powered device, limit the output current of the powered device, and then control the output power of the powered device, thereby improving the operational stability of the Power Ethernet.

[0186] Step 102: sampling and acquiring a current signal of the target powered device in real time, and performing differential adjustment on the current signal according to the power matching information to obtain a current control signal.

[0187] When determining the voltage control signal, the system also samples the current signal of the powered device in real time, specifically the device's input current data. It then differentially adjusts the acquired current signal based on the power matching information of the power supply device to generate a corresponding current control signal. By adjusting the powered device's current signal based on the power matching information to generate a current control signal, the system then uses the current control signal to adjust the device's output current, thereby adjusting the device's output power. This secondary adjustment of the output power further ensures the stability and reliability of the device's power output.

[0188] Specifically, the real-time sampling and obtaining of the current signal of the target powered device, and the differential adjustment of the current signal according to the power matching information to obtain the current control signal, in this embodiment, include:

[0189] sampling the input current of the target powered device in real time to obtain the current signal, and inputting the current signal and the logic control signal into a current analog switch of a gain adjustment circuit so that the current analog switch adjusts the output impedance of the gain adjustment circuit according to the current signal and the logic control signal;

[0190] The output differential current of the gain adjustment circuit is adjusted according to the adjusted output impedance, and the adjusted output differential current is output as the current control signal.

[0191] By sampling the input current of the powered device to obtain a current signal, the current signal and the logic control signal converted from the power matching information are input into the current analog switch of the gain adjustment circuit together, so that the current analog switch adjusts its output impedance according to the above two signals, and then adjusts the output current of the gain adjustment circuit through the output impedance, and outputs the adjusted output differential current signal as the current control signal, thereby achieving adjustment of the current control signal.

[0192] By adjusting the output impedance of the gain circuit, the output current of the gain circuit is adjusted, that is, the current control signal is adjusted according to the power matching information, thereby adjusting the output power of the powered device, further ensuring that the output power of the powered device does not trigger the overload protection of the power supply device, thereby ensuring the operational reliability of the power Ethernet.

[0193] In this embodiment, see Figure 6 , Figure 6 This is a circuit diagram of an embodiment of the gain adjustment circuit provided by the present invention. Specifically, Figure 6 The gain adjustment circuit shown, i.e., the gain adjustment circuit in the current limit threshold adjustment circuit described in this embodiment, includes: a current analog switch, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor; wherein:

[0194] The first pin of the current simulation switch is electrically connected to the first output terminal of the gain adjustment circuit through the eighth resistor;

[0195] The second pin of the current simulation switch is electrically connected to the first output end of the gain adjustment circuit through the ninth resistor;

[0196] The fourth pin of the current simulation switch is electrically connected to the first output terminal of the gain adjustment circuit through the twelfth resistor;

[0197] The fifth pin of the current simulation switch is electrically connected to the first output terminal of the gain adjustment circuit through the thirteenth resistor;

[0198] The eleventh pin of the current simulation switch is electrically connected to the second output terminal of the gain adjustment circuit through the fifteenth resistor;

[0199] The twelfth pin of the current analog switch is electrically connected to the second output end of the gain adjustment circuit through the fourteenth resistor;

[0200] The fourteenth pin of the current analog switch is electrically connected to the second output end of the gain adjustment circuit through the eleventh resistor;

[0201] The fifteenth pin of the current simulation switch is electrically connected to the second output end of the gain adjustment circuit through the tenth resistor;

[0202] The third pin of the current simulation switch is electrically connected to the first input terminal of the gain adjustment circuit;

[0203] The thirteenth pin of the current simulation switch is electrically connected to the second input terminal of the gain adjustment circuit;

[0204] The sixteenth pin of the current simulation switch is electrically connected to the external power supply;

[0205] The sixth pin of the current simulation switch is grounded;

[0206] The seventh pin of the current simulation switch is grounded;

[0207] The eighth pin of the current simulation switch is grounded.

[0208] When the current analog switch U3 in the gain adjustment circuit of the system's current limit threshold adjustment circuit receives the current signal sent by the resistance sampling unit, it will adjust the conduction state of each channel of the analog switch U3 based on the received current signal. The channels corresponding to the first, second, fourth, and fifth pins of the analog switch U3 are all connected to the first output terminal of the gain adjustment circuit. Therefore, the input resistance of the first output terminal of the adjustment circuit is determined by the resistance values ​​of the eighth resistor R8, the ninth resistor R9, the twelfth resistor R12, and the thirteenth resistor R13 electrically connected to the analog switch. By adjusting the conduction state of the above four channels of the analog switch U3, the output resistance of the first output terminal of the gain adjustment circuit can be adjusted, thereby adjusting the output current of the first output terminal.

[0209] At the same time, the channels corresponding to the 11th, 12th, 14th, and 15th pins of the current analog switch represent the second output terminal of the gain adjustment circuit. This means that by adjusting the conduction states of these four channels, the system can adjust the resistors connected to these four channels, i.e., the output resistance of the second output terminal of the gain adjustment circuit, thereby adjusting the output current of the second output terminal. Therefore, by adjusting the conduction states of the eight channels of the current analog switch U3, the current control signal output by the gain adjustment circuit can be adjusted.

[0210] like Figure 6 As shown, the current analog switch in the gain adjustment circuit of this embodiment is Figure 6 As shown in U3, Figure 6 The current analog switch U3 shown is model CD4052, and each output channel connected to it adjusts the output resistance of the circuit in a differential form.

[0211] Depend on Figure 6It can be seen that the system will control the switching of each channel of the current analog switch U3 through the logic control signals IO-0 and IO-1 output by the MCU, and by adjusting the switching of each channel of the current analog switch U3, the output resistance of the circuit will be correspondingly adjusted. The difference in the circuit output resistance, that is, the output impedance of the circuit described in this embodiment, will change the gain of the current sampling amplifier inside the power management IC, that is, the output current of the circuit is adjusted by the output impedance of the circuit described in this embodiment, and the output current of the circuit can be used as a current control signal to adjust the internal parameters of the power management chip accordingly.

[0212] Step 103: adjusting the duty cycle of the initial driving signal according to the voltage control signal and the current control signal, outputting a corresponding driving signal, and then adjusting the initial output power of the target powered device according to the driving signal, obtaining and outputting the adjusted output power.

[0213] By determining the power matching information of the self-powered device, the corresponding current control signal and voltage control signal are determined. The output current and voltage of the powered device are then adjusted based on the determined current and voltage control signals. This limits and adjusts the output power, improving the stability of the powered device's normal power output while also reducing the device's power limitation limitations. By adjusting the powered device's output power based on the power matching information of the power supply device, the powered device's output power is adaptively adjusted, improving its adaptability and compatibility with different PoE standards.

[0214] Specifically, in this embodiment, adjusting the duty cycle of the initial driving signal according to the voltage control signal and the current control signal and outputting the corresponding driving signal specifically includes:

[0215] Inputting the voltage control signal into a power management chip, so that the power management chip determines a duty cycle threshold of the drive signal according to the voltage control signal, and adjusts the initial drive signal according to the duty cycle threshold to obtain a first drive signal;

[0216] The current control signal is input into the power management chip so that the current gain of the power management chip is adjusted accordingly, and the first drive signal is adjusted according to the comparison result of the output voltage after gain adjustment and the preset reference voltage to obtain and output the drive signal.

[0217] After obtaining the voltage control signal and the current control signal, the system inputs the above two signals into the power management chip respectively, so that the power management chip adjusts the internal parameters of the chip accordingly according to the two received signals.

[0218] If the received signal is determined to be a voltage control signal, the system will adjust the duty cycle threshold of the drive signal output by the chip according to the voltage control signal, and adjust the initial drive signal according to the adjusted duty cycle threshold to obtain a first drive signal. That is, the voltage control signal is used to limit the maximum duty cycle of the drive signal, thereby limiting the output power of the powered device.

[0219] If the received signal is determined to be a current control signal, the system will adjust the current gain inside the chip according to the current control signal, and compare the chip output voltage after gain adjustment with the reference voltage preset in the chip, and then make a secondary adjustment to the first drive signal output by the chip based on the comparison result to obtain the drive signal.

[0220] In this embodiment, see Figure 7 , Figure 7 This is a circuit diagram of an embodiment of the power management circuit provided by the present invention. Specifically, Figure 7 The power management circuit shown, i.e., the power management circuit described in this embodiment, includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a second diode, and a synchronous buck controller; wherein:

[0221] The first pin of the synchronous buck controller is electrically connected to an external power supply;

[0222] The first pin of the synchronous buck controller is grounded through the first capacitor;

[0223] The first pin of the synchronous buck controller is electrically connected to the second pin of the synchronous buck controller through the sixteenth resistor;

[0224] The first pin of the synchronous buck controller is grounded via the sixteenth resistor and the eighteenth resistor in sequence;

[0225] The second pin of the synchronous buck controller is grounded via the third capacitor;

[0226] The second pin of the synchronous buck controller is grounded through the eighteenth resistor;

[0227] The third pin of the synchronous buck controller is grounded through the nineteenth resistor;

[0228] The fourth pin of the synchronous buck controller is electrically connected to the external power supply through the seventeenth resistor;

[0229] The fourth pin of the synchronous buck controller is grounded through the fifth capacitor;

[0230] The fifth pin of the synchronous buck controller is grounded via the sixth capacitor;

[0231] The sixth pin of the synchronous buck controller is grounded;

[0232] The seventh pin of the synchronous buck controller is grounded through the seventh capacitor;

[0233] The eighth pin of the synchronous buck controller is grounded via the twenty-third resistor;

[0234] The eighth pin of the synchronous buck controller is electrically connected to the ninth pin of the synchronous buck controller through the ninth capacitor;

[0235] The eighth pin of the synchronous buck controller is electrically connected to the ninth pin of the synchronous buck controller via the eighth capacitor and the twentieth resistor in sequence;

[0236] The eighth pin of the synchronous buck controller is electrically connected to the tenth pin of the synchronous buck controller through the twenty-second resistor;

[0237] The ninth pin of the synchronous buck controller is electrically connected to the output end of the voltage clamping circuit in the current limit threshold adjustment circuit;

[0238] The tenth pin of the synchronous buck controller is connected to the ground via the twenty-second resistor and the twenty-third resistor in sequence;

[0239] The eleventh pin of the synchronous buck controller is grounded via a twenty-first resistor;

[0240] The twelfth pin of the synchronous buck controller is electrically connected to the second output end of the gain adjustment circuit in the current limit threshold adjustment circuit;

[0241] The thirteenth pin of the synchronous buck controller is electrically connected to the first output end of the gain adjustment circuit in the current limit threshold adjustment circuit;

[0242] The fourteenth pin of the synchronous buck controller is grounded;

[0243] The sixteenth pin of the synchronous buck controller is grounded via the fourth capacitor;

[0244] The sixteenth pin of the synchronous buck controller is electrically connected to the eighteenth pin of the synchronous buck controller through the second diode;

[0245] The sixteenth pin of the synchronous buck controller is electrically connected to the eighteenth pin of the synchronous buck controller through the second capacitor;

[0246] The seventeenth pin of the synchronous buck controller is electrically connected to an external power supply.

[0247] The twelfth and thirteenth pins of the synchronous buck controller in the power management circuit of the system provided by the embodiment of the present invention are electrically connected to the first and second output terminals of the gain adjustment circuit in the current limit threshold adjustment circuit. In other words, the synchronous buck controller receives the current control signal output by the gain adjustment circuit via the twelfth and thirteenth pins. Furthermore, the ninth pin of the synchronous buck controller is electrically connected to the output terminal of the voltage clamp circuit in the current limit threshold adjustment circuit. In other words, the synchronous buck controller receives the voltage control signal output by the voltage clamp circuit via the ninth pin.

[0248] Therefore, when the synchronous buck controller of the power management circuit receives the current control signal output by the gain adjustment circuit and the voltage control signal output by the voltage clamp circuit, the synchronous buck controller can analyze the above two types of signals, and then adjust the duty cycle of the initial drive signal according to the above two signals to obtain the corresponding adjusted drive signal and output it to the power output unit of the powered device.

[0249] like Figure 7 As shown, the power management chip, i.e., the synchronous buck controller described in this embodiment, is model LM5116. The twelfth and thirteenth pins of the synchronous buck controller are electrically connected to the gain adjustment circuit of the current limit threshold adjustment circuit, and the ninth pin of the synchronous buck controller is electrically connected to the voltage clamping circuit of the current limit threshold adjustment circuit, that is, the twelfth and thirteenth pins of the synchronous buck controller are used to receive current control signals, and the ninth pin is used to receive voltage control signals.

[0250] When the power management chip provided by the system is Figure 7 After the synchronous buck controller receives the corresponding voltage control signal and current control signal through the ninth pin, the twelfth pin and the thirteenth pin, the duty cycle of the driving signal in the controller can be adjusted according to the two received control signals to obtain the corresponding first driving signal.

[0251] In this embodiment, the current control signal can be used to Figure 3 The gain of the current sampling amplifier inside the power management IC is adjusted, that is, the current gain is adjusted in this embodiment. After the gain adjustment, the output voltage of the current sampling amplifier is compared with a reference voltage inside the power management IC, that is, the preset reference voltage in this embodiment. The system can perform a secondary adjustment on the duty cycle of the first drive signal according to the comparison result, that is, control the output voltage of the powered device and limit the output current of the powered device, thereby ensuring that the output power of the powered device will not trigger the overload protection of the power supply device, thereby improving the operational stability of the POE system.

[0252] The above dual adjustment method can effectively limit the duty cycle of the driving signal output by the power management chip, and then adjust the output power of the powered device by the driving signal output by the chip, thereby achieving adaptive limiting adjustment of the output power of the powered device.

[0253] Furthermore, in this embodiment, the initial output power of the target powered device is adjusted according to the driving signal, and the adjusted output power is obtained and outputted, specifically:

[0254] The initial output voltage of the target powered device is adjusted according to the driving signal, so that the initial output power of the target powered device is adjusted accordingly, and the adjusted output power is obtained and output.

[0255] The driving signal adjusts the output power of the powered device by adjusting the output voltage of the powered device.

[0256] In order to better illustrate the working principle and process flow of the adaptive power adjustment method and system for a powered device of the present invention, reference may be made to, but is not limited to, the relevant descriptions above.

[0257] Accordingly, participate Figure 2 , Figure 2 This is a structural diagram of an embodiment of the adaptive power adjustment system for powered devices provided by the present invention. Figure 2 As shown, the adaptive power adjustment system 20 includes a powered device detection circuit 201, a control unit 202, a current limit threshold adjustment circuit 203, a power management circuit 204, a resistance sampling unit 205 and a powered device power output unit 206; wherein:

[0258] The powered device detection circuit 201 is used to obtain power matching information of the target power supply device and transmit the power matching information to the control unit;

[0259] The control unit 202 is configured to adjust the voltage clamping circuit in the current limit threshold adjustment circuit according to the power matching information;

[0260] The powered device power output unit 206 is configured to receive the initial power signal transmitted by the powered device detection unit, and adjust the initial power signal according to the driving signal received from the power management circuit to obtain an adjusted output power;

[0261] The resistance sampling unit 205 is used to sample the current signal of the power output unit of the powered device and send the current signal to the gain adjustment circuit of the current limit threshold adjustment circuit;

[0262] The current limit threshold adjustment circuit 203 is used to adjust the received power matching information and the current signal, and obtain and send the output voltage control signal and current control signal to the power management circuit;

[0263] The power management circuit 204 is configured to adjust the duty cycle of the initial driving signal according to the voltage control signal and the current control signal, and output the corresponding driving signal to the power output unit of the powered device.

[0264] To achieve adaptive power adjustment for a target powered device, the system provided by the present invention first obtains power matching information from the target power supply device through a powered device detection circuit. This information is then transmitted to a control unit. The control unit then adjusts the parameters of the voltage clamping circuit in the current limit threshold adjustment circuit based on a logic control signal derived from analyzing the matching information, thereby generating a voltage control signal. A resistance sampling unit then samples the current signal from the target powered device in real time and transmits the sampled current signal to the current limit threshold adjustment circuit. The current limit threshold adjustment circuit then adjusts the received current signal accordingly, after it has been adjusted by the control unit using the logic control signal, thereby generating a current control signal.

[0265] The obtained voltage control signal and current control signal are then input into the power management circuit. The power management circuit adjusts the duty cycle of the initial drive signal based on the two received control signals and outputs the adjusted drive signal to the power output unit of the powered device. Upon receiving the adjusted drive signal, the power output unit of the powered device adjusts the initial output power of the target powered device based on the drive signal to obtain the corresponding output power. Through this adaptive power adjustment process, the power adjustment system can achieve adaptive adjustment of the output power of the powered device, thereby improving the adaptability and compatibility of the powered device with different POE standards.

[0266] In summary, the embodiments of the present invention provide an adaptive power adjustment method and system for a powered device. The method adjusts the voltage clamping circuit by obtaining power matching information from the target power supply device to obtain a voltage control signal. The current signal of the target powered device is sampled in real time and differentially adjusted according to the power matching information to obtain a current control signal. The duty cycle of the initial determination signal is adjusted according to the voltage control signal and the current control signal, and then the initial output power of the target powered device is adjusted according to the adjusted drive signal to obtain the adjusted output power. The corresponding current control signal and voltage control signal are determined by the power matching information, and then the output power of the powered device is limited and adjusted according to the determined control signal, thereby improving the stability and reliability of the device's output power and the device's adaptability and compatibility to different POE standards, and reducing the device's limitations in power limitation.

[0267] The specific embodiments described above further illustrate the objectives, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. An adaptive power adjustment method for a powered device, characterized in that: The following steps are involved: Obtaining power matching information of a target power supply device, adjusting a voltage clamping circuit according to the power matching information, and obtaining a voltage control signal; real-time sampling to obtain a current signal of a target powered device, and differentially adjusting the current signal according to the power matching information to obtain a current control signal; The duty cycle of the initial driving signal is adjusted according to the voltage control signal and the current control signal, and a corresponding driving signal is output. Then, the initial output power of the target powered device is adjusted according to the driving signal, and the adjusted output power is obtained and output.

2. The adaptive power adjustment method for a powered device according to claim 1, wherein: The adjusting the voltage clamping circuit according to the power matching information to obtain a voltage control signal specifically includes: parsing the power matching information to obtain a corresponding logic control signal, and inputting the logic control signal into a voltage analog switch of the voltage clamp circuit so that the voltage analog switch adjusts the input impedance of the voltage reference according to the logic control signal; The output voltage of the voltage clamp circuit is adjusted according to the input impedance of the voltage reference, and the adjusted output voltage is output as the voltage control signal.

3. The adaptive power adjustment method for a powered device according to any one of claims 1 to 2, characterized in that: The real-time sampling to obtain the current signal of the target powered device, and performing differential adjustment on the current signal according to the power matching information to obtain a current control signal, includes: sampling the input current of the target powered device in real time to obtain the current signal, and inputting the current signal and a logic control signal into a current analog switch of a gain adjustment circuit so that the current analog switch adjusts the output impedance of the gain adjustment circuit according to the current signal and the logic control signal; The output differential current of the gain adjustment circuit is adjusted according to the adjusted output impedance, and the adjusted output differential current is output as the current control signal.

4. The adaptive power adjustment method for a powered device according to claim 1, wherein: The step of adjusting the duty cycle of the initial driving signal according to the voltage control signal and the current control signal and outputting a corresponding driving signal specifically includes: Inputting the voltage control signal into a power management chip, so that the power management chip determines a duty cycle threshold of the drive signal according to the voltage control signal, and adjusts the initial drive signal according to the duty cycle threshold to obtain a first drive signal; The current control signal is input into the power management chip so that the current gain of the power management chip is adjusted accordingly, and the first drive signal is adjusted according to the comparison result of the output voltage after gain adjustment and the preset reference voltage to obtain and output the drive signal.

5. The adaptive power adjustment method for a powered device according to claim 1, wherein: The adjusting the initial output power of the target powered device according to the driving signal, and obtaining and outputting the adjusted output power, is specifically: The initial output voltage of the target powered device is adjusted according to the driving signal, so that the initial output power of the target powered device is adjusted accordingly, and the adjusted output power is obtained and output.

6. An adaptive power adjustment system for a powered device, characterized in that: The adaptive power adjustment system includes a powered device detection circuit, a control unit, a current limit threshold adjustment circuit, a power management circuit, a resistance sampling unit and a powered device power output unit; The powered device detection circuit is used to obtain power matching information of the target power supply device and transmit the power matching information to the control unit; The control unit is configured to adjust the voltage clamping circuit in the current limit threshold adjustment circuit according to the power matching information and output a voltage control signal; The powered device power output unit is configured to receive an initial power signal transmitted by the powered device detection unit, and adjust the initial power signal according to a driving signal received from the power management circuit to obtain an adjusted output power; The resistance sampling unit is used to sample the current signal of the power output unit of the powered device and send the current signal to the gain adjustment circuit of the current limit threshold adjustment circuit; The current limit threshold adjustment circuit is used to adjust the current signal according to the received power matching information, and obtain and output a current control signal to the power management circuit; The power management circuit is used to adjust the duty cycle of the initial driving signal according to the voltage control signal and the current control signal, and output the corresponding driving signal to the power output unit of the powered device.

7. The adaptive power adjustment system for a powered device according to claim 6, wherein: The voltage clamping circuit in the current limit threshold adjustment circuit includes: a voltage analog switch, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first diode and a voltage reference; the voltage analog switch adopts a CD4052 chip; wherein: The first pin of the voltage simulation switch is electrically connected to the first end of the third resistor, and the second end of the third resistor is grounded through the seventh resistor; The second pin of the voltage simulation switch is electrically connected to the first end of the fourth resistor, and the second end of the fourth resistor is grounded through the seventh resistor; The fourth pin of the voltage simulation switch is electrically connected to the first end of the fifth resistor, and the second end of the fifth resistor is grounded through the seventh resistor; The fifth pin of the voltage simulation switch is electrically connected to the first end of the sixth resistor, and the second end of the sixth resistor is grounded through the seventh resistor; The third pin of the voltage simulation switch is grounded; The sixth pin of the voltage simulation switch is grounded; The seventh pin of the voltage simulation switch is grounded; The eighth pin of the voltage simulation switch is grounded; The sixteenth pin of the voltage simulation switch is electrically connected to the external power supply; The cathode of the voltage reference is electrically connected to the external power supply through the first resistor, the reference end is electrically connected to the second end of the third resistor, and the anode is grounded; The cathode of the voltage reference is electrically connected to the cathode of the first diode; The second end of the fourth resistor is electrically connected to the reference end of the voltage reference; The second end of the fifth resistor is electrically connected to the reference end of the voltage reference; The second end of the sixth resistor is electrically connected to the reference end of the voltage reference; The cathode of the first diode is electrically connected to the first end of the second resistor, and the anode of the first diode is electrically connected to the output end of the voltage clamping circuit; The second end of the second resistor is grounded through the seventh resistor.

8. An adaptive power adjustment system for a powered device according to any one of claims 6 to 7, characterized in that: The gain adjustment circuit in the current limit threshold adjustment circuit includes: a current analog switch, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor; the current analog switch uses a CD4052 chip; wherein: The first pin of the current simulation switch is electrically connected to the first output terminal of the gain adjustment circuit through the eighth resistor; The second pin of the current simulation switch is electrically connected to the first output end of the gain adjustment circuit through the ninth resistor; The fourth pin of the current simulation switch is electrically connected to the first output terminal of the gain adjustment circuit through the twelfth resistor; The fifth pin of the current simulation switch is electrically connected to the first output terminal of the gain adjustment circuit through the thirteenth resistor; The eleventh pin of the current simulation switch is electrically connected to the second output terminal of the gain adjustment circuit through the fifteenth resistor; The twelfth pin of the current analog switch is electrically connected to the second output end of the gain adjustment circuit through the fourteenth resistor; The fourteenth pin of the current analog switch is electrically connected to the second output end of the gain adjustment circuit through the eleventh resistor; The fifteenth pin of the current simulation switch is electrically connected to the second output end of the gain adjustment circuit through the tenth resistor; The third pin of the current simulation switch is electrically connected to the first input terminal of the gain adjustment circuit; The thirteenth pin of the current simulation switch is electrically connected to the second input terminal of the gain adjustment circuit; The sixteenth pin of the current simulation switch is electrically connected to the external power supply; The sixth pin of the current simulation switch is grounded; The seventh pin of the current simulation switch is grounded; The eighth pin of the current simulation switch is grounded.

9. The adaptive power adjustment system for a powered device according to claim 6, wherein: The power management circuit includes: a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a second diode, and a synchronous buck controller; the synchronous buck controller uses an LM5116 chip; wherein: The first pin of the synchronous buck controller is electrically connected to an external power supply; The first pin of the synchronous buck controller is grounded through the first capacitor; The first pin of the synchronous buck controller is electrically connected to the second pin of the synchronous buck controller through the sixteenth resistor; The first pin of the synchronous buck controller is grounded via the sixteenth resistor and the eighteenth resistor in sequence; The second pin of the synchronous buck controller is grounded via the third capacitor; The second pin of the synchronous buck controller is grounded through the eighteenth resistor; The third pin of the synchronous buck controller is grounded through the nineteenth resistor; The fourth pin of the synchronous buck controller is electrically connected to the external power supply through the seventeenth resistor; The fourth pin of the synchronous buck controller is grounded through the fifth capacitor; The fifth pin of the synchronous buck controller is grounded via the sixth capacitor; The sixth pin of the synchronous buck controller is grounded; The seventh pin of the synchronous buck controller is grounded through the seventh capacitor; The eighth pin of the synchronous buck controller is grounded via the twenty-third resistor; The eighth pin of the synchronous buck controller is electrically connected to the ninth pin of the synchronous buck controller through the ninth capacitor; The eighth pin of the synchronous buck controller is electrically connected to the ninth pin of the synchronous buck controller via the eighth capacitor and the twentieth resistor in sequence; The eighth pin of the synchronous buck controller is electrically connected to the tenth pin of the synchronous buck controller through the twenty-second resistor; The ninth pin of the synchronous buck controller is electrically connected to the output end of the voltage clamping circuit in the current limit threshold adjustment circuit; The tenth pin of the synchronous buck controller is connected to the ground via the twenty-second resistor and the twenty-third resistor in sequence; The eleventh pin of the synchronous buck controller is grounded via a twenty-first resistor; The twelfth pin of the synchronous buck controller is electrically connected to the second output end of the gain adjustment circuit in the current limit threshold adjustment circuit; The thirteenth pin of the synchronous buck controller is electrically connected to the first output end of the gain adjustment circuit in the current limit threshold adjustment circuit; The fourteenth pin of the synchronous buck controller is grounded; The sixteenth pin of the synchronous buck controller is grounded via the fourth capacitor; The sixteenth pin of the synchronous buck controller is electrically connected to the eighteenth pin of the synchronous buck controller through the second diode; The sixteenth pin of the synchronous buck controller is electrically connected to the eighteenth pin of the synchronous buck controller through the second capacitor; The seventeenth pin of the synchronous buck controller is electrically connected to an external power supply.

10. The adaptive power adjustment system for a powered device according to claim 9, wherein: The powered device detection circuit includes: a first light-emitting diode, a second light-emitting diode, a third light-emitting diode, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a twenty-ninth resistor, a thirtieth resistor, a thirty-first resistor, a thirty-second resistor, a thirty-third resistor, and a powered device detection chip; the powered device detection chip adopts an MP8020GQV-Z chip; wherein: The fourth pin of the powered device detection chip is electrically connected to the fifth pin of the powered device detection chip via the twenty-seventh resistor; The fourth pin of the powered device detection chip is connected to ground via the twenty-seventh resistor and the twenty-eighth resistor in sequence; The fifth pin of the powered device detection chip is grounded via the twenty-eighth resistor; The sixth pin of the powered device detection chip is grounded via the twenty-ninth resistor; The seventh pin of the powered device detection chip is grounded through the 30th resistor; The eighth pin of the powered device detection chip is grounded via the thirty-first resistor; The tenth pin of the powered device detection chip is grounded via the thirty-second resistor; The eleventh pin of the powered device detection chip is grounded via the thirty-third resistor; The twelfth pin of the powered device detection chip is electrically connected to the cathode of the third light emitting diode; The anode of the third light emitting diode is electrically connected to the external power supply via the twenty-sixth resistor; The thirteenth pin of the powered device detection chip is electrically connected to the cathode of the second light-emitting diode; The anode of the second light emitting diode is electrically connected to the external power supply via the twenty-fifth resistor; The fourteenth pin of the powered device detection chip is electrically connected to the cathode of the first light-emitting diode; The anode of the first light emitting diode is electrically connected to the external power supply through the twenty-fourth resistor.

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