Data storage device and method of operating data storage device

Abstract

The invention relates to a data storage device and a method of operating the data storage device. The data storage device includes: a memory device including a plurality of first storage areas and a plurality of second storage areas, the plurality of first storage areas and the plurality of second storage areas respectively storing a primary index corresponding to a primary key provided from a host and a primary value corresponding to the primary index; and a memory controller for controlling the memory device. The memory controller is configured to: generate a primary index according to a request from a host, the primary index including a primary key and address information of a target second storage area among the plurality of second storage areas that stores a primary value corresponding to the primary key; generating a secondary key according to an additional request of the host, the secondary key corresponding to a secondary value including a portion of the primary value; and generating a secondary index including the secondary key and address information of the target second storage area.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0113499, filed on August 29, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to an electronic device, and more particularly, to a data storage device and a method of operating the data storage device. Background Art

[0004] A data storage device is a device that stores data under the control of a host device such as a computer or a smartphone. The data storage device may include a memory device that stores data and a memory controller that controls the memory device. The memory device may be a volatile memory device or a non-volatile memory device.

[0005] A volatile memory device is a memory device that stores data only when power is supplied and loses the stored data when power is interrupted. The volatile memory device may be a static random access memory (SRAM), a dynamic random access memory (DRAM), or the like.

[0006] A nonvolatile memory device is a memory device that retains data stored therein even when power is interrupted. A nonvolatile memory device may be a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM, an electrically erasable ROM (EEROM), a flash memory, etc. Summary of the invention

[0007] Embodiments of the present disclosure provide a data storage device and an operating method of the data storage device capable of increasing the speed of searching for a specific value.

[0008] According to an embodiment of the present disclosure, a data storage device is provided, comprising: a memory device, comprising a plurality of first storage areas and a plurality of second storage areas, the plurality of first storage areas storing primary indexes corresponding to primary keys provided from a host, and the plurality of second storage areas storing primary values ​​corresponding to the primary indexes; and a memory controller configured to control the memory device, wherein the memory controller is configured to: generate a primary index according to a request from the host, the primary index including the primary key and address information of a target second storage area storing the primary value corresponding to the primary key among the plurality of second storage areas; generate a secondary key according to an additional request from the host, the secondary key corresponding to a secondary value including a portion of the primary value; and generate a secondary index, the secondary index including the secondary key and address information of the target second storage area.

[0009] According to another embodiment of the present disclosure, there is provided a data storage device, comprising: a memory device, comprising a plurality of storage areas, the plurality of storage areas storing a primary value corresponding to a primary key, a primary index including the primary key, and a secondary index including secondary keys, the secondary keys respectively corresponding to secondary values ​​respectively including a portion of the primary value; and a memory controller, configured to control the memory device to read a target index including a secondary key corresponding to a request key included in the read request among the secondary indexes according to a read request from a host, and read the secondary value corresponding to the request key based on the target index.

[0010] The memory controller may provide the host with a secondary value corresponding to the request key or a primary key corresponding to the request key.

[0011] The request key may include a start key and an end key, and the memory controller may control the memory device to read a secondary value corresponding to a secondary key corresponding to the request key between the start key and the end key.

[0012] When the secondary values ​​corresponding to the request keys are greater than a predetermined size, the memory controller may provide the host with some secondary values ​​corresponding to some of the request keys and offset information of the remaining request keys among the request keys.

[0013] The memory controller may provide the host with remaining secondary values ​​corresponding to remaining request keys based on the offset information according to subsequent read requests received after the read request received from the host.

[0014] The memory controller may read the target index based on the secondary index metadata including address information of a first storage area storing the secondary index among the plurality of storage areas.

[0015] The memory controller may control the memory device to read a second target index including a maximum secondary key among the target indexes based on duplicate key information indicating whether the same secondary key as that included in a first target index among the target indexes is included.

[0016] According to the offset information and the length information received from the host, the secondary value may correspond to a specified value among the primary values.

[0017] The secondary index may include a primary key corresponding to the secondary key, address information of a second storage area storing secondary values ​​among multiple storage areas, and offset information and length information of the secondary value, which indicates the location where the secondary value is stored in the second storage area.

[0018] According to another embodiment of the present disclosure, there is provided an operating method of a data storage device, which is used to control a memory device including a first storage area and a second storage area, the first storage area storing a primary index corresponding to a primary key, and the second storage area storing a primary value corresponding to the primary index, the method comprising: generating a primary index, the primary index including the primary key and address information of the second storage area storing the primary value corresponding to the primary key; generating a secondary key, the secondary key corresponding to a secondary value including a portion of the primary value; and generating a secondary index, the secondary index including the secondary key and address information of the second storage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Various embodiments of the present disclosure will be described more fully below with reference to the accompanying drawings; however, the various embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the embodiments to those skilled in the art.

[0020] In the accompanying drawings, dimensions may be exaggerated for ease of illustration. It should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals refer to the same elements throughout.

[0021] Figure 1 is a diagram illustrating a data storage device including a memory controller according to an embodiment of the present disclosure.

[0022] Figure 2 is a diagram for describing an operation of generating a primary index according to an embodiment of the present disclosure.

[0023] Figure 3 is a diagram for describing a primary index according to an embodiment of the present disclosure.

[0024] Figure 4 is a diagram for describing primary index metadata according to an embodiment of the present disclosure.

[0025] Figure 5 is a diagram for describing an operation of providing a primary value corresponding to a primary key in response to a read request according to an embodiment of the present disclosure.

[0026] Figure 6 and Figure 7 is a diagram for describing an operation of generating a secondary index according to an embodiment of the present disclosure.

[0027] Figure 8 is a diagram for describing a secondary index according to an embodiment of the present disclosure.

[0028] Fig. 9is a diagram for describing secondary index metadata according to an embodiment of the present disclosure.

[0029] Fig.10 is a diagram for describing an operation of reading a secondary value corresponding to a secondary key received from a host according to an embodiment of the present disclosure.

[0030] Fig.11 is a diagram for describing an operation of reading a secondary value corresponding to a request key received from a host according to an embodiment of the present disclosure.

[0031] Fig.12 is a flowchart for describing the operation of generating a secondary index by a data storage device according to an embodiment of the present disclosure.

[0032] Fig.13 is a flowchart for describing an operation of a data storage device providing a secondary value according to a read request of a host according to an embodiment of the present disclosure.

[0033] Fig.14 is a diagram illustrating a memory controller according to an embodiment of the present disclosure.

[0034] Fig.15 According to the embodiment of the present disclosure Figure 1 Detailed schematic diagram of a non-volatile memory device shown in FIG. DETAILED DESCRIPTION

[0035] The specific structural or functional descriptions disclosed herein are only used to illustrate embodiments of the concepts according to the present disclosure. Embodiments of the concepts according to the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0036] Figure 1 is a diagram illustrating a data storage device 50 including a memory controller 200 according to an embodiment of the present disclosure.

[0037] Reference Figure 1 , the data storage device 50 may include a nonvolatile memory device 100, a memory controller 200, and a volatile memory device 300. The data storage device 50 may be a device included in a mobile phone, a computer, an in-vehicle infotainment system, etc., and stores data under the control of a host 400 as an external device.

[0038] The data storage device 50 may be manufactured as any of various types of storage devices such as a solid state drive (SSD) and a universal flash memory (UFS) according to a host interface as a communication scheme with the host 400. The data storage device 50 may be manufactured as any of various package types such as a system on chip (SOC).

[0039] The nonvolatile memory device 100 may store data. The nonvolatile memory device 100 may operate under the control of the memory controller 200.

[0040] The nonvolatile memory device 100 may receive a command and an address from the memory controller 200, and perform an operation indicated by the command on a region selected by the address. The nonvolatile memory device 100 may perform a program operation (write operation) of storing data in a region selected by the address, a read operation of reading data from a region selected by the address, or an erase operation of erasing data in a region selected by the address.

[0041] The memory controller 200 may control the operation of the data storage device 50 .

[0042] When power is applied to the data storage device 50, the memory controller 200 may run firmware (FW). In an embodiment, the memory controller 200 may control communication between the host 400 and the nonvolatile memory device 100 by running the FW. In an embodiment, the memory controller 200 may convert a logical address of the host 400 into a physical address of the nonvolatile memory device 100.

[0043] The memory controller 200 may control the nonvolatile memory device 100 to perform a program operation, a read operation, an erase operation, etc. according to a request of the host 400. The memory controller 200 may provide a command, a physical address, or data to the nonvolatile memory device 100 according to a write operation, a read operation, or an erase operation.

[0044] In an embodiment, the memory controller 200 may autonomously generate commands, addresses, and data regardless of any request from the host 400, and send the commands, addresses, and data to the nonvolatile memory device 100. For example, the memory controller 200 may provide commands, addresses, and data to the nonvolatile memory device 100, which are used to perform read operations and programming operations accompanying operations such as wear leveling, read recycling, and garbage collection.

[0045] In an embodiment, the memory controller 200 may control two or more nonvolatile memory devices. The memory controller 200 may control the nonvolatile memory devices according to an interleaving scheme to improve operation performance. The interleaving scheme may be a scheme for controlling operations of two or more nonvolatile memory devices to overlap with each other.

[0046] The volatile memory device 300 may temporarily store data provided from the host 400, or temporarily store data read from the nonvolatile memory device 100. In an embodiment, the volatile memory device 300 may be a dynamic random access memory (DRAM) or a static random access memory (SRAM). In an embodiment, the volatile memory device 300 may be located outside or inside the memory controller 200.

[0047] The host 400 may communicate with the data storage device 50 using various communication schemes. In an embodiment, the host 400 may include a host processor 410 and a host memory 420. The host processor 410 may control the operation of the host 400. The host memory 420 may be a volatile memory device. The host memory 420 may store key-value pairs including primary keys and primary values ​​corresponding to the primary keys, respectively.

[0048] In an embodiment, the host 400 may provide a write request, a primary key, and primary values ​​respectively corresponding to the primary keys to the data storage device 50 .

[0049] In response to a write request, the memory controller 200 may temporarily store the master key and the master value in the volatile memory device 300. In an embodiment, the volatile memory device 300 may include a key buffer 310 and a value buffer 320. The key buffer 310 may temporarily store the master key. The value buffer 320 may temporarily store the master value.

[0050] In an embodiment, the memory controller 200 may control the volatile memory device 300 to store the master key received from the host 400 in the key buffer 310, and to store the master value received from the host 400 in the value buffer 320. When the master key and the master value having a predetermined size are stored in the key buffer 310 and the value buffer 320, the memory controller 200 may flush the master key and the master value to the nonvolatile memory device 100.

[0051] In an embodiment, the nonvolatile memory device 100 may include a primary key storage area 111 and a value storage area 112. Each of the primary key storage area 111 and the value storage area 112 may include a plurality of storage blocks. The nonvolatile memory device 100 may store a primary key in the primary key storage area 111 and a primary value in the value storage area 112 under the control of the memory controller 200.

[0052] In an embodiment, in order to obtain a primary value corresponding to a primary key, the host 400 may provide a read request including the primary key to the data storage device 50. The memory controller 200 may read the primary value corresponding to the primary key from the value storage area 112 according to the read request of the host 400 and provide the read primary value to the host 400. In an embodiment, the memory controller 200 may generate a primary index including information related to the primary value corresponding to the primary key, and provide the primary value corresponding to the primary key included in the read request of the host 400 to the host 400 based on the primary index. Figure 2 The operation of the memory controller 200 to generate a primary index is described.

[0053] Figure 2 is a diagram for describing an operation of generating a primary index according to an embodiment of the present disclosure.

[0054] Reference Figure 2 , the memory controller 200 may control the nonvolatile memory device 100 to store the primary key received from the host 400 and the primary values ​​respectively corresponding to the primary key in the primary key storage area 111 and the value storage area 112. Thereafter, the memory controller 200 may generate a primary index according to the primary index generation request PI Request received from the host 400.

[0055] Specifically, the memory controller 200 can read the primary key from the primary key storage area 111 (① Read Primary Key). The memory controller 200 can generate a primary index based on the primary key (② Generate Primary Index). The primary index may include the primary key and information PrimaryValue Info related to the primary value corresponding to the primary key. The information Primary Value Info related to the primary value may include address information of a storage block storing the primary value, and first offset information and first length information indicating the location where the primary value is stored in the storage block storing the primary value.

[0056] When the number of generated primary indexes reaches a first threshold, the memory controller 200 may sort the primary indexes based on the primary keys included in the primary indexes. In an embodiment, the memory controller 200 may sort the primary indexes in ascending order according to the size of the primary keys included in the primary indexes.

[0057] The memory controller 200 may store the sorted primary index in the nonvolatile memory device 100 (③ Write Primary Index). The primary index may be stored in the primary index storage area 113 of the nonvolatile memory device 100. The primary index may be stored in a storage block among a plurality of storage blocks included in the primary index storage area 113.

[0058] The memory controller 200 may read the primary value corresponding to the primary index based on the sorted primary index. The memory controller 200 may sort the primary value to correspond to the sorted primary index. The memory controller 200 may sort the primary values ​​corresponding to the primary key according to the order in which the primary index is sorted. The memory controller 200 may store the sorted primary values ​​in the nonvolatile memory device 100. The sorted primary values ​​may be stored in the value storage area 112. The sorted primary values ​​may be stored in a storage block among a plurality of storage blocks included in the value storage area 112.

[0059] The memory controller 200 may generate primary index metadata based on the primary index (④ Generate Primary Index Meta Data). The primary index metadata may include information Primary Index Info related to the primary index. The information Primary Index Info related to the primary index may include address information of a storage block storing the primary index, and information of a maximum primary key having a maximum value among the primary keys included in the primary index. The memory controller 200 may temporarily store the primary index metadata in the volatile memory device 300.

[0060] Figure 3 is a diagram for describing a primary index according to an embodiment of the present disclosure.

[0061] Will refer to Figure 2 To describe Figure 3 . Reference Figure 3 , the memory controller 200 may generate a primary index based on the primary key and store the primary index in the primary index storage area 113. The primary index may include first to tenth primary indexes Primary Index 1 to Primary Index 10. Figure 3 In the description, the case of configuring ten main indexes will be taken as an example.

[0062] Each of the first to tenth primary indexes Primary Index1 to Primary Index10 may include a primary key and information related to a primary value corresponding to the primary key. The information related to the primary value may include address information ADDR, first offset information Offset1, and first length information Length1. The address information ADDR may be information indicating an address of a storage block storing a primary value corresponding to the primary key. The first offset information Offset1 and the first length information Length1 may be information indicating a location where the primary value is stored in the storage block.

[0063] In an embodiment, the first primary index Primary Index1 may include first to tenth primary keys PK1 to PK10. The address information corresponding to the first primary key PK1 may be a first address ADDR1. The first primary value corresponding to the first primary key PK1 may be stored in a first storage block corresponding to the first address ADDR1. The first offset information corresponding to the first primary key PK1 may be 30, and the first length information corresponding to the first primary key PK1 may be 10. The first primary value may be stored at a designated location in the first storage block according to the first offset information 30 and the first length information 10.

[0064] The first primary index Primary Index1 may include address information, first offset information, and first length information, which correspond to the second to tenth primary keys PK2 to PK10, respectively, and are the same as the address information, first offset information, and first length information corresponding to the first primary key PK1. The memory controller 200 may read the first to tenth primary values ​​corresponding to the first to tenth primary keys PK1 to PK10, respectively, based on the first primary index Primary Index1.

[0065] Similar to the first primary index Primary Index1 , the second to tenth primary indexes Primary Index2 to Primary Index10 may include address information, first offset information, and first length information, which correspond to the eleventh to one hundredth primary keys PK11 to PK100 , respectively.

[0066] Figure 4 is a diagram for describing primary index metadata according to an embodiment of the present disclosure.

[0067] Will refer to Figure 2 and Figure 3 To describe Figure 4 . Reference Figure 4 , the memory controller 200 may generate primary index metadata based on the first to tenth primary indexes Primary Index1 to Primary Index10, and store the primary index metadata in the volatile memory device 300. The primary index metadata may include the first to tenth primary index metadata PI Meta Data1 to PI Meta Data10.

[0068] In an embodiment, the first to tenth primary index metadata PI Meta Data1 to PI Meta Data10 may be metadata respectively associated with the first to tenth primary indexes Primary Index1 to Primary Index10. The first to tenth primary index metadata PI Meta Data1 to PI Meta Data10 may respectively include information related to the first to tenth primary indexes Primary Index1 to Primary Index10.

[0069] For example, the first primary index metadata PI Meta Data1 may be metadata associated with the first primary index Primary Index1. The first primary index metadata PI Meta Data1 may include information related to the first primary index Primary Index1. The information related to the first primary index Primary Index1 may include information of the maximum primary key having the maximum value among the primary keys included in the first primary index PrimaryIndex1 and address information ADDR_P11 of the first primary index Primary Index1. The address information ADDR_P11 of the first primary index Primary Index1 may be information indicating the address of a storage block storing the first primary index Primary Index1.

[0070] Specifically, the first primary index metadata PI Meta Data1 may include information of the tenth primary key PK10 having the maximum value among the first to tenth primary keys PK1 to PK10 included in the first primary index Primary Index1 and address information ADDR_P11 of the first primary index Primary Index1. The address information ADDR_P11 of the first primary index Primary Index1 may be information indicating the address of a storage block storing the first primary index Primary Index1.

[0071] Similarly, the second primary index metadata PI Meta Data2 may be metadata associated with the second primary index PrimaryIndex2. The second primary index metadata PI Meta Data2 may include information related to the second primary index PrimaryIndex2. The second primary index metadata PI Meta Data2 may include information about the twentieth primary key PK20 having the maximum value among the eleventh to twentieth primary keys PK11 to PK20 included in the second primary index PrimaryIndex2 and the address information ADDR_P12 of the second primary index Primary Index2. The address information ADDR_P12 of the second primary index Primary Index2 may be information indicating the address of the storage block storing the second primary index Primary Index2.

[0072] The tenth primary index metadata PI Meta Data10 may be metadata associated with the tenth primary index Primary Index10. The tenth primary index metadata PI Meta Data10 may include information of the 100th primary key PK100 having the maximum value among the 91st to 100th primary keys PK91 to PK100 included in the tenth primary index Primary Index10 and address information ADDR_PI10 of a storage block storing the tenth primary index Primary Index10. The address information ADDR_PI10 of the tenth primary index PrimaryIndex10 may be information indicating the address of the storage block storing the tenth primary index Primary Index10.

[0073] Figure 5 is a diagram for describing an operation of providing a primary value corresponding to a primary key in response to a read request according to an embodiment of the present disclosure.

[0074] Reference Figure 5 , the memory controller 200 may receive a read request Read Request including a thirteenth primary key Primary Key13 as a primary key requested by the host 400. The memory controller 200 may control the nonvolatile memory device 100 to read a thirteenth primary value Primary Value13 corresponding to the thirteenth primary key Primary Key13 in response to the read request ReadRequest.

[0075] Specifically, the memory controller 200 may read the primary index metadata from the volatile memory device 300. The memory controller 200 may read the primary index including the thirteenth primary key Primary Key13 based on the information of the largest primary key included in the primary index metadata.

[0076] In an embodiment, since the information of the maximum primary key included in the first primary index metadata PI Meta Data1 is the tenth primary key PK10, and the information of the maximum primary key included in the second primary index metadata PI Meta Data 2 is the twentieth primary key PK20, the memory controller 200 can recognize that the thirteenth primary key Primary Key13 is included in the second primary index Primary Index 2. The memory controller 200 can control the non-volatile memory device 100 to read the second primary index Primary Index2 based on the address information ADDR_P12 of the second primary index Primary Index2 included in the second primary index metadata PI Meta Data2.

[0077] The memory controller 200 may provide the read command Read CMD and address information ADDR_P12 of the second primary index Primary Index2 to the nonvolatile memory device 100. The nonvolatile memory device 100 may provide the second primary index Primary Index2 to the memory controller 200 in response to the read command Read CMD.

[0078] The memory controller 200 may identify the address of the storage block storing the thirteenth primary value Primary Value13 corresponding to the thirteenth primary key Primary Key 13 based on the second primary index Primary Index2. Specifically, since the address information corresponding to the thirteenth primary key Primary Key13 is the thirteenth address ADDR13, the memory controller 200 may identify that the address of the storage block storing the thirteenth primary value Primary Value13 is the thirteenth address ADDR13. The memory controller 200 may control the nonvolatile memory device 100 to read the data stored in the thirteenth storage block Block13 corresponding to the thirteenth address ADDR13.

[0079] The memory controller 200 may provide a read command Read CMD and a thirteenth address ADDR13 to the nonvolatile memory device 100. The nonvolatile memory device 100 may provide data stored in the thirteenth memory block Block13 to the memory controller 200 in response to the read command Read CMD.

[0080] The memory controller 200 may identify a thirteenth primary value Primary Value13 corresponding to the thirteenth primary key Primary Key 13 based on the first offset information Offset1 and the first length information Length1 corresponding to the thirteenth primary key Primary Key 13. The memory controller 200 may identify the designated data, that is, the thirteenth primary value Primary Value13, among the data stored in the thirteenth memory block Block13 according to the first offset information Offset1 20 and the first length information Length1 10. The memory controller 200 may provide the thirteenth primary value Primary Value13 corresponding to the thirteenth primary key Primary Key13 to the host 400.

[0081] Figure 6 and Figure 7 is a diagram for describing an operation of generating a secondary index according to an embodiment of the present disclosure.

[0082] First, refer to Figure 6 The memory controller 200 may generate a secondary index SecondaryIndex based on the primary index Primary Index and the primary value Primary Value in response to a secondary index generation request SI Request received from the host 400 .

[0083] Specifically, the memory controller 200 may receive a secondary index generation request SI Request including offset information Offset and length information Length from the host 400. The memory controller 200 may read the primary index Primary Index from the nonvolatile memory device 100 in response to the secondary index generation request SI Request (① Read Primary Index).

[0084] The memory controller 200 may read the primary value Primary Value corresponding to the primary key from the nonvolatile memory device 100 based on the information Primary Value Info related to the primary value Primary Value included in the primary index Primary Index (② Read Primary Value).

[0085] The memory controller 200 may specify a secondary value Secondary Value including a portion of the primary value Primary Value based on the offset information Offset and the length information Length. The memory controller 200 may generate a secondary key Secondary Key corresponding to the secondary value Secondary Value. The memory controller 200 may generate a secondary index Secondary Index based on the secondary key Secondary Key and the primary index Primary Index (③ Generate Secondary Index).

[0086] The secondary index Secondary Index may include a secondary key Secondary Key and information Secondary Value Info related to a secondary value corresponding to the secondary key. The information Secondary Value Info related to the secondary value may include address information of a storage block storing the secondary value, and second offset information and second length information indicating a storage location of the secondary value in the storage block storing the secondary value.

[0087] The memory controller 200 may provide the secondary index Secondary Index to the nonvolatile memory device 100 (④ Write Secondary Index). The secondary index Secondary Index may be stored in the secondary index storage area 114 of the nonvolatile memory device 100. The secondary index storage area 114 may include a plurality of memory blocks.

[0088] In an embodiment, the memory controller 200 may generate secondary indexes and temporarily store the secondary indexes in the volatile memory device 300. When the number of generated secondary indexes reaches a second threshold, the memory controller 200 may clear the generated secondary indexes from the volatile memory device 300 to the nonvolatile memory device 100.

[0089] Next, refer to Figure 7, the memory controller 200 can read the secondary indexes corresponding to the second threshold value from the non-volatile memory device 100 (⑤ Read Secondary Indexes). The memory controller 200 can merge the secondary indexes to correspond to a predetermined size, and sort the secondary indexes according to the size of the secondary keys included in the secondary indexes (⑥ Merge and Sort Secondary Indexes). For example, the memory controller 200 can sort the secondary indexes in ascending order according to the order from the secondary keys with smaller sizes to the secondary keys with larger sizes among the secondary keys included in the secondary indexes. Afterwards, the memory controller 200 can provide the secondary index Secondary Index to the non-volatile memory device 100 (⑦ Write Secondary Index). The secondary index Secondary Index can be stored in a storage block among the multiple storage blocks included in the secondary index storage area 114.

[0090] The memory controller 200 may generate secondary index metadata Secondary Index Meta Data based on the secondary index Secondary Index (⑧Generate Secondary Index MetaData). The secondary index metadata Secondary Index Meta Data may include information Secondary Index Info related to the secondary index. The information Secondary Index Info related to the secondary index may include address information of a storage block storing the secondary index and information of a maximum secondary key having a maximum value among the secondary keys included in the secondary index. The memory controller 200 may temporarily store the secondary index metadata Secondary Index Meta Data in the volatile memory device 300.

[0091] Figure 8 is a diagram for describing a secondary index according to an embodiment of the present disclosure.

[0092] Will refer to Figure 6 and Figure 7 describe Figure 8 . Reference Figure 8 , the memory controller 200 may generate a secondary index including a secondary key based on the primary index and the primary key, and store the secondary index in the secondary index storage area 114. The secondary index may include first to tenth secondary indexes Secondary Index 1 to Secondary Index 10. Figure 8In the description, the case of configuring ten secondary indexes will be taken as an example.

[0093] The first to tenth secondary indexes Secondary Index1 to Secondary Index10 may respectively include a primary key Primary Key corresponding to a secondary key Secondary Key and information related to a secondary value corresponding to the secondary key Secondary Key. The information related to the secondary value may include address information ADDR, second offset information Offset2, and second length information Length2. The address information ADDR may be information indicating an address of a storage block storing a secondary value corresponding to the secondary key. The second offset information Offset2 and the second length information Length2 may be information indicating a location where the secondary value is stored in a storage block.

[0094] In an embodiment, the first secondary index Secondary Index1 may include ten secondary keys. For example, the first secondary index Secondary Index1 may include a first secondary key SK1, a tenth primary key PK10 corresponding to the first secondary key SK1, and address information, second offset information, and second length information corresponding to the first secondary key SK1. The address information corresponding to the first secondary key SK1 may be the tenth address ADDR10. The first secondary value corresponding to the first secondary key SK1 may be stored in the tenth storage block corresponding to the tenth address ADDR10. The second offset information corresponding to the first secondary key SK1 may be 22, and the second length information corresponding to the first secondary key SK1 may be 6. The first secondary value may be stored in a specified location using the second offset information 22 and the second length information 6.

[0095] In an embodiment, since the first secondary key SK1 corresponds to the tenth primary key PK10, the first secondary value corresponding to the first secondary key SK1 may include a portion of the tenth primary value corresponding to the tenth primary key PK10. According to the offset information and the length information received from the host 400, the first secondary value may be designated as a portion of the tenth primary value.

[0096] In addition, refer to Figure 3 Since the first offset information of the tenth primary value corresponding to the tenth primary key PK10 is 20, when the offset information 2 is received from the host 400, the second offset information of the first secondary value including a part of the tenth primary value corresponding to the tenth primary key PK10 can be 22 obtained by adding 2 to 20.

[0097] The memory controller 200 may read a first secondary value corresponding to the first secondary key SK1 based on the first secondary index SecondaryIndex1 including the first secondary key SK1.

[0098] Fig. 9 is a diagram for describing secondary index metadata according to an embodiment of the present disclosure.

[0099] Will refer to Figures 6 to 8 To describe Fig. 9 . Reference Fig. 9 , the memory controller 200 may generate secondary index metadata Secondary Index Meta Data based on the first to tenth secondary indexes Secondary Index 1 to Secondary Index 10, and temporarily store the secondary index metadata Secondary Index Meta Data in the volatile memory device 300. The secondary index metadata Secondary Index Meta Data may include first to tenth secondary index metadata SI Meta Data 1 to SI Meta Data 10.

[0100] In an embodiment, the first to tenth secondary index metadata SI Meta Data 1 to SI Meta Data 10 may be metadata respectively associated with the first to tenth secondary indexes Secondary Index 1 to Secondary Index 10. The first to tenth secondary index metadata SI Meta Data 1 to SI Meta Data 10 may respectively include information related to the first to tenth secondary indexes Secondary Index 1 to Secondary Index 10.

[0101] For example, the first secondary index metadata SIMeta Data1 may be metadata associated with the first secondary index SecondaryIndex1. The first secondary index metadata SIMeta Data1 may include information related to the first secondary index Secondary Index1. The information related to the first secondary index Secondary Index1 may include information of a maximum secondary key having a maximum value among the secondary keys included in the first secondary index Secondary Index1, address information ADDR_SI1 of the first secondary index Secondary Index1, and duplicate key information Dup Info. For example, the address information ADDR_SI1 of the first secondary index Secondary Index1 may be information indicating an address of a storage block storing the first secondary index SecondaryIndex1. The duplicate key information Dup Info may be information indicating whether a secondary key identical to the maximum secondary key included in the first secondary index Secondary Index1 is included in another secondary index.

[0102] Specifically, the first secondary index metadata SIMeta Data1 may include information of the tenth secondary key SK10 having a maximum value among the secondary keys included in the first secondary index SecondaryIndex1 and address information ADDR_SI1 of the first secondary index Secondary Index1. Since the tenth secondary key SK10, which is the maximum secondary key included in the first secondary index Secondary Index1, is included in the second secondary index Secondary Index2, the first secondary index metadata SIMeta Data1 may include duplicate key information Dup Info indicating that another secondary index includes a duplicate key.

[0103] Similarly, the second secondary index metadata SIMeta Data2 may be metadata associated with the second secondary index SecondaryIndex2. The second secondary index metadata SIMeta Data2 may include information of the eighteenth secondary key SK18 having the maximum value among the secondary keys included in the second secondary index Secondary Index2, address information ADDR_SI2 of the second secondary index Secondary Index2, and duplicate key information Dup Info.

[0104] The tenth secondary index metadata SI Meta Data 10 may be metadata associated with the tenth secondary index Secondary Index 10. The tenth secondary index metadata SI Meta Data 10 may include information of the hundredth secondary key SK 100 having a maximum value among the secondary keys included in the tenth secondary index Secondary Index 10, address information ADDR_SI10 of the tenth secondary index Secondary Index 10, and duplicate key information Dup Info.

[0105] The memory controller 200 may read the first to tenth secondary indexes Secondary Index1 to Secondary Index10 based on the first to tenth secondary index metadata SIMeta Data1 to SIMetaData10.

[0106] Fig.10 is a diagram for describing an operation of reading a secondary value corresponding to a secondary key received from a host according to an embodiment of the present disclosure.

[0107] Reference Fig.10 , the memory controller 200 may receive a read request ReadRequest including a request key from the host 400. Fig.10In the description, a case where the request key is the third secondary key SK3 will be taken as an example.

[0108] The memory controller 200 may read the secondary index metadata SecondaryIndex Meta Data from the volatile memory device 300. The memory controller 200 may read the secondary index including the third secondary key SK3 based on information of the maximum secondary key included in the secondary index metadata Secondary Index MetaData.

[0109] In an embodiment, since the information of the maximum secondary key included in the first secondary index metadata SIMeta Data1 is the tenth secondary key SK10, and the information of the maximum secondary key included in the second secondary index metadata SIMeta Data2 is the eighteenth secondary key SK18, the memory controller 200 can recognize that the third secondary key SK3 is included in the first secondary index Secondary Index 1. The memory controller 200 can read the first secondary index Secondary Index 1 from the nonvolatile memory device 100 based on the address information ADDR_SI1 of the first secondary index included in the first secondary index metadata SIMeta Data1.

[0110] The memory controller 200 may provide the read command Read CMD and address information ADDR_SI1 of the first secondary index Secondary Index1 to the nonvolatile memory device 100. The nonvolatile memory device 100 may provide the first secondary index Secondary Index1 to the memory controller 200 in response to the read command Read CMD.

[0111] The memory controller 200 can identify the address storing the third secondary value corresponding to the third secondary key SK3 based on the first secondary index Secondary Index 1. Specifically, since the address information ADDR corresponding to the third secondary key SK3 is the thirteenth address ADDR13, the memory controller 200 can identify that the address of the storage block storing the third secondary value is the thirteenth address ADDR13. The memory controller 200 can control the nonvolatile memory device 100 to read the data stored in the thirteenth storage block Block13 corresponding to the thirteenth address ADDR13.

[0112] The memory controller 200 may provide a read command Read CMD and a thirteenth address ADDR13 to the nonvolatile memory device 100. The nonvolatile memory device 100 may provide data stored in the thirteenth memory block Block13 to the memory controller 200 in response to the read command Read CMD.

[0113] The memory controller 200 can identify the third secondary value Secondary Value3 corresponding to the third secondary key SK3 based on the second offset information Offset2 and the second length information Length2 corresponding to the third secondary key SK3. The memory controller 200 can identify the specified data, that is, the third secondary value Secondary Value3, among the data stored in the thirteenth storage block Block13 according to the second offset information 22 and the second length information 6. The third secondary value SecondaryValue3 can be a value designated as a part of the thirteenth primary value Primary Value13 corresponding to the thirteenth primary key PK13.

[0114] The memory controller 200 may provide the host 400 with a third secondary value Secondary Value3 corresponding to the third secondary key SK3 and a thirteenth primary key PK13 corresponding to the third secondary key SK3 .

[0115] In an embodiment, the memory controller 200 may receive a read request including a request key from the host 400. In an embodiment, the request key may include a secondary key. The memory controller 200 may read a target index including a secondary key corresponding to the request key among the secondary indexes based on the secondary index metadata. The memory controller 200 may read data stored in a storage block storing a secondary value corresponding to the request key based on the address information ADDR included in the target index. The memory controller 200 may identify a secondary value corresponding to the request key among the data stored in the storage block based on the second offset information Offset2 and the second length information Length2 included in the target index. The memory controller 200 may provide the host 400 with a secondary value corresponding to the request key and a primary key corresponding to the request key.

[0116] In an embodiment, the memory controller 200 may generate a secondary key corresponding to a secondary value including a portion of a primary value corresponding to the primary key, and generate a secondary index including the secondary key. The memory controller 200 may use the secondary index to obtain a secondary value corresponding to a portion of the primary value, and increase the speed at which the secondary value is provided to the host 400.

[0117] Fig.11 is a diagram for describing an operation of reading a secondary value corresponding to a request key received from a host according to an embodiment of the present disclosure.

[0118] Will refer to Figure 8 and Fig. 9 To describe Fig.11 . Reference Fig.11, the memory controller 200 may receive a read request Read Request including a request key from the host 400, where the request key includes a secondary index name SI Name, a start key Start Key, and an end key End Key. Fig.11 In the description, a case where the start key Start Key is the first secondary key SK1 and the end key End Key is the tenth secondary key SK10 will be taken as an example.

[0119] In an embodiment, when a secondary index iterator SI Iterator corresponding to the secondary index name SI Name received from the host 400 is not generated, the memory controller 200 may generate a secondary index iterator SI Iterator based on the secondary index metadata.

[0120] The memory controller 200 may successively read secondary values ​​corresponding to secondary keys corresponding to keys between the start key Start Key and the end key End Key using the secondary index iterator SI Iterator and provide the secondary values ​​to the host 400 .

[0121] Specifically, the memory controller 200 may use the secondary index metadata to identify the secondary index including the start key Start Key and the end key End Key. The memory controller 200 may identify that the secondary index including the first secondary key SK1 as the start key Start Key and the tenth secondary key SK10 is the first secondary index Secondary Index1 based on the tenth secondary key SK10 as the information of the maximum secondary key included in the first secondary index metadata SIMetaData1. In addition, the memory controller 200 may identify that the secondary key identical to the tenth secondary key SK10 as the maximum secondary key included in the first secondary index Secondary Index1 is included in the secondary index Secondary Index2 based on the duplicate key information DupInfo included in the first secondary index metadata SIMeta Data1.

[0122] Since the first secondary key SK1 and the tenth secondary key SK10 are included in the first secondary index Secondary Index1 and the second secondary index Secondary Index2, the memory controller 200 may generate a secondary index iterator SI Iterator for reading the first secondary index Secondary Index1 and the second secondary index Secondary Index2. The secondary index iterator SI Iterator may include a secondary index name SI Name, the first secondary key SK1 as a start key Start Key, the tenth secondary key SK10 as an end key End Key, address information ADDR_SI1 of the first secondary index, address information ADDR_SI2 of the second secondary index, and offset information Offset Info. When only secondary values ​​corresponding to some of the secondary keys corresponding to the keys between the start key Start Key and the end key End Key are provided to the host 400, the offset information Offset Info may be information indicating other secondary keys among the secondary keys corresponding to other secondary values ​​that are not provided to the host 400.

[0123] The memory controller 200 may provide a read command Read CMD, address information ADDR_SI1 of the first secondary index, and address information ADDR_SI2 of the second secondary index to the nonvolatile memory device 100. The nonvolatile memory device 100 may provide the first secondary index Secondary Index1 and the second secondary index Secondary Index2 to the memory controller 200 in response to the read command Read CMD.

[0124] The memory controller 200 may identify the address information of the secondary value corresponding to the secondary key corresponding to the key between the start key Start Key and the end key End Key based on the first secondary index Secondary Index1 and the second secondary index Secondary Index2. For example, the memory controller 200 may identify that the address information of the secondary value corresponding to the secondary key corresponding to the key between the first to tenth secondary keys SK1 to SK10 is the first to twentieth addresses ADDR1 to ADDR20. The memory controller 200 may control the nonvolatile memory device 100 to read the data stored in the first to twentieth storage blocks Block1 to Block20 corresponding to the first to twentieth addresses ADDR1 to ADD20, respectively.

[0125] In an embodiment, the memory controller 200 may provide a read command ReadCMD and first to twentieth addresses ADDR1 to ADDR20 to the nonvolatile memory device 100. The nonvolatile memory device 100 may provide data stored in the first to twentieth memory blocks Block1 to Block20 to the memory controller 200 in response to the read command Read CMD.

[0126] The memory controller 200 may identify a secondary value corresponding to a secondary key corresponding to a key between a start key Start Key and an end key End Key among data stored in the first to twentieth memory blocks Block1 to Block20 based on the second offset information and the second length information included in the first secondary index Secondary Index1 and the second secondary index Secondary Index2. The memory controller 200 may provide the host 400 with a secondary value corresponding to a secondary key corresponding to a key between the first to tenth secondary keys SK1 to SK10. The memory controller 200 may provide the host 400 with a primary key corresponding to a secondary key corresponding to a key between the first to tenth secondary keys SK1 to SK10.

[0127] In an embodiment, when the size of a secondary value to be provided to the host 400 is larger than the size of a host memory 420 included in the host 400, the memory controller 200 may provide offset information to the host 400, the offset information indicating some secondary values ​​corresponding to some secondary keys among the secondary keys corresponding to the keys between the start key Start Key and the end key End Key, and other secondary keys among the secondary keys.

[0128] When receiving the offset information Offset Info, the host 400 may recognize that all secondary values ​​corresponding to the secondary keys corresponding to the keys between the start key Start Key and the end key End Key have not been received. Therefore, when receiving the offset information Offset Info, the host 400 may send a subsequent read request to the memory controller 200.

[0129] In response to a subsequent read request, the memory controller 200 may provide the host 400 with other secondary values ​​corresponding to other requested keys among the secondary keys corresponding to the keys between the start key Start Key and the end key End Key.

[0130] For example, the memory controller 200 may provide the host 400 with offset information indicating first to fifth secondary values ​​corresponding to the first to fifth secondary keys and a sixth secondary key corresponding to the sixth secondary value that is not provided to the host 400. In addition, the memory controller 200 may provide the host 400 with sixth to tenth secondary values ​​corresponding to the sixth to tenth secondary keys in response to a subsequent read request.

[0131] Fig.12 It is a flowchart for describing that a data storage device generates a secondary index according to an embodiment of the present disclosure.

[0132] In operation S1201, the data storage device 50 may read a primary index and a primary value in response to a request received from a host. The primary index may include a primary key, address information of a storage block storing a primary value corresponding to the primary key, and first offset information and first length information indicating a location where the primary value is stored in the storage block.

[0133] In operation S1203, the data storage device 50 may generate a secondary key corresponding to a secondary value including a portion of the primary value based on the offset information and the length information included in the request of the host. The secondary value may be designated as a portion of the primary value according to the offset information and the length information.

[0134] In operation S1205, the data storage device 50 may generate a secondary index including a secondary key and information related to a secondary value. The information related to the secondary value may include address information of a storage block storing a secondary value corresponding to the secondary key, and second offset information and second length information indicating a location where the secondary value is stored in the storage block.

[0135] Fig.13 is a flowchart for describing that a data storage device according to an embodiment of the present disclosure provides a secondary value according to a read request of a host.

[0136] In operation S1301 , the data storage device 50 may receive a read request from a host.

[0137] In operation S1303, the data storage device 50 may read a target index including a secondary key corresponding to a request key included in a read request among the secondary indexes based on the secondary index metadata. The secondary index metadata may include address information of a storage block storing the secondary index and information of a maximum secondary key having a maximum value among the secondary keys included in the secondary index. The request key may include a start key and an end key.

[0138] In operation S1305, the data storage device 50 may provide the host with a secondary value corresponding to the request key based on the target index. The data storage device 50 may read a secondary value corresponding to a secondary key corresponding to a key between the start key and the end key and provide the read secondary value to the host.

[0139] Fig.14 is a diagram illustrating a memory controller 1400 according to an embodiment of the present disclosure.

[0140] Reference Fig.14 , the memory controller 1400 may include a processor 1410 , a RAM 1420 , an error correction code (ECC) circuit 1430 , a host interface 1440 , a ROM 1450 , and a memory interface 1460 .

[0141] The processor 1410 may control the operation of the memory controller 1400. The processor 1410 may control the operation of the memory controller 1400 to store data requested from the host 400 in the nonvolatile memory device 100. In an embodiment, the processor 1410 may read the primary index and the primary value according to a secondary index generation request of the host 400, generate a secondary key corresponding to the secondary value including a portion of the primary value, and generate a secondary index including the secondary key. The processor 1410 may read a target index including a secondary key corresponding to the request key among the secondary indexes in response to the read request, and acquire a secondary value corresponding to the request key from the nonvolatile memory device 100 based on the target index.

[0142] The RAM 1420 may be used as a buffer memory, a cache memory, a working memory, etc. of the memory controller 1400. In an embodiment, the RAM 1420 may temporarily store primary index metadata and secondary index metadata.

[0143] The ECC circuit 1430 may perform error correction. The ECC circuit 1430 may perform ECC encoding based on data to be written in the nonvolatile memory device 100 through the memory interface 1460. The ECC-encoded data may be transmitted to the nonvolatile memory device 100 through the memory interface 1460. The ECC circuit 1430 may perform ECC decoding on data received from the nonvolatile memory device 100 through the memory interface 1460.

[0144] The ROM 1450 may store various information required when operating the memory controller 1400 in the form of firmware.

[0145] The memory controller 1400 may communicate with an external device (eg, the host 400, an application processor, etc.) through the host interface 1440. The memory controller 1400 may receive a primary key and a primary value corresponding to the primary key through the host interface 1440. In an embodiment, the host interface 1440 may receive a read request from the host 400.

[0146] The memory controller 1400 may communicate with the nonvolatile memory device 100 through the memory interface 1460. The memory controller 1400 may send commands, addresses, data, etc. to the nonvolatile memory device 100 through the memory interface 1460. The memory interface 2160 may provide the nonvolatile memory device 100 with a read command for acquiring a secondary value corresponding to a secondary key.

[0147] Fig.15 According to the embodiment of the present disclosure Figure 1 Detailed schematic diagram of a non-volatile memory device 100 is shown in FIG.

[0148] Reference Fig.15 , the nonvolatile memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0149] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be connected to the address decoder 121 through the row line RL. The plurality of memory blocks BLK1 to BLKz may be connected to the page buffer group 123 through the bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory cells connected to the same word line among the plurality of memory cells may be defined as one physical page. In an embodiment, a physical page may be a unit for storing data or reading stored data. One physical page may include a plurality of logical pages. A memory block may be a unit for erasing data.

[0150] Each of the memory cells may be configured as a single-level cell (SLC) storing one bit of data, a multi-level cell (MLC) storing two bits of data, a triple-level cell (TLC) storing three bits of data, a quad-level cell (QLC) storing four bits of data, or a memory cell storing five or more bits of data.

[0151] The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation under the control of the control logic 130. In another example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLm under the control of the control logic 130, or discharge the applied voltages.

[0152] The peripheral circuit 120 may include an address decoder 121 , a voltage generator 122 , a page buffer group 123 , a data input / output circuit 124 , and a sensing circuit 125 .

[0153] The address decoder 121 may be connected to the memory cell array 110 through row lines RL. The row lines RL may include a drain selection line, a word line, a source selection line, and a source line.

[0154] The address decoder 121 may operate under the control of the control logic 130. The address decoder 121 may receive an address ADDR from the control logic 130.

[0155] The address decoder 121 may decode the block address in the received address ADDR. The address decoder 121 may select at least one memory block among the memory blocks BLK1 to BLKz according to the decoded block address. The address decoder 121 may decode the row address in the received address ADDR. The address decoder 121 may select at least one word line WL of the selected memory block by applying a voltage provided from the voltage generator 122 to the at least one word line WL according to the decoded row address.

[0156] In a programming operation, the address decoder 121 may apply a program voltage to a selected word line and apply a pass voltage having a level lower than the program voltage level to a non-selected word line. In a program verification operation, the address decoder 121 may apply a verification voltage to a selected word line and apply a verification pass voltage having a level higher than the verification voltage to a non-selected word line.

[0157] In a read operation, the address decoder 121 may apply a read voltage to a selected word line, and apply a read pass voltage having a level higher than the read voltage to non-selected word lines.

[0158] The address decoder 121 may decode a column address in the received address ADDR. The decoded column address may be transmitted to the page buffer group 123. The address decoder 121 may include components such as a row decoder, a column decoder, and an address buffer.

[0159] The voltage generator 122 may generate a plurality of operating voltages Vop by using an external power supply voltage provided to the nonvolatile memory device 100. The voltage generator 122 may operate under the control of the control logic 130.

[0160] In an embodiment, the voltage generator 122 may generate various operation voltages Vop for programming, reading, and erasing operations in response to the operation signal OPSIG. For example, the voltage generator 122 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of selection read voltages, and a plurality of non-selection read voltages. The plurality of operation voltages Vop may be provided to the memory cell array 110 by the address decoder 121.

[0161] The page buffer group 123 may include first to mth page buffers PB1 to PBm. The first to mth page buffers PB1 to PBm may be connected to the memory cell array 110 through first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm may operate under the control of the control logic 130.

[0162] The first to mth page buffers PB1 to PBm may communicate data DATA with the data input / output circuit 124. In a program operation, the first to mth page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 124 and the data lines DL.

[0163] In a programming operation, the first page buffer to the mth page buffer PB1 to PBm can transmit the data DATA received through the data input / output circuit 124 to the selected memory cell through the bit lines BL1 to BLm. The selected memory cell can be programmed according to the transmitted data DATA. The memory cell connected to the bit line to which the programming enable voltage (e.g., the ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cell connected to the bit line to which the programming prohibition voltage (e.g., the power supply voltage) is applied can be maintained. In a verification operation, the first page buffer to the mth page buffer PB1 to PBm can read the data DATA stored in the selected memory cell from the selected memory cell through the bit lines BL1 to BLm.

[0164] In a read operation, the page buffer group 123 may read data DATA from memory cells of a selected page through the bit lines BL and store the read data DATA in the first to mth page buffers PB1 to PBm.

[0165] The data input / output circuit 124 may be connected to the first to m-th page buffers PB1 to PBm through the data lines DL The data input / output circuit 124 may operate under the control of the control logic 130 .

[0166] The data input / output circuit 124 may include a plurality of input / output buffers (not shown) that receive input data DATA. In a program operation, the data input / output circuit 124 may receive data DATA to be stored from the memory controller 200. In a read operation, the data input / output circuit 124 may output data DATA transmitted from the first page buffer PB1 to the mth page buffer PBm included in the page buffer group 123 to the memory controller 200.

[0167] In a read operation or a verification operation, the sensing circuit 125 may generate a reference current in response to an enable bit VRYBIT generated by the control logic 130, and output a pass signal PASS or a fail signal FAIL to the control logic 130 by comparing the sensing voltage VPB received from the page buffer group 123 with the reference voltage generated by the reference current. For example, when the magnitude of the sensing voltage VPB is less than the magnitude of the reference voltage, the sensing circuit 125 may output a pass signal to the control logic 130. In another example, when the magnitude of the sensing voltage VPB is greater than the magnitude of the reference voltage, the sensing circuit 125 may output a fail signal to the control logic 130.

[0168] The control logic 130 may be connected to the address decoder 121, the voltage generator 122, the page buffer group 123, the data input / output circuit 124, and the sensing circuit 125. The control logic 130 may control the operation of the nonvolatile memory device 100. The control logic 130 may operate in response to a command CMD transmitted from the memory controller 200.

[0169] The control logic 130 may control the peripheral circuit 120 by generating several signals in response to the command CMD and the address ADDR. For example, the control logic 130 may generate an operation signal OPSIG, an address ADDR, a page buffer control signal PBSIG, and an enable bit VRYBIT in response to the command CMD and the address ADDR. The control logic 130 may output the operation signal OPSIG to the voltage generator 122, the address ADDR to the address decoder 121, the page buffer control signal PBSIG to the page buffer group 123, and the enable bit VRYBIT to the sensing circuit 125. In addition, the control logic 130 may determine whether the verification operation is passed or failed in response to the pass signal PASS or the fail signal FAIL output by the sensing circuit 125.

[0170] According to an embodiment of the present disclosure, a memory controller capable of increasing a speed of searching for a specific value and a data storage device including the memory controller may be provided.

[0171] Although the present disclosure has been illustrated and described with reference to certain embodiments of the present disclosure, it should be understood by those skilled in the art that various changes may be made to the form and details of the present disclosure without departing from the spirit and scope of the present disclosure as defined by the attached claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but is determined not only by the attached claims but also by the equivalents of the present disclosure.

[0172] In the above-described embodiments, all operations may be selectively performed, or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the order described, but may be reordered. The embodiments disclosed in this specification and the accompanying drawings are merely examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be understood by those skilled in the art that various modifications may be made on the basis of the technical scope of the present disclosure.

[0173] Embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to describe embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and there may be many changes within the spirit and scope of the present disclosure. It should be understood by those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure. In addition, these embodiments may be combined to form other embodiments.

Claims

1. A data storage device, comprising: A memory device comprising a plurality of first storage areas and a plurality of second storage areas, the plurality of first storage areas storing primary indexes corresponding to primary keys provided from a host, the plurality of second storage areas storing primary values ​​corresponding to the primary indexes; as well as a memory controller, controlling the memory device, Wherein, the memory controller: generating the primary index according to a request from the host, the primary index including the primary key and address information of a target second storage area storing a primary value corresponding to the primary key among the plurality of second storage areas; generating a secondary key corresponding to a secondary value including a portion of the primary value in response to an additional request from the host; and A secondary index is generated, where the secondary index includes the secondary key and address information of the target second storage area.

2. The data storage device according to claim 1, wherein: The address information of the target second storage area includes first offset information and first length information, and the first offset information and the first length information indicate the location where the main value is stored in the target second storage area.

3. The data storage device according to claim 1, wherein: When the number of primary indexes generated according to the request from the host reaches a first threshold, the memory controller sorts the generated primary indexes based on primary keys included in the generated primary indexes.

4. The data storage device according to claim 3, wherein: The memory controller controls the memory device to store the sorted primary index in a target first storage area among the plurality of first storage areas.

5. The data storage device according to claim 3, wherein: The memory controller sorts the primary values ​​to correspond to the sorted primary indices.

6. The data storage device according to claim 5, wherein: The memory controller controls the memory device to store the sorted primary values ​​in the target second storage area.

7. The data storage device according to claim 4, wherein: The memory controller generates primary index metadata including address information of the target first storage area.

8. The data storage device according to claim 7, wherein: The primary index metadata includes information of a maximum primary key having a maximum value among primary keys included in the primary index stored in the target first storage area.

9. The data storage device according to claim 1, wherein: The memory controller generates the secondary key by selecting the secondary value among the primary values ​​using second offset information and second length information corresponding to an attach request from the host.

10. The data storage device according to claim 1, wherein: The secondary index includes third offset information and third length information, and the third offset information and the third length information indicate a location where the secondary value is stored in the target second storage area.

11. The data storage device according to claim 1, wherein: When the number of secondary indexes generated according to the additional request from the host reaches a second threshold, the memory controller sorts the generated secondary indexes based on secondary keys included in the generated secondary indexes.

12. The data storage device according to claim 11, wherein: The memory device includes a plurality of third storage areas, and The memory controller controls the memory device to store the sorted secondary indexes in a target third storage area among the plurality of third storage areas.

13. The data storage device according to claim 12, wherein: The memory controller generates secondary index metadata including address information of the target third storage area.

14. The data storage device according to claim 13, wherein: The secondary index metadata includes information of a maximum secondary key having a maximum value among secondary keys included in the secondary index stored in the target third storage area.

15. The data storage device according to claim 14, wherein: The secondary index metadata includes duplicate key information indicating whether a duplicate key secondary index including a secondary key identical to the maximum secondary key exists in a third storage area other than the target third storage area among the plurality of third storage areas.

16. A method of operating a data storage device, the data storage device controlling a memory device including a first storage area and a second storage area, the first storage area storing a primary index corresponding to a primary key, the second storage area storing a primary value corresponding to the primary index, the method comprising: generating a primary index, the primary index including the primary key and address information of a second storage area storing a primary value corresponding to the primary key; generating a secondary key corresponding to a secondary value including a portion of the primary value; as well as A secondary index is generated, where the secondary index includes the secondary key and address information of the second storage area.

17. The method according to claim 16, wherein: The primary index includes first offset information and first length information, and the first offset information and the first length information indicate a location where the primary value is stored in the second storage area.

18. The method according to claim 16, wherein: A portion of the primary value is designated as the secondary value based on second offset information and second length information received from the host.

19. The method according to claim 16, wherein: The secondary index includes third offset information and third length information, and the third offset information and the third length information indicate a location where the secondary value is stored in the second storage area.

20. The method of claim 16, further comprising: storing the secondary index in a third storage area of ​​the memory device; as well as Secondary index metadata is generated, where the secondary index metadata includes address information of the third storage area.

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