Redundant code identification method and device, computer equipment and readable storage medium

Abstract

The invention relates to a redundant code identification method and device, computer equipment and a readable storage medium. The method comprises the following steps: acquiring a compiled initial hardware description language code, compiling the initial hardware description language code, performing code rule check on the compiled initial hardware description language code, performing simulation analysis and code coverage rate analysis on the compiled hardware description language code, and performing simulation analysis and code coverage rate analysis on the compiled hardware description language code. And identifying and marking the uncovered target hardware description language codes, identifying redundant codes in the target hardware description language codes according to the marking information of the target hardware description language codes, and processing the redundant codes. By adopting the method, the redundant codes can be effectively identified and processed, the code quality and the system performance are improved, and the reliability and maintainability of the system are enhanced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a redundant code identification method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] Verilog is a hardware description language that describes the structure and behavior of digital system hardware in text form. It is mainly used in FPGA (Field-Programmable Gate Array) and CPLD (Complex Programmable Logic Device) related programming.

[0003] In the actual code writing process, the code is often developed by multiple people, and the original code needs to be updated and upgraded according to actual needs. This will lead to the problem of invalid redundant code, that is, some code is not used in the specific operation process. The code redundancy problem will increase the compilation and synthesis time, and may also cause some potential errors and vulnerabilities.

[0004] At present, the identification of redundant code problems relies more on manual experience for judgment and analysis, or checking related codes after encountering problems. This method is inefficient and it is easy to miss redundant codes, making it difficult to identify real redundant codes. Summary of the invention

[0005] Based on this, it is necessary to provide a more accurate redundant code identification method, device, computer equipment, computer readable storage medium and computer program product to address the above technical problems.

[0006] In a first aspect, the present application provides a redundant code identification method, comprising:

[0007] Obtaining the written initial hardware description language code, and compiling the initial hardware description language code;

[0008] Performing code rule checking on the compiled initial hardware description language code;

[0009] Perform simulation analysis and code coverage analysis on the compiled hardware description language code, identify and mark the target hardware description language code that is not covered;

[0010] According to the annotation information of the target hardware description language code, redundant codes in the target hardware description language code are identified, and the redundant codes are processed.

[0011] In one embodiment, the identifying redundant code in the target hardware description language code according to the annotation information of the target hardware description language code, and processing the redundant code includes:

[0012] Determining a code level of the target hardware description language code according to the annotation information of the target hardware description language code;

[0013] According to the correspondence between the level and the redundant code, the redundant code in the target hardware description language code is identified and the redundant code is processed.

[0014] In one embodiment, the tagging information of the target hardware description language code includes code function, code location and code importance; and determining the code level of the target hardware description language code according to the tagging information of the target hardware description language code includes:

[0015] The code level of the target hardware description language code is determined according to at least one factor of code function, code location and code importance.

[0016] In one embodiment, the identifying redundant code in the target hardware description language code according to the correspondence between the level and the redundant code and processing the redundant code includes:

[0017] When the code level of the target hardware description language code is the first level, the target hardware description language code is determined to be a redundant code, and the redundant code is deleted.

[0018] In one embodiment, after performing code rule checking on the compiled hardware description language code, the method further comprises:

[0019] In response to the code iteration update message, the initial hardware description language code is updated;

[0020] Comparing the iteratively updated hardware description language code with the initial hardware description language code, screening out the modified or added incremental hardware description language code, and marking the incremental hardware description language code with target annotation information;

[0021] The hardware description language codes in the target hardware description language codes are marked as not having the target marking information.

[0022] In one embodiment, the method further comprises:

[0023] When abnormal hardware description language code that does not comply with the code checking rule is detected, the abnormal hardware description language code is adjusted.

[0024] In a second aspect, the present application also provides a redundant code identification device, comprising:

[0025] A data compiling module, used for acquiring the written initial hardware description language code and compiling the initial hardware description language code;

[0026] A data checking module, used for performing code rule checking on the compiled initial hardware description language code;

[0027] A data analysis and marking module is used to perform simulation analysis and code coverage analysis on the compiled hardware description language code, and identify and mark the target hardware description language code that is not covered;

[0028] The redundant code identification module is used to identify the redundant code in the target hardware description language code according to the annotation information of the target hardware description language code, and process the redundant code.

[0029] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0030] Obtaining the written initial hardware description language code, and compiling the initial hardware description language code;

[0031] Performing code rule checking on the compiled initial hardware description language code;

[0032] Perform simulation analysis and code coverage analysis on the compiled hardware description language code, identify and mark the target hardware description language code that is not covered;

[0033] According to the annotation information of the target hardware description language code, redundant codes in the target hardware description language code are identified, and the redundant codes are processed.

[0034] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0035] Obtaining the written initial hardware description language code, and compiling the initial hardware description language code;

[0036] Performing code rule checking on the compiled initial hardware description language code;

[0037] Perform simulation analysis and code coverage analysis on the compiled hardware description language code, identify and mark the target hardware description language code that is not covered;

[0038] According to the annotation information of the target hardware description language code, redundant codes in the target hardware description language code are identified, and the redundant codes are processed.

[0039] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0040] Obtaining the written initial hardware description language code, and compiling the initial hardware description language code;

[0041] Performing code rule checking on the compiled initial hardware description language code;

[0042] Perform simulation analysis and code coverage analysis on the compiled hardware description language code, identify and mark the target hardware description language code that is not covered;

[0043] According to the annotation information of the target hardware description language code, redundant codes in the target hardware description language code are identified, and the redundant codes are processed.

[0044] The redundant code identification method, device, computer equipment, computer-readable storage medium and computer program product can obtain and compile the initial hardware description language code, and then quickly find the code segments that do not comply with the code checking rules by performing code rule checking on the compiled initial hardware description language code, thereby improving the standardization of the code. By performing simulation analysis on the code, the function and performance of the code can be verified, so that the performance of the code in actual operation meets expectations. By performing code coverage analysis on the code, the code segments that are not covered by the test are identified and marked, and possible redundant code or potential problem areas can be discovered in time. Finally, by processing redundant code, the code quality and system performance can be improved, potential errors can be reduced, and the maintainability of the system can be improved. The entire solution can effectively identify and process redundant code, improve code quality and system performance, and enhance the reliability and maintainability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0046] FIG1 is an application environment diagram of a redundant code identification method according to an embodiment;

[0047] Figure 2A schematic diagram of a flow chart of a redundant code identification method in one embodiment;

[0048] Figure 3 A schematic flow chart of a redundant code identification method in another embodiment;

[0049] Figure 4 A schematic diagram of a flow chart of a redundant code identification method in another embodiment;

[0050] Figure 5 A schematic diagram of a flow chart of a redundant code identification method in yet another embodiment;

[0051] Figure 6 A detailed flowchart of a redundant code identification method in one embodiment;

[0052] Figure 7 is a structural block diagram of a redundant code identification device in one embodiment;

[0053] Figure 8 It is a structural block diagram of a redundant code identification device in another embodiment;

[0054] FIG. 9 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0056] The redundant code identification method provided in the embodiment of the present application can be applied in the application environment shown in FIG1. ​​In which, the terminal 102 communicates with the server 104 through the network. The data storage system can store the data that the server 104 needs to process. The data storage system can be integrated on the server 104, or it can be placed on the cloud or other network servers.

[0057] Specifically, the user may submit the written hardware description language code to the server 104 through the terminal 102. After receiving the written hardware description language code, the server 104 compiles the initial hardware description language code, performs a code rule check on the compiled initial hardware description language code, and then performs simulation analysis and code coverage analysis on the compiled hardware description language code to identify and mark the target hardware description language code that is not covered. Finally, based on the annotation information of the target hardware description language code, the server 104 identifies the redundant code in the target hardware description language code and processes the redundant code.

[0058] The terminal 102 may be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, IoT devices, and portable wearable devices. The IoT devices may be smart speakers, smart TVs, smart air conditioners, smart car devices, projection devices, etc. Portable wearable devices may be smart watches, smart bracelets, head-mounted devices, etc. Head-mounted devices may be virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc. The server 104 may be an independent physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides cloud computing services.

[0059] In an exemplary embodiment, Figure 2 As shown, a redundant code identification method is provided, and the method is applied to the server 104 in FIG. 1 as an example for explanation, including the following steps S200 to S800. It can be understood that the method can also be applied to a terminal. Among them:

[0060] S200, obtaining the written initial hardware description language code, and compiling the initial hardware description language code.

[0061] In this embodiment, the hardware description language includes but is not limited to Verilog language and VHDL (VHSIC Hardware Description Language, very high speed integrated circuit hardware description language). Compilation refers to the process of converting source code into a form that can be processed by a simulator or synthesis tool. In some embodiments, because the Verilog language is a hardware description language, the hardware description language code will be compiled and synthesized in two steps, that is, compilation can be understood as two actions of compilation and synthesis. Among them, synthesis is a process in which programming software processes code. The compilation process will check for syntax errors, type mismatches and other problems to ensure that the code can be correctly parsed by subsequent tools.

[0062] In actual applications, after obtaining the already written initial hardware description language code (hereinafter referred to as code), the server can compile and synthesize the already written hardware description language code. For example, if the initial hardware description language code is an FPGA design code written in Verilog. After the server obtains the FPGA design code, it can use a Verilog compiler (such as ModelSim, Vivado, etc.) to load this code. The compiler will read the file and check for syntax errors, type mismatches, and other problems. If there is an error, the compiler will output an error message, and the developer can make corresponding modifications based on the location of the error and the cause of the error indicated by the software. The server will then recompile the modified code.

[0063] S400, performing code rule checking on the compiled initial hardware description language code.

[0064] Code rule checking refers to the process of checking whether the code meets the requirements according to certain coding specifications or standards to improve the quality and maintainability of the code. In practical applications, the conditional code rule checking of the code rule checking can be pre-set according to one's own needs and regulations, and then the compiled initial hardware description language is subjected to code rule checking according to the preset code rule checking conditions. For example, it may include but is not limited to checking whether the signal naming is standardized and meets the requirements; checking whether the signal is repeatedly defined and whether there are problems with the structure of the code. It is understandable that in other embodiments, the conditions for code rule checking can also be set according to actual needs and regulations, such as code style checking, naming convention compliance checking, and consistency checking of interface definitions.

[0065] S600, performing simulation analysis and code coverage analysis on the compiled hardware description language code, identifying and marking target hardware description language code that is not covered.

[0066] Simulation analysis is the process of simulating the behavior of hardware circuits in a software environment to verify the correctness of their functions. Code coverage refers to the ratio of the executed part of the tested code to the total executable code part during the test process. This ratio is usually expressed as a percentage. The higher the code coverage, the more comprehensive the coverage of the code by the test case, and the higher the quality of the software in theory. In this embodiment, code coverage analysis may include but is not limited to statement coverage analysis, branch coverage analysis, condition coverage analysis, and path coverage analysis. Among them, statement coverage refers to the ratio of executed statements in the tested code to the total executable statements. Branch coverage analysis refers to analyzing whether each branch of each conditional judgment in the tested code is executed. Condition coverage analysis refers to analyzing whether each sub-expression in each conditional expression is tested to true (True) and false (False).

[0067] In specific implementation, the simulation test file can be determined according to the functional principle and requirements of the code, and then the Questa Sim software is used to simulate and analyze the code, and the simulation coverage analysis is performed on the code. Since Verilog code is a hardware description language and is implemented through hardware, each code will have input and output, and the simulation file is mainly determined according to the different functions of the code. For example, the code mainly processes video data with a resolution of 1920×1080. During simulation, a video input data with a resolution of 1920×1080 is set, and then the results of the code operation are checked. In other words, select the appropriate simulation signal source according to the function of the code and the type of input signal it acts on.

[0068] Run the design through the simulation tool to verify whether its behavior is as expected. Perform code coverage analysis on the code to determine which parts of the code have been fully tested and which parts may have problems or have not been tested. Subsequently, mark the code that is not covered in the code coverage analysis, and determine the marked hardware description language code as the target hardware description language code. Specifically, the uncovered code can be marked with numbers or letters, such as using identification A and identification B for marking.

[0069] For example, you can use tools such as ModelSim or Vivado Simulator to set up a test bench and write test vectors to stimulate the design. After running the simulation, waveforms and log files can be provided to help developers analyze the behavior of the design. At the same time, the code coverage option can be enabled to generate a coverage report to show which modules or paths have not been tested.

[0070] S800, identifying redundant codes in the target hardware description language code according to the annotation information of the target hardware description language code, and processing the redundant codes.

[0071] Redundant code refers to code snippets that do not affect the execution results of the program but exist in the code and consume resources. Specifically, it includes code that is irrelevant to the implementation function or is not executed under the premise that the code is error-free. Since Verilog code is a hardware description language, each part of the code has a practical role. In actual applications, a note is added after each code sentence to note the role of the code. The note information includes but is not limited to the code function, code impact, code location, and code importance.

[0072] Continuing from the previous embodiment, after obtaining the code coverage analysis results and simulation analysis results carrying annotation information, redundant code in the target hardware description language code can be identified according to the annotation information of the target hardware description language code, and the redundant code can be processed. Specifically, the processing of the redundant code can include deleting, adjusting or optimizing the redundant code.

[0073] In the above redundant code identification method, after obtaining and compiling the initial hardware description language code, by performing code rule checking on the compiled initial hardware description language code, code segments that do not comply with the code checking rules can be quickly found, thereby improving the standardization of the code. By performing simulation analysis on the code, the function and performance of the code can be verified, so that the performance of the code in actual operation meets expectations. By performing code coverage analysis on the code, code segments that are not covered by the test are identified and marked, and possible redundant code or potential problem areas can be discovered in a timely manner. Finally, by processing redundant code, code quality and system performance can be improved, potential errors can be reduced, and the maintainability of the system can be improved. The entire solution can effectively identify and process redundant code, improve code quality and system performance, and enhance the reliability and maintainability of the system.

[0074] like Figure 3 As shown, in some exemplary embodiments, the method further includes: S500, when abnormal hardware description language code that does not comply with the code checking rule is detected, adjusting the abnormal hardware description language code.

[0075] Abnormal hardware description language code (hereinafter referred to as abnormal code) refers to code that does not comply with preset code checking rules, including but not limited to code with syntax errors, inconsistent styles, functional errors, performance issues, maintainability and readability issues, etc.

[0076] Since some problems that do not comply with the code rule check will not be reported in the compilation and synthesis, such as irregular signal naming, the same signal being defined multiple times, or not being defined, etc., will not be reported in the compilation and synthesis process. Therefore, the corresponding code check rules can be set to further detect abnormal hardware description language codes.

[0077] During specific implementation, if abnormal hardware description language code that does not comply with the code checking rules is detected, the detected abnormal hardware description language code can be pushed, and the relevant abnormal reasons can be given so that the developer can modify and adjust the abnormal hardware description language code according to the abnormal reasons. In other embodiments, the server can also automatically adjust and optimize the abnormal code according to the preset abnormal code adjustment optimization principles. For example, if it is a problem of inconsistent style, it can be adjusted according to the team's code style guide, such as adding spaces, comments, and indents. After the modification is completed, re-run the simulation and synthesis tools to ensure that the modification does not introduce new errors and meets the expected functional requirements.

[0078] In this embodiment, by adjusting and optimizing abnormal codes that do not comply with code checking rules, problems in the hardware description language code can be effectively solved, and the code quality and consistency can be ensured.

[0079] The identification of redundant codes can be determined based on the level of the code. Figure 4 As shown, in some exemplary embodiments, S800 includes:

[0080] S820: Determine the code level of the target hardware description language code according to the annotation information of the target hardware description language code.

[0081] S840, identifying redundant codes in the target hardware description language code according to the correspondence between the level and the redundant codes, and processing the redundant codes.

[0082] In practical applications, the code level can be divided into several levels in advance according to factors such as the importance of the code and the functions implemented, and it can be determined which levels of code are redundant code, and the corresponding relationship between redundant code and code can be established.

[0083] In this embodiment, the uncovered codes can be divided into three levels: I, II, and III according to functions, impacts, simulation test methods, etc. Among them, the I level code is redundant code. Specifically:

[0084] Level I code is non-impact code. The main source of this part of code is some experimental code added during iteration, upgrade and update. It is mainly the code added to meet the requirements during the debugging process, and the part of code that is constantly tested and changed in the process of gradually meeting the requirements. After analysis, it is confirmed that the part of code that has no impact on the entire program function is the redundant code added during the function realization test.

[0085] Level II code is due to the simulation test method, that is, due to the incomplete coverage of the input source simulation, which leads to the partial coverage of the code. This part of the uncovered code is Level II code. Specifically, after the code is iteratively upgraded, in order to achieve new requirements, the original code needs to be optimized. The reasons for adding the optimized part of the code are analyzed, and then whether it is Level II code is confirmed based on whether it involves the processing of the input source signal and whether it involves new functions.

[0086] Level III code refers to the code that is not covered due to the limitation of simulation methods, such as some codes with protection functions, such as the default state processing code in the CASE statement. Since the simulation is an ideal state, there will be inconsistencies between the simulation state and the actual state, such as no sudden changes in signals in the simulation, no discontinuous changes in signals, etc. Some codes are used to protect the correct processing of data, and some sudden situations will not occur in the simulation process like in actual applications, so this part of the code will not be covered in the simulation.

[0087] In specific implementation, the target hardware description language code can be divided into codes of corresponding levels according to the above-mentioned code division principles, and corresponding level marking information can be added to each code fragment. Subsequently, the level of the code can be determined according to the level marking information, and then redundant code can be filtered out and further processed.

[0088] In this embodiment, by pre-building the correspondence between redundant codes and code levels and combining the code annotation information, the code levels can be accurately divided and the redundant codes can be identified.

[0089] like Figure 5 As shown, in some exemplary embodiments, the annotation information of the target hardware description language code includes code function, code location and code importance; S820, including:

[0090] S822, determining a code level of the target hardware description language code according to at least one factor of code function, code location, and code importance.

[0091] In this embodiment, the annotation information of the code mainly includes three parts: the implemented function (corresponding requirement) + the position of the code in the function + the importance of the code.

[0092] In specific implementation, the codes may be first classified into levels according to at least one factor of the overall function of the code, the position of the code in the function, and the importance of the code.

[0093] For example, this embodiment determines the code level based on three dimensions: the overall function of the code, the position of the code in the function, and the importance of the code. For example, a program for processing video data can be divided into the following according to its function:

[0094] ① Receive data

[0095] ②Data synchronization

[0096] ③Preliminary analysis of data (resolution identification)

[0097] ④Data caching

[0098] ⑤Conversion of data bit number

[0099] ⑥Data verification

[0100] ⑦Conversion of the number of bits of data

[0101] ⑧ Pack the data (add data packet header and data packet tail)

[0102] ⑨Send data

[0103] First, according to the above functions, the words A001 to A009 can be added in front of the mark, A001 represents function ①, and all codes related to the implementation of function ① are annotated with the mark A001.

[0104] Then, the second segment is marked according to the step of the code in the function (i.e. the position in the function). For example, if the line of code is in the second step of data synchronization, it is marked as A001_B002. If the line of code is very important in this step and is a key code. It is irreplaceable, it is marked as A001_B002_3. Among them, "3" represents the importance level of the code.

[0105] Finally, the server can determine the code level based on the importance mark after the uncovered code sentence. If the importance is level 1, it is determined to be level I code. If the importance is level 2, find the codes with the same first two marks and determine all the codes with the same marks to be level II codes. The codes are processed together. If the importance is 3, it is determined to be level III code.

[0106] In this embodiment, the code level of the target hardware description language can be accurately and efficiently determined through code function, code location and code importance.

[0107] like Figure 5 As shown, in some exemplary embodiments, S840 includes: S842, when the code level of the target hardware description language code is the first level, determining that the target hardware description language code is redundant code, and deleting the redundant code.

[0108] In this embodiment, the first level is the above-mentioned level I. In specific implementation, if the target hardware description language code is identified as level I code, it is characterized as a non-impact code, which will not affect the entire program function, and may be a redundant code added during the function implementation test. Therefore, if the target hardware description language code is level I code, it is determined that the code is a redundant code and the redundant code is deleted.

[0109] If the target hardware description language code is identified as Level II code, it means that this part of the code may be the newly added code not covered after the code iteration upgrade due to incomplete input source simulation coverage. For this part of Level II code, the input source used for the simulation can be adjusted according to the functional role of the Level II code, so as to achieve coverage of the Level II code.

[0110] For example, the simulation test input is a video data signal with a resolution of 1920×1080, but the uncovered code processes a video data signal with a resolution of 1200×900. The function of this part of the code that I have not covered is to process when the input data does not meet the conditions. This part of the code will not run when the input data is normal, and will only run when there is a problem with the input data. Therefore, the input data needs to be changed to make this part of the code run normally to achieve code coverage.

[0111] If the target hardware description language code is identified as Level III code, it indicates that this part of the code is not covered due to the limitation of the simulation method. In this case, this part of the code can be retained without being processed.

[0112] In this embodiment, by eliminating redundant codes, code quality and system performance can be effectively improved.

[0113] like Figure 6 As shown, in some exemplary embodiments, after S400, the method further includes:

[0114] S900, responding to the code iteration update message, and updating the initial hardware description language code.

[0115] S920, comparing the iteratively updated hardware description language code with the initial hardware description language code, screening out the modified or added incremental hardware description language code, and marking the incremental hardware description language code with target annotation information.

[0116] S940, marking the hardware description language codes that do not have the target marking information in the target hardware description language codes.

[0117] In actual applications, the code often needs to be iteratively upgraded according to new requirements. After updating the upgraded code, it is necessary to determine whether there is redundant code and optimize the relevant redundant code.

[0118] If the developer modifies and adjusts the relevant hardware description language code according to the new requirements, after the modification is completed, the modified latest version of the hardware description language code can be submitted to the server through the terminal, and a code iteration update message can be sent to the server. The server responds to the message and iteratively updates the hardware description language code. Subsequently, the iteratively updated hardware description language code is compared with the initial hardware description language code to filter out the incremental hardware description language code that has been modified or added, and the incremental hardware description language code is marked with the target annotation information (such as using marker A). Subsequently, after detecting the target hardware description language code that is not covered through simulation analysis and code coverage analysis, the target hardware description language code can be marked with marker B.

[0119] Subsequently, the hardware description language code with mark B but not mark A can be filtered out from the target hardware description language code, and then the reasons why it is not covered can be analyzed, such as insufficient test cases or difficult input conditions to simulate, etc. Finally, special marking is performed according to the reasons so that developers can further analyze, determine targeted test strategies, add new test cases or improve existing test cases to improve code coverage.

[0120] In this embodiment, by marking and recording code changes, the evolution of the code can be better managed and tracked. Special marking based on the specific reasons for uncovered code can help team members better understand the importance of these codes and identify areas where testing is insufficient, thereby improving test coverage in a targeted manner.

[0121] In order to make a clearer description of the redundant code identification method provided by the present application, a specific embodiment is described below, and the specific embodiment includes the following steps:

[0122] Step 1, obtaining the written hardware description language code and compiling the initial hardware description language code.

[0123] Step 2: Perform code rule checking on the compiled initial hardware description language code.

[0124] Step 3: When abnormal hardware description language code that does not comply with the code checking rule is detected, the abnormal hardware description language code is adjusted.

[0125] Step 4: Perform simulation analysis and code coverage analysis on the compiled hardware description language code to identify and mark target hardware description language codes that are not covered.

[0126] Step 5: Determine the code level of the target hardware description language code based on at least one factor of the code function, the code location, and the code importance.

[0127] Step 6: When the code level of the target hardware description language code is the first level, determine that the target hardware description language code is a redundant code, and delete the redundant code.

[0128] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0129] Based on the same inventive concept, the embodiment of the present application also provides a redundant code identification device for implementing the redundant code identification method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more redundant code identification device embodiments provided below can refer to the limitations of the redundant code identification method above, and will not be repeated here.

[0130] In an exemplary embodiment, Figure 7 As shown, a redundant code identification device 700 is provided, comprising: a data compilation module 710, a data checking module 720, a data analysis marking module 730 and a redundant code identification module 740, wherein:

[0131] The data compiling module 710 is used to obtain the written initial hardware description language code and compile the initial hardware description language code.

[0132] The data checking module 720 is used to perform code rule checking on the compiled initial hardware description language code.

[0133] The data analysis and marking module 730 is used to perform simulation analysis and code coverage analysis on the compiled hardware description language code, and identify and mark the target hardware description language code that is not covered.

[0134] The redundant code identification module 740 is used to identify the redundant code in the target hardware description language code according to the annotation information of the target hardware description language code, and process the redundant code.

[0135] After the redundant code identification device obtains and compiles the initial hardware description language code, it can quickly find the code segments that do not comply with the code checking rules by performing code rule checking on the compiled initial hardware description language code, thereby improving the standardization of the code. By performing simulation analysis on the code, the function and performance of the code can be verified, so that the performance of the code in actual operation meets expectations. By performing code coverage analysis on the code, the code segments that are not covered by the test are identified and marked, and possible redundant code or potential problem areas can be discovered in time. Finally, by processing redundant code, the code quality and system performance can be improved, potential errors can be reduced, and the maintainability of the system can be improved. The entire solution can effectively identify and process redundant code, improve code quality and system performance, and enhance the reliability and maintainability of the system.

[0136] In an exemplary embodiment, the redundant code identification module 740 is also used to determine the code level of the target hardware description language code based on the annotation information of the target hardware description language code, identify the redundant code in the target hardware description language code based on the correspondence between the level and the redundant code, and process the redundant code.

[0137] In one embodiment, the redundant code identification module 740 is further configured to determine the code level of the target hardware description language code according to at least one factor of the code function, the code location, and the code importance.

[0138] In one embodiment, the redundant code identification module 740 is further configured to determine that the target hardware description language code is redundant code and delete the redundant code when the code level of the target hardware description language code is the first level.

[0139] like Figure 8 As shown, in one embodiment, the device also includes a data marking module 750, which is used to respond to the code iteration update message, update the initial hardware description language code, compare the iteratively updated hardware description language code with the initial hardware description language code, screen out the incremental hardware description language code that has been modified or added, mark the incremental hardware description language code with the target marking information, and mark the hardware description language code in the target hardware description language code that does not have the target marking information.

[0140] like Figure 8 As shown, in one embodiment, the device also includes a data adjustment module 722 for

[0141] When abnormal hardware description language code that does not comply with the code checking rule is detected, the abnormal hardware description language code is adjusted.

[0142] Each module in the redundant code identification device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0143] In an exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be shown in FIG9. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. The processor, the memory and the input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data such as hardware description language codes and abnormal causes. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a redundant code identification method is implemented.

[0144] Those skilled in the art will understand that the structure shown in FIG. 9 is merely a block diagram of a partial structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different arrangement of components.

[0145] In an exemplary embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the steps in any one of the above redundant code identification method embodiments are implemented.

[0146] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in any one of the above redundant code identification method embodiments are implemented.

[0147] In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements the steps in any one of the above redundant code identification method embodiments.

[0148] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0149] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0150] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0151] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A redundant code identification method, characterized in that: The method comprises: Obtaining the written initial hardware description language code, and compiling the initial hardware description language code; Performing code rule checking on the compiled initial hardware description language code; Perform simulation analysis and code coverage analysis on the compiled hardware description language code, identify and mark the target hardware description language code that is not covered; According to the annotation information of the target hardware description language code, redundant codes in the target hardware description language code are identified, and the redundant codes are processed.

2. The method according to claim 1, characterized in that The identifying redundant code in the target hardware description language code according to the annotation information of the target hardware description language code and processing the redundant code comprises: Determining a code level of the target hardware description language code according to the annotation information of the target hardware description language code; According to the correspondence between the level and the redundant code, the redundant code in the target hardware description language code is identified and the redundant code is processed.

3. The method according to claim 2, characterized in that The tagging information of the target hardware description language code includes code function, code location and code importance; and the code level of the target hardware description language code is determined according to the tagging information of the target hardware description language code, including: The code level of the target hardware description language code is determined according to at least one factor of code function, code location and code importance.

4. The method according to claim 2 or 3, characterized in that: The step of identifying redundant codes in the target hardware description language code according to the correspondence between the level and the redundant codes and processing the redundant codes comprises: When the code level of the target hardware description language code is the first level, the target hardware description language code is determined to be a redundant code, and the redundant code is deleted.

5. The method according to claim 4, characterized in that After performing code rule checking on the compiled hardware description language code, the method further includes: In response to the code iteration update message, the initial hardware description language code is updated; Comparing the iteratively updated hardware description language code with the initial hardware description language code, screening out the modified or added incremental hardware description language code, and marking the incremental hardware description language code with target annotation information; The hardware description language codes in the target hardware description language codes are marked as not having the target marking information.

6. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: When abnormal hardware description language code that does not comply with the code checking rule is detected, the abnormal hardware description language code is adjusted.

7. A redundant code identification device, characterized in that: The device comprises: A data compiling module, used for acquiring the written initial hardware description language code and compiling the initial hardware description language code; A data checking module, used for performing code rule checking on the compiled initial hardware description language code; A data analysis and marking module is used to perform simulation analysis and code coverage analysis on the compiled hardware description language code, and identify and mark the target hardware description language code that is not covered; The redundant code identification module is used to identify the redundant code in the target hardware description language code according to the annotation information of the target hardware description language code, and process the redundant code.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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