Cooperative computing method, system and equipment based on SIMD and SIMT

Abstract

The invention provides a collaborative computing method, system and device based on SIMD and SIMT, and belongs to the technical field of computer processing. The method is applied to a Warp composed of a plurality of SPs, and the Warp comprises an SIMT front end and an SIMD rear end. Each SP corresponds to a vector register combined by a plurality of short registers; generating instruction fetching indication information under the condition that a thread bundle scheduler at the front end of the SIMT determines that a first thread bundle corresponding to the calculation task is in an activated state; obtaining a first cache instruction corresponding to the first thread bundle through an instruction fetching unit, and sending the first cache instruction to a decoding unit at the front end of the SIMT for analysis; obtaining one or more corresponding required operands through an operand collection unit at the rear end of the SIMD; and distributing the required operands to the corresponding calculation management units through the SIMD rear end to execute the corresponding calculation tasks, and writing the calculation results corresponding to the calculation tasks back to the storage unit through the write-back unit.

Description

Technical Field

[0001] The present application relates to the field of computer processing technology, and in particular to a collaborative computing method, system and device based on single instruction multiple data (SIMD) and single instruction multiple threads (SIMT). Background Art

[0002] In today's computing field, with the explosive growth of data and the emergence of various complex application scenarios, the demand for computing performance is becoming increasingly urgent. At present, central processing units (CPUs) and DSP chips generally use SIMD technology to achieve acceleration. By providing the Intrinsic programming interface, developers can directly operate the underlying registers, which to a certain extent achieves performance improvement and power consumption reduction.

[0003] However, this SIMD-based acceleration method has significant limitations. It only supports writing with SIMD instructions, which makes it incapable of handling large-scale matrix operations that require highly parallel processing and complex computing logic. Large-scale matrix operations often involve parallel processing of massive amounts of data and diverse computing operations, and the limitations of SIMD instructions make it impossible to efficiently meet these complex requirements.

[0004] On the other hand, graphics processing units (GPUs) and ASIC chips use SIMT technology to achieve acceleration and improve program parallelism. However, their single matrix computing units cannot use wide registers to merge similar calculations like SIMD. This results in the inability of SIMT's single computing unit to fully utilize the potential of the hardware in some scenarios that require extremely high computing efficiency, thus affecting the overall computing performance.

[0005] The inventors have discovered that by introducing SIMD technology while utilizing the overall processing power of the SIMT matrix computing unit to fully leverage its advantages in vectorized computing and achieve an organic combination of the two, the processing power of the hardware can be effectively improved, thereby significantly improving the performance and development flexibility of the application.

[0006] Based on this, there is an urgent need for a technical solution that can combine SIMD and SIMT to improve the performance and development flexibility of applications. Summary of the invention

[0007] The embodiments of the present application provide a collaborative computing method, system and device based on SIMD and SIMT for solving the technical problem that the respective limitations of SIMD and SIMT seriously restrict the further improvement of application performance, and also greatly restrict the flexibility of developers in the programming process, making it difficult for them to flexibly select appropriate computing methods according to actual needs.

[0008] On the one hand, an embodiment of the present application provides a collaborative computing method based on SIMD and SIMT, the method is applied to a thread bundle Warp composed of multiple stream processors SP, the Warp includes a SIMT front end and a SIMD back end; each SP corresponds to a vector register composed of multiple short registers; the method includes: When the thread warp scheduler of the SIMT front end determines that the first thread warp corresponding to the computing task is in an activated state, generating instruction fetch indication information; wherein the activation state is determined based on the execution dependent resource of the computing task in the task queue state; In response to the instruction fetch indication information, obtaining a first cache instruction corresponding to the first thread warp through an instruction fetch unit, and sending the first cache instruction to a decoding unit of the SIMT front end for parsing, so as to dispatch the parsed instruction to a SIMD back end; Acquire one or more required operands corresponding to the parsed instruction through the operand collection unit of the SIMD backend; Through the SIMD backend, each of the required operands is distributed to a corresponding calculation management unit to execute the corresponding calculation task, and the calculation result corresponding to the calculation task is written back to the storage unit through a write-back unit.

[0009] In one implementation of the present application, the plurality of short register combinations are obtained based on the bit width of the computing task; specifically including: Determining the corresponding required register length according to the bit width of the computing task; Determine a register combination to be selected in a preset available register set according to the required register length and the current register available state; wherein the preset available register set includes a plurality of 32-bit registers; A selected register combination is determined according to each of the candidate register combinations and a preset register cost function, so as to obtain the vector register according to the selected register combination.

[0010] In one implementation of the present application, determining a selected register combination according to each of the candidate register combinations and a preset register cost function specifically includes: By using a gradient descent algorithm, an optimization operation is performed on the preset register cost function; wherein the preset register cost function at least includes a time delay cost and an energy consumption cost corresponding to a corresponding register combination; When the gradient modulus corresponding to the gradient descent algorithm is less than a preset threshold, the iteration is stopped, and the corresponding candidate register combination is determined to be the selected register combination.

[0011] In one implementation of the present application, the instruction cache unit of the first cache instruction includes vector instructions added using RISC-V; the vector instructions include: configuration setting instructions, vector load and store instructions, vector integer instructions, vector fixed-point instructions, and vector floating-point instructions.

[0012] In one implementation of the present application, the Warp corresponds to 7 CSR registers, including: a vector starting position register, a fixed-point saturation flag register, a fixed-point rounding mode register, a vector control and status register, a vector length register, a vector data type register, and a vector register length register.

[0013] In one implementation of the present application, the method further includes: Before adding vector instructions using RISC-V, a front-end vector operation interface of the front-end instruction is defined in a vector instruction description file of RISC-V by using a tablegen tool; the front-end vector operation interface is at least used for vector addition, vector multiplication and vector loading; The interface header file corresponding to the front-end vector operation interface is stored in a preset tool chain so that the encapsulated vector instructions can be called through the preset tool chain to perform RISC-V vector programming.

[0014] In one implementation of the present application, an Intrinsic interface is provided; the Intrinsic interface is used to utilize hardware register resources for vectorization acceleration when writing device-side code at an upper layer.

[0015] In one implementation of the present application, the method further includes: According to the functional category and operation complexity of the vector instruction and a preset operation code subspace comparison table, the operation code of the corresponding vector instruction is mapped to the operation code space of the RISC-V basic instruction format; wherein the preset operation code subspace comparison table includes the comparison relationship between operation codes of different functional categories and different operation complexities and different subspaces.

[0016] On the other hand, an embodiment of the present application further provides a collaborative computing system based on SIMD and SIMT, the system being applied to a thread bundle Warp composed of multiple stream processors SP, the Warp including a SIMT front end and a SIMD back end; each SP corresponds to a vector register composed of multiple short registers; the system comprising: A generating module, configured to generate instruction fetch indication information when a thread warp scheduler of a SIMT front end determines that a first thread warp corresponding to a computing task is in an activated state; wherein the activation state is determined based on an execution dependent resource of the computing task in a task queue state; an acquisition and sending module, configured to, in response to the instruction fetch indication information, acquire the first cache instruction corresponding to the first thread warp through an instruction fetch unit, and send the first cache instruction to the decoding unit of the SIMT front end for parsing, so as to dispatch the parsed instruction to the SIMD back end; An acquisition module, configured to acquire one or more required operands corresponding to the parsed instruction through an operand collection unit of the SIMD backend; The distribution module is used to distribute each of the required operands to the corresponding calculation management unit through the SIMD back end to execute the corresponding calculation task, and write the calculation result corresponding to the calculation task back to the storage unit through the write-back unit.

[0017] On the other hand, an embodiment of the present application further provides a collaborative computing device based on SIMD and SIMT, the device comprising: At least one processor; and a memory in communication with the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform a collaborative computing method based on SIMD and SIMT as described above.

[0018] Compared with the prior art, the present invention has the following significant effects: (1) Combining SIMD with SIMT, it integrates the advantages of SIMD single-core vector processing capability and SIMT multi-core parallel execution, and can fully utilize SIMT's multi-threaded management and SIMD's data parallel capability to improve computing efficiency and performance. It is especially suitable for tasks with a large amount of parallelism and data-level parallelism, such as graphics processing, scientific computing, and deep learning, and significantly improves application performance. At the same time, each SP is configured with flexibly combinable vector registers, which optimizes register allocation and improves resource utilization.

[0019] (2) This application also adds vector instructions based on RISC-V, updates the compiler and tool chain, and provides an Intrinsic interface to facilitate developers to utilize hardware vectorization capabilities and improve development flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A flowchart of a collaborative computing method based on SIMD and SIMT in an embodiment of the present application; Figure 2 A schematic diagram of a Warp architecture in a collaborative computing method based on SIMD and SIMT in an embodiment of the present application; Figure 3 A schematic diagram of register combination in a collaborative computing method based on SIMD and SIMT in an embodiment of the present application; Figure 4 A schematic diagram of a modification setting flow of adding a vector instruction in a collaborative computing method based on SIMD and SIMT in an embodiment of the present application; Figure 5 Another flowchart of a collaborative computing method based on SIMD and SIMT in an embodiment of the present application; Figure 6 A structural diagram of a SIMD and SIMT-based collaborative computing system in an embodiment of the present application; Figure 7 It is a structural diagram of a collaborative computing device based on SIMD and SIMT in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0022] The embodiments of the present application provide a collaborative computing method, system and device based on SIMD and SIMT, which are used to solve the technical problem that the respective limitations of SIMD and SIMT seriously restrict the further improvement of application performance, and also greatly restrict the flexibility of developers in the programming process, making it difficult for them to flexibly select appropriate computing methods according to actual needs.

[0023] The following describes in detail various embodiments of the present application in conjunction with the accompanying drawings.

[0024] The embodiment of the present application provides a collaborative computing method based on SIMD and SIMT, which is applied to a thread bundle Warp composed of multiple stream processors (SP), and the Warp includes a SIMT front end and a SIMD back end. Each SP corresponds to a vector register composed of multiple short registers. Figure 1 As shown, the method may include steps S101-S104: S101 : When a warp scheduler of a SIMT front end determines that a first warp corresponding to a computing task is in an activated state, instruction fetch indication information is generated.

[0025] The activation state is determined based on the execution dependent resources of the computing task in the task queue state.

[0026] It should be noted that the GPU can be used as the execution subject of the collaborative computing method based on SIMD and SIMT, which is only for exemplary purposes. The execution subject is not limited to the GPU, and this application does not make any specific limitations on this.

[0027] In an embodiment of the present application, when the GPU executes a computing task, the thread warp scheduler of the SIMT front end of a Warp can monitor the status of each thread warp at all times. Among them, the thread warp scheduler maintains a task queue, which stores computing tasks waiting to be executed. When a new computing task is submitted to the task queue, the thread warp scheduler will first check the status of the task queue. If there are unprocessed tasks in the task queue, and the current execution dependent resources (such as a sufficient number of free registers for storing operands) can meet the basic requirements of task execution, the thread warp scheduler will mark the first thread warp related to the task as an activatable state. For example, in a task of parallel computing matrix multiplication, after the task queue receives the matrix multiplication task, the scheduler will evaluate whether there are currently enough idle computing units and memory bandwidth to support the execution of the thread warp. If so, the thread warp responsible for the matrix multiplication calculation is set to an activated state. Subsequently, the thread warp scheduler sends an indication to the instruction fetch unit, and the value fetch unit fetches instructions from the instruction cache according to the instruction fetch indication information.

[0028] The SIMT front end of this application includes three stages: instruction fetch, decoding, and dispatch, and SIMD includes three stages: operand collection, execution, and data writeback. The architecture diagram corresponding to Warp is shown in the figure below. Figure 2As shown, the SIMT front end includes Fetch, Instruction buffer, Decode, Score board, Select, and SIMT Engine; the SIMD back end includes Operand Collector, Register, Special Function Unit (SFU), Arithmetic Logic Unit (ALU), Load Store Unit (LSU); Instruction Cache (I-Cache); Data Cache (D-Cache) The instruction fetcher is responsible for fetching instructions and is the starting point of the entire process. It fetches the instructions to be executed from the memory. The instruction buffer is used to temporarily store the fetched instructions for subsequent processing. The decoding unit decodes the instructions in the instruction buffer to make them executable. The scoreboard is used to record the execution status and resource usage of each instruction to avoid conflicts and ensure the correct execution order. The selection unit selects the next instruction to be executed based on the scoreboard and other information. The SIMT engine is the core of the entire SIMT part and is responsible for managing and executing instructions from multiple threads to achieve parallel computing. The operand collector is used to collect The processor is composed of a set of operands required to execute instructions; registers are used to temporarily store data and intermediate results and are fast-access storage units in the processor; special function units are used to perform some special mathematical operations, such as trigonometric functions and logarithms; arithmetic logic units perform basic arithmetic and logical operations, such as addition, subtraction, AND, OR, etc.; load storage units are responsible for loading and storing data between memory and registers; instruction cache is used to cache already acquired instructions, increase the speed of instruction acquisition, and reduce the number of memory accesses; data cache is used to cache frequently used data, increase the speed of data access, and reduce memory access delays.

[0029] An algorithm calculation process based on the above architecture diagram is as follows: the Fetch module of the SIMT front end takes out the instruction from the I-Cache and sends it to the Decode module for decoding, and sets the flag bits corresponding to the source and destination registers in the Score module, and stores the control information in the I-Buffer. The Select module and the SIMT Engine module detect the control information in the I-Buffer and distribute it to the Operand Collector modules of different channels, and then determine the register file according to the type of instruction and other conditions and perform related register operations. Finally, the SFU, ALU, LSU and other modules are called according to different instructions.

[0030] In another embodiment of the present application, the above-mentioned multiple short register combinations are obtained based on the bit width of the computing task, specifically including: According to the bit width of the computing task, the corresponding required register length is determined. According to the required register length and the current register available state, a candidate register combination in the preset available register set is determined. Among them, the preset available register set includes a number of 32-bit registers. According to each candidate register combination and the preset register cost function, a selected register combination is determined to obtain a vector register according to the selected register combination.

[0031] In layman's terms, for example, for computing tasks that require registers with a length of 256 bits, eight registers with a length of 32 bits are used; for computing tasks that require registers with a length of 128 bits, four registers with a length of 32 bits are used; for computing tasks that require registers with a length of 64 bits, two registers with a length of 32 bits are used; and for registers with a length of 32 bits, one register with a length of 32 bits is used. Figure 3 As shown. In order to effectively select register combinations, this application considers the following factors: The bit width requirement of the computing task, that is, the register length required for each computing task. Performance optimization goals, considering how to combine registers to maximize the throughput and minimize latency of the computing task. The current state of available resources, the number of existing registers in the system and their usage.

[0032] This application defines the following variables Represents the set of all available registers in the system, represents the set of all pending computing tasks, Represents a computing task The required register length, Indicates register The current allocation status of (0 for unallocated, 1 for allocated), Indicates the task Using Registers The preset register cost function is an overall evaluation of time delay and energy consumption, ,in represents the cost of time delay, Represents the cost of energy consumption. These two goals are usually conflicting. For example, in some cases it may be necessary to use longer registers to achieve a reduction in time delay, but using longer registers will increase energy consumption.

[0033] Furthermore, the above-mentioned determining the selected register combination according to each candidate register combination and the preset register cost function specifically includes: The preset register cost function is optimized by the gradient descent algorithm. The preset register cost function includes at least the time delay cost and the energy consumption cost corresponding to the corresponding register combination. When the gradient modulus corresponding to the gradient descent algorithm is less than the preset threshold, the iteration is stopped, and the corresponding candidate register combination is determined as the selected register combination.

[0034] That is to say, this application uses the gradient descent algorithm to optimize the above preset register cost function. The specific steps are as follows: Set the objective function to , select an initial set of register allocation schemes, namely and It has been determined that this set of parameters is used as the initial value and substituted into the calculation of the objective function score , calculate the gradient function When the gradient is small enough, stop the iteration, and a set of local minima are found; otherwise, To iterate: , ,make , Iterate in the opposite direction of the gradient.

[0035] Through the above solution, flexibly combinable vector registers are configured for each SP, and register allocation is optimized through comprehensive consideration of factors and gradient descent algorithm to improve register resource utilization.

[0036] S102, in response to the instruction fetch indication information, obtaining a first cache instruction corresponding to the first thread warp through an instruction fetch unit, and sending the first cache instruction to a decoding unit of a SIMT front end for parsing, so as to dispatch the parsed instruction to a SIMD back end.

[0037] That is to say, after the decoding unit completes decoding of the instruction, it sends the relevant information of the instruction (such as operation code, operand address, etc.) to the dispatch unit. The dispatch unit decides when to dispatch the instruction to the SIMD backend for execution based on the information provided by modules such as the scoreboard.

[0038] The instruction cache unit of the first cache instruction includes vector instructions added by RISC-V. The vector instructions include: configuration setting instructions, vector load and store instructions, vector integer instructions, vector fixed-point instructions, and vector floating-point instructions.

[0039] For example, configuration setting instructions: vsetvli, vsetivli, vsetvl. Vector load and store instructions: vle <eew>.v、vlm.v、vlseg <nf> e <eew>.v、vlsseg <nf> e <eew>.v、vl <nf> re <eew>.v、vse <eew>.v、vsm.v、vsseg <nf> e <eew>.v、vs <nf>rv. Among them, eew indicates the bit width of the register, which can specify multiple values ​​such as 32, 64, 128, 256, 512, etc. .v indicates that it is a vectorized instruction. Vector integer instructions: vadd, vsub, vminu, vmin, vmaxu, vmax, vand, vor, vxor, vadc, vmadc, vsbc, vmseq, vmsne, vmsleu, vmsle, vmsgtu, vmsgt, vdivu, vdiv, vremu, vrem, vsll, vmul, vsrl, vsra, vmadd, vnmsub, vmacc, vnmsac, vwaddu, vwadd, vwsubu, vwsub, vwaddu.w, vwadd.w, vwsubu.w, vwsub.w, vwmulu, vwmul. Vector fixed-point instructions: vaaddu, vaadd, vasubu, vasub, vsaddu, vsadd, vssubu, vssub, vsmulu, vssrl, vssra. Vector floating-point instructions: vfadd, vfsub, vfmin, vfmax, vfcvt, vfwcvt, vfncvt, vfsqrt, vmfeq, vmfle, vmflt, vmfne, vmfgt, vmfge, vfdiv, vfmadd, vfnmadd, vfmsub, vfmacc, vfnmacc, vfwadd, vfwsub, vfwadd.w, vfwsub.w, vfwmul.

[0040] That is to say, when supporting collaborative computing combining SIMD and SIMT, the present application may involve new instructions in the instruction set in advance, including instruction encoding, opcodes, register usage, operands, and execution effects. RISC-V is specifically used to implement the addition of vector instructions. Warp corresponds to 7 CSR registers, including: vector starting position register, fixed-point saturation flag register, fixed-point rounding mode register, vector control and status register, vector length register, vector data type register, and vector register length register. They are vstart, vxsat, vxrm, vscr, vl, vtype, and vlenb respectively. vstart is the vector starting position, vxsat is the fixed-point saturation flag, vxm is the fixed-point rounding mode, vscr is the vector control and status register, vl is the vector length, vtype is the vector data type register, and vlenb is the byte length of the vector register.

[0041] Among them, vl and vtype are the registers most involved by users. vl is used to calculate the instruction vector length through vset(i)vl(i). vtype contains several fields, vill, vma, vta, vlmul, and vsew, to represent the element attributes in each instruction. Vill is an illegal identifier. If the value is 1, the other fields are invalid; vma is a mask bit; the vmul segment represents the vector register grouping, which can be a fraction or an integer. The integer n represents n registers as a group for calculation, and the fraction 1 / n represents 1 register split into n registers for calculation; vsew represents the element width.

[0042] When adding vector instructions, this application includes modifications to the hardware and software parts, such as Figure 4 As shown, it includes the hardware part: determining the hardware operation type, customizing instructions, modifying Verilog, modifying macro definitions, modifying decoding modules, modifying hardware logic, adjusting data and control links, and instruction simulation; the software part: customizing instructions, opcode definitions, compiler and tool chain modifications, Intrinsic interfaces, and testing.

[0043] Specifically, start: the starting point of the process. Determine the type of hardware operation: First, it is necessary to clarify the type of operation that the hardware needs to perform, which is the basis and basis for subsequent work. Custom instructions: According to the determined type of hardware operation, design custom instructions to meet specific computing needs. Modify Verilog: Verilog is a hardware description language, which needs to be modified here to realize the function of custom instructions in hardware. Adjust data and control links: Adjust the data transmission path and control signal transmission path in the hardware to ensure that the custom instructions can correctly process data and control the operation of the hardware. Instruction simulation: Simulate the custom instructions to verify whether their functions and performance in the hardware meet expectations. Modify macro definitions, decoder module modifications, and hardware logic modifications: These steps are to modify and optimize some underlying definitions, modules, and logics during the hardware design process to support the implementation of custom instructions and overall hardware functions. Software part; custom instructions: Corresponding to the custom instructions in the hardware part, the software part also needs to define these instructions so that the software can work with the hardware. Operation code definition: Define operation codes for custom instructions. Operation codes are an important part of the computer instruction system, which are used to identify the operation type and function of instructions. Compiler and toolchain modifications: Due to the introduction of custom instructions, the compiler and related toolchains need to be modified so that they can recognize and process these new instructions and correctly compile programs written in high-level languages ​​into code that can run on hardware. Intrinsic interface: The Intrinsic interface is a programming interface used to directly call the functions of the underlying hardware in a high-level language. Corresponding settings and modifications need to be made here so that the software can efficiently utilize the custom instructions of the hardware through the Intrinsic interface. Testing: Test the software part to ensure that the software can interact with the hardware correctly and that the custom instructions can work properly at the software level to achieve the expected performance and functional requirements. End: The end point of the entire process, indicating that the development or improvement work of the hardware and software parts is completed.

[0044] The above solution realizes the development and optimization of a computing system or chip with a custom instruction function.

[0045] In addition, before using RISC-V to add vector instructions, the present application defines the front-end vector operation interface of the front-end instruction in the vector instruction description file of RISC-V through the tablegen tool. The front-end vector operation interface is at least used for vector addition, vector multiplication and vector loading. The interface header file corresponding to the front-end vector operation interface is stored in the preset tool chain, so that the encapsulated vector instruction can be called through the preset tool chain to perform RISC-V vector programming.

[0046] The front-end interface is generated using tablegen. The front-end instructions are defined in riscv_vector.td to generate the builtin interface. The interface header file will be stored in the tool chain's lib / clang / 12.0.1 / include / riscv_vector.h. This file contains all the front-end builtin interfaces of RISC-VVector. Using LLVM compilation optimization, the potential vectorized code in the code can be optimized, and the optimized instruction set can be used for performance acceleration.

[0047] This approach allows compilers and toolchains to be updated to recognize and generate code containing the new instructions.

[0048] In addition, with compiler optimization, on the one hand, the upper layer cannot be optimized in the acceleration method expected by the program developer, and the flexibility and versatility are poor. On the other hand, since the compiler cannot accelerate in every case, the performance improvement brought by optimization is limited, and there are many limitations on application-related optimization. Therefore, this application also provides an Intrinsic interface; the Intrinsic interface is used to use hardware register resources for vectorized acceleration when writing device-side code in the upper layer.

[0049] In another embodiment of the present application, in order to better improve the execution efficiency of vector instructions, the present application also provides the following embodiments: According to the functional category and operation complexity of the vector instruction and the preset opcode subspace comparison table, the opcode of the corresponding vector instruction is mapped to the opcode space of the RISC-V basic instruction format. Among them, the preset opcode subspace comparison table includes the comparison relationship between opcodes of different functional categories and different operation complexities and different subspaces.

[0050] For example, for vector configuration instructions (such as vsetvli, etc.), the opcode is mapped to a specific high-order opcode subspace, where the lower bits of the opcode further refine the opcode information according to different vector configuration parameters, which not only ensures the uniqueness of the opcode, but also realizes the logical grouping of functions. For vector arithmetic instructions (such as vadd, vsub, etc.), the opcode is mapped to another subspace, and the lower bits of the opcode are used to distinguish different arithmetic operations and data types. The above technical solution improves the scalability of instructions. When new vector instructions need to be added, it is only necessary to expand the opcode in the corresponding function category subspace without readjusting the entire opcode layout, which reduces the hardware and software modification costs when the instruction set is expanded and improves the maintainability of the instruction set.

[0051] S103, obtaining one or more required operands corresponding to the parsed instruction through the operand collection unit of the SIMD backend.

[0052] When the instruction is ready to be executed (for example, the operands are ready), the dispatch unit notifies the operand collection unit to start collecting the operands required for the instruction. For example, after an addition instruction is dispatched, the operand collection unit obtains two operands from the register file / RAM and uses them for the addition operation.

[0053] S104, distribute each required operand to a corresponding computing management unit through the SIMD backend to execute the corresponding computing task, and write the computing result corresponding to the computing task back to the storage unit through the write-back unit.

[0054] After the operand collection unit collects the required operands, it sends them to the cross data distribution module, which then distributes the operands to the integer computing unit, FPU computing unit, etc. for parallel computing and execution of computing tasks. The write-back unit is responsible for storing the results to the specified location for use by subsequent instructions.

[0055] This application combines the SIMD instructions of CPU and other chips with the SIMT working methods of GPU, making full use of the vectorization processing capabilities of SIMD in single-core processing and the advantages of multi-core parallel execution of SIMT, which can greatly improve the performance of the application. Based on RISC-V, vector instructions are added to support the compiler to analyze and optimize the potential code, and the Intrinsic interface method is provided for developers to flexibly apply hardware vectorization processing capabilities to accelerate application performance.

[0056] Figure 5 Another flowchart of a collaborative computing method based on SIMD and SIMT provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, it includes the instruction fetch stage, decoding stage, and dispatch stage executed by the SIMT front end; and the operand collection stage, execution stage, and write-back stage executed by the SIMD back end.

[0057] Take the calculation task of performing a vector addition as an example: Instruction fetch stage: Instruction cache: Assume that the vector addition instruction to be executed is already stored in the instruction cache. Thread warp scheduler: Since this is a simple computational task, there may be only one thread warp (e.g. W0) in the active state, and the corresponding program counter PC0 points to the location of the vector addition instruction in the instruction cache. Instruction fetch unit: According to the instructions of the thread warp scheduler, fetch the vector addition instruction from the instruction cache.

[0058] Decoding stage: Decoding unit: decodes the fetched vector addition instruction to determine that it is an operation involving the addition of two vectors, as well as information such as the address of the operands; instruction buffer: the decoded instructions are temporarily stored in the instruction buffer. Scoreboard: records the relevant information of the instruction, such as it needs to read the operands of two vectors and is currently waiting for the operands. Dispatch unit: since the scoreboard shows that the instruction is not ready to execute (missing operands), it is not dispatched for the time being.

[0059] Operand collection stage: Register file / RAM: Assume that the two vectors to be added are already stored in the register file or RAM. Polling arbitration RR: When the dispatch unit of the SIMT front end is ready to dispatch instructions, multiple operand requests that may be made simultaneously (including other possible instructions) are determined by polling arbitration RR to decide who accesses the register file / RAM first. Operand collection unit: Assuming that after polling arbitration, the vector addition instruction obtains access rights, the operand collection unit collects the corresponding elements of the two vectors from the register file / RAM as operands.

[0060] Execution phase: Cross data distribution: distribute the collected operands of the two vectors to the integer calculation unit (assuming that the vector elements are integers). Integer calculation unit: perform addition operations on the corresponding elements of the two vectors, for example, add the first element of the first vector to the first element of the second vector, and so on, to achieve parallel calculations. Branch management unit: In this simple vector addition task, branch operations may not be required, so the branch management unit does not play a role for the time being.

[0061] Write-back stage: Write-back unit: writes the result calculated by the integer calculation unit, that is, the new vector after adding the two vectors, back to the register file / RAM to update the data.

[0062] The above-mentioned simple vector addition calculation task is completed through instruction acquisition, decoding and scheduling of SIMT front-end and efficient data parallel processing of SIMD back-end. In actual applications, there may be more complex instructions and more thread bundles working at the same time. This architecture can make full use of SIMT's multi-thread management and SIMD's data parallel capabilities to improve computing efficiency and performance, especially for tasks with large amounts of parallelism and data-level parallelism, such as graphics processing, scientific computing, and deep learning.

[0063] Through the above solution, SIMD and SIMT are combined, integrating the advantages of SIMD single-core vector processing capabilities and SIMT multi-core parallel execution, and can fully utilize SIMT's multi-threaded management and SIMD's data parallel capabilities to improve computing efficiency and performance. It is especially suitable for tasks with a large amount of parallelism and data-level parallelism such as graphics processing, scientific computing, and deep learning, which significantly improves application performance. At the same time, each SP is configured with flexibly combined vector registers, which optimizes register allocation and improves resource utilization.

[0064] In addition, this application also adds vector instructions based on RISC-V, updates the compiler and tool chain, and provides an Intrinsic interface to facilitate developers to take advantage of hardware vectorization capabilities and improve development flexibility.

[0065] Figure 6 A structural diagram of a SIMD and SIMT-based collaborative computing system provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the system is applied to a thread bundle Warp composed of multiple stream processors SP, and the Warp includes a SIMT front end and a SIMD back end. Each SP corresponds to a vector register composed of multiple short registers. The collaborative computing system 600 based on SIMD and SIMT includes: The generation module 601 is used to generate instruction fetch indication information when the thread warp scheduler of the SIMT front end determines that the first thread warp corresponding to the computing task is in an activated state. The activation state is determined based on the execution dependent resources of the computing task in the task queue state. The acquisition and sending module 602 is used to obtain the first cache instruction corresponding to the first thread warp through the instruction fetch unit in response to the instruction fetch indication information, and send it to the decoding unit of the SIMT front end for parsing, so as to dispatch the parsed instruction to the SIMD back end. The acquisition module 603 is used to obtain one or more required operands corresponding to the parsed instruction through the operand collection unit of the SIMD back end. The distribution module 604 is used to distribute each required operand to the corresponding computing management unit through the SIMD back end to execute the corresponding computing task, and write the calculation result corresponding to the computing task back to the storage unit through the write-back unit.

[0066] Figure 7 A structural diagram of a SIMD and SIMT-based collaborative computing device provided in an embodiment of the present application, such as Figure 7 As shown, the device includes: At least one processor; and a memory in communication with the at least one processor. The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute: When the thread warp scheduler of the SIMT front end determines that the first thread warp corresponding to the computing task is in an activated state, instruction fetch indication information is generated. The activation state is determined based on the execution dependent resources of the computing task in the task queue state. In response to the instruction fetch indication information, the first cache instruction corresponding to the first thread warp is obtained by the instruction fetch unit, and sent to the decoding unit of the SIMT front end for parsing, so as to dispatch the parsed instruction to the SIMD back end. One or more required operands corresponding to the parsed instruction are obtained by the operand collection unit of the SIMD back end. Each required operand is distributed to the corresponding computing management unit through the SIMD back end to execute the corresponding computing task, and the calculation result corresponding to the computing task is written back to the storage unit through the write back unit.

[0067] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system and device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0068] The system and equipment provided in the embodiments of the present application correspond one-to-one to the method. Therefore, the system and equipment also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the system and equipment will not be repeated here.

[0069] It should also be noted that the term "includes", "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the existence of other identical elements in the process, method, commodity or device including the element.

[0070] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.< / nf> < / eew> < / nf> < / eew> < / eew> < / nf> < / eew> < / nf> < / eew> < / nf> < / eew>

Claims

1. A collaborative computing method based on SIMD and SIMT, characterized in that: The method is applied to a thread bundle Warp composed of multiple stream processors SP, the Warp includes a SIMT front end and a SIMD back end; each SP corresponds to a vector register composed of multiple short registers; the method includes: When the thread warp scheduler of the SIMT front end determines that the first thread warp corresponding to the computing task is in an activated state, generating instruction fetch indication information; wherein the activation state is determined based on the execution dependent resource of the computing task in the task queue state; In response to the instruction fetch indication information, obtaining a first cache instruction corresponding to the first thread warp through an instruction fetch unit, and sending the first cache instruction to a decoding unit of the SIMT front end for parsing, so as to dispatch the parsed instruction to a SIMD back end; Acquire one or more required operands corresponding to the parsed instruction through the operand collection unit of the SIMD backend; Through the SIMD backend, each of the required operands is distributed to a corresponding calculation management unit to execute the corresponding calculation task, and the calculation result corresponding to the calculation task is written back to the storage unit through a write-back unit.

2. The collaborative computing method based on SIMD and SIMT according to claim 1, characterized in that: The multiple short register combinations are obtained based on the bit width of the computing task; specifically including: Determining the corresponding required register length according to the bit width of the computing task; Determine a register combination to be selected in a preset available register set according to the required register length and the current register available state; wherein the preset available register set includes a plurality of 32-bit registers; A selected register combination is determined according to each of the candidate register combinations and a preset register cost function, so as to obtain the vector register according to the selected register combination.

3. The collaborative computing method based on SIMD and SIMT according to claim 2, characterized in that: Determining a selected register combination according to each of the candidate register combinations and the preset register cost function specifically includes: By using a gradient descent algorithm, an optimization operation is performed on the preset register cost function; wherein the preset register cost function at least includes a time delay cost and an energy consumption cost corresponding to a corresponding register combination; When the gradient modulus corresponding to the gradient descent algorithm is less than a preset threshold, the iteration is stopped, and the corresponding candidate register combination is determined to be the selected register combination.

4. The collaborative computing method based on SIMD and SIMT according to claim 1, characterized in that: The instruction cache unit of the first cache instruction includes vector instructions added using RISC-V; the vector instructions include: configuration setting instructions, vector load and store instructions, vector integer instructions, vector fixed-point instructions, and vector floating-point instructions.

5. The collaborative computing method based on SIMD and SIMT according to claim 4, characterized in that: The Warp corresponds to 7 CSR registers, including: vector starting position register, fixed-point saturation flag register, fixed-point rounding mode register, vector control and status register, vector length register, vector data type register, and vector register length register.

6. The collaborative computing method based on SIMD and SIMT according to claim 4, characterized in that: The method further comprises: Before adding vector instructions using RISC-V, a front-end vector operation interface of the front-end instruction is defined in a vector instruction description file of RISC-V by using a tablegen tool; the front-end vector operation interface is at least used for vector addition, vector multiplication and vector loading; The interface header file corresponding to the front-end vector operation interface is stored in a preset tool chain so that the encapsulated vector instructions can be called through the preset tool chain to perform RISC-V vector programming.

7. The collaborative computing method based on SIMD and SIMT according to claim 1, characterized in that: An Intrinsic interface is provided; the Intrinsic interface is used to utilize hardware register resources for vectorization acceleration when writing device-side code at an upper layer.

8. The collaborative computing method based on SIMD and SIMT according to claim 4, characterized in that: The method further comprises: According to the functional category and operation complexity of the vector instruction and a preset operation code subspace comparison table, the operation code of the corresponding vector instruction is mapped to the operation code space of the RISC-V basic instruction format; wherein the preset operation code subspace comparison table includes the comparison relationship between operation codes of different functional categories and different operation complexities and different subspaces.

9. A collaborative computing system based on SIMD and SIMT, characterized in that: The system is applied to a thread bundle Warp composed of multiple stream processors SP, the Warp includes a SIMT front end and a SIMD back end; each SP corresponds to a vector register composed of multiple short registers; the system includes: A generating module, configured to generate instruction fetch indication information when a thread warp scheduler of a SIMT front end determines that a first thread warp corresponding to a computing task is in an activated state; wherein the activation state is determined based on an execution dependent resource of the computing task in a task queue state; an acquisition and sending module, configured to, in response to the instruction fetch indication information, acquire the first cache instruction corresponding to the first thread warp through an instruction fetch unit, and send the first cache instruction to the decoding unit of the SIMT front end for parsing, so as to dispatch the parsed instruction to the SIMD back end; An acquisition module, configured to acquire one or more required operands corresponding to the parsed instruction through an operand collection unit of the SIMD backend; The distribution module is used to distribute each of the required operands to the corresponding calculation management unit through the SIMD back end to execute the corresponding calculation task, and write the calculation result corresponding to the calculation task back to the storage unit through the write-back unit.

10. A collaborative computing device based on SIMD and SIMT, characterized in that: The device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute a collaborative computing method based on SIMD and SIMT as described in any one of claims 1 to 8.

Images