Control Circuit, Hard Disk Boot Circuit, Electronic Device, and Peak-Shifting Boot Control Method

Abstract

The present invention provides a control circuit, a hard disk startup circuit, an electronic device, and a peak-shifting startup control method, which are applied to the technical field of hard disk peak-shifting power-on. The control circuit includes: a backplane execution circuit and a backplane control circuit; the backplane execution circuit is connected to the backplane control circuit and is used to control the backplane control circuit to power on and work; the backplane control circuit includes at least two groups of signal transmission ends, which are respectively connected to the corresponding hard disks, and a startup signal is sent to the corresponding hard disk through any one group of signal transmission ends. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk has started up, a startup signal is sent to the corresponding hard disk through any one of the remaining signal transmission ends until all the hard disks have completed the startup process. It can be seen that in the process of controlling the hard disk to power on and start up, the present invention first sends a startup signal to any one hard disk, and after the hard disk has started up, a startup signal is sent to any one of the remaining hard disks, which reduces the design cost of the peak-shifting circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of hard disk power-on staggering, and particularly to a control circuit, a hard disk startup circuit, an electronic device, and a power-on staggering startup control method. Background Art

[0002] With the development of big data technology, electronic devices (such as storage servers) have developed rapidly and their performance has become higher and higher. As the main configuration of storage-type models, the performance of hard disks is particularly important, and the reliability of hard disk power supply is the basic condition for the normal operation of hard disks. In storage servers, to prevent a large inrush current during the startup process of hard disks, it is usually required that multiple hard disks in the storage server start up in a staggered manner.

[0003] In recent years, in order to achieve staggered startup of multiple hard disks in a storage server, a startup circuit is separately configured for each hard disk on the hard disk backplane, which greatly increases the cost of the storage server.

[0004] It can be seen that how to achieve staggered startup of hard disks by using a low-cost design method is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a control circuit, a hard disk startup circuit, an electronic device, and a power-on staggering startup control method, which can solve the cost problem caused by configuring a startup circuit for each hard disk in the prior art to achieve staggered startup of hard disks.

[0006] To solve the above technical problems, on the one hand, the embodiments of the present invention provide a control circuit, which is applied to a hard disk backplane and includes: a backplane execution circuit and a backplane control circuit;

[0007] Wherein, the backplane execution circuit is connected to the backplane control circuit and is used to control the backplane control circuit to power on and work;

[0008] The backplane control circuit includes at least two groups of signal transmission ends, which are respectively connected to corresponding hard disks, and send startup signals to the corresponding hard disks through any one group of signal transmission ends. When the hard disk signals fed back by the corresponding hard disks indicate that the hard disks start up, startup signals are sent to the corresponding hard disks through any remaining one group of signal transmission ends until all hard disks complete the startup process.

[0009] In some embodiments, the backplane execution circuit is a first programmable memory;

[0010] Wherein, the output end of the first programmable memory is connected to the first ends of each hard disk;

[0011] The status signal end of the first programmable memory is connected to the first end of the backplane control circuit;

[0012] The enable signal terminal of the first programmable memory is connected to the second terminal of the backplane control circuit;

[0013] The input terminal of the first programmable memory is connected to the power supply.

[0014] In some embodiments, the backplane execution circuit further includes: a first resistor, a second resistor, a third resistor, a first capacitor, and a second capacitor;

[0015] The first terminal of the first resistor is connected to the output terminal of the first programmable memory, and the second terminal of the first resistor is connected to the status signal terminal of the first programmable memory, the first terminal of the second resistor, and the first terminal of the first capacitor;

[0016] The second terminal of the second resistor and the first terminal of the first capacitor are connected and grounded;

[0017] The first terminal of the third resistor is connected to the enable signal terminal of the first programmable memory and the first terminal of the second capacitor;

[0018] The second terminal of the third resistor and the second terminal of the second capacitor are connected and grounded.

[0019] In some embodiments, the backplane control circuit is a complex programmable logic device;

[0020] The status signal input terminal of the complex programmable logic device is used as the first terminal of the backplane control circuit and is connected to the status signal terminal of the first programmable memory;

[0021] The enable signal input terminal of the complex programmable logic device is used as the second terminal of the backplane control circuit and is connected to the enable signal terminal of the first programmable memory;

[0022] Each enable signal detection terminal of the complex programmable logic device is respectively connected to the second terminal of the corresponding hard disk;

[0023] Each presence signal detection terminal of the complex programmable logic device is respectively connected to the third terminal of the corresponding hard disk;

[0024] Each status signal detection terminal of the complex programmable logic device is respectively connected to the fourth terminal of the corresponding hard disk; wherein, each enable signal detection terminal of the complex programmable logic device, each presence signal detection terminal of the complex programmable logic device, and each status signal detection terminal of the complex programmable logic device constitute each group of the signal transmission terminals of the backplane control circuit.

[0025] On the other hand, the present invention also provides a hard disk startup circuit, applied to a hard disk, including: a hard disk execution circuit and a hard disk control circuit;

[0026] The hard disk control circuit is connected to the hard disk backplane, and is used to determine the startup time according to the startup signal sent by the hard disk backplane, and determine the drive signal based on the startup signal;

[0027] The hard disk execution circuit is respectively connected to the hard disk control circuit and the hard disk backplane, and is used to determine the corresponding hard disk signal according to the drive signal, and send the hard disk signal to the hard disk backplane, so that when the hard disk backplane determines that the hard disk signal indicates that the hard disk starts up, a startup signal is sent to the remaining hard disk startup circuits.

[0028] In some embodiments, the hard disk execution circuit is a second programmable memory;

[0029] Wherein, the input end of the second programmable memory is connected to the first end of the hard disk control circuit and the first end of the hard disk backplane;

[0030] The status signal end of the second programmable memory is connected to the second end of the hard disk backplane;

[0031] The enable signal end of the second programmable memory is connected to the second end of the hard disk control circuit.

[0032] In some embodiments, the hard disk execution circuit further includes: a fourth resistor, a fifth resistor, and a third capacitor;

[0033] Wherein, the first end of the fourth resistor is connected to the output end of the second programmable memory;

[0034] The second end of the fourth resistor is connected to the status signal end of the second programmable memory, the first end of the fifth resistor, and the first end of the third capacitor;

[0035] The second ends of the fifth resistor and the third capacitor are connected and grounded.

[0036] In some embodiments, the hard disk control circuit includes: a comparator, an AND logic operation unit, a first MOS transistor, a zener diode, and a sixth resistor;

[0037] Wherein, the non-inverting input end of the comparator is connected to the first end of the sixth resistor, and they are jointly used as the first end of the hard disk control circuit and are connected to the input end of the second programmable memory;

[0038] The inverting input end of the comparator is connected to the second end of the sixth resistor and the negative electrode of the zener diode;

[0039] The pin end of the comparator is connected to the clamping voltage source, and the output end of the comparator is connected to the first end of the AND logic operation unit;

[0040] The gate of the first MOS transistor serves as the third end of the hard disk control circuit and is connected to the third end of the hard disk backplane, and serves as the fourth end of the hard disk control circuit and is connected to the fourth end of the hard disk backplane;

[0041] The drain of the first MOS transistor is connected to the clamping voltage source and the second terminal of the AND logic operation unit;

[0042] The third terminal of the AND logic operation unit is used as the second terminal of the hard disk control circuit and is connected to the enable signal terminal of the second programmable memory;

[0043] The source of the first MOS transistor and the positive electrode of the voltage stabilizing diode are grounded.

[0044] In some embodiments, the hard disk control circuit further includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor;

[0045] Wherein, the first terminal of the seventh resistor is connected to the first terminal of the sixth resistor, and the second terminal of the seventh resistor is connected to the first terminal of the eighth resistor and the non-inverting input terminal of the comparator;

[0046] The first terminal of the ninth resistor is connected to the second terminal of the sixth resistor and the negative electrode of the voltage stabilizing diode, and the second terminal of the ninth resistor is connected to the first terminal of the tenth resistor and the inverting input terminal of the comparator;

[0047] The second terminal of the tenth resistor is connected to the first terminal of the eleventh resistor;

[0048] The second terminal of the eleventh resistor is connected to the second terminal of the eighth resistor and is grounded.

[0049] In some embodiments, the hard disk control circuit further includes: a second MOS transistor;

[0050] Wherein, the gate of the second MOS transistor is connected to the output terminal of the comparator and the first terminal of the AND logic operation unit;

[0051] The source of the second MOS transistor is connected to the second terminal of the eighth resistor and the second terminal of the eleventh resistor and is grounded;

[0052] The drain of the second MOS transistor is connected to the second terminal of the tenth resistor and the first terminal of the eleventh resistor.

[0053] In some embodiments, the hard disk control circuit further includes: a twelfth resistor and a fourth capacitor;

[0054] Wherein, the first terminal of the twelfth resistor is connected to the output terminal of the comparator;

[0055] The second terminal of the twelfth resistor is connected to the first terminal of the fourth capacitor, the gate of the second MOS transistor, and the first terminal of the AND logic operation unit;

[0056] The second terminal of the fourth capacitor is grounded.

[0057] In some embodiments, the hard disk control circuit further includes: a thirteenth resistor, a fourteenth resistor, and a fifth capacitor;

[0058] The first end of the thirteenth resistor is connected to the clamping voltage source;

[0059] The second end of the thirteenth resistor is connected to the drain of the first MOS transistor;

[0060] The first end of the fourteenth resistor is connected to the first end of the fifth capacitor, the gate of the first MOS transistor, and the fourth end of the hard disk backplane;

[0061] The second end of the fifth capacitor is connected to the third end of the hard disk backplane;

[0062] The second end of the fourteenth resistor is grounded.

[0063] In some embodiments, the hard disk control circuit further includes: a fuse;

[0064] The first end of the fuse is connected to the input end of the second programmable memory;

[0065] The second end of the fuse is connected to the first end of the sixth resistor and the first end of the seventh resistor.

[0066] On the other hand, the present invention further provides an electronic device, including the above control circuit and / or hard disk startup circuit.

[0067] On the other hand, the present invention further provides a peak-shifting startup control method, applied to the above control circuit, including:

[0068] Sending a startup signal to the corresponding hard disk startup control circuit based on any group of signal transmission terminals;

[0069] Obtaining a hard disk signal fed back by the hard disk according to the startup signal;

[0070] When the hard disk signal indicates that the hard disk starts up, sending a startup signal to the corresponding hard disk through any remaining group of signal transmission terminals until all hard disks have completed the startup process.

[0071] In some embodiments, when the hard disk signal indicates that the hard disk starts up, sending a startup signal to the corresponding hard disk through any remaining group of signal transmission terminals includes:

[0072] Judging whether the hard disk signal is a high-level signal within a preset time;

[0073] If the hard disk signal is a high-level signal within the preset time, the hard disk signal indicates that the hard disk starts up, and a startup signal is sent to the corresponding hard disk startup control circuit through any remaining group of signal transmission terminals;

[0074] If the hard disk signal is a low-level signal within a preset time, and the hard disk signal indicates that the hard disk has not started, then a turn-off signal is sent to the currently corresponding hard disk, and a start signal is sent to the corresponding hard disk through any remaining set of signal transmission terminals.

[0075] In some embodiments, after the hard disk signal indicates that the hard disk has not started, it further includes:

[0076] Trigger the alarm system corresponding to the current hard disk so that the operator can determine the start state of the hard disk.

[0077] On the other hand, the present invention also provides a peak-shifting start control device, including:

[0078] A memory for storing a computer program;

[0079] A processor for executing the computer program to implement the steps of the above peak-shifting start control method.

[0080] On the other hand, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above peak-shifting start control method are implemented.

[0081] On the other hand, the present invention also provides a computer program product, including computer programs / instructions, and when the computer programs / instructions are executed by a processor, the steps of the above peak-shifting start control method are implemented.

[0082] It can be seen from the above technical solutions that the present invention provides a control circuit, which is applied to a hard disk backplane and includes: a backplane execution circuit and a backplane control circuit; wherein, the backplane execution circuit is connected to the backplane control circuit and is used to control the backplane control circuit to power on and work; the backplane control circuit includes at least two groups of signal transmission terminals, which are respectively connected to the corresponding hard disks, and a start signal is sent to the corresponding hard disk through any one group of signal transmission terminals. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk has started, a start signal is sent to the corresponding hard disk through any remaining one group of signal transmission terminals until all the hard disks have completed the start process. Thus, it can be seen that the present invention uses a control circuit to control the peak-shifting power-on start of at least two or more hard disks. During the process of controlling the power-on start of the hard disks, a start signal is first sent to any one hard disk, and after the hard disk has started, a start signal is sent to any one of the remaining hard disks, so that the hard disks start in sequence with a peak shift according to the order of receiving the start signals. Since there is only one backplane execution circuit and one backplane control circuit in the control circuit provided by the present invention, compared with the prior art peak-shifting start circuit for hard disks, the design cost is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] To more clearly illustrate the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0084] Figure 1 The structural diagram of a control circuit provided by an embodiment of the present invention;

[0085] Figure 2 The circuit diagram of hard disk off-peak startup provided by the prior art;

[0086] Figure 3 The circuit diagrams of a backplane execution circuit and a backplane control circuit provided by an embodiment of the present invention;

[0087] Figure 4 The structural diagram of a hard disk startup circuit provided by an embodiment of the present invention;

[0088] Figure 5 The circuit diagrams of a hard disk execution circuit and a hard disk control circuit provided by an embodiment of the present invention;

[0089] Figure 6 The structural diagram of an electronic device provided by an embodiment of the present invention;

[0090] Figure 7 The flowchart of an off-peak startup control method provided by an embodiment of the present invention;

[0091] Figure 8 The structural diagram of an off-peak startup control device provided by an embodiment of the present invention. Detailed implementation manners

[0092] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0093] The terms "include" and "have" in the specification of the present invention and the accompanying drawings above, as well as any variations related to "include" and "have", are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may include steps or units not listed.

[0094] To enable those skilled in the art to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0095] Next, a control circuit provided by an embodiment of the present invention will be introduced in detail. Figure 1 The structural diagram of a control circuit provided by an embodiment of the present invention is as Figure 1 shown. This control circuit is applied to the hard disk backplane 1 and includes: a backplane execution circuit 11 and a backplane control circuit 12. In addition, Figure 1 it also includes a hard disk 2. The connection relationship of its control circuit is: the backplane execution circuit 11 is connected to the backplane control circuit 12, and the backplane control circuit 12 includes at least two groups of signal transmission ends, which are respectively connected to the corresponding hard disks 2.

[0096] In the embodiment, with the development of big data technology, electronic devices (such as storage servers) have developed rapidly and their performance has become higher and higher. As the main configuration of storage-type models, the performance of hard disks is particularly important, and the reliability of hard disk power supply is the basic condition for the normal operation of hard disks. In storage servers, to prevent a large inrush current during the hard disk startup process, it is usually required that multiple hard disks in the storage server start at staggered times. In recent years, in order to achieve staggered startup of multiple hard disks in a storage server, a separate backplane startup circuit (PU11 - PU1N) is configured for each hard disk on the hard disk backplane, and a corresponding hard disk startup circuit (PU21 - PU2N) is also configured in the hard disk. The enable signal of the backplane startup circuit on the hard disk backplane is controlled by a complex programmable logic device (CPLD) in the entire electronic device. The circuit diagram for realizing staggered startup of hard disks in the current electronic device is as Figure 2As shown, in the backplane startup circuit (PU11 - PU1N), each backplane startup circuit includes a one-time programmable memory (EFUSE) and the corresponding three resistors and two capacitors. In the hard disk startup circuit (PU21 - PU2N), each hard disk startup circuit includes a one-time programmable memory (EFUSE) and the corresponding three or four resistors and two capacitors. The hard disk enable signal EN is obtained by dividing the input voltage. When the input voltage is low, the EFUSE will start working and supply power to its subsequent load, which easily causes the hard disk EUFSE to be protected and thus lose power. In this design, the hard disk enable signals P12V_NVME1_EN - P12V_NVMEN_EN are respectively obtained by dividing the corresponding input voltages P12V_NVME1_VIN - P12V_NVMEN_VIN. During the power-down process, it will cause the outputs P12V_NVME1 - P12V_NVMEN to have an output again. In the case of non-monotonic power-down, it even causes P12V_NVME1_PG - P12V_NVMEN_PG to become high level again, resulting in false detection. Among them, for the one-time programmable memory (EFUSE) in the backplane startup circuit, the power supply signal it obtains is P12V_STBY, and the enable signals are P12V_NVME1_VIN_EN - P12V_NVMEN_VIN_EN. It can be seen that the current design requires a large number of backplane startup circuits, resulting in a tight space on the board and increasing the costs of the hard disk backplane and the server.

[0097] For this reason, the present invention provides a control circuit. In the design of the control circuit provided by the present invention, only one backplane execution circuit 11 and one backplane control circuit 12 need to be designed on the hard disk backplane 1. In Figure 1 In the circuit connection relationship of the shown control circuit, the backplane control circuit 12 includes at least two groups of signal transmission terminals, which are respectively connected to the corresponding hard disks 2. It mainly sends a startup signal to the corresponding hard disk 2 through any one group of signal transmission terminals. After receiving the startup signal, the hard disk 2 will generate a corresponding hard disk signal and re-send the hard disk signal to the backplane control circuit 12. At this time, the backplane control circuit 12 will judge the hard disk signal. If the current hard disk signal indicates that the hard disk starts, then the backplane control circuit 12 sends a startup signal to the corresponding hard disk 2 through any remaining group of signal transmission terminals until all the hard disks 2 complete the startup process.

[0098] Here, it should be noted that if the backplane control circuit 12 determines that the hard disk signal indicates that the hard disk has not started, then at this time, the backplane control circuit 12 needs to resend the shutdown signal to the corresponding hard disk 2 through the current signal transmission terminal. The main reason is as follows: If the backplane control circuit 12 determines that the hard disk signal indicates that the hard disk has not started, it means that the current hard disk 2 may be abnormal, resulting in the inability of the hard disk 2 to start. Then, in order to ensure that the hard disk 2 is not further damaged, a shutdown signal needs to be sent to the hard disk 2 at this time to prevent the hard disk 2 from continuing the startup process.

[0099] For example: If the control circuit controls three hard disks (the first hard disk, the second hard disk, and the third hard disk) to power on in sequence, the backplane control circuit 12 includes three groups of signal transmission terminals, namely the first group of signal transmission terminals, the second group of signal transmission terminals, and the third group of signal transmission terminals. At this time, the connection relationship of the circuit is as follows: The first group of signal transmission terminals in the backplane control circuit 12 is connected to the first hard disk; the second group of signal transmission terminals in the backplane control circuit 12 is connected to the second hard disk; the third group of signal transmission terminals in the backplane control circuit 12 is connected to the third hard disk.

[0100] The control circuit in the current design realizes the staggered startup of the hard disk, including the following steps:

[0101] Step 1: The backplane control circuit 12 sends a startup signal to the first hard disk through the first group of signal transmission terminals, so that the first hard disk generates a first hard disk signal according to the startup signal.

[0102] Step 2: The backplane control circuit 12 receives the first hard disk signal through the first group of signal transmission terminals. If the first hard disk signal indicates that the first hard disk has started, the backplane control circuit 12 sends a startup signal to the second hard disk through the second group of signal transmission terminals, so that the second hard disk generates a second hard disk signal according to the startup signal; if the first hard disk signal indicates that the first hard disk has not started, the backplane control circuit 12 sends a shutdown signal to the first hard disk through the first group of signal transmission terminals, and then sends a startup signal to the second hard disk through the second group of signal transmission terminals, so that the second hard disk generates a second hard disk signal according to the startup signal.

[0103] Step 3: The backplane control circuit 12 receives the second hard disk signal through the second group of signal transmission terminals. If the second hard disk signal indicates that the second hard disk has started, the backplane control circuit 12 sends a startup signal to the third hard disk through the third group of signal transmission terminals, so that the third hard disk generates a third hard disk signal according to the startup signal; if the second hard disk signal indicates that the second hard disk has not started, the backplane control circuit 12 sends a shutdown signal to the second hard disk through the second group of signal transmission terminals, and then sends a startup signal to the third hard disk through the third group of signal transmission terminals, so that the third hard disk generates a third hard disk signal according to the startup signal.

[0104] Step 4: The backplane control circuit 12 receives the third hard disk signal through the third set of signal transmission terminals. If the third hard disk signal indicates that the third hard disk has started, the control circuit in the current design completes the staggered start of the hard disk. If the third hard disk signal indicates that the third hard disk has not started, the backplane control circuit 12 sends a turn-off signal to the third hard disk through the third set of signal transmission terminals, and then the control circuit in the current design completes the staggered start of the hard disk.

[0105] Step 5: The backplane control circuit 12 summarizes the current signal or data indicating that the hard disk has not started and displays it through the connected display device for the operator to view.

[0106] It should be noted that Step 5 is an optional step and can exist or not exist in the staggered start process of the hard disk. It can be set according to the user's needs.

[0107] It should also be noted that the specific process in the example provided by the present invention starts in the order of the first hard disk, the second hard disk, and the third hard disk. This is just one achievable way, but it is not limited to only this implementation method and can be adjusted according to the user's needs.

[0108] It can be seen from the above technical solutions that the present invention provides a control circuit applied to a hard disk backplane, including: a backplane execution circuit and a backplane control circuit; wherein, the backplane execution circuit is connected to the backplane control circuit and is used to control the backplane control circuit to power on and work; the backplane control circuit includes at least two sets of signal transmission terminals, which are respectively connected to the corresponding hard disks, and send start signals to the corresponding hard disks through any one set of signal transmission terminals. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk has started, start signals are sent to the corresponding hard disk through any remaining set of signal transmission terminals until all the hard disks have completed the start process. Thus, the present invention uses one control circuit to control the staggered power-on start of at least two or more hard disks. During the process of controlling the power-on start of the hard disks, a start signal is first sent to any one hard disk. After the hard disk has started, a start signal is sent to any one of the remaining hard disks, so that the hard disks start in a staggered manner in the order of receiving the start signals. Since there is only one backplane execution circuit and one backplane control circuit in the control circuit provided by the present invention, compared with the prior art staggered start circuit for hard disks, the design cost is reduced.

[0109] In some embodiments, such as Figure 3As shown, its backplane execution circuit 11 is the first programmable memory EFUSE1. The output terminal (VOUT) of the first programmable memory EFUSE1 is used as the first terminal of the backplane execution circuit 11 and is connected to the first terminals of each hard disk 2 to realize the transmission of the power supply signal P12V_NVME; the status signal terminal (PG) of the first programmable memory EFUSE1 is used as the second terminal of the backplane execution circuit 11 and is connected to the first terminal of the backplane control circuit 12 to realize the transmission of the backplane power status signal P12V_NVME_PG; the enable signal terminal (EN) of the first programmable memory EFUSE1 is used as the third terminal of the backplane execution circuit 11 and is connected to the second terminal of the backplane control circuit 12 to realize the transmission of the backplane enable signal P12V_NVME_EN; the input terminal (VIN) of the first programmable memory EFUSE1 is used as the fourth terminal of the backplane execution circuit 11 and is connected to the power supply to obtain the required power supply signal P12V_STBY for itself.

[0110] In addition, to ensure the normal transmission of signals and that the voltage does not exceed the threshold of electronic components, the backplane execution circuit 11 further includes: a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, and a second capacitor C2. The circuit connection relationship at this time is: the first terminal of the first resistor R1 is connected to the output terminal (VOUT) of the first programmable memory EFUSE1, and the second terminal of the first resistor R1 is connected to the status signal terminal (PG) of the first programmable memory EFUSE1, the first terminal of the second resistor R2, and the first terminal of the first capacitor C1; the second terminal of the second resistor R2 and the first terminal of the first capacitor C1 are connected and grounded; the first terminal of the third resistor R3 is connected to the enable signal terminal (EN) of the first programmable memory EFUSE1 and the first terminal of the second capacitor C2; the second terminal of the third resistor R3 and the second terminal of the second capacitor C2 are connected and grounded.

[0111] In some embodiments, such as Figure 3As shown in the figure, its backplane control circuit 12 is a complex programmable logic device CPLD. When the backplane control circuit 12 is a complex programmable logic device CPLD, the connection relationship of its circuit is as follows: The status signal input terminal of the complex programmable logic device CPLD is used as the first terminal of the backplane control circuit 12 and is connected to the status signal terminal (PG) of the first programmable memory EFUSE1 to realize the transmission of the backplane power status signal P12V_NVME_PG; The enable signal input terminal of the complex programmable logic device CPLD is used as the second terminal of the backplane control circuit 12 and is connected to the enable signal terminal (EN) of the first programmable memory EFUSE1. Each enable signal detection terminal of the complex programmable logic device CPLD is respectively connected to the second terminal of the corresponding hard disk 2 to start the transmission of the signal (which can also be understood as the hard disk enable signal) P12V_NVME1 / 3 _EN_N. At the same time, each enable signal detection terminal of the complex programmable logic device CPLD is also connected to the power supply to obtain the P3V3_STBY power signal; Each presence signal detection terminal of the complex programmable logic device CPLD is respectively connected to the third terminal of the corresponding hard disk 2 to obtain the presence signal P12V_NVME1 / 3 _INDEF_R_N representing the disk position number in each current hard disk 2. At the same time, each presence signal detection terminal of the complex programmable logic device CPLD is also connected to the power supply to obtain the P3V3_STBY power signal; Each status signal detection terminal of the complex programmable logic device CPLD is respectively connected to the fourth terminal of the corresponding hard disk to obtain the hard disk signal P12V_NVME1 / 3 _PG output by the hard disk 2 (which can also be understood as the hard disk power status signal of the current hard disk 2).

[0112] In addition, to ensure the normal transmission of signals and so on and that the voltage does not exceed the threshold of electronic components, the circuit also includes: resistors. The resistors are specifically set on each enable signal detection terminal and each presence signal detection terminal of the complex programmable logic device CPLD. The resistors are respectively: R104, R105, R106, R107, R108, and R109.

[0113] Among them, it should be noted that Figure 3 In the shown embodiment, the complex programmable logic device CPLD includes three enable signal detection terminals, three presence signal detection terminals, and three status signal detection terminals. However, this is only a feasible way and can be set by the user according to needs.

[0114] In the current embodiment, one enable signal detection terminal, one presence signal detection terminal, and one status signal detection terminal constitute a group of signal transmission terminals of the backplane control circuit 12. Thus, it can be seen that Figure 3 In the shown embodiment, the complex programmable logic device CPLD includes three groups of signal transmission terminals, that is, it can be connected to three hard disks 2 to realize the staggered start of the three hard disks.

[0115] As can be seen from the above technical solution, the present invention uses a control circuit to control the off-peak power-on startup of at least two or more hard disks. During the process of controlling the hard disk to power on and start, a startup signal is first sent to any one of the hard disks. After the hard disk starts, a startup signal is then sent to any one of the remaining hard disks, so that the hard disks start in off-peak order according to the order of receiving the startup signals. Since there is only one backplane execution circuit and one backplane control circuit in the control circuit provided by the present invention, compared with the prior art's off-peak startup circuit for controlling hard disks, the design cost is reduced.

[0116] On the other hand, the present invention provides a hard disk startup circuit, as Figure 4 shown. The hard disk startup circuit is applied to hard disk 2. The hard disk startup circuit includes: a hard disk execution circuit 22 and a hard disk control circuit 21. In addition, Figure 4 the circuit shown includes a hard disk backplane 1. The circuit connection relationship at this time is: the hard disk control circuit 21 is connected to the hard disk backplane 1; the hard disk execution circuit 22 is respectively connected to the hard disk control circuit 21 and the hard disk backplane 1.

[0117] In the embodiment, the hard disk control circuit 21 obtains the startup signal sent by the hard disk backplane 1 by being connected to the hard disk backplane 1. It should be noted that the hard disk startup circuit only realizes the power-on process of the hard disk after the hard disk control circuit 21 receives the startup signal. After the hard disk control circuit 21 receives the startup signal, it processes the startup signal to obtain the corresponding drive signal. The hard disk execution circuit 22 obtains the drive signal through its connection with the hard disk control circuit 21. After the drive signal passes through the hard disk execution circuit 22, a hard disk signal is output, and the hard disk signal indicates whether the hard disk starts successfully. The hard disk backplane 1 obtains the hard disk signal generated by the hard disk execution circuit 22 at this time through its connection with the hard disk execution circuit 22. If the current hard disk signal indicates that the hard disk has started, then the hard disk backplane 1 sends a startup signal to the hard disk control circuit 21 in the remaining hard disks 2; if the hard disk backplane 1 determines that the hard disk signal indicates that the hard disk has not started, then the hard disk backplane 1 needs to send a shutdown signal to the hard disk control circuit 21 corresponding to the current hard disk 2 again and send a startup signal to the hard disk control circuit 21 in the remaining hard disks 2.

[0118] As can be seen from the above technical solution, the present invention provides a hard disk startup circuit, which is applied to a hard disk and includes: a hard disk execution circuit and a hard disk control circuit; the hard disk control circuit is connected to the hard disk backplane, and is used to determine the startup time according to the startup signal sent by the hard disk backplane, and determine the drive signal based on the startup signal; the hard disk execution circuit is respectively connected to the hard disk control circuit and the hard disk backplane, and is used to determine the corresponding hard disk signal according to the drive signal, and send the hard disk signal to the hard disk backplane, so that when the hard disk backplane determines that the hard disk signal indicates that the hard disk starts up, a startup signal is sent to the remaining hard disk startup circuits. Thus, the present invention uses a hard disk backplane to control the startup time of the hard disk. During the power-on startup process of the hard disk, it realizes its own startup based on the startup signal sent by the hard disk backplane, and the time when the hard disk backplane sends the startup signal is controllable. Therefore, when multiple hard disks exist, staggered startup of the hard disks can be achieved. Compared with the prior art for controlling the staggered startup circuit of the hard disk, the design cost is reduced.

[0119] In some embodiments, as Figure 5 shown, the hard disk execution circuit 22 is the second programmable memory EFUSE2. When the hard disk execution circuit 22 is the second programmable memory EFUSE2, the connection relationship of the circuit is: the input terminal (VIN) of the second programmable memory EFUSE2 is connected to the first terminal of the hard disk control circuit 21 and the first terminal of the hard disk backplane 1, and is used to realize the transmission of the power supply signal P12V_NVME; the status signal terminal (PG) of the second programmable memory EFUSE2 is connected to the second terminal of the hard disk backplane 1, and is used to realize the transmission of the hard disk signal P12V_NVME1 / N_PG; the enable signal terminal (EN) of the second programmable memory EFUSE2 is connected to the second terminal of the hard disk control circuit 21, and is used to realize the transmission of the drive signal P12V_NVME1 / N_EN corresponding to the hard disk execution circuit 22; in addition, the output terminal (OUT) of the second programmable memory EFUSE2 outputs the power supply signal P12V_NVME1 / N.

[0120] In addition, to ensure the normal transmission of signals, etc. and that the voltage does not exceed the threshold of the electronic components, Figure 5 the hard disk execution circuit 22 shown also includes: a fourth resistor R4, a fifth resistor R5, and a third capacitor C3. Based on this, the connection relationship of the hard disk execution circuit 22 is: the first terminal of the fourth resistor R4 is connected to the output terminal (OUT) of the second programmable memory EFUSE2; the second terminal of the fourth resistor R4 is connected to the status signal terminal (PG) of the second programmable memory EFUSE2, the first terminal of the fifth resistor R5, and the first terminal of the third capacitor C3; the second terminal of the fifth resistor R5 and the second terminal of the third capacitor C3 are connected and grounded.

[0121] In some embodiments, as Figure 5As shown, the hard disk control circuit 21 includes: a comparator U1, an AND logic operation unit U2, a first MOS transistor Q1, a voltage stabilizing diode D1, and a sixth resistor R6. The connection relationship of the circuit at this time is as follows: the non-inverting input terminal of the comparator U1 is connected to the first terminal of the sixth resistor R6, and they are jointly used as the first terminal of the hard disk control circuit 21 to be connected to the input terminal (VIN) of the second programmable memory EFUSE2; the inverting input terminal of the comparator U1 is connected to the second terminal of the sixth resistor R6 and the negative electrode of the voltage stabilizing diode D1; the pin terminal of the comparator U1 is connected to the clamping voltage source, and the output terminal of the comparator U1 is connected to the first terminal of the AND logic operation unit U2; the gate of the first MOS transistor Q1 is used as the third terminal of the hard disk control circuit 21 to be connected to the third terminal of the hard disk backplane 1 for realizing the transmission of the start signal P12V_NVME1 / N _EN_N, and is used as the fourth terminal of the hard disk control circuit 21 to be connected to the fourth terminal of the hard disk backplane 1 for realizing the transmission of the disk position signal P12V_NVME1 / N _INDEF_R_N; the drain of the first MOS transistor Q1 is connected to the clamping voltage source and the second terminal of the AND logic operation unit U2; the third terminal of the AND logic operation unit U2 is used as the second terminal of the hard disk control circuit 21 to be connected to the enable signal terminal (EN) of the second programmable memory EFUSE2 for realizing the transmission of the drive signal P12V_NVME1 / N_EN; the source of the first MOS transistor Q1 and the positive electrode of the voltage stabilizing diode D1 are grounded.

[0122] In addition, Figure 5In the illustrated embodiment, the hard disk control circuit 21 further includes: a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a second MOS transistor Q2, a twelfth resistor R12, a fourth capacitor C4, a thirteenth resistor R13, a fourteenth resistor R14, a fifth capacitor C5, and a fuse F1. The connection relationship of the hard disk control circuit 21 at this time is as follows: The first end of the seventh resistor R7 is connected to the first end of the sixth resistor R6, and the second end of the seventh resistor R7 is connected to the first end of the eighth resistor R8 and the non-inverting input terminal of the comparator U1; The first end of the ninth resistor R9 is connected to the second end of the sixth resistor R6 and the negative electrode of the zener diode D1, and the second end of the ninth resistor R9 is connected to the first end of the tenth resistor R10 and the inverting input terminal of the comparator U1; The second end of the tenth resistor R10 is connected to the first end of the eleventh resistor R11; The second end of the eleventh resistor R11 is connected to the second end of the eighth resistor R8 and grounded; The gate of the second MOS transistor Q2 is connected to the output terminal of the comparator U1 and the first terminal of the logic operation unit U2; The source of the second MOS transistor Q2 is connected to the second end of the eighth resistor R8 and the second end of the eleventh resistor R11 and grounded; The drain of the second MOS transistor Q2 is connected to the second end of the tenth resistor R10 and the first end of the eleventh resistor R11; The first end of the twelfth resistor R12 is connected to the output terminal of the comparator U1; The second end of the twelfth resistor R12 is connected to the first end of the fourth capacitor C4, the gate of the second MOS transistor Q2, and the first terminal of the logic operation unit U2; The second end of the fourth capacitor C4 is grounded; The first end of the thirteenth resistor R13 is connected to the clamping voltage source; The second end of the thirteenth resistor R13 is connected to the drain of the first MOS transistor Q1; The first end of the fourteenth resistor R14 is connected to the first end of the fifth capacitor C5, the gate of the first MOS transistor Q1, and the first four-terminal of the hard disk backplane 1; The second end of the fifth capacitor C5 is connected to the third terminal of the hard disk backplane 1; The second end of the fourteenth resistor R14 is grounded; The first end of the fuse F1 is connected to the input terminal (VIN) of the second programmable memory EFUSE2; The second end of the fuse F1 is connected to the first end of the sixth resistor R6 and the first end of the seventh resistor R7.

[0123] It should be noted that the supply voltage of the clamping voltage source is the voltage clamped by the zener diode D1, and the voltage at this time is VDD_D21.

[0124] In the embodiment, Figure 5The working principle of the complete hard disk control circuit 21 shown is as follows: Its signal P12V_NVME passes through the fuse F1 to the sixth resistor R6. When the backend circuit is short-circuited, the fuse F1 quickly blows to play a protective role. The hard disk control circuit 21 can determine whether the output of P12V_NVME1 / N_EN_1 is high level or low level according to the magnitude of the input voltage of P12V_NVME. When P12V_NVME increases to the threshold value input to the hard disk control circuit 21, the output P12V_NVME1 / N_EN_1 is high level. When P12V_NVME1 / N_EN_1 is high level, it controls the conduction of the second MOS transistor Q2, so that the current hard disk control circuit 21 has a hysteresis function. The hard disk control circuit 21 can determine whether the output of P12V_NVME1 / N_EN_2 is high level or low level according to the high and low level states of FM_NVME1 / N_IFDET_R_N. When FM_NVME1 / N_IFDET_R_N is low level, P12V_NVME1 / N_EN_2 outputs high level. And when both P12V_NVME1 / N_EN_1 and P12V_NVME1 / N_EN_2 are high level, the output P12V_NVME1 / N_EN is high level.

[0125] In the hard disk control circuit 21, when P12V_NVME increases to 3.3V, the zener diode D1 conducts, and the voltage VDD_D21 is clamped at 3.3V.

[0126] At this time, the voltage of the inverting input terminal Vin- of the comparator U1 is:

[0127] Vin- = UR+ = 3.3*(R 10 +R 11 ) / (R9+R 10 +R 11 );

[0128] Among them, R 10 is the resistance value of the tenth resistor R10; R 11 is the resistance value of the eleventh resistor R11; R9 is the resistance value of the ninth resistor R9.

[0129] At this time, the voltage of the non-inverting input terminal Vin+ of the comparator U1 is:

[0130] Vin+ = P12V_NVME*R8 / (R7+R8);

[0131] Among them, R8 is the resistance value of the eighth resistor R8; R7 is the resistance value of the seventh resistor R7.

[0132] Based on this, Vin+ has a linear relationship with P12V_NVME and increases as P12V_NVME increases. When Vin+ = Vin- = UR+, the output P12V_NVME1 / N_EN_1 of comparator U1 is at a high level. When P12V_NVME1 / N_EN_1 is at a high level, it drives the second MOS transistor Q2 to conduct, and the eleventh resistor R11 is short-circuited.

[0133] At this time, the voltage of the inverting input terminal Vin- of comparator U1 is:

[0134] Vin- = UR- = 3.3 * R 10 / (R9 + R 10 );

[0135] Since UR- is less than UR+ and comparator U1 has a hysteresis function, it prevents the output P12V_NVME1 / N_EN_1 from fluctuating between high and low levels due to the fluctuation of the input voltage of P12V_NVME.

[0136] It should be noted that the hard disk startup circuit in any one of the hard disks 2 is the circuit structure shown above. Figure 5 shown circuit structure.

[0137] In addition, since the specific structure of the hard disk startup circuit provided by the present invention is relatively complex, when any one of the electronic components fails, the finally output signal will fail, which will further cause problems in the hard disk power-on startup process. Therefore, three groups of detection circuits are added to the hard disk startup circuit provided by the present invention, namely the first group of detection circuits, the second group of detection circuits and the third group of detection circuits. The first group of detection circuits is used to connect the first end of the fuse F1 and the output end of the comparator U1 to detect P12V_NVME and P12V_NVME1 / N_EN_1; the second group of detection circuits is used to connect the gate of the first MOS transistor Q1 and the drain of the first MOS transistor Q1 to detect P12V_NVME1 / N_EN, FM_NVME1 / N_IFDET_R_N and P12V_NVME1 / N_EN_2; the third group of detection circuits is used to connect the first end, the second end and the third end of the logic operation unit U2 to detect P12V_NVME1 / N_EN_1, P12V_NVME1 / N_EN_2 and P12V_NVME1 / N_EN. When any one of the signals does not conform to the normal corresponding relationship, the corresponding detection circuit generates an alarm signal for the operator to view.

[0138] It can be seen that the present invention uses a hard disk backplane to control the startup time of the hard disk. During the power-on startup process of the hard disk, it realizes its own startup based on the startup signal sent by the hard disk backplane, and the time when the hard disk backplane sends the startup signal is controllable. Therefore, when multiple hard disks exist, staggered startup of the hard disks can be achieved. Compared with the prior art for controlling the staggered startup circuit of the hard disk, the design cost is reduced.

[0139] On the other hand, the present invention also provides an electronic device, including the above control circuit and / or hard disk startup circuit, and having the same beneficial effects.

[0140] For the electronic device to achieve staggered startup of the hard disk, the electronic device includes multiple hard disks 2. That is to say, in the currently designed electronic device, the hard disk backplane 1 includes a control circuit 13 composed of a backplane execution circuit 11 and a backplane control circuit 12, and the electronic device includes multiple hard disks 2. Each hard disk 2 includes a hard disk startup circuit 23 composed of a hard disk execution circuit 22 and a hard disk control circuit 21, as Figure 6 shown.

[0141] To sum up, combining Figure 3 、 Figure 5 and Figure 6 the circuits shown, the steps to achieve staggered startup of the hard disk 2 in the electronic device are as follows:

[0142] Step 1: Construct the structure shown in Figure 6 、 Figure 3 and Figure 5 shown.

[0143] Step 2: When the backplane control circuit 12 and the backplane execution circuit 11 are operating normally, at this time P12V_NVME_EN = 1 (high level), P12V_NMVE outputs normally, and P12V_NVME_PG = 1.

[0144] Step 3: The backplane control circuit 12 detects the signal states of FM_NVME1 / N_IFDET_R_N and P12V_NVME1 / N_PG sent by all hard disks 2.

[0145] Step 4: Screen out the disk positions (the labels of the hard disks 2 themselves) where FM_NVME1 / N_IFDET_R_N = 0 and P12V_NVME1 / N_PG = 0.

[0146] Step 5: Enable bay 101 (the first hard disk 2), and output P12V_NVME1_EN_N = 0 (low level). When P12V_NVME1_EN_N = 0, the first MOS transistor Q1 is not turned on, and P12V_NVME1_EN_2 is at a high level. If both P12V_NVME1_EN_1 and P12V_NVME1_EN_2 are at a high level, then the output P12V_NVME1_EN of the AND logic operation unit U2 is at a high level. At this time, the hard disk execution circuit 22 works normally, P12V_NMVE0 outputs normally, and P12V_NVME1_PG = 1.

[0147] Step 6: If within a preset time (e.g., 1 s), P12V_NVME1_PG = 1, then enable bay 102 (the second hard disk 2 starts), and output P12V_NVME2_EN_N = 0;

[0148] If within the preset time, P12V_NVME1_PG = 0, then disable bay 101, output P12V_NVME1_EN_N = 1, and then enable bay 102, output P12V_NVME2_EN_N = 0.

[0149] Step 7: If within the preset time, P12V_NVME2_PG = 1, then enable bay 103, and output P12V_NVME3_EN_N = 0;

[0150] If within the preset time, P12V_NVME2_PG = 0, then disable bay 102, output P12V_NVME2_EN_N = 1, and then enable bay 103, output P12V_NVME3_EN_N = 0.

[0151] Step 8: If within the preset time, P12V_NVME3_PG = 1, then enable bay 104, and output P12V_NVME4_EN_N = 0;

[0152] If within the preset time, P12V_NVME3_PG = 0, then disable bay 103, output P12V_NVME3_EN_N = 1, and then enable bay 104, output P12V_NVME4_EN_N = 0.

[0153] Step 9: The same actions are repeated for the next bay until all bays have completed their work.

[0154] As can be seen from the above technical solution, the present invention provides an electronic device, including: a control circuit and multiple hard disk startup circuits; wherein, the control circuit is arranged in the hard disk backplane, and the hard disk startup circuit is arranged in the corresponding hard disk. The hard disk backplane first sends a startup signal to any one of the hard disks, and after the hard disk starts up, it then sends a startup signal to any one of the remaining hard disks, so that the hard disks start up in a staggered manner in sequence according to the order of receiving the startup signals. Since there is only one control circuit in the electronic device provided by the present invention, compared with the prior art staggered startup circuit for controlling hard disks, the design cost is reduced, and the space layout of the hard disk backplane is relieved. At the same time, in the specific control circuit and hard disk startup circuit structure, the hard disk execution circuit can be controlled to start up under a higher input voltage, avoiding the protection of the hard disk execution circuit due to startup at a lower input voltage, resulting in power failure. And during the power-down process of the hard disk execution circuit, the output signal drops monotonously and will not become a high level within a short time due to fluctuations, thus affecting the service life of the hard disk.

[0155] On the other hand, the present invention also provides a staggered startup control method, which is applied to the above control circuit, as Figure 7 shown, and its staggered startup control method includes the following processes:

[0156] S10: Send a startup signal to the corresponding hard disk based on any group of signal transmission terminals.

[0157] S11: Obtain the hard disk signal fed back by the hard disk according to the startup signal.

[0158] S12: When the hard disk signal indicates that the hard disk has started up, send a startup signal to the corresponding hard disk through any remaining group of signal transmission terminals until all hard disks have completed the startup process.

[0159] The specific implementation manner of its step S12 is as follows:

[0160] Judge whether the hard disk signal is a high-level signal within a preset time;

[0161] If the hard disk signal is a high-level signal within a preset time, the hard disk signal indicates that the hard disk has started up, and a startup signal is sent to the corresponding hard disk startup control circuit through any remaining group of signal transmission terminals;

[0162] If the hard disk signal is a low-level signal within a preset time, the hard disk signal indicates that the hard disk has not started up, then a shutdown signal is sent to the current corresponding hard disk, and a startup signal is sent to the corresponding hard disk through any remaining group of signal transmission terminals;

[0163] After the hard disk signal indicates that the hard disk has not started up, it further includes:

[0164] Trigger the alarm system corresponding to the current hard disk so that the operator can determine the startup state of the hard disk.

[0165] In an embodiment, the present invention further provides a peak-shifting startup control method, which is applied to a control circuit. The control circuit includes: a backplane execution circuit and a backplane control circuit; wherein, the backplane execution circuit is connected to the backplane control circuit and is used to control the backplane control circuit to power on and work; the backplane control circuit includes at least two groups of signal transmission terminals, which are respectively connected to corresponding hard disks, and a startup signal is sent to the corresponding hard disk through any one group of signal transmission terminals. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk has started up, a startup signal is sent to the corresponding hard disk through any remaining one group of signal transmission terminals until all the hard disks have completed the startup process. It can be seen that the present invention adopts a peak-shifting startup control method and uses the specific structure of the control circuit to realize the peak-shifting startup of multiple hard disks. Since the principle provided by the present invention is that one control circuit controls multiple hard disks, compared with the prior art peak-shifting startup circuit for controlling hard disks, the design cost is reduced, and the space layout tension of the hard disk backplane is alleviated.

[0166] Figure 8 The following is a structural diagram of a peak-shifting startup control device provided by an embodiment of the present invention. As Figure 8 shown, the peak-shifting startup control device includes: a memory 60, which is used to store a computer program;

[0167] a processor 61, which is used to implement the steps of the peak-shifting startup control method in the above embodiment when executing the computer program.

[0168] The peak-shifting startup control device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a notebook computer, or a desktop computer, etc.

[0169] Among them, the processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 61 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may further include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0170] The memory 60 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 60 may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 60 is at least used to store the following computer program 601. After the computer program is loaded and executed by the processor 61, it can implement the relevant steps of the peak-shift start control method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may further include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 602 may include Windows, Unix, Linux, etc.

[0171] In some embodiments, the peak-shift start control device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.

[0172] Those skilled in the art can understand that Figure 8 the structure shown in

[0173] It can be understood that if the peak-shift start control method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), electrically erasable programmable ROMs, registers, hard disks, removable disks, CD-ROMs, magnetic disks, or optical discs.

[0174] Based on this, the embodiments of the present invention further provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the peak-shift start control method as described above are implemented.

[0175] Based on this, the embodiments of the present invention further provide a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the peak-shift start control method as described above are implemented.

[0176] The above has introduced in detail a peak-shift start control device provided by the embodiments of the present invention. The various embodiments in the specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts between the various embodiments, reference can be made to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple. For the relevant parts, reference can be made to the description in the method part.

[0177] Those skilled in the art can further realize that the units and algorithm steps of the various examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described according to their functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0178] The above has introduced in detail a control circuit, a hard disk startup circuit, an electronic device, and a peak-shifting startup control method provided by the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A control circuit, characterized in that: Applied to hard disk backplane, including: backplane execution circuit and backplane control circuit; Wherein, the backplane execution circuit is connected to the backplane control circuit and is used to control the power-on operation of the backplane control circuit; The backplane control circuit includes at least two groups of signal transmission ends, which are respectively connected to corresponding hard disks. A startup signal is sent to the corresponding hard disk through any group of the signal transmission ends. When the hard disk signal fed back by the corresponding hard disk indicates that the hard disk is started, a startup signal is sent to the corresponding hard disk through any remaining group of the signal transmission ends until all the hard disks perform the startup process. The backplane execution circuit includes: a first programmable memory, a first resistor, a second resistor, a third resistor, a first capacitor and a second capacitor; Wherein, the output end of the first programmable memory is connected to the first end of each of the hard disks and the first end of the first resistor; The state signal terminal of the first programmable memory is connected to the first terminal of the backplane control circuit, the second terminal of the first resistor, the first terminal of the second resistor and the first terminal of the first capacitor; The enable signal terminal of the first programmable memory is connected to the second terminal of the backplane control circuit, the first terminal of the third resistor and the first terminal of the second capacitor; An input terminal of the first programmable memory is connected to a power supply; The second end of the second resistor is connected to the second end of the first capacitor and is grounded; The second end of the third resistor is connected to the second end of the second capacitor and is grounded.

2. The control circuit according to claim 1, characterized in that: The backplane control circuit is a complex programmable logic device; The state signal input terminal of the complex programmable logic device is connected to the state signal terminal of the first programmable memory as the first terminal of the backplane control circuit; The enable signal input terminal of the complex programmable logic device is connected to the enable signal terminal of the first programmable memory as the second terminal of the backplane control circuit; Each enable signal detection terminal of the complex programmable logic device is respectively connected to the second terminal of the corresponding hard disk; Each in-place signal detection terminal of the complex programmable logic device is respectively connected to the corresponding third terminal of the hard disk; Each status signal detection terminal of the complex programmable logic device is respectively connected to the corresponding fourth terminal of the hard disk, wherein each enable signal detection terminal of the complex programmable logic device, each in-place signal detection terminal of the complex programmable logic device and each status signal detection terminal of the complex programmable logic device constitute each group of signal transmission terminals of the backplane control circuit.

3. A hard disk startup circuit, characterized in that: Applied to hard disk, including: hard disk execution circuit and hard disk control circuit; The hard disk control circuit is connected to the hard disk backplane, and is used to determine the startup time according to the startup signal sent by the hard disk backplane, and determine the driving signal based on the startup signal; The hard disk execution circuit is connected to the hard disk control circuit and the hard disk backplane respectively, and is used to determine the corresponding hard disk signal according to the drive signal, and send the hard disk signal to the hard disk backplane, so that when the hard disk backplane determines that the hard disk signal represents hard disk startup, the startup signal is sent to the remaining hard disk startup circuits; The hard disk execution circuit includes: a second programmable memory, a fourth resistor, a fifth resistor and a third capacitor; Wherein, the input end of the second programmable memory is connected to the first end of the hard disk control circuit and the first end of the hard disk backplane; The output terminal of the second programmable memory is connected to the first terminal of the fourth resistor; The state signal end of the second programmable memory is connected to the second end of the hard disk backplane, the second end of the fourth resistor, the first end of the fifth resistor and the first end of the third capacitor; The enable signal terminal of the second programmable memory is connected to the second terminal of the hard disk control circuit; The second end of the fifth resistor is connected to the second end of the third capacitor and is grounded.

4. The hard disk startup circuit according to claim 3, characterized in that: The hard disk control circuit includes: a comparator, an AND logic operation unit, a first MOS tube, a voltage regulator diode and a sixth resistor; Wherein, the non-inverting input terminal of the comparator is connected to the first terminal of the sixth resistor, and together they serve as the first terminal of the hard disk control circuit and are connected to the input terminal of the second programmable memory; The inverting input terminal of the comparator is connected to the second end of the sixth resistor and the cathode of the voltage stabilizing diode; The pin end of the comparator is connected to a clamp voltage source, and the output end of the comparator is connected to the first end of the AND logic operation unit; The gate of the first MOS tube is connected to the third end of the hard disk backplane as the third end of the hard disk control circuit, and is connected to the fourth end of the hard disk backplane as the fourth end of the hard disk control circuit; The drain of the first MOS tube is connected to the clamping voltage source and the second end of the AND logic operation unit; The third terminal of the AND logic operation unit is connected to the enable signal terminal of the second programmable memory as the second terminal of the hard disk control circuit; The source of the first MOS tube and the anode of the voltage regulator diode are grounded.

5. The hard disk startup circuit according to claim 4, characterized in that: The hard disk control circuit further includes: a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor and an eleventh resistor; Wherein, the first end of the seventh resistor is connected to the first end of the sixth resistor, and the second end of the seventh resistor is connected to the first end of the eighth resistor and the non-inverting input end of the comparator; The first end of the ninth resistor is connected to the second end of the sixth resistor and the cathode of the voltage stabilizing diode, and the second end of the ninth resistor is connected to the first end of the tenth resistor and the inverting input end of the comparator; The second end of the tenth resistor is connected to the first end of the eleventh resistor; The second end of the eleventh resistor is connected to the second end of the eighth resistor and is grounded.

6. The hard disk startup circuit according to claim 5, characterized in that: The hard disk control circuit further includes: a second MOS tube; Wherein, the gate of the second MOS tube is connected to the output end of the comparator and the first end of the AND logic operation unit; The source of the second MOS tube is connected to the second end of the eighth resistor and the second end of the eleventh resistor, and is grounded; The drain of the second MOS tube is connected to the second end of the tenth resistor and the first end of the eleventh resistor.

7. The hard disk startup circuit according to claim 6, characterized in that: The hard disk control circuit further includes: a twelfth resistor and a fourth capacitor; Wherein, the first end of the twelfth resistor is connected to the output end of the comparator; The second end of the twelfth resistor is connected to the first end of the fourth capacitor, the gate of the second MOS tube and the first end of the AND logic operation unit; A second terminal of the fourth capacitor is grounded.

8. The hard disk startup circuit according to claim 7, characterized in that: The hard disk control circuit further includes: a thirteenth resistor, a fourteenth resistor and a fifth capacitor; The first end of the thirteenth resistor is connected to the clamping voltage source; The second end of the thirteenth resistor is connected to the drain of the first MOS tube; The first end of the fourteenth resistor is connected to the first end of the fifth capacitor, the gate of the first MOS tube and the fourth end of the hard disk backplane; The second end of the fifth capacitor is connected to the third end of the hard disk backplane; A second terminal of the fourteenth resistor is grounded.

9. The hard disk startup circuit according to claim 8, characterized in that: The hard disk control circuit further includes: a fuse; The first end of the fuse is connected to the input end of the second programmable memory; The second end of the fuse is connected to the first end of the sixth resistor and the first end of the seventh resistor.

10. An electronic device, characterized in that: It comprises the control circuit described in any one of claims 1-2 and / or the hard disk startup circuit described in any one of claims 3-9.

11. A peak-shift start control method, characterized in that: The control circuit as claimed in claim 1 comprises: Sending a start signal to a corresponding hard disk based on any set of signal transmission terminals; Acquire a hard disk signal fed back by the hard disk according to the start signal; When the hard disk signal indicates that the hard disk is started, a start signal is sent to the corresponding hard disk through any remaining group of the signal transmission ends until all the hard disks perform the start-up process.

12. The peak-shift start control method according to claim 11, characterized in that: When the hard disk signal indicates that the hard disk is started, sending a start signal to the corresponding hard disk through any remaining group of the signal transmission ends includes: Determining whether the hard disk signal is a high level signal within a preset time; If the hard disk signal is a high level signal within the preset time, the hard disk signal indicates that the hard disk is started, and a start signal is sent to the corresponding hard disk through any remaining group of the signal transmission ends; If the hard disk signal is a low-level signal within the preset time, and the hard disk signal indicates that the hard disk is not started, a shutdown signal is sent to the currently corresponding hard disk, and a start signal is sent to the corresponding hard disk through any remaining set of the signal transmission ends.

13. The peak-shift start control method according to claim 12, characterized in that: After the hard disk signal indicates that the hard disk is not started, the method further includes: The alarm system corresponding to the hard disk is triggered so that the operator can determine the startup status of the hard disk.

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