A parallel processing architecture optimization method and system for testing equipment

Abstract

The present invention discloses a method and system for optimizing the parallel processing architecture of a test device, and relates to the technical field of test device optimization. The method includes: collecting state parameters of the test device in real time during operation through data monitoring, preprocessing the state parameters, calculating a multi-dimensional architecture optimization index, setting an optimization objective function and constraints, constructing a multi-objective optimization model, optimizing the multi-objective optimization model according to a preset multi-objective optimization algorithm, solving the resource allocation of the processing unit, generating a resource allocation plan, applying it to a parallel processing architecture, adjusting the resource allocation in real time, and continuously monitoring the operating state of the test device through a closed-loop feedback mechanism, dynamically adjusting the optimization strategy, and ensuring that the architecture is optimized under different conditions. By calculating the multi-dimensional architecture optimization index and combining it with a dynamic adaptive optimization mechanism, it is possible to comprehensively consider the key performance indicators of the test device, adjust the resource allocation plan in real time, and flexibly respond to complex test tasks.

Description

Technical Field

[0001] The present invention relates to the technical field of test equipment optimization, and in particular to a method and system for optimizing a parallel processing architecture of a test equipment. Background Art

[0002] As modern test equipment continues to increase its requirements for performance and processing power, the parallel processing architecture of test equipment has become one of the key factors in improving performance. In complex test tasks, test equipment usually involves multiple processing units working together to complete the task, and these processing units need to frequently share resources and transfer data. However, traditional parallel processing architectures often have certain bottlenecks in terms of load adaptability, collaborative processing efficiency, data transmission, and synchronization stability.

[0003] In the existing technology, many optimization methods for parallel processing architectures focus on a single resource allocation strategy and fail to fully consider the multi-dimensional performance tuning of the system under different operating conditions. For example, existing methods usually only consider the balanced distribution of processing unit loads, ignoring the relationship between multiple factors such as data transmission delay, bandwidth utilization, and synchronization efficiency. This single optimization method makes it impossible for the parallel processing architecture to adaptively adjust under changing workloads and dynamic resource requirements, resulting in resource waste or performance bottlenecks.

[0004] In addition, existing resource optimization methods mostly rely on static preset rules or empirical formulas, and lack flexible dynamic adjustment mechanisms. When the test equipment is connected to a new device or the operating conditions change, it is often impossible to optimize and adjust in real time according to the new status parameters, and the performance potential of the test equipment cannot be fully utilized. Summary of the invention

[0005] Based on the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method and system for optimizing the parallel processing architecture of a test device to solve the above-mentioned technical problems.

[0006] To achieve the above object, the present invention provides the following technical solution: a method for optimizing the parallel processing architecture of a test device, comprising:

[0007] S1: collecting state parameters of the test equipment in real time during operation through data monitoring, and preprocessing the state parameters;

[0008] S2: Calculate a multi-dimensional architecture optimization index based on the pre-processed state parameters, wherein the multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index, and a synchronization stability index;

[0009] S3: setting an optimization objective function and constraint conditions according to the multi-dimensional architecture optimization index, constructing a multi-objective optimization model, optimizing the multi-objective optimization model according to a preset multi-objective optimization algorithm, solving resource allocation of processing units, and generating a resource allocation plan;

[0010] S4: Apply the optimized resource allocation scheme to the parallel processing architecture, adjust resource allocation in real time, continuously monitor the operating status of the test equipment through a closed-loop feedback mechanism, dynamically adjust the optimization strategy, and ensure that the architecture is optimized under different conditions.

[0011] The present invention is further configured such that the state parameters include the load of the processing unit, the load change rate, the resource adjustment rate, the data sharing amount, the collaborative processing time, the number of collaborative tasks, the data transmission amount, the transmission delay, the bandwidth utilization rate, the data compression rate, the number of synchronizations, the number of data conflicts, the data consistency error rate and the synchronization delay, and the preprocessing of the state parameters includes data cleaning and data standardization, the data cleaning is used to remove noise and fill missing values, and the data standardization is used to unify the scale of the state parameters.

[0012] The present invention is further configured that, based on the preprocessed state parameters, a multi-dimensional architecture optimization index is calculated, and the multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index and a synchronization stability index, including:

[0013] Calculate the load adaptability index based on the load, load change rate and resource adjustment rate;

[0014] The collaborative effectiveness index is calculated based on the amount of data sharing, collaborative processing time, and number of collaborative tasks;

[0015] Calculate the data transmission optimization index based on data transmission volume, transmission delay, bandwidth utilization and data compression rate;

[0016] The synchronization stability index is calculated based on the number of synchronizations, the number of data conflicts, the data consistency error rate, and the synchronization delay.

[0017] The present invention is further configured such that the calculation logic of the load adaptability index is: , wherein the for The load adaptability index at the moment, for The load at the moment, for The load change rate at a given moment, is the resource adjustment rate, indicating the resource allocation strategy in time adjustment speed.

[0018] The present invention is further configured such that the calculation logic of the synergistic efficiency index is: ,in, for The synergy efficiency index of the moment, is the number of processing units, Processing Unit and exist The amount of data shared at any given moment, Processing Unit and exist The collaborative processing time of the moment, Processing Unit and exist The number of collaborative tasks at a given moment, is the saturation processing coefficient of the number of collaborative tasks.

[0019] The present invention is further configured such that the calculation logic of the data transmission optimization index is: ,in, for The data transmission optimization index at each moment, for The amount of data transmitted at a time, for The data compression ratio at the moment, for The transmission delay of the moment, for Bandwidth utilization at a given time.

[0020] The present invention is further configured such that the calculation logic of the synchronization stability index is: ,in, is the synchronization stability index, for The number of synchronizations at a time, for The number of data conflicts at a given moment, for The data consistency error rate at each moment, for Time synchronization delay.

[0021] The present invention is further configured that step S3 comprises:

[0022] Performing weighted summation on the load adaptability index, the synergy efficiency index, the data transmission optimization index, and the synchronization stability index to generate an optimization objective function, wherein the sum of weight coefficients is 1;

[0023] Define constraints, where constraints include: ,in, for The number of processing units that need to allocate resources at any time, for Moment The resource allocation amount of the processing unit that needs resource allocation, for The amount of idle resources at a given moment; ,in, for The transmission delay of the moment, is the maximum permissible transmission delay, ,in, for The synchronization delay of time, is the maximum allowed synchronization delay;

[0024] A multi-objective optimization model is constructed according to the optimization objective function and the constraint conditions, and the multi-objective optimization model is optimized according to a preset multi-objective optimization algorithm to solve the resource allocation of the processing unit and generate a resource allocation plan, wherein the preset multi-objective optimization algorithm includes a genetic algorithm, a particle swarm optimization and an ant colony algorithm.

[0025] The present invention is further configured that step S4 comprises:

[0026] When a new device to be tested is connected to the test device, the state parameters of the test device during operation are collected, and a multi-dimensional architecture optimization index is calculated in real time;

[0027] According to the multi-dimensional architecture optimization index, the optimization objective function and constraints are set, a multi-objective optimization model is constructed, the multi-objective optimization model is optimized according to a preset multi-objective optimization algorithm, the resource allocation of the processing unit is solved, a new resource allocation plan is generated, and a closed-loop feedback mechanism is implemented.

[0028] The present invention also provides a parallel processing architecture optimization system for a test device, the system comprising:

[0029] Parameter acquisition module: collects the state parameters of the test equipment in real time during operation through data monitoring, and pre-processes the state parameters;

[0030] Index calculation module: based on the preprocessed state parameters, calculates the multi-dimensional architecture optimization index, wherein the multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index, and a synchronization stability index;

[0031] Model building module: setting optimization objective functions and constraints according to the multi-dimensional architecture optimization index, building a multi-objective optimization model, optimizing the multi-objective optimization model according to a preset multi-objective optimization algorithm, solving resource allocation of processing units, and generating a resource allocation plan;

[0032] Architecture optimization module: applies the optimized resource allocation scheme to the parallel processing architecture, adjusts resource allocation in real time, continuously monitors the operating status of the test equipment through a closed-loop feedback mechanism, and dynamically adjusts the optimization strategy to ensure that the architecture is optimized under different conditions.

[0033] The present invention provides a method and system for optimizing the parallel processing architecture of a test device. The method collects state parameters of the test device in real time during operation through data monitoring, and pre-processes the state parameters; based on the pre-processed state parameters, a multi-dimensional architecture optimization index is calculated, and the multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index, and a synchronization stability index; according to the multi-dimensional architecture optimization index, an optimization objective function and a constraint condition are set, a multi-objective optimization model is constructed, and the multi-objective optimization model is optimized according to a preset multi-objective optimization algorithm, and the resource allocation of the processing unit is solved to generate a resource allocation plan; the optimized resource allocation plan is applied to the parallel processing architecture, and the resource allocation is adjusted in real time. Through a closed-loop feedback mechanism, the operating state of the test device is continuously monitored, and the optimization strategy is dynamically adjusted to ensure that the architecture optimization is maintained under different conditions. The beneficial effects produced include:

[0034] 1. Multi-dimensional performance optimization: By calculating the multi-dimensional architecture optimization index, including the load adaptability index, the synergy efficiency index, the data transmission optimization index and the synchronization stability index, the present invention can comprehensively consider multiple key performance indicators during the operation of the test equipment and accurately optimize different system bottlenecks, thereby improving the overall performance and resource utilization of the test equipment;

[0035] 2. Dynamic adaptive optimization: With real-time monitoring and closed-loop feedback mechanisms, when a new device under test is connected or the operating conditions change, the present invention can dynamically adjust the resource allocation scheme based on the state parameters collected in real time, ensuring that the parallel processing architecture of the test equipment is always in the best resource allocation state under different workloads and operating conditions. This dynamic optimization capability overcomes the static optimization limitations of traditional methods and can effectively respond to changes in the test environment;

[0036] 3. Strong adaptability and ability to cope with complex test tasks: The optimization method of the present invention can adapt to a variety of different types of test tasks and equipment. By flexibly adjusting the architecture resource allocation, it ensures that the system can achieve optimal performance under both high and low load conditions. It is particularly suitable for complex and changeable test environments.

[0037] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0039] Figure 1 A flowchart of a method for optimizing a parallel processing architecture of a test device is shown as an exemplary embodiment of the present invention;

[0040] Figure 2 The present invention is a schematic diagram of the structure of a parallel processing architecture optimization system for a test device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0041] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0042] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0043] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0044] Embodiment 1

[0045] A method for optimizing the parallel processing architecture of a test device, such as Figure 1 As shown, including:

[0046] S1: collecting state parameters of the test equipment in real time during operation through data monitoring, and preprocessing the state parameters;

[0047] S2: Calculate a multi-dimensional architecture optimization index based on the pre-processed state parameters, wherein the multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index, and a synchronization stability index;

[0048] S3: setting an optimization objective function and constraint conditions according to the multi-dimensional architecture optimization index, constructing a multi-objective optimization model, optimizing the multi-objective optimization model according to a preset multi-objective optimization algorithm, solving resource allocation of processing units, and generating a resource allocation plan;

[0049] S4: Apply the optimized resource allocation scheme to the parallel processing architecture, adjust resource allocation in real time, continuously monitor the operating status of the test equipment through a closed-loop feedback mechanism, dynamically adjust the optimization strategy, and ensure that the architecture is optimized under different conditions.

[0050] The present invention is further configured such that the state parameters include the load of the processing unit, the load change rate, the resource adjustment rate, the data sharing amount, the collaborative processing time, the number of collaborative tasks, the data transmission amount, the transmission delay, the bandwidth utilization rate, the data compression rate, the number of synchronizations, the number of data conflicts, the data consistency error rate and the synchronization delay, and the preprocessing of the state parameters includes data cleaning and data standardization, the data cleaning is used to remove noise and fill missing values, and the data standardization is used to unify the scale of the state parameters. Specifically, load refers to the amount of tasks being processed by a processing unit at a certain moment, reflecting the work intensity of the processing unit. The load is obtained by real-time monitoring of the CPU or GPU occupancy rate and memory occupancy of the processing unit. The load data is collected regularly through the resource monitoring tools provided by the operating system, including the top command, perf tool, or custom performance monitoring module; the load change rate refers to the rate of change of the load in a short period of time, reflecting the fluctuation of the load. The load change rate is calculated by the ratio of the difference between two consecutive load values ​​and the time interval; the resource adjustment rate indicates the adjustment speed of the resource allocation strategy of the processing unit per unit time, reflecting the flexibility of the system resource configuration adjustment. The resource adjustment rate is obtained by monitoring the update frequency of the resource allocation strategy and the amplitude of each adjustment; the amount of data sharing refers to the amount of data shared between multiple processing units during the collaborative computing process. A higher amount of data sharing usually means that more communication is required between processing units. The amount of data sharing can be obtained by monitoring the amount of data transmission between processing units; the collaborative processing time refers to the time spent by multiple processing units to complete a task together when working together. The time includes multiple stages such as data exchange, synchronization and calculation. The collaborative processing time is The number of collaborative tasks refers to the number of tasks completed by multiple processing units during parallel processing. The amount of data transmission refers to the total amount of data transmitted between processing units during processing. The amount of data transmission can be obtained in real time through the traffic monitoring tools of the network interface, including iftop, nload or data transmission statistics module. The transmission delay refers to the time required for data to be transmitted from one processing unit to another. The transmission delay is obtained by measuring the transmission time of data from the source processing unit to the target processing unit. The bandwidth utilization rate indicates the ratio of the bandwidth actually used by the system to the total available bandwidth within a certain period of time. The bandwidth utilization rate is obtained through the bandwidth usage of the network interface and is monitored in real time using tools such as netstat and sar. The data compression rate refers to the ratio of the amount of compressed data to the amount of original data during data transmission. The data compression rate is calculated by comparing the size of the data before and after compression and is automatically counted during data compression. The number of synchronizations refers to the number of times multiple processing units need to be synchronized during parallel processing. The number of synchronizations is counted through the collaborative protocol and synchronization mechanism between multiple processing units.The number of data conflicts refers to the number of conflicts that occur when multiple processing units share data. The number of data conflicts is obtained by inserting a conflict detection mechanism when sharing data. Conflicts are usually detected through a lock mechanism or version control. The data consistency error rate refers to the proportion of data consistency errors that occur when multiple processing units work together. The data consistency error rate is obtained by verifying and comparing the shared data between processing units through the monitoring system, and relies on the consistency check function provided by the distributed computing platform. The synchronization delay refers to the time required for synchronization operations between multiple processing units. The synchronization delay is calculated by recording the start time and end time of the synchronization operation. The monitoring of synchronization delay can be obtained through the synchronization module in the scheduling system. ;

[0051] The present invention is further configured that, based on the preprocessed state parameters, a multi-dimensional architecture optimization index is calculated, and the multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index and a synchronization stability index, including:

[0052] The load adaptability index is calculated according to the load, the load change rate and the resource adjustment rate; the present invention is further configured that the calculation logic of the load adaptability index is: , wherein the for The load adaptability index at the moment, for The load at the moment, for The load change rate at a given moment, is the resource adjustment rate, indicating the resource allocation strategy in time The load adaptability index is an index that measures how effectively the system resources of the test equipment can adapt to different loads. In a parallel processing architecture, load, load change rate, and resource adjustment rate are key factors affecting system performance and resource allocation efficiency. Therefore, the load adaptability index aims to comprehensively consider these factors and evaluate the resource adaptability of the processing unit under dynamic load changes; the numerator is It means that as the load increases, the load adaptability index also increases. The use of exponential form makes the load adaptability index more sensitive to changes in load, especially when the load is large, which helps to reflect the load pressure of the system in a timely manner. The logarithmic function representing the load change rate can smooth load fluctuations and avoid instability caused by extreme changes. By adding 1, it ensures that when the load change rate is negative (load reduction), the logarithm can still produce a non-negative value; the denominator The square root effect of the resource adjustment rate makes the relationship between the index and the resource adjustment rate more balanced. A larger resource adjustment rate will reduce the load adaptability index value, thereby avoiding system instability caused by too fast resource adjustment; the load adaptability index can reflect the system's adaptability to load fluctuations in real time, and help determine whether the configuration of system resources is reasonable. If the load adaptability index is low, it may indicate that the system load changes greatly, but the resource adjustment is not timely, resulting in insufficient resource utilization or overload; if the load adaptability index is high, it means that the system can flexibly respond to load changes and resource allocation is more optimized.

[0053] The collaborative efficiency index is calculated according to the data sharing amount, collaborative processing time and the number of collaborative tasks; the present invention is further configured such that the calculation logic of the collaborative efficiency index is: ,in, for The synergy efficiency index of the moment, is the number of processing units, Processing Unit and exist The amount of data shared at any given moment, Processing Unit and exist The collaborative processing time of the moment, Processing Unit and exist The number of collaborative tasks at a given moment, is the saturation processing coefficient of the number of collaborative tasks. Specifically, the synergy efficiency index is used to measure the collaborative work efficiency between multiple processing units, reflecting the relationship between data sharing, collaborative processing time and the number of collaborative tasks between processing units in the parallel processing architecture. The larger the synergy efficiency index, the higher the synergy efficiency of the system and the more effective the collaboration between processing units. Represents a processing unit and The product of the amount of data sharing and the collaborative processing time between the two processing units. The higher the amount of data sharing and the collaborative processing time, the closer the collaborative work between the processing units and the higher the collaborative efficiency. The influence of the number of collaborative tasks on the collaborative effectiveness index is controlled. Less than saturation coefficient When the exponential term is close to 1, the collaborative efficiency increases with the number of tasks; when the number of collaborative tasks is greater than When the number of tasks increases, the index item will decrease rapidly, limiting the growth of synergy efficiency, thereby avoiding excessive load or diminishing efficiency of the system due to too many tasks. By calculating the synergy efficiency index, the system can dynamically evaluate the efficiency of the collaborative work between multiple processing units, identify processing units with poor collaboration or insufficient resource sharing, and adjust resource allocation or task scheduling strategies.

[0054] The data transmission optimization index is calculated according to the data transmission volume, transmission delay, bandwidth utilization and data compression rate; the present invention is further configured that the calculation logic of the data transmission optimization index is: ,in, for The data transmission optimization index at each moment, for The amount of data transmitted at a time, for The data compression ratio at the moment, for The transmission delay of the moment, for The data transmission optimization index is used to measure the comprehensive performance of data transmission efficiency in the parallel processing architecture of the test equipment, taking into account four key factors: data transmission volume, data compression rate, transmission delay and bandwidth utilization. By optimizing these factors, the data transmission optimization index can evaluate and improve the data transmission performance of the test equipment, ensuring that the system can complete the task with lower latency, higher bandwidth utilization and higher data compression rate. This means that as the amount of data transmitted increases, the impact of the compression ratio will also increase. The logarithmic form of the data compression ratio The impact of the compression ratio will gradually increase, but will not cause extreme changes due to excessive compression ratio (especially when the compression ratio is close to 1). This ensures that the contribution of the compression ratio to the data transmission optimization index is small when the compression efficiency is low (i.e. smaller) is more significant; the denominator of It directly affects the data transmission efficiency. Higher latency will significantly reduce the data transmission optimization index, so it appears in the denominator, bandwidth utilization. The square root form appears in the denominator, which means that when bandwidth utilization is close to 1, its contribution to the denominator increases less, and when bandwidth utilization is low, its impact is greater. The square root form ensures that the impact of bandwidth utilization on the data transmission optimization index is smooth. By comprehensively considering the data transmission volume, compression rate, transmission delay and bandwidth utilization, DTOR provides a comprehensive and optimized data transmission efficiency evaluation method. The system can improve the overall data transmission efficiency by adjusting the data compression rate, optimizing bandwidth utilization and reducing transmission delay.

[0055] The synchronization stability index is calculated according to the number of synchronizations, the number of data conflicts, the data consistency error rate and the synchronization delay; the present invention is further configured such that the calculation logic of the synchronization stability index is: ,in, is the synchronization stability index, for The number of synchronizations at a time, for The number of data conflicts at a given moment, for The data consistency error rate at each moment, for The synchronization delay at the moment. Specifically, the synchronization stability index is used to measure the synchronization performance and stability in a multi-processing unit system. By considering four key factors: the number of synchronizations, the number of data conflicts, the data consistency error rate, and the synchronization delay, the efficiency and stability of the system in the synchronization process are comprehensively evaluated. Conflicts, delays, and consistency issues in the synchronization process may lead to errors or performance degradation in data processing. Therefore, the synchronization stability index aims to evaluate how these factors affect the synchronization stability of the system. The numerator part By multiplying the number of synchronizations and the number of data conflicts, and by exponential form Enhance the impact of the number of data conflicts on the index. The purpose of this item is to balance the impact of the number of synchronizations and data conflicts on synchronization stability. Specifically, if the number of conflicts is large, the exponential term will increase significantly, making the numerator larger, indicating that the synchronization performance is degraded; the denominator The data consistency error rate and synchronization delay jointly affect the denominator. The greater the increase in the denominator after the two are multiplied, the lower the synchronization stability of the system. Higher data consistency error rates and synchronization delays will reduce the synchronization stability of the system. Therefore, they affect the denominator in the form of a product, ensuring that even if the number of synchronizations and conflicts is high, if the data consistency error rate and synchronization delay are large, the synchronization stability index will still be suppressed, reflecting the instability of system synchronization. By comprehensively considering the number of synchronizations, data conflicts, data consistency error rates, and synchronization delays, SSF can evaluate the stability of system synchronization in real time. When SSF is high, it means that the system's synchronization mechanism is effective and the processing units can work together and maintain efficient operation.

[0056] The present invention is further configured that step S3 comprises:

[0057] The load adaptability index, the synergy efficiency index, the data transmission optimization index and the synchronization stability index are weighted and summed to generate an optimization objective function, wherein the sum of the weight coefficients is 1; specifically, the objective function is the key to the optimization process, and a comprehensive objective function is formed by weighted summing of multiple optimization indicators, including the load adaptability index, the synergy efficiency index, the data transmission optimization index and the synchronization stability index, which respectively measures the system's load adaptability, collaborative processing capability, data transmission efficiency and synchronization stability; the weighted summation of these multiple performance indices is intended to make them jointly affect resource allocation during the optimization process. The sum of the weight coefficients is 1, which ensures the relative importance of each indicator in the objective function. Different application scenarios may have different preferences for different indicators. By adjusting the weight coefficients, a balance between different optimization goals can be achieved;

[0058] Define constraints, where constraints include: ,in, for The number of processing units that need to allocate resources at any time, for Moment The resource allocation amount of the processing unit that needs resource allocation, for The amount of idle resources at a given moment; ,in, for The transmission delay of the moment, is the maximum permissible transmission delay, ,in, for The synchronization delay of time, is the maximum allowed synchronization delay; specifically, constraints are used to limit resource allocation during the optimization process so that the optimization results meet the physical or logical limitations of the system. Defining constraints helps ensure that the resulting resource allocation solution is reasonable and executable;

[0059] A multi-objective optimization model is constructed according to the optimization objective function and the constraint conditions, and the multi-objective optimization model is optimized according to a preset multi-objective optimization algorithm to solve the resource allocation of the processing unit and generate a resource allocation plan, wherein the preset multi-objective optimization algorithm includes a genetic algorithm, a particle swarm optimization and an ant colony algorithm. Specifically, the genetic algorithm is an optimization algorithm that simulates the natural selection process and is suitable for solving complex multi-objective problems. Through operations such as selection, crossover, and mutation, the genetic algorithm can find an approximate optimal solution in a large search space; the particle swarm optimization is an optimization algorithm that simulates the foraging behavior of a flock of birds, and gradually approaches the optimal solution through the group collaboration of particles, and is suitable for solving multi-objective optimization problems with nonlinear and multi-peak problems; the ant colony algorithm simulates the accumulation and exchange of pheromones in the foraging process of ants to optimize path search, and is suitable for solving combinatorial optimization problems, and can effectively explore the optimization space and find the best resource allocation plan; the above-mentioned multi-objective optimization algorithms are all prior art and will not be elaborated here.

[0060] The present invention is further configured that step S4 comprises:

[0061] When a new device to be tested is connected to the test device, the state parameters of the test device during operation are collected, and the multi-dimensional architecture optimization index is calculated in real time; specifically, when a new device to be tested is connected to an existing test device, the system will automatically detect the access of the new device and start collecting the runtime state parameters of the test device. These state parameters may include information such as load, resource utilization, data transmission volume, synchronization delay, etc., reflecting the current operating status of the system; the access of the device may have an impact on the system, especially in terms of load, resource utilization and task allocation. By real-time monitoring of state parameters, the system can accurately capture these changes and respond quickly to ensure that resource allocation is reasonable and does not affect the stability of the system; the multi-dimensional architecture optimization index is calculated by comprehensively considering multiple factors. Through the dynamic calculation of these indices, the system can evaluate the optimization degree of the current resource allocation strategy in real time and identify existing bottlenecks or resource waste; each time a device is connected or the state changes, the system will calculate the multi-dimensional architecture optimization index in real time to ensure that the calculation result accurately reflects the current state of the system. This helps to discover potential resource allocation problems and make timely adjustments;

[0062] According to the multi-dimensional architecture optimization index, the optimization objective function and constraint conditions are set, a multi-objective optimization model is constructed, and the multi-objective optimization model is optimized according to the preset multi-objective optimization algorithm, the resource allocation of the processing unit is solved, a new resource allocation plan is generated, and a closed-loop feedback mechanism is realized. Specifically, by real-time monitoring of the state parameters of the equipment, the system can continuously track the optimization effect. If the resource allocation strategy fails to achieve the expected effect, the system will adjust the optimization goal and resource allocation plan again according to the real-time data. This closed-loop feedback mechanism ensures that the system can adaptively adjust the resource allocation and always maintain the optimal performance state; even if the state of the system changes, the closed-loop feedback mechanism can ensure that the optimization process is continuously carried out, and the optimization strategy is adjusted in real time to cope with new loads, equipment changes or performance bottlenecks. Through the combination of multi-dimensional architecture optimization index, optimization objective function and constraint conditions, the system can adjust the resource allocation plan in real time to improve the performance and stability of the test equipment. The closed-loop feedback mechanism ensures that the system can perform adaptive optimization in a constantly changing environment and always maintain an efficient operating state.

[0063] Embodiment 2

[0064] See also Figure 2 , the exemplary parallel processing architecture optimization system of a test device includes:

[0065] Parameter acquisition module: collects the state parameters of the test equipment in real time during operation through data monitoring, and pre-processes the state parameters;

[0066] Index calculation module: based on the preprocessed state parameters, calculates the multi-dimensional architecture optimization index, wherein the multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index, and a synchronization stability index;

[0067] Model building module: setting optimization objective functions and constraints according to the multi-dimensional architecture optimization index, building a multi-objective optimization model, optimizing the multi-objective optimization model according to a preset multi-objective optimization algorithm, solving resource allocation of processing units, and generating a resource allocation plan;

[0068] Architecture optimization module: applies the optimized resource allocation scheme to the parallel processing architecture, adjusts resource allocation in real time, continuously monitors the operating status of the test equipment through a closed-loop feedback mechanism, and dynamically adjusts the optimization strategy to ensure that the architecture is optimized under different conditions.

[0069] It should be noted that the parallel processing architecture optimization system for a test device provided in the above embodiment and the parallel processing architecture optimization method for a test device provided in the above embodiment belong to the same concept, wherein the specific manner in which each module and unit performs operations has been described in detail in the method embodiment and will not be repeated here. In actual applications, the parallel processing architecture optimization system for a test device provided in the above embodiment can allocate the above functions to different functional modules as needed, that is, divide the internal structure of the system into different functional modules to complete all or part of the functions described above, and this is not limited here.

[0070] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0071] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0072] In this application, "at least one" means one or more, and "more than one" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0073] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0074] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0075] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0076] In the several embodiments provided in the present application, it should be understood that the disclosed system can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0077] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0078] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0079] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage media include: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0080] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for optimizing a parallel processing architecture of a test device, characterized in that: include: S1: collect state parameters of the test equipment in real time during operation through data monitoring, and pre-process the state parameters; the state parameters include the load of the processing unit, the load change rate, the resource adjustment rate, the data sharing amount, the collaborative processing time, the number of collaborative tasks, the data transmission amount, the transmission delay, the bandwidth utilization rate, the data compression rate, the number of synchronizations, the number of data conflicts, the data consistency error rate and the synchronization delay. The pre-processing of the state parameters includes data cleaning and data standardization. The data cleaning is used to remove noise and fill missing values, and the data standardization is used to unify the scale of the state parameters; S2: Calculate a multi-dimensional architecture optimization index based on the pre-processed state parameters, wherein the multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index, and a synchronization stability index; The multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index and a synchronization stability index, including: calculating the load adaptability index according to the load, the load change rate and the resource adjustment rate; calculating the synergy efficiency index according to the data sharing amount, the collaborative processing time and the number of collaborative tasks; calculating the data transmission optimization index according to the data transmission amount, the transmission delay, the bandwidth utilization rate and the data compression rate; calculating the synchronization stability index according to the number of synchronizations, the number of data conflicts, the data consistency error rate and the synchronization delay; S3: setting an optimization objective function and constraints according to the multi-dimensional architecture optimization index, constructing a multi-objective optimization model, optimizing the multi-objective optimization model according to a preset multi-objective optimization algorithm, solving the resource allocation of the processing unit, and generating a resource allocation plan; including: performing weighted summation on the load adaptability index, the synergy efficiency index, the data transmission optimization index, and the synchronization stability index to generate an optimization objective function, wherein the sum of the weight coefficients is 1; defining constraints, wherein the constraints include: , where p is the number of processing units that need to allocate resources at time t, R j is the resource allocation amount of the jth processing unit that needs resource allocation at time t, and the R freel is the amount of idle resources at time t; ,in, is the transmission delay at time t, is the maximum permissible transmission delay, , where M(t) is the synchronization delay at time t, M max is the maximum allowable synchronization delay; constructing a multi-objective optimization model according to the optimization objective function and the constraint conditions, optimizing the multi-objective optimization model according to a preset multi-objective optimization algorithm, solving the resource allocation of the processing unit, and generating a resource allocation plan, wherein the preset multi-objective optimization algorithm includes a genetic algorithm, a particle swarm optimization, and an ant colony algorithm; S4: Apply the optimized resource allocation scheme to the parallel processing architecture, adjust resource allocation in real time, continuously monitor the operating status of the test equipment through a closed-loop feedback mechanism, dynamically adjust the optimization strategy, and ensure that the architecture is optimized under different conditions.

2. The method for optimizing the parallel processing architecture of a test device according to claim 1, characterized in that: The calculation logic of the load adaptability index is: , where RLAI(t) is the load adaptability index at time t, L(t) is the load at time t, is the load change rate at time t, and R(t) is the resource adjustment rate, which indicates the adjustment speed of the resource allocation strategy at time t.

3. The method for optimizing the parallel processing architecture of a test device according to claim 1, characterized in that: The calculation logic of the synergistic efficiency index is: , where MSEC(t) is the synergy efficiency index at time t, m is the number of processing units, S ij (t) is the data sharing amount between processing units i and j at time t, T ij (t) is the collaborative processing time of processing units i and j at time t, N ij (t) is the number of collaborative tasks between processing units i and j at time t, is the saturation processing coefficient of the number of collaborative tasks.

4. The method for optimizing the parallel processing architecture of a test device according to claim 1, characterized in that: The calculation logic of the data transmission optimization index is: , where DTOR(t) is the data transmission optimization index at time t, D(t) is the data transmission volume at time t, and C(t) is the data compression rate at time t. is the transmission delay at time t, and B(t) is the bandwidth utilization at time t.

5. The method for optimizing the parallel processing architecture of a test device according to claim 1, characterized in that: The calculation logic of the synchronization stability index is: , where SSF is the synchronization stability index, X(t) is the number of synchronizations at time t, Y(t) is the number of data conflicts at time t, E(t) is the data consistency error rate at time t, and M(t) is the synchronization delay at time t.

6. The method for optimizing the parallel processing architecture of a test device according to claim 1, characterized in that: Step S4 includes: When a new device to be tested is connected to the test device, the state parameters of the test device during operation are collected, and a multi-dimensional architecture optimization index is calculated in real time; According to the multi-dimensional architecture optimization index, the optimization objective function and constraints are set, a multi-objective optimization model is constructed, the multi-objective optimization model is optimized according to a preset multi-objective optimization algorithm, the resource allocation of the processing unit is solved, a new resource allocation plan is generated, and a closed-loop feedback mechanism is implemented.

7. A parallel processing architecture optimization system for a test device, used to implement a parallel processing architecture optimization method for a test device according to any one of claims 1 to 6, characterized in that: include: Parameter acquisition module: collects the state parameters of the test equipment in real time during operation through data monitoring, and pre-processes the state parameters; Index calculation module: based on the preprocessed state parameters, calculates the multi-dimensional architecture optimization index, wherein the multi-dimensional architecture optimization index includes a load adaptability index, a synergy efficiency index, a data transmission optimization index, and a synchronization stability index; Model building module: setting optimization objective functions and constraints according to the multi-dimensional architecture optimization index, building a multi-objective optimization model, optimizing the multi-objective optimization model according to a preset multi-objective optimization algorithm, solving resource allocation of processing units, and generating a resource allocation plan; Architecture optimization module: applies the optimized resource allocation scheme to the parallel processing architecture, adjusts resource allocation in real time, continuously monitors the operating status of the test equipment through a closed-loop feedback mechanism, and dynamically adjusts the optimization strategy to ensure that the architecture is optimized under different conditions.

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