Memory device control method and related flash memory controller and memory device

Abstract

A memory device control method, a flash memory controller and a memory device are disclosed. The control method includes reading a first data from a first section and decoding the first data, wherein the first section is located in a first data page in a super data page, and the super data page includes a plurality of data pages located in a plurality of data pages respectively; if the first section fails to be decoded, obtaining data of a plurality of corresponding sections of the first section, wherein the plurality of corresponding sections are located in other data pages in the super data page respectively; and if the data of the plurality of corresponding sections cannot be successfully decoded, determining whether to give up the decoding operation of the first section according to a status weight of the first section and at least one status weight of at least one corresponding section in the plurality of corresponding sections which cannot be successfully decoded.

Description

Technical Field

[0001] This invention relates to a flash memory controller. Background Technology

[0002] To better protect the data within the flash memory module, the encoder in the flash memory controller uses a redundant array of independent disks (RAID) encoding method to encode the data written to the flash memory module, generating multiple parity codes. However, with the miniaturization of flash memory manufacturing processes and its move towards 3-dimension, the probability of flash memory failing to be successfully decoded using low-density parity-check (LDPC) codes during reading has increased significantly. This leads to a substantial increase in the number of times RAID decoding is required. Furthermore, the time required for decoding using RAID in previous technologies resulted in a decrease in decoding efficiency. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a flash memory controller with a highly efficient RAID decoding method to solve the problems described in the prior art.

[0004] In one embodiment of the present invention, a control method for a memory device is disclosed, wherein the memory device includes a flash memory module, the flash memory module includes multiple data planes, each data plane includes multiple blocks, each block includes multiple data pages, each data page includes multiple segments, and the control method includes: reading and decoding a first data from a first segment, wherein the first segment is located in a first data page in a super data page, and the super data page includes multiple data pages respectively located in the multiple data planes; if the decoding of the first segment fails, obtaining data from multiple corresponding segments of the first segment, wherein the multiple corresponding segments are respectively located in other data pages in the super data page besides the first data page; if the data of the multiple corresponding segments can be successfully decoded, generating decoded data for the specific segment based on multiple decoded data from the multiple corresponding segments; and if not all the data of the multiple corresponding segments can be successfully decoded, determining whether to abandon the decoding operation of the first segment based on a symptom weight of the first segment and at least one symptom weight of at least one corresponding segment that failed to be decoded.

[0005] In one embodiment of the present invention, a flash memory controller is disclosed, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprising multiple data surfaces, each data surface comprising multiple blocks, each block comprising multiple data pages, and each data page comprising multiple segments. The flash memory controller includes a read-only memory, a buffer memory, and a microprocessor, wherein the read-only memory is used to store program code, and the microprocessor is used to execute the program code to control access to the flash memory module. The microprocessor is configured to perform the following operations: read and decode first data from a first segment, wherein the first segment is located in a first data page in a super data page, and the super data page contains multiple data pages located in the multiple data planes respectively; if the decoding of the first segment fails, obtain data from multiple corresponding segments of the first segment, wherein the multiple corresponding segments are located in other data pages in the super data page besides the first data page respectively; if the data of the multiple corresponding segments can be successfully decoded, generate decoded data for the specific segment based on multiple decoded data from the multiple corresponding segments; and if not all the data of the multiple corresponding segments can be successfully decoded, determine whether to abandon the decoding operation of the first segment based on a symptom weight of the first segment and at least one symptom weight of at least one corresponding segment that failed to be decoded.

[0006] In one embodiment of the present invention, a memory device is disclosed, comprising a flash memory module and a flash memory controller. The flash memory module includes multiple data planes, each data plane includes multiple blocks, each block includes multiple data pages, and each data page includes multiple segments. The flash memory controller is used to access the flash memory module, and the flash memory controller performs the following operations: reading and decoding a first data segment from a first segment, wherein the first segment is located in a first data page in a super data page, and the super data page contains multiple data pages located in the multiple data planes respectively; if the decoding of the first segment fails, obtaining data from multiple corresponding segments of the first segment, wherein the multiple corresponding segments are located in other data pages in the super data page besides the first data page; if the data of the multiple corresponding segments can be successfully decoded, generating decoded data for the specific segment based on multiple decoded data from the multiple corresponding segments; and if not all the data of the multiple corresponding segments can be successfully decoded, deciding whether to abandon the decoding operation of the first segment based on a symptom weight of the first segment and at least one symptom weight of at least one corresponding segment that failed to be decoded. Attached Figure Description

[0007] Figure 1This is a schematic diagram of a memory device according to one embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram illustrating how blocks belonging to different data planes within a flash memory module are configured as a single superblock.

[0009] Figure 3 This is a diagram illustrating the configuration of a super data page.

[0010] Figure 4 This is a schematic diagram of a RAID encoding method according to an embodiment of the present invention.

[0011] Figure 5 , Figure 6 , Figure 7 This is a flowchart of a method for accessing a flash memory module according to an embodiment of the present invention.

[0012] Figure 8 This is a schematic diagram illustrating the generation of hard information and soft information according to an embodiment of the present invention.

[0013] Figure 9 This is a schematic diagram illustrating the generation of a specific pattern according to an embodiment of the present invention.

[0014] [Symbol Explanation]

[0015] 100: Memory device

[0016] 110: Flash memory controller

[0017] 112: Microprocessor

[0018] 112M: Read-Only Memory

[0019] 112C: Program Code

[0020] 114: Control Logic

[0021] 116: Buffer memory

[0022] 118: Interface Logic

[0023] 120: Flash memory module

[0024] 130: Main unit

[0025] 132: Encoder

[0026] 134: Decoder

[0027] 136: Randomizer

[0028] 138: Derandomizer

[0029] 210_1~210_A: Grain

[0030] 212_1~212_2A: Data plane

[0031] 230_1, 230_2: Superblock

[0032] 310_1~310_B

[0033] 330_1, 330_2: Super Data Page

[0034] 500~552: Step 910: Specific Pattern

[0035] B0~BN: Blocks

[0036] D0, D1, D2: Data

[0037] P1, P2, P3: Data Pages

[0038] S0, S1: State

[0039] Vr,(Vr-Δ),(Vr+Δ),(Vr-2Δ),(Vr+2Δ): Read voltage Detailed Implementation

[0040] Figure 1 This is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 includes a flash memory module 120 and a flash memory controller 110, and the flash memory controller 110 is used to access the flash memory module 120. According to this embodiment, the flash memory controller 110 includes a microprocessor 112, a read-only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory 112M is used to store program code 112C, and the microprocessor 112 is used to execute the program code 112C to control access to the flash memory module 120. The control logic 114 includes an encoder 132, a decoder 134, a randomizer 136, and a de-randomizer 138. The encoder 132 is used to encode the data written to the flash memory module 120 to generate a corresponding check code (or error correction code, ECC). The decoder 134 is used to decode the data read from the flash memory module 120. The randomizer 136 is used to randomize the data written to the flash memory module 120, and the de-randomizer 138 is used to de-randomize the data read from the flash memory module 120.

[0041] In a typical configuration, flash memory module 120 comprises multiple flash memory chips, and each flash memory chip contains multiple blocks. The flash memory controller 110 performs data copying, erasing, and merging operations on flash memory module 120 in units of blocks. Furthermore, a block can record a specific number of data pages, and the flash memory controller 110 writes data to flash memory module 120 in units of data pages. In other words, a block is the smallest unit of erasure in flash memory module 120, and a data page is the smallest unit of writing in flash memory module 120.

[0042] In practice, the flash memory controller 110, which executes program code 112C through microprocessor 112, can perform various control operations using its internal components, such as: using control logic 114 to control the access operations of flash memory module 120 (especially the access operations of at least one block or at least one data page), using buffer memory 116 to perform the required buffering operations, and using interface logic 118 to communicate with a host device 130.

[0043] In one embodiment, the memory device 100 may be a portable memory device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards), and the main device 130 may be an electronic device that can be connected to the memory device, such as a mobile phone, laptop, desktop computer, etc. In another embodiment, the memory device 100 may be a solid-state drive or an embedded storage device conforming to Universal Flash Storage (UFS) or Embedded Multi Media Card (EMMC) specifications, and may be disposed in an electronic device, such as a mobile phone, watch, portable medical monitoring device (e.g., medical bracelet), laptop, or desktop computer, and in this case, the main device 130 may be a processor of the electronic device.

[0044] In this embodiment, the flash memory module 120 is a 3D NAND-type flash memory module, wherein each block is composed of multiple word lines, multiple bit lines, and multiple memory cells. Since the architecture of 3D NAND-type flash memory is well known to those skilled in the art, it will not be described in detail in this specification.

[0045] In the implementation of flash memory module 120, flash memory controller 110 configures blocks belonging to different data planes within flash memory module 120 into a superblock to facilitate data access management. Specifically, refer to... Figure 2 The schematic diagram of the flash memory module 120 shown includes multiple flash memory dies 210_1 to 210_A, where A can be any suitable positive integer, such as A equal to 2, 4, 6, 8, etc.; and each flash memory die includes two data planes, for example, flash memory die 210_1 includes two data planes 212_1 and 212_2, flash memory die 210_2 includes two data planes 212_3 and 212_4, ..., and flash memory die 210_A includes two data planes 212_(2A-1) and 212_2A. Furthermore, each data plane includes multiple blocks B0 to BN, where N can be any suitable positive integer, such as N equal to 64, 128, etc. During the initialization of the flash memory module 120, the flash memory controller 110 configures the first block B0 of each data plane as a superblock 230_1, the second block B1 of each data plane as a superblock 230_2, and so on. For example... Figure 2 As shown, superblock 230_1 contains (2*A) physical blocks. When the flash memory controller 110 accesses superblock 230_1, it is similar to a regular block. For example, superblock 230_1 itself is an erasure unit. That is, although the (2*A) blocks B0 of superblock 230_1 can be erased separately, the flash memory controller 110 will always erase all (2*A) blocks B0 together.

[0046] Furthermore, when writing data to superblock 230_1, data can be written sequentially from the first data page of data plane 212_1, the first data page of data plane 212_2, the first data page of data plane 212_3, the first data page of data plane 212_4, ..., the first data page of data plane 212_(2A-1), and the first data page of data plane 212_2A. Data is then written sequentially to the second data page of data plane 212_1, the second data page of data plane 212_2, ..., and so on, only after the first data page of data plane 212_2A has finished writing. Figure 3 To illustrate, the flash memory controller 110 configures blocks belonging to different data planes within each superblock as a super data page to facilitate data access management. Figure 3In the process, the flash memory controller 110 configures the first data page P1 of block B0 in data plane 212_1, the first data page P1 of block B0 in data plane 212_2, ..., and the first data page P1 of block B0 in data plane 212_2A as a super data page 330_1; and the flash memory controller 110 configures the second data page P2 of block B0 in data plane 212_1, the second data page P2 of block B0 in data plane 212_2, ..., and the second data page P2 of block B0 in data plane 212_2A as a super data page 330_2, ... and so on. Furthermore, each data page can contain multiple chunks (or sectors) 310_1 to 310_B, where each chunk 310_1 to 310_B can be considered an encoding / decoding unit. That is, the encoder 132 encodes a piece of data to be written to the flash memory module 120 to generate encoded data, which is then written to a chunk. This encoded data includes the data and the corresponding error correction code. The decoder 134 can read data from a chunk from the flash memory module 120 and decode the chunk to generate decoded data. In one example, the size of a data page can be 16 kilobytes (KB) or 32 KB, and the size of a chunk can be 4 KB, but the invention is not limited thereto.

[0047] To provide better protection for the data in the flash memory module 120, the flash memory controller 110 employs RAID encoding when writing data to the flash memory module 120. Taking the embodiments in Figures 2 and 3 as an example, in superblock 230_1, one data plane block B0 can be dedicated to storing checksums for other data planes. For instance, data page P1 of block B0 in data plane 212_2A is used to store the result of an exclusive OR (XOR) operation on data pages P1 of blocks B0 in data planes 212_1 to 210_(2A-1). Data page P2 of block B0 in data plane 212_2A is used to store the result of an exclusive OR (XOR) operation on data pages P2 of blocks B0 in data planes 212_1 to 210_(2A-1), and so on. Figure 4For example, each data page contains multiple data entries D0, D1, D3, ..., where each data entry can be a single bit. The encoder 132 can sequentially perform XOR operations on the data D0 of data page P1 in block B0 of data plane 212_1, the data D0 of data page P1 in block B0 of data plane 212_2, ..., and the data D0 of data page P1 in block B0 of data plane 212_(2A-1) to generate a result, which is then written to the data plane 212_2A. The data page P1 of block B0 is used as its data D0; the encoder 132 can sequentially perform XOR operations on the data D1 of data page P1 of block B0 in data plane 212_1, the data D1 of data page P1 of block B0 in data plane 212_2, ..., the data D1 of data page P1 of block B0 in data plane 212_(2A-1) to generate a result, and then write it to the data page P1 of block B0 in data plane 212_2A as its data D1, ..., and so on. Through Figure 4 The RAID encoding method shown can restore data regardless of which data page P1 in the super data page 330_1 becomes unreadable, by performing an XOR operation on the data of all other data pages in the super data page 330_1.

[0048] Figures 5 to 7 This is a flowchart illustrating a method for accessing a flash memory module 120 according to an embodiment of the present invention. (See also...) Figures 5 to 7 In step 500, the process begins, and the memory device 100 has been powered on and completed initialization. In step 502, the microprocessor 112 in the flash memory controller 110 receives a read instruction, such as a read instruction from the host device 130, to begin reading a super data page. In the following embodiments, reading the super data page 330_1 of Figures 3 and 4 is used as an example for explanation. In step 504, the flash memory controller 110 sequentially reads each segment of each data page in the super data page 330_1 and performs decoding. In this embodiment, the decoding process of each segment by the flash memory controller 110 may include hardware decoding or software decoding. Hardware decoding may be a BCH (Bose-Chaudhuri-Hocquenghem code) or low-density parity-check code (LDPC) decoding method, while software decoding may be an LDPC decoding method.

[0049] refer to Figure 8 The example shown will be used to illustrate this, in which Figure 8This description assumes that each memory unit in each segment is used to store only one bit; that is, the super data page 330_1 is a single-level storage (SLC) data page. However, this invention is not limited to this. (See references.) Figure 8Each memory cell stores one bit and has one of two states, S0 and S1, where state S0 corresponds to the logic value "0" and state S1 corresponds to the logic value "1". The control circuit in the flash memory module 120 can use a read voltage Vr to read each memory cell to determine its logic value. If the memory cell is turned on when the read voltage Vr is applied, it is determined that the memory cell corresponds to the logic value "1"; if the memory cell is not turned on when the read voltage Vr is applied, the control circuit 320 determines that the memory cell corresponds to the logic value "0". The logic value of each memory cell determined above can be called a sign bit, and the multiple sign bits corresponding to all memory cells in a segment can be called hard information. It should be noted that due to the voltage distribution of states S0 and S1, the sign bit of the memory cell determined by the flash memory module 120 may not be the actual logic value. Furthermore, the decoder 134 in the flash memory controller 110 can perform hard decoding on a segment of hard information to attempt to obtain decoded data. If the decoder 134 fails to successfully decode the hard information, the flash memory controller 110 will control the flash memory module 120 to generate additional soft information for soft decoding. For example, the flash memory module 120 can again use read voltages (Vr+Δ) and (Vr-Δ) to read each memory cell in the segment to determine a first soft bit of the memory cell. For example, if the memory cell is turned on when the read voltage (Vr+Δ) is applied, or if the memory cell is not turned on when the read voltage (Vr-Δ) is applied, the flash memory module 120 determines that the memory cell corresponds to a strong region, and the first soft bit of the memory cell is a strong bit "1". If the memory cell is turned on when a read voltage (Vr-Δ) is applied, and is not turned on when a read voltage (Vr+Δ) is applied, then the flash memory module 120 determines that the memory cell corresponds to a weak region, and the first soft bit of the memory cell is a weak bit "0". Furthermore, the flash memory module 120 can again use another read voltage, such as read voltages (Vr+2*Δ) and (Vr-2*Δ), to read each memory cell in the segment to determine the second soft bit of the memory cell. For example, if the memory cell is turned on when a read voltage (Vr+2*Δ) is applied, or is not turned on when a read voltage (Vr-2*Δ) is applied, then the flash memory module 120 determines that the memory cell corresponds to a strong region, and the second soft bit of the memory cell is a strong bit "1".If the memory cell is turned on when a read voltage (Vr-2*Δ) is applied, and is not turned on when a read voltage (Vr+2*Δ) is applied, then the flash memory module 120 determines that the memory cell corresponds to a weak region, and the second soft bit of the memory cell is a weak bit "0". The plurality of first soft bits and the plurality of second soft bits corresponding to all memory cells in this region can be referred to as soft information. After obtaining the soft information of this region, the decoder 134 can use the hard information and soft information of this region to perform soft decoding in an attempt to obtain the decoded data.

[0050] In step 506, the decoder 134 in the flash memory controller 110 determines whether the currently decoded segment has been successfully decoded. If yes, the process proceeds to step 512; otherwise, the process proceeds to step 508. In this embodiment, "whether the segment has been successfully decoded" refers to whether the decoder 134 can use the hard and soft information of the segment to perform software decoding to successfully generate decoded data.

[0051] In step 508, decoder 134 determines whether it has decoded the last segment of super data page 330_1. If yes, the process proceeds to step 510 and decoder 134 has completed the decoding operation of super data page 330_1. If no, the process returns to step 504 to continue decoding the next segment.

[0052] In step 512, the decoder 134 in the flash memory controller 110 determines whether a syndrome or syndrome weight of the segment that failed to decode is greater than a syndrome threshold. If yes, the process proceeds to step 514; otherwise, the process proceeds to step 534. It should be noted that the syndrome weight mentioned above refers to the number of parity check equations that are not satisfied during the decoding process. The syndrome weight can be used to reflect the data quality; a smaller syndrome weight indicates better data quality (fewer error bits in the segment), while a higher syndrome weight indicates worse data quality (more error bits in the segment). In this embodiment, if the syndrome weight of a segment is greater than the syndrome threshold, it indicates that the segment's data has serious errors and cannot be decoded using the LDPC decoding method. Furthermore, since the meaning and calculation method of the aforementioned symptoms and symptom weights are well known to those with ordinary knowledge in the art, such as US Patent Application Publication No. US20190158115 and Taiwan Patent Publication No. TWI718060, the relevant calculation details will not be elaborated here.

[0053] For ease of the following description, the above-mentioned decoding failure segments are described as Uncorrectable Error Correction Code (UECC) segments.

[0054] In step 514, decoder 134 sequentially obtains the data of the corresponding segments of the aforementioned UECC segment located on other data planes. For example, suppose the UECC segment mentioned in steps 506 and 512 is... Figure 3 If the data page P1 segment 310_1 of block B0 in data plane 212_1 is a data plane, then the flash memory controller 110 needs to obtain the data page P1 segment 310_1 of block B0 in each data plane from data plane 212_2 to 212_2A; and if the UECC segment mentioned in steps 506 and 512 is a data plane, then the flash memory controller 110 needs to obtain the data page P1 segment 310_1 of block B0 in each data plane from data plane 212_2 to 212_2A. Figure 3 If the data page P1 of block B0 in data plane 212_2A is segment 310_1, then the flash memory controller 110 needs to obtain the data page P1 segment 310_1 of block B0 in each of data planes 212_2 to 212_(2A-1). Furthermore, regarding the data of the corresponding segment of the UECC segment located on other data planes obtained in step 514, if the relevant data is already present in the control logic 114 or the buffer memory 116, the decoder 134 can read it directly; otherwise, if the relevant data is not yet present in the control logic 114 or the buffer memory 116, it needs to be read and decoded through the flash memory module 120.

[0055] In step 516, decoder 134 determines whether the data of the corresponding segments of the UECC segment located on other data planes can be successfully decoded. That is, only the UECC segment in super data page 330_1 is a segment that cannot be successfully decoded. If yes, the process proceeds to step 518; otherwise, the process proceeds to step 520.

[0056] In step 518, decoder 134 uses RAID decoding, that is, it performs an XOR operation on the data of the corresponding segment of the UECC segment located on other data planes, and the result of this XOR operation can be used as the decoded data of the aforementioned UECC segment. Figure 4 To illustrate, if segment 310_1 of data page P1 in block B0 of data plane 212_1 is a UECC segment, then decoder 134 can perform an XOR operation on segment 310_1 of data page P1 in each data plane from data plane 212_2 to 212_2A to generate the decoded data of segment 310_1 of data page P1 in block B0 of data plane 212_1.

[0057] In step 520, decoder 134 determines whether there is another segment that is also a UECC segment in the process of data of the corresponding segment located on other data planes of the above-mentioned UECC segment in step 514, and whether its symptoms or symptom weight is greater than the symptom threshold. If yes, the process proceeds to step 522; if no, the process proceeds to step 524.

[0058] In step 522, the decoder 134 determines that the data in the UECC segment cannot be successfully decoded through RAID decoding and abandons the decoding of this UECC segment.

[0059] In step 524, the microprocessor 112 or the decoder 134 determines whether the number of UECC segments in the super data page 330_1 during the operations in steps 506 and 514 is greater than a threshold value. If yes, the process proceeds to step 522; otherwise, the process proceeds to step 526. In this embodiment, the threshold value can be any suitable positive integer less than "2A".

[0060] In step 526, the microprocessor 112 or the decoder 134 generates a specific pattern based on the contents of all segments of the super data page 330_1 in steps 506 and 514, such as the contents of segment 310_1 of data page P1 in block B0 of each data plane 212_1 to 212_2A. This specific pattern is a possible error pattern, used to indicate which bit in the aforementioned UECC segment might be erroneous. Specifically, refer to... Figure 9 The microprocessor 112 or decoder 134 can sequentially XOR the contents of segment 310_1 of data page P1 in block B0 of each data plane 212_1 to 212_2A to generate a specific pattern 910. That is, the microprocessor 112 or decoder 134 sequentially XORs the data D0 of data page P1 in block B0 of each data plane 212_1 to 212_2A to generate data D0 of specific pattern 910, sequentially XORs the data D1 of data page P1 in block B0 of each data plane 212_1 to 212_2A to generate data D1 of specific pattern 910, and so on. It should be noted that in... Figure 9 In each embodiment, if the segment can be successfully decoded by the decoder 134, the content of the segment used to calculate the specific pattern 910 can be the decoded data (i.e., the correct data) or the data before decoding (i.e., the data containing a small number of error bits); and if the segment is a UECC segment, the content of the segment used to calculate the specific pattern 910 is the data before decoding.

[0061] In step 528, the microprocessor 112 or the decoder 134 determines the possible erroneous bits in the aforementioned UECC segment based on the specific pattern 910. Figure 9 In the embodiments, while referring to Figure 4 Since the data page P1 of block B0 in each data plane 212_2A is used to store the result of the XOR operation of data page P1 of block B0 in data planes 212_1 to 210_(2A-1), if all segments 310_1 can be successfully decoded, then every piece of data in specific pattern 910 will be "0". Therefore, if a "1" appears in specific pattern 910, it means that the corresponding data in the above segment may be incorrect. Specifically, assuming that the data D0 of specific pattern 910 is "1", it means that at least one data D0 in the data page P1 of block B0 in data planes 212_1 to 212_2A is incorrect. Therefore, the microprocessor 112 or the decoder 134 can determine multiple specific data that may be erroneous bits in the UECC segment based on the data with "1" in the specific pattern 910. That is, if the data D0 in the specific pattern 910 is "1", then the UECC segment judged in steps 506 and 512, and the value of the data D0 of the UECC segment judged in steps 514 to 524 may be erroneous.

[0062] In step 530, decoder 134 adjusts the soft information of at least a plurality of specific data in the UECC segment to generate adjusted soft information, wherein the adjusted soft information selectively and significantly reduces the reliability of the hard information of each specific data compared to the original soft information. For example, while referring to... Figure 8 Regarding its related content, assuming that the hard information, first soft bit, and second soft bit of a specific data in the UECC segment are (1,1,1), then the adjusted first soft bit and adjusted second soft bit contained in the hard information and the adjusted soft information can be (1,0,0) respectively.

[0063] In one embodiment, since the data in the UECC segment corresponding to a specific pattern 910 that is "0" also has a low probability of being erroneous, the decoder 134 can also adjust the soft information of the other data in the UECC segment besides the multiple specific data (i.e., the data corresponding to the specific pattern 910 that is "0") to generate adjusted soft information, wherein the adjusted soft information selectively and slightly reduces the reliability of the hard information of each data item compared to the original soft information. For example, while referring to... Figure 8Regarding its related content, assuming that the hard information, first soft bit, and second soft bit of a piece of data in the UECC segment are (1,1,1), then the adjusted first soft bit and adjusted second soft bit contained in the hard information and the adjusted soft information can be (1,1,0) respectively.

[0064] In step 532, decoder 134 uses the adjusted soft information of the UECC segment to decode the UECC segment again to obtain decoded data.

[0065] about Figure 7 The operations in steps 534, 536, and 538 of the process shown are the same as those in steps 514, 516, and 518, and therefore will not be described again. In step 540, it is determined whether there are two other segments that are also UECC segments and whose symptoms or symptom weights are greater than the symptom threshold during the data processing of the corresponding segments of the UECC segment located on other data planes in step 514. If yes, the process proceeds to step 542; otherwise, the process proceeds to step 544. Furthermore, the operations in steps 542 to 552 are the same as those in steps 522 to 532, and therefore will not be described again.

[0066] In the embodiments described above regarding Figures 5-7, steps 528-532 and 518-552 are performed on the UECC segments identified in steps 506 and 512, but the present invention is not limited thereto. In other embodiments, since other UECC segments may be identified in steps 514-524 or 534-544, the operations of steps 528-532 and 518-552 can also process these other UECC segments simultaneously to accelerate the overall execution efficiency.

[0067] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A control method for a memory device, wherein the memory device includes a flash memory module, the flash memory module includes multiple data planes, each data plane includes multiple blocks, each block includes multiple data pages, each data page includes multiple segments, and the control method includes: Read and decode a first data from a first segment, wherein the first segment is located in a first data page in a super data page, and the super data page contains multiple data pages located in the multiple data planes respectively; If the decoding of the first segment fails, data from multiple corresponding segments of the first segment are obtained, wherein the multiple corresponding segments are located in other data pages of the super data page besides the first data page; If the data in the multiple corresponding segments can be successfully decoded, the decoded data of the first segment is generated based on the multiple decoded data from the multiple corresponding segments; and If not all of the data in the multiple corresponding segments can be successfully decoded, the decision to abandon the decoding operation for the first segment is made based on the syndrome weight of the first segment and the syndrome weight of at least one corresponding segment that cannot be successfully decoded among the multiple corresponding segments.

2. The control method as described in claim 1, characterized in that, If not all data in the multiple corresponding segments can be successfully decoded, the steps for deciding whether to abandon the decoding operation on the first segment based on the symptom weight of the first segment and the symptom weight of at least one corresponding segment that failed to be decoded include: If at least two of the first segment and the corresponding segments have a symptom weight greater than a symptom threshold, the decoding operation for the first segment is abandoned; and If the number of segments in the first segment and the multiple corresponding segments whose symptom weight is greater than the symptom threshold is less than two, the content of the first data is adjusted to generate an adjusted first data, and the adjusted first data is decoded.

3. The control method as described in claim 2, characterized in that, The steps of adjusting the content of the first data to generate the adjusted first data and decoding the adjusted first data include: A specific pattern is generated based on the first data of the first segment and the data of the plurality of corresponding segments, wherein the specific pattern indicates which bit in the first data of the first segment may be erroneous; as well as The content of the first data is adjusted according to the specific pattern.

4. The control method as described in claim 3, characterized in that, The step of generating the specific pattern based on the first data of the first segment and the data of the plurality of corresponding segments includes: The first data of the first segment and the data of the multiple corresponding segments are subjected to a mutually exclusive OR (XOR) operation to generate the specific pattern.

5. The control method as described in claim 3, characterized in that, The first data includes multiple hard information and multiple soft information corresponding to multiple memory cells, and the step of adjusting the content of the first data according to the specific pattern includes: The specific pattern is used to adjust at least a portion of the soft information in the first data to reduce the reliability of the corresponding hard information represented by the at least a portion of the soft information.

6. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprising multiple data planes, each data plane comprising multiple blocks, each block comprising multiple data pages, each data page comprising multiple segments, and the flash memory controller comprising: A read-only memory is used to store a program code; A buffer memory; and A microprocessor is used to execute the program code to control access to the flash memory module; The microprocessor is used to perform the following operations: Read and decode a first data from a first segment, wherein the first segment is located in a first data page in a super data page, and the super data page contains multiple data pages located in the multiple data planes respectively; If the decoding of the first segment fails, data from multiple corresponding segments of the first segment are obtained, wherein the multiple corresponding segments are located in other data pages of the super data page besides the first data page; If the data in the multiple corresponding segments can be successfully decoded, the decoded data of the first segment is generated based on the multiple decoded data from the multiple corresponding segments; and If not all of the data in the multiple corresponding segments can be successfully decoded, the decision to abandon the decoding operation for the first segment is made based on the syndrome weight of the first segment and the syndrome weight of at least one corresponding segment that cannot be successfully decoded among the multiple corresponding segments.

7. The flash memory controller as described in claim 6, characterized in that, If not all data in the multiple corresponding segments can be successfully decoded, the steps for deciding whether to abandon the decoding operation on the first segment based on the symptom weight of the first segment and the symptom weight of at least one corresponding segment that failed to be decoded include: If at least two of the first segment and the corresponding segments have a symptom weight greater than a symptom threshold, the decoding operation for the first segment is abandoned; and If the number of segments in the first segment and the multiple corresponding segments whose symptom weight is greater than the symptom threshold is less than two, the content of the first data is adjusted to generate an adjusted first data, and the adjusted first data is decoded.

8. The flash memory controller as described in claim 7, characterized in that, The steps of adjusting the content of the first data to generate the adjusted first data and decoding the adjusted first data include: A specific pattern is generated based on the first data of the first segment and the data of the plurality of corresponding segments, wherein the specific pattern indicates which bit in the first data of the first segment may be erroneous; as well as The content of the first data is adjusted according to the specific pattern.

9. The flash memory controller as described in claim 8, characterized in that, The step of generating the specific pattern based on the first data of the first segment and the data of the plurality of corresponding segments includes: The first data of the first segment and the data of the multiple corresponding segments are subjected to a mutually exclusive OR (XOR) operation to generate the specific pattern.

10. The flash memory controller as described in claim 8, characterized in that, The first data includes multiple hard information and multiple soft information corresponding to multiple memory cells, and the step of adjusting the content of the first data according to the specific pattern includes: The specific pattern is used to adjust at least a portion of the soft information in the first data to reduce the reliability of the corresponding hard information represented by the at least a portion of the soft information.

11. A memory device comprising: A flash memory module, wherein the flash memory module includes multiple data planes, each data plane includes multiple blocks, each block includes multiple data pages, and each data page includes multiple segments; and A flash memory controller for accessing the flash memory module; The flash memory controller performs the following operations: Read and decode a first data from a first segment, wherein the first segment is located in a first data page in a super data page, and the super data page contains multiple data pages located in the multiple data planes respectively; If the decoding of the first segment fails, data from multiple corresponding segments of the first segment are obtained, wherein the multiple corresponding segments are located in other data pages of the super data page besides the first data page; If the data in the multiple corresponding segments can be successfully decoded, the decoded data of the first segment is generated based on the multiple decoded data from the multiple corresponding segments; and If not all of the data in the multiple corresponding segments can be successfully decoded, the decision to abandon the decoding operation for the first segment is made based on the syndrome weight of the first segment and the syndrome weight of at least one corresponding segment that cannot be successfully decoded among the multiple corresponding segments.

12. The memory device as claimed in claim 11, characterized in that, If not all data in the multiple corresponding segments can be successfully decoded, the steps for deciding whether to abandon the decoding operation on the first segment based on the symptom weight of the first segment and the symptom weight of at least one corresponding segment that failed to be decoded include: If at least two of the first segment and the corresponding segments have a symptom weight greater than a symptom threshold, the decoding operation for the first segment is abandoned; and If the number of segments in the first segment and the multiple corresponding segments whose symptom weight is greater than the symptom threshold is less than two, the content of the first data is adjusted to generate an adjusted first data, and the adjusted first data is decoded.

13. The memory device as claimed in claim 12, characterized in that, The steps of adjusting the content of the first data to generate the adjusted first data and decoding the adjusted first data include: A specific pattern is generated based on the first data of the first segment and the data of the plurality of corresponding segments, wherein the specific pattern indicates which bit in the first data of the first segment may be erroneous; as well as The content of the first data is adjusted according to the specific pattern.

14. The memory device as claimed in claim 13, characterized in that, The step of generating the specific pattern based on the first data of the first segment and the data of the plurality of corresponding segments includes: The first data of the first segment and the data of the multiple corresponding segments are subjected to a mutually exclusive OR (XOR) operation to generate the specific pattern.

15. The memory device as claimed in claim 13, characterized in that, The first data includes multiple hard information and multiple soft information corresponding to multiple memory cells, and the step of adjusting the content of the first data according to the specific pattern includes: The specific pattern is used to adjust at least a portion of the soft information in the first data to reduce the reliability of the corresponding hard information represented by the at least a portion of the soft information.

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