A DDR controller error checking and retransmission system

Abstract

The invention relates to a processor microstructure, and in particular to a DDR controller check error retransmission system, comprising a DDR controller DDRC, a DDR physical layer DDR PHY and a DDR particle DRAM, wherein the DDR controller DDRC comprises a controller, a retransmission FIFO, a data selector MUX1, a command address register, a write data cache, a data selector MUX2, a read data register group, a read data valid register group and a read tag processing module, wherein the read tag processing module comprises a data selector MUX3, a read tag FIFO1, a read tag FIFO2, an equal comparator and an AND gate; the technical solution provided by the invention can effectively overcome the defects of the prior art that the check error can only be retransmitted once, the hardware structure is complex, and the read command transmission efficiency is low.

Description

Technical Field

[0001] The invention relates to a processor microstructure, and in particular to a DDR controller check error retransmission system. Background Art

[0002] In DDR particle DRAM, in order to ensure the correctness of the signal transmitted from the DDR controller DDRC, there are two forms of verification, namely, the parity check (CA Parity) of the command address and the CRC check of the write data. When any of the above two checks is wrong, the DDR particle DRAM will pull the output signal Alert_n low to notify the upstream DDR controller DDRC of the verification error. At this time, the DDR controller DDRC needs to take certain remedial measures to handle the error.

[0003] In the prior art, the most effective way for the DDR controller DDRC to handle command address parity errors and write data CRC errors is retransmission, that is, resending the command address and write data and other information corresponding to the parity error. The existing retransmission scheme is to put a FIFO with a sufficiently large depth in the DDR controller DDRC to store the command address and write data and other information sent by the DDR controller DDRC; each FIFO address is configured with a countdown timer, and the initial value of the countdown timer is the maximum number of cycles from the issuance of all different types of commands to the receipt of the corresponding DFI bus signal Dfi_alert_n return; when new data is written to an address in the FIFO, the countdown timer corresponding to the address will start counting down from the initial value. Once the timer value reaches 0, it means that the command and other information corresponding to the address are correctly transmitted to the DDR particle DRAM, and the FIFO address can receive new data at this time.

[0004] When a checksum error occurs, the DFI bus signal Dfi_alert_n will be pulled low, the DDR controller DDRC stops writing new data to the FIFO, and all countdown timers in the FIFO stop counting. At this time, the DDR controller DDRC selects to send the data corresponding to the address in the FIFO whose countdown value is not 0. If the checksum error signal is not detected within a period of time after the data is transmitted, the DDR controller DDRC and FIFO will return to normal working state and successfully handle the error; if these data are still wrong during the transmission process, since the relevant data in the FIFO has been taken out and cannot be retransmitted again, further software intervention is required.

[0005] In addition, when processing a read command, a delay needs to be added to the returned Dfi_rddata value, so that the read data of the read command corresponding to the address with a countdown value other than 0 is returned after the DFI bus signal Dfi_alert_n is pulled low, so that the DDR controller DDRC discards the read data; and the read data of the read command corresponding to the address with a countdown value of 0 needs to be returned before the DFI bus signal Dfi_alert_n is pulled low, so that the DDR controller DDRC receives the read data. By adding a delay to the read data path, it is prevented that the read data corresponding to the same read command before and after retransmission is received multiple times or the read data corresponding to the read command that is not within the retransmission range cannot be received, thereby avoiding errors in the DDR controller DDRC when processing read commands.

[0006] In the prior art, although the DDR controller DDRC implements the functions of command address parity check and write data CRC check error retransmission, it can only be retransmitted once. When the check error occurs again during the retransmission process, the hardware cannot continue to correct it, so software intervention is required, which greatly reduces the transmission efficiency. At the same time, the implementation of the countdown timer function in the FIFO will increase the difficulty of circuit design, increase the number of hardware logic units, and increase the area. In addition, since it is necessary to consider the extreme situation where the two checks exist at the same time, the number of delay cycles that need to be added when the read data is returned is relatively large, thereby reducing the transmission efficiency of the read command. Summary of the invention

[0007] In view of the above shortcomings of the prior art, the present invention provides a DDR controller check error retransmission system, which can effectively overcome the defects of the prior art that a check error can only be retransmitted once, the hardware structure is complex, and the read command transmission efficiency is low.

[0008] To achieve the above objectives, the present invention is implemented through the following technical solutions:

[0009] A DDR controller check error retransmission system includes a DDR controller DDRC, a DDR physical layer DDR PHY and a DDR particle DRAM, wherein the DDR controller DDRC includes:

[0010] The controller is used to generate a command Cmd, an address Addr, write data Wr data and a read tag Rd token, and receive read data Rd data;

[0011] Retransmission FIFO is used to store the command Cmd, address Addr, write data Wr data and read tag Rdtoken sent by the controller. It is also the information source of the command Cmd and address Addr required for retransmission after a verification error occurs.

[0012] A data selector MUX1 is used to select an input signal of a controller / retransmission FIFO as an output signal;

[0013] The command address register is used to store the command Cmd and address Addr output by the data selector MUX1, and transmit them to the DDR physical layer DDR PHY through the DFICA bus;

[0014] A write data cache, used to store the write data Wr data output by the data selector MUX1;

[0015] The data selector MUX2 is used to select the write data cache data / invalid data as the output signal and transmit it to the DDR physical layer DDR PHY through the Dfi_wrdata bus;

[0016] The read data register group is used to store the Dfi_rddata value returned by the DDR physical layer DDR PHY, and register M beats, that is, the read data Rd_data corresponding to the Dfi_rddata value is delayed for M cycles and then transmitted to the controller;

[0017] The read data valid register group is used to store the read data valid value Dfi_rddata_valid returned by the DDR physical layer DDR PHY, and registers M beats, that is, the read data valid value Dfi_rddata_valid is delayed for M cycles and then transmitted to the data selector MUX3;

[0018] The read tag processing module is used to process the value of the read data valid register group and generate read pointer data Rd_token_out_1 and a read data valid signal Rd_data_valid to the controller.

[0019] Preferably, the tag reading processing module includes:

[0020] A data selector MUX3 is used to select the value / invalid value of the read data valid register group as an output signal;

[0021] Read tag FIFO1 is used to store the read tag Rd token sent by the controller only when the system is in normal working state and receives the read command Rdcmd sent by the controller. When the system is in retransmission state, no new data is stored, and the current read pointer data Rd_token_out_1 is output to the controller and the equal comparator; when the last beat read data valid signal Rddata_last_en obtained after the output signal of the data selector MUX3 is processed is high level, and the output signal Is_eq of the equal comparator is high level, the current read pointer is increased by 1, so as to output the next data;

[0022] Read tag FIFO2 is used to store the read tag Rd token output by the data selector MUX1 when receiving the read command Rd cmd output by the data selector MUX1. It is valid when the system is in normal working state / retransmission state, and outputs the current read pointer data Rd_token_out_2 to the equal comparator; when the last beat read data valid signal Rddata_last_en is high level, the current read pointer is increased by 1, so as to output the next data;

[0023] The equal comparator is used to compare the current read pointer data Rd_token_out_1 output by the read tag FIFO1 with the current read pointer data Rd_token_out_2 output by the read tag FIFO2. When the two values ​​are equal, the output signal Is_eq is high level;

[0024] The AND gate is used to AND the last beat read data valid signal Rddata_last_en and the output signal Is_eq of the comparator to control whether the read pointer of the read tag FIFO1 is increased by 1.

[0025] Preferably, each unit entry inside the retransmission FIFO stores the command Cmd, address Addr, write data Wr data and read tag Rd token sent by the controller, and includes three pointers, namely, pointer wr_p, pointer rd_p and pointer ini_p;

[0026] Pointer wr_p points to the target address of the next write data Wr data. When Push is performed, the data at the address pointed to by pointer wr_p is written in this cycle, and then pointer wr_p is incremented by 1.

[0027] Pointer rd_p points to the target address of the current read data Rd_data. When Pop is executed, the data at the address pointed to by pointer rd_p is output in this cycle, and then pointer rd_p is incremented by 1.

[0028] The pointer ini_p is the same as the pointer rd_p when the system is in a non-retransmission state. When the retransmission cycle is started, it is fixed to point to the read start address within the retransmission cycle. If a check error occurs again within the retransmission cycle, the pointer rd_p is moved to the address pointed to by the pointer ini_p as the read start address within the next retransmission cycle.

[0029] Preferably, the operation mode of the retransmission FIFO includes:

[0030] When there is no retransmission request, when the retransmission FIFO is full of data, if you continue to push, the pointers wr_p, rd_p and ini_p will increase together. At this time, the full flag will be ignored, and the data in the retransmission FIFO will continue to be updated and will always be full.

[0031] When executing a retransmission request, the pointers wr_p and ini_p remain unchanged, and the pointer rd_p increases with Pop until rd_p=wr_p is satisfied. At this time, all valid data in the retransmission FIFO has completed a Pop; after waiting for a certain delay, if the DFI bus signal Dfi_alert_n is not pulled low again, the retransmission is completed, otherwise the pointer rd_p is moved to the address pointed to by the pointer ini_p to start the next retransmission.

[0032] Preferably, the method for calculating the depth N of the retransmission FIFO includes:

[0033] There are two situations for command address parity timing:

[0034] 1) When T5 ≥ T4, the read data Rd_data corresponding to the read command RDm+1 is returned before the DFI bus signal Dfi_alert_n is pulled low. Since the read command RDm+1 is within the tPAR_UNKNOWN time, the corresponding read data Rd_data should be invalid data. It is necessary to delay the read data Rd_data and the read data valid value Dfi_rddata_valid for M cycles, so that the read data Rd_data is moved to the DFI bus signal Dfi_alert_n after it is pulled low and returned. At this time, the depth N of the retransmission FIFO should be greater than or equal to the maximum number of cycles corresponding to T5;

[0035] 2) When T5<T4, the read data Rd_data corresponding to the read command RDm is returned after the DFI bus signal Dfi_alert_n is pulled low, and the read data Rd_data is discarded. Therefore, the read command RDm needs to be retransmitted and must be included in the retransmission FIFO, that is, within the tMARGIN time. At this time, tMARGIN should be greater than or equal to the number of cycles corresponding to (T4-T5+T6), and the depth N of the retransmission FIFO should be greater than or equal to the maximum number of cycles corresponding to (T4+T6);

[0036] For write data CRC check timing:

[0037] The write data CRC check corresponding to the write command WRm is wrong. At this time, the depth N of the retransmission FIFO should be greater than or equal to the maximum number of cycles corresponding to T8;

[0038] Considering the three situations corresponding to the command address parity check timing and the command address parity check timing, it is found that the depth N of the retransmission FIFO should take the maximum value of the three maximum cycle numbers, that is, the maximum cycle number corresponding to N=MAX(T5,T4+T6,T8);

[0039] Among them, T5 = tPAR_UNKNOWN + T1 + tPAR_ALERT_ON + T3;

[0040] tPAR_UNKNOWN is the uncertain time of command address parity error, which is defined in the standard protocol and its maximum value is the parity delay PL;

[0041] T1 is the delay time of the command signal from the DFI bus to the DDR particle DRAM, and its value is determined by the DDR physical layer DDR PHY delay and PCB board delay;

[0042] tPAR_ALERT_ON is the time when the command address parity error occurs, which is defined in the standard protocol and its maximum value is the parity delay PL + 6ns;

[0043] T3 is the delay time of the output signal Alert_n of the DDR particle DRAM from the DDR particle DRAM to the DFI bus, and its value is determined by the DDR physical layer DDR PHY delay and the PCB board delay;

[0044] T4=T1+RL+T2;

[0045] RL is the time corresponding to the number of cycles from read command to read data in DDR particle DRAM, which is defined in the standard protocol. Its maximum value is determined by the specific model of DDR particle DRAM.

[0046] T2 is the delay time of reading data from DDR DRAM to DFI bus, and its value is determined by DDR PHY delay and PCB board delay.

[0047] tMARGIN is the time corresponding to the error tolerance margin of the retransmission FIFO depth N;

[0048] T6 is the time corresponding to the maximum number of valid cycles for reading data;

[0049] T8=T1+WL+T7+tCRC_ALERT+T3;

[0050] WL is the time corresponding to the number of cycles from write command to write data in DDR particle DRAM, which is defined in the standard protocol. Its maximum value is determined by the specific model of DDR particle DRAM;

[0051] T7 is the time corresponding to the maximum valid number of cycles of writing data plus CRC value;

[0052] tCRC_ALERT is the time when a write data CRC check error occurs. It is defined in the standard protocol and its maximum value is 13ns.

[0053] Preferably, when the system is in a normal working state, the data selector MUX1 selects the input signal of the controller as the output signal;

[0054] When the system is in the retransmission state, the data selector MUX1 selects the input signal of the retransmission FIFO as the output signal.

[0055] Preferably, when the command address register outputs a write command Wr cmd, the data selector MUX2 selects the write data cache data as the output signal;

[0056] When the command address register outputs a non-write command, the data selector MUX2 selects invalid data as an output signal.

[0057] Preferably, the read data register group consists of M read data registers, and the read data valid register group consists of M read data valid registers, corresponding to the read data Rd_data and the read data valid value Dfi_rddata_valid being delayed by M cycles;

[0058] The calculation method of M value includes:

[0059] 1) When T5 ≥ T4, M is the number of cycles corresponding to (T5-T4), that is, the number of cycles corresponding to (tPAR_UNKNOWN+tPAR_ALERT_ON+T3-RL-T2);

[0060] 2) When T5<T4, M is 0 cycle number.

[0061] Preferably, when the DFI bus signal Dfi_alert_n is at a high level, the data selector MUX3 selects the value of the read data valid register group as the output signal;

[0062] When the DFI bus signal Dfi_alert_n is at a low level, the data selector MUX3 selects the read data invalid value as the output signal to discard the currently returned read data valid value Dfi_rddata_valid when a verification error occurs, so that the corresponding read data Rd_data cannot be received by the controller.

[0063] Preferably, the DDR controller DDRC communicates and interacts with the DDR physical layer DDR PHY via a DFI bus, and the DDR physical layer DDR PHY communicates and interacts with the DDR particles DRAM via a CA bus and a DATA bus.

[0064] Compared with the prior art, the DDR controller check error retransmission system provided by the present invention supports multiple retransmissions when command address parity check errors and write data CRC check errors occur, and by redefining the function of the retransmission FIFO, the complexity of circuit design is reduced, the number of hardware logic units and the hardware area are effectively reduced, and at the same time, the additional delay on the read data path is small, so that the transmission efficiency of the read command is basically not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0066] Figure 1 It is a system schematic diagram of the present invention;

[0067] Figure 2 For the present invention Figure 1 The circuit diagram of DDR controller DDRC;

[0068] Figure 3 For the present invention Figure 2 Schematic diagram of the structure of the retransmission FIFO;

[0069] Figure 4 It is a schematic diagram of the operation mode of the retransmission FIFO in the present invention when there is no retransmission request;

[0070] Figure 5 It is a schematic diagram of the operation mode of the retransmission FIFO in the present invention when executing a retransmission request;

[0071] Figure 6 The timing of the command address parity check in the present invention Figure 1 ;

[0072] Figure 7 The timing of the command address parity check in the present invention Figure 2 ;

[0073] Figure 8 This is a timing diagram of the CRC check of write data in the present invention. DETAILED DESCRIPTION

[0074] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0075] A DDR controller check error retransmission system, such as Figure 1 and Figure 2 As shown, it includes a DDR controller DDRC, a DDR physical layer DDR PHY and a DDR particle DRAM. The DDR controller DDRC includes:

[0076] The controller is used to generate a command Cmd, an address Addr, write data Wr data and a read tag Rd token, and receive read data Rd data;

[0077] Retransmission FIFO is used to store the command Cmd, address Addr, write data Wr data and read tag Rdtoken sent by the controller. It is also the information source of the command Cmd and address Addr required for retransmission after a verification error occurs.

[0078] A data selector MUX1 is used to select an input signal of a controller / retransmission FIFO as an output signal;

[0079] The command address register is used to store the command Cmd and address Addr output by the data selector MUX1, and transmit them to the DDR physical layer DDR PHY through the DFICA bus;

[0080] A write data cache, used to store the write data Wr data output by the data selector MUX1;

[0081] The data selector MUX2 is used to select the write data cache data / invalid data as the output signal and transmit it to the DDR physical layer DDR PHY through the Dfi_wrdata bus;

[0082] The read data register group is used to store the Dfi_rddata value returned by the DDR physical layer DDR PHY, and register M beats, that is, the read data Rd_data corresponding to the Dfi_rddata value is delayed for M cycles and then transmitted to the controller;

[0083] The read data valid register group is used to store the read data valid value Dfi_rddata_valid returned by the DDR physical layer DDR PHY, and registers M beats, that is, the read data valid value Dfi_rddata_valid is delayed for M cycles and then transmitted to the data selector MUX3;

[0084] The read tag processing module is used to process the value of the read data valid register group and generate read pointer data Rd_token_out_1 and a read data valid signal Rd_data_valid to the controller.

[0085] In the technical solution of this application, the tag reading processing module includes:

[0086] A data selector MUX3 is used to select the value / invalid value of the read data valid register group as an output signal;

[0087] Read tag FIFO1 is used to store the read tag Rd token sent by the controller only when the system is in normal working state and receives the read command Rdcmd sent by the controller. When the system is in retransmission state, no new data is stored, and the current read pointer data Rd_token_out_1 is output to the controller and the equal comparator; when the last beat read data valid signal Rddata_last_en obtained after the output signal of the data selector MUX3 is processed is high level, and the output signal Is_eq of the equal comparator is high level, the current read pointer is increased by 1, so as to output the next data;

[0088] Read tag FIFO2 is used to store the read tag Rd token output by the data selector MUX1 when receiving the read command Rd cmd output by the data selector MUX1. It is valid when the system is in normal working state / retransmission state, and outputs the current read pointer data Rd_token_out_2 to the equal comparator; when the last beat read data valid signal Rddata_last_en is high level, the current read pointer is increased by 1, so as to output the next data;

[0089] The equal comparator is used to compare the current read pointer data Rd_token_out_1 output by the read tag FIFO1 with the current read pointer data Rd_token_out_2 output by the read tag FIFO2. When the two values ​​are equal, the output signal Is_eq is high level;

[0090] The AND gate is used to AND the last beat read data valid signal Rddata_last_en and the output signal Is_eq of the comparator to control whether the read pointer of the read tag FIFO1 is increased by 1.

[0091] In the technical solution of this application, if Figure 1 As shown, the DDR controller DDRC communicates with the DDR physical layer DDR PHY through the DFI bus, and the DDR physical layer DDR PHY communicates with the DDR particle DRAM through the CA bus and the DATA bus.

[0092] In the technical solution of this application, the read tag Rd token signal is introduced to solve the problem that the read data corresponding to the same read command is returned to the controller multiple times during normal operation and retransmission. Figure 6 As shown, during normal operation or retransmission, before the DFI bus signal Dfi_alert_n is pulled low, the read data corresponding to the read command RDm is valid and successfully returned to the controller; after the DFI bus signal Dfi_alert_n is pulled low, the system performs the next retransmission, and all commands inside the retransmission FIFO are re-executed. At this time, the DDR particle DRAM will return the corresponding read data again after receiving the read command RDm. If the read data is not intercepted, it will cause the same read command to have the problem of multiple read data returns. Therefore, the technical solution of the present application introduces the read tag Rd token signal.

[0093] When the read data corresponding to the read command RDm is successfully returned to the controller for the first time, the read tag FIFO1 will pop out the tag corresponding to the read command RDm. When the read command RDm is retransmitted later and returns valid read data again, its corresponding tag does not exist in the read tag FIFO1, making the Rd_token_out_1 value and the Rd_token_out_2 value unequal. The read data valid signal Rd_data_valid sent to the controller is low, thereby intercepting the read data. Ultimately, the same read command can only return valid read data once before and after the retransmission.

[0094] No special processing is required for write commands, because the write data is sent from the DDR controller DDRC to the DDR particle DRAM. The write command and its corresponding write data will be stored in the retransmission FIFO at the same time. During retransmission, the write command and write data will be sent again, so that the DDR particle DRAM will overwrite the previously received write data, which has no effect on the result. This is also true for multiple retransmissions.

[0095] like Figure 3 As shown, each unit entry inside the retransmission FIFO stores the command Cmd, address Addr, write data Wr data and read tag Rd token sent by the controller, and contains three pointers, namely pointer wr_p, pointer rd_p and pointer ini_p;

[0096] Pointer wr_p points to the target address of the next write data Wr data. When Push is performed, the data at the address pointed to by pointer wr_p is written in this cycle, and then pointer wr_p is incremented by 1.

[0097] Pointer rd_p points to the target address of the current read data Rd_data. When Pop is executed, the data at the address pointed to by pointer rd_p is output in this cycle, and then pointer rd_p is incremented by 1.

[0098] The pointer ini_p is the same as the pointer rd_p when the system is in a non-retransmission state. When the retransmission cycle is started, it is fixed to point to the read start address within the retransmission cycle. If a check error occurs again within the retransmission cycle, the pointer rd_p is moved to the address pointed to by the pointer ini_p as the read start address within the next retransmission cycle.

[0099] In the technical solution of the present application, the operation mode of the retransmission FIFO includes:

[0100] When there is no retransmission request, Figure 4 As shown in the figure, when the retransmission FIFO is full of data, if you continue to push, the pointers wr_p, rd_p and ini_p will increase together. At this time, the full flag will be ignored. At the same time, the data inside the retransmission FIFO will continue to be updated and will always be full.

[0101] When executing a retransmission request, if Figure 5 As shown, the pointers wr_p and ini_p remain unchanged, and the pointer rd_p increases with Pop until rd_p=wr_p is satisfied. At this time, all valid data in the retransmission FIFO has completed a Pop. After waiting for a certain delay, if the DFI bus signal Dfi_alert_n is not pulled low again, the retransmission ends, otherwise the pointer rd_p is moved to the address pointed to by the pointer ini_p to start the next retransmission.

[0102] In the technical solution of the present application, the method for calculating the depth N of the retransmission FIFO includes:

[0103] There are two situations for command address parity timing:

[0104] 1) When T5 ≥ T4, if Figure 6As shown, the read data Rd_data corresponding to the read command RDm+1 is returned before the DFI bus signal Dfi_alert_n is pulled low. Since the read command RDm+1 is within the tPAR_UNKNOWN time, the corresponding read data Rd_data should be invalid data. It is necessary to delay the read data Rd_data and the read data valid value Dfi_rddata_valid for M cycles, so that the read data Rd_data is moved to the DFI bus signal Dfi_alert_n after it is pulled low and returned. At this time, the depth N of the retransmission FIFO should be greater than or equal to the maximum number of cycles corresponding to T5.

[0105] 2) When T5<T4, if Figure 7 As shown, the read data Rd_data corresponding to the read command RDm is returned after the DFI bus signal Dfi_alert_n is pulled low, and the read data Rd_data is discarded. Therefore, the read command RDm needs to be retransmitted and must be included in the retransmission FIFO, that is, within the tMARGIN time. At this time, tMARGIN should be greater than or equal to the number of cycles corresponding to (T4-T5+T6), and the depth N of the retransmission FIFO should be greater than or equal to the maximum number of cycles corresponding to (T4+T6);

[0106] For write data CRC check timing:

[0107] The write data CRC check corresponding to the write command WRm is wrong, such as Figure 8 As shown, at this time, the depth N of the retransmission FIFO should be greater than or equal to the maximum number of cycles corresponding to T8;

[0108] Considering the three situations corresponding to the command address parity check timing and the command address parity check timing, it is found that the depth N of the retransmission FIFO should take the maximum value of the three maximum cycle numbers, that is, the maximum cycle number corresponding to N=MAX(T5,T4+T6,T8);

[0109] Among them, T5 = tPAR_UNKNOWN + T1 + tPAR_ALERT_ON + T3;

[0110] tPAR_UNKNOWN is the uncertain time of command address parity error, which is defined in the standard protocol and its maximum value is the parity delay PL;

[0111] T1 is the delay time of the command signal from the DFI bus to the DDR particle DRAM, and its value is determined by the DDR physical layer DDR PHY delay and PCB board delay;

[0112] tPAR_ALERT_ON is the time when the command address parity error occurs, which is defined in the standard protocol and its maximum value is the parity delay PL + 6ns;

[0113] T3 is the delay time of the output signal Alert_n of the DDR particle DRAM from the DDR particle DRAM to the DFI bus, and its value is determined by the DDR physical layer DDR PHY delay and the PCB board delay;

[0114] T4=T1+RL+T2;

[0115] RL is the time corresponding to the number of cycles from read command to read data in DDR particle DRAM, which is defined in the standard protocol. Its maximum value is determined by the specific model of DDR particle DRAM.

[0116] T2 is the delay time of reading data from DDR DRAM to DFI bus, and its value is determined by DDR PHY delay and PCB board delay.

[0117] tMARGIN is the time corresponding to the error tolerance margin of the retransmission FIFO depth N;

[0118] T6 is the time corresponding to the maximum number of valid cycles for reading data;

[0119] T8=T1+WL+T7+tCRC_ALERT+T3;

[0120] WL is the time corresponding to the number of cycles from write command to write data in DDR particle DRAM, which is defined in the standard protocol. Its maximum value is determined by the specific model of DDR particle DRAM;

[0121] T7 is the time corresponding to the maximum valid number of cycles of writing data plus CRC value;

[0122] tCRC_ALERT is the time when a write data CRC check error occurs. It is defined in the standard protocol and its maximum value is 13ns.

[0123] For data selector MUX1:

[0124] When the system is in normal working state, the data selector MUX1 selects the input signal of the controller as the output signal;

[0125] When the system is in the retransmission state, the data selector MUX1 selects the input signal of the retransmission FIFO as the output signal.

[0126] For data selector MUX2:

[0127] When the command address register outputs the write command Wr cmd, the data selector MUX2 selects the write data cache data as the output signal;

[0128] When the command address register outputs a non-write command, the data selector MUX2 selects invalid data as the output signal.

[0129] The read data register group is composed of M read data registers, and the read data valid register group is composed of M read data valid registers, corresponding to the read data Rd_data and the read data valid value Dfi_rddata_valid being delayed by M cycles;

[0130] The calculation method of M value includes:

[0131] 1) When T5 ≥ T4, M is the number of cycles corresponding to (T5-T4), that is, the number of cycles corresponding to (tPAR_UNKNOWN+tPAR_ALERT_ON+T3-RL-T2);

[0132] 2) When T5<T4, M is 0 cycle number.

[0133] It can be seen from the calculation formula of the above M value that the values ​​of each time parameter used are determined by the standard protocol or specific hardware equipment. Once the hardware equipment used is determined, the M value can be uniquely calculated, so that the additional delay on the read data path is small and the transmission efficiency of the read command is basically unaffected.

[0134] For data selector MUX3:

[0135] When the DFI bus signal Dfi_alert_n is at a high level, the data selector MUX3 selects the value of the read data valid register group as the output signal;

[0136] When the DFI bus signal Dfi_alert_n is at a low level, the data selector MUX3 selects the read data invalid value as the output signal to discard the currently returned read data valid value Dfi_rddata_valid when a verification error occurs, so that the corresponding read data Rd_data cannot be received by the controller.

[0137] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A DDR controller error checking and retransmission system, characterized in that: It includes a DDR controller DDRC, a DDR physical layer DDRPHY and a DDR particle DRAM, and the DDR controller DDRC includes: The controller is used to generate a command Cmd, an address Addr, write data Wr data and a read tag Rd token, and receive read data Rd data; The retransmission FIFO is used to store the command Cmd, address Addr, write data Wr data and read tag Rdtoken sent by the controller, and contains three pointers, namely pointer wr_p, pointer rd_p and pointer ini_p, which are used to realize the multiple retransmission function; In the non-retransmission state, the pointers ini_p and rd_p point to the same address. When the retransmission FIFO is full of data, if Push continues, the pointers wr_p, rd_p, and ini_p will increase together, and the data in the retransmission FIFO will be continuously updated. When executing a retransmission request, the pointers wr_p and ini_p remain unchanged, and the pointer rd_p starts from the address pointed to by the pointer ini_p and increases with Pop until rd_p=wr_p is satisfied. If no check error occurs after a certain delay, the retransmission ends. Otherwise, the pointer rd_p is moved again to the address pointed to by the pointer ini_p to start the next retransmission. A data selector MUX1 is used to select an input signal of a controller / retransmission FIFO as an output signal; The command address register is used to store the command Cmd and address Addr output by the data selector MUX1, and transmit them to the DDR physical layer DDR PHY through the DFI CA bus; A write data cache, used to store the write data Wr data output by the data selector MUX1; The data selector MUX2 is used to select the write data cache data / invalid data as the output signal and transmit it to the DDR physical layer DDR PHY through the Dfi_wrdata bus; The read data register group is used to store the Dfi_rddata value returned by the DDR physical layer DDR PHY, and register M beats, that is, the read data Rd_data corresponding to the Dfi_rddata value is delayed for M cycles and then transmitted to the controller; The read data valid register group is used to store the read data valid value Dfi_rddata_valid returned by the DDR physical layer DDR PHY, and registers M beats, that is, the read data valid value Dfi_rddata_valid is delayed for M cycles and then transmitted to the data selector MUX3; The read tag processing module is used to process the value of the read data valid register group and generate read pointer data Rd_token_out_1 and a read data valid signal Rd_data_valid to the controller.

2. The DDR controller error checking and retransmission system according to claim 1, characterized in that: The tag reading processing module includes: A data selector MUX3 is used to select the value / invalid value of the read data valid register group as an output signal; Read tag FIFO1 is used to store the read tag Rd token sent by the controller only when the system is in normal working state and receives the read command Rd cmd sent by the controller. When the system is in retransmission state, no new data is stored, and the current read pointer data Rd_token_out_1 is output to the controller and the equal comparator; when the last beat read data valid signal Rddata_last_en obtained after the output signal of the data selector MUX3 is processed is high level, and the output signal Is_eq of the equal comparator is high level, the current read pointer is increased by 1, so as to output the next data; Read tag FIFO2 is used to store the read tag Rd token output by the data selector MUX1 when receiving the read command Rd cmd output by the data selector MUX1. It is valid when the system is in normal working state / retransmission state, and outputs the current read pointer data Rd_token_out_2 to the equal comparator; when the last beat read data valid signal Rddata_last_en is high level, the current read pointer is increased by 1, so as to output the next data; The equal comparator is used to compare the current read pointer data Rd_token_out_1 output by the read tag FIFO1 with the current read pointer data Rd_token_out_2 output by the read tag FIFO2. When the two values ​​are equal, the output signal Is_eq is high level; The AND gate is used to AND the last beat read data valid signal Rddata_last_en and the output signal Is_eq of the comparator to control whether the read pointer of the read tag FIFO1 is increased by 1.

3. The DDR controller error checking and retransmission system according to claim 1, characterized in that: Each unit entry in the retransmission FIFO stores the command Cmd, address Addr, write data Wr data and read tag Rdtoken sent by the controller, and contains three pointers, namely, pointer wr_p, pointer rd_p and pointer ini_p; Pointer wr_p points to the target address of the next write data Wr data. When Push is performed, the data at the address pointed to by pointer wr_p is written in this cycle, and then pointer wr_p is incremented by 1. Pointer rd_p points to the target address of the current read data Rd_data. When Pop is executed, the data at the address pointed to by pointer rd_p is output in this cycle, and then pointer rd_p is incremented by 1. The pointer ini_p is the same as the pointer rd_p when the system is in a non-retransmission state. When the retransmission cycle is started, it is fixed to point to the read start address within the retransmission cycle. If a check error occurs again within the retransmission cycle, the pointer rd_p is moved to the address pointed to by the pointer ini_p as the read start address within the next retransmission cycle.

4. The DDR controller error checking and retransmission system according to claim 1, characterized in that: The method for calculating the depth N of the retransmission FIFO comprises: There are two situations for command address parity timing: 1) When T5 ≥ T4, the read data Rd_data corresponding to the read command RDm+1 is returned before the DFI bus signal Dfi_alert_n is pulled low. Since the read command RDm+1 is within the tPAR_UNKNOWN time, the corresponding read data Rd_data should be invalid data. It is necessary to delay the read data Rd_data and the read data valid value Dfi_rddata_valid for M cycles, so that the read data Rd_data is moved to the DFI bus signal Dfi_alert_n after it is pulled low and returned. At this time, the depth N of the retransmission FIFO should be greater than or equal to the maximum number of cycles corresponding to T5; 2) When T5<T4, the read data Rd_data corresponding to the read command RDm is returned after the DFI bus signal Dfi_alert_n is pulled low, and the read data Rd_data is discarded. Therefore, the read command RDm needs to be retransmitted and must be included in the retransmission FIFO, that is, within the tMARGIN time. At this time, tMARGIN should be greater than or equal to the number of cycles corresponding to (T4-T5+T6), and the depth N of the retransmission FIFO should be greater than or equal to the maximum number of cycles corresponding to (T4+T6); For write data CRC check timing: The write data CRC check corresponding to the write command WRm is wrong. At this time, the depth N of the retransmission FIFO should be greater than or equal to the maximum number of cycles corresponding to T8; Considering the three situations corresponding to the command address parity check timing and the command address parity check timing, it is found that the depth N of the retransmission FIFO should take the maximum value of the three maximum cycle numbers, that is, the maximum cycle number corresponding to N=MAX(T5,T4+T6,T8); Among them, T5 = tPAR_UNKNOWN + T1 + tPAR_ALERT_ON + T3; tPAR_UNKNOWN is the uncertain time of command address parity error, which is defined in the standard protocol and its maximum value is the parity delay PL; T1 is the delay time of the command signal from the DFI bus to the DDR particle DRAM, and its value is determined by the DDR physical layer DDR PHY delay and PCB board delay; tPAR_ALERT_ON is the time when the command address parity error occurs, which is defined in the standard protocol and its maximum value is the parity delay PL + 6ns; T3 is the delay time of the output signal Alert_n of the DDR particle DRAM from the DDR particle DRAM to the DFI bus, and its value is determined by the DDR physical layer DDR PHY delay and the PCB board delay; T4=T1+RL+T2; RL is the time corresponding to the number of cycles from read command to read data in DDR particle DRAM, which is defined in the standard protocol. Its maximum value is determined by the specific model of DDR particle DRAM. T2 is the delay time of reading data from DDR DRAM to DFI bus, and its value is determined by DDR PHY delay and PCB board delay. tMARGIN is the time corresponding to the error tolerance margin of the retransmission FIFO depth N; T6 is the time corresponding to the maximum number of valid cycles for reading data; T8=T1+WL+T7+tCRC_ALERT+T3; WL is the time corresponding to the number of cycles from write command to write data in DDR particle DRAM, which is defined in the standard protocol. Its maximum value is determined by the specific model of DDR particle DRAM; T7 is the time corresponding to the maximum valid number of cycles of writing data plus CRC value; tCRC_ALERT is the time when a write data CRC check error occurs. It is defined in the standard protocol and its maximum value is 13ns.

5. The DDR controller error checking and retransmission system according to claim 1, characterized in that: When the system is in normal working state, the data selector MUX1 selects the input signal of the controller as the output signal; When the system is in the retransmission state, the data selector MUX1 selects the input signal of the retransmission FIFO as the output signal.

6. The DDR controller error checking and retransmission system according to claim 1, characterized in that: When the command address register outputs a write command Wr cmd, the data selector MUX2 selects the write data cache data as the output signal; When the command address register outputs a non-write command, the data selector MUX2 selects invalid data as an output signal.

7. The DDR controller error checking and retransmission system according to claim 1, characterized in that: The read data register group is composed of M read data registers, and the read data valid register group is composed of M read data valid registers, corresponding to the read data Rd_data and the read data valid value Dfi_rddata_valid being delayed by M cycles; The calculation method of M value includes: 1) When T5 ≥ T4, M is the number of cycles corresponding to (T5-T4), that is, the number of cycles corresponding to (tPAR_UNKNOWN+tPAR_ALERT_ON+T3-RL-T2); 2) When T5<T4, M is 0 cycle number.

8. The DDR controller error checking and retransmission system according to claim 2, characterized in that: When the DFI bus signal Dfi_alert_n is at a high level, the data selector MUX3 selects the value of the read data valid register group as the output signal; When the DFI bus signal Dfi_alert_n is at a low level, the data selector MUX3 selects the read data invalid value as the output signal to discard the currently returned read data valid value Dfi_rddata_valid when a verification error occurs, so that the corresponding read data Rd_data cannot be received by the controller.

9. The DDR controller error checking and retransmission system according to any one of claims 1 to 8, characterized in that: The DDR controller DDRC communicates with the DDR physical layer DDR PHY via a DFI bus, and the DDR physical layer DDRPHY communicates with the DDR particle DRAM via a CA bus and a DATA bus.

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